Data read-write method and system, and device and storage medium

Abstract

The present application relates to the technical field of memory extension. Provided are a data read-write method and system, and a device and a storage medium. The method comprises: a request parsing module parsing a received data read-write request for target data, to obtain a local command; an address decoding module parsing the local command to determine location information for data reading and writing; on the basis of the location information, a request decomposition module generating a plurality of data read-write sub-requests; a request allocation module sending the plurality of data read-write sub-requests to target extended memory controllers; and on the basis of the plurality of data read-write sub-requests, controlling the target extended memory controllers to execute data read-write operations in parallel. The present application aims to improve the efficiency of accessing extended memories.

Description

Data reading and writing method, system, device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on February 5, 2024, with application number 202410166050.0 and application name “A data reading and writing method, system, device and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of memory expansion technology, and in particular to a data reading and writing method, system, device and storage medium. Background Art

[0004] Currently, the memory access bottleneck of the CPU (Central Processing Unit) comes from the mismatch between the CPU clock speed and the memory clock speed. Memory access bandwidth is the main factor causing the CPU memory access bottleneck. Therefore, how to effectively increase memory access bandwidth and reduce memory access latency to improve data reading and writing efficiency is the focus of current research. Summary of the Invention

[0005] In view of this, the present application provides a data reading and writing method, system, device and storage medium, aiming to improve the access efficiency of extended memory.

[0006] In a first aspect of an embodiment of the present application, a data reading and writing method is provided, which is applied to a logic management controller. The logic management controller communicates with a CPU and at least two extended memory controllers based on the CXL protocol. The logic management controller includes a request parsing module, an address decoding module, a request decomposition module, and a request allocation module. The method includes:

[0007] Parsing the received data read and write request for the target data through the request parsing module to obtain the local command;

[0008] The local command is parsed through the address decoding module to determine the location information for data reading and writing;

[0009] The request decomposition module generates multiple data read and write sub-requests based on the location information;

[0010] Sending multiple data read and write sub-requests to each target extended memory controller through a request distribution module;

[0011] According to multiple data read and write sub-requests, each target extended memory controller is controlled to perform data read and write operations in parallel.

[0012] Optionally, when the data read / write request is a data write sub-request, the address decoding module parses the local command to determine the location information for data read / write, including:

[0013] The local command is parsed through the address decoding module to determine the logical starting address, data length and data content for data writing.

[0014] Optionally, the request decomposition module generates multiple data read and write sub-requests based on the location information, including:

[0015] Determining the number of write times for data writing according to the data length in the location information;

[0016] Determining a target amount of target extended memory for data writing according to the number of writes and the total amount of extended memory;

[0017] Determine each target extended memory for data writing according to the logical start address and the target quantity;

[0018] According to the number of write times and each target extended memory, a plurality of write data sub-requests with positioning identifiers equal in number to the number of write times are generated, wherein the positioning identifier is used to determine the target extended memory controller to which the write data sub-request is sent.

[0019] Optionally, each target extended memory for data writing is determined based on the logical start address and the target quantity, including:

[0020] According to the logical start address, the extended memory corresponding to the logical start address is determined as the target extended memory;

[0021] According to the idleness and target quantity of each extended memory, a plurality of extended memories ranked higher in idleness are determined as target extended memories, so as to obtain the target quantity of target extended memories.

[0022] Optionally, based on the number of writes and each target extended memory, multiple write data sub-requests with positioning identifiers equal in number to the number of writes are generated, including:

[0023] Determine the number of write data sub-requests corresponding to each target extended memory according to the number of writes and the number of targets;

[0024] Determining, in the target extended memory, a plurality of logical start addresses equal to the number of write data sub-requests corresponding to the target extended memory and a single data write amount according to the number of write data sub-requests corresponding to the target extended memory;

[0025] According to all the determined logical start addresses and the single data writing amount, a plurality of write data sub-requests with positioning identifiers are generated, the number of which is the same as the number of write times.

[0026] Optionally, a request allocation module sends multiple data read and write sub-requests to each target extended memory controller, including:

[0027] The multiple write data sub-requests are respectively sent to their corresponding target extended memory controllers through a request allocation module according to their respective positioning identifiers.

[0028] Optionally, sending the multiple write data sub-requests to their corresponding target extended memory controllers respectively through the request allocation module according to the respective positioning identifiers of the multiple write data sub-requests includes:

[0029] sending the plurality of write data sub-requests to the command queues of the respective corresponding target extended memory controllers through a request allocation module according to the respective positioning identifiers of the plurality of write data sub-requests;

[0030] When all write data sub-requests are sent, each target extended memory controller is notified to read the write data sub-requests in the respective command queues.

[0031] Optionally, the method further includes:

[0032] According to the number of write times, the data content is divided into multiple data fragments with the same number of write times;

[0033] According to the determined target extended memories, the plurality of data fragments are cyclically stored in sequence in the respective buffer areas of the target extended memories.

[0034] Optionally, based on multiple data read and write sub-requests, controlling each target extended memory controller to perform data read and write operations in parallel includes:

[0035] Control each target extended memory controller to obtain write data sub-requests in its own command queue in parallel;

[0036] According to the acquired write data sub-requests in the respective command queues, each target extended memory controller is controlled to perform write operations on the corresponding data segments in the corresponding cache areas in parallel.

[0037] Optionally, determining the number of write times for data writing according to the data length in the location information includes:

[0038] Determine the amount of data written in a single time according to the data length in the location information;

[0039] The number of times data is written is determined according to the data length in the position information and the amount of data written at a time.

[0040] Optionally, determining a target amount of target extended memory for data writing based on the number of writes and the total amount of extended memory includes:

[0041] Determine the relationship between the number of writes and the total amount of extended memory;

[0042] In a case where the number of write times is greater than or equal to the total number, determining the target number of target extended memories for data writing to be the total number of all extended memories;

[0043] When the number of write times is less than the total number, the target number of target extended memories for data writing is determined to be equal to the number of write times.

[0044] Optionally, when the data read / write request is a read data sub-request, the address decoding module parses the local command to determine the location information for data reading / writing, including:

[0045] The local command is parsed through the address decoding module to determine the logical starting address and data length for data reading.

[0046] Optionally, the request decomposition module generates multiple data read and write sub-requests based on the location information, including:

[0047] Determine, according to the logical starting address and the data length, the first logical starting address and the first data length of each of the data segments included in the data to be read;

[0048] A plurality of read data sub-requests with positioning identifiers are generated according to the first logical starting addresses and data lengths of all the data fragments, wherein the positioning identifier is used to determine the target extended memory controller to which the read data sub-requests are sent.

[0049] Optionally, the method further includes:

[0050] Determining target extended memories for data reading according to first logical start addresses of all data fragments;

[0051] The request dispatch module sends multiple data read and write sub-requests to each target extended memory controller, including:

[0052] The multiple read data sub-requests are respectively sent to their corresponding target extended memory controllers through a request allocation module according to their respective positioning identifiers.

[0053] Optionally, sending the multiple read data sub-requests to their corresponding target extended memory controllers respectively through a request allocation module according to the respective positioning identifiers of the multiple read data sub-requests includes:

[0054] sending the multiple read data sub-requests to the command queues of the corresponding target extended memory controllers respectively through the request allocation module according to the respective positioning identifiers of the multiple read data sub-requests;

[0055] When all read data sub-requests are sent, each target extended memory controller is notified to read the read data sub-requests in the respective command queues.

[0056] Optionally, based on multiple data read and write sub-requests, controlling each target extended memory controller to perform data read and write operations in parallel includes:

[0057] Control each target extended memory controller to obtain read data sub-requests in its own command queue in parallel;

[0058] Controlling each target extended memory controller to execute a read operation on the corresponding target extended memory in parallel according to the read data sub-requests obtained in the respective command queues, and storing the read data in the corresponding buffer areas;

[0059] After all data read operations are completed, all read data fragments are sorted and packaged based on the order in which the read data fragments form the target data to obtain the target data;

[0060] Send target data to the CPU.

[0061] In a second aspect of the embodiments of the present application, the present application provides a data reading and writing system, the system comprising: a CPU, a logic management controller, an extended memory controller and an extended memory, the logic management controller comprising a request parsing module, an address decoding module, a request decomposition module, and a request allocation module;

[0062] The CPU is used to initiate data read and write requests for target data;

[0063] A request parsing module is used to parse the received data read and write requests for the target data to obtain local commands;

[0064] The address decoding module is used to parse local commands and determine the location information for data reading and writing;

[0065] The request decomposition module is used to generate multiple data read and write sub-requests based on the location information;

[0066] a request allocation module, configured to send multiple data read and write sub-requests to each target extended memory controller;

[0067] Each target extended memory controller in the extended memory controller is used to control the corresponding target extended memory to perform corresponding data read and write operations in parallel according to the data read and write sub-requests received by the respective target extended memory controllers.

[0068] Optional, logical management controller, including:

[0069] The data synthesis module is used to sort and package all the read data fragments based on the order in which the read data fragments compose the target data after all the read data operations are completed, obtain the target data, and send the target data to the CPU.

[0070] In the third aspect of the embodiments of the present application, the present application provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and running on the processor. When the computer program is executed by the processor, the steps in a data reading and writing method of the first aspect of the present application are implemented.

[0071] In the fourth aspect of the embodiments of the present application, the present application provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in a data reading and writing method as in the first aspect of the present application are implemented.

[0072] Compared with the prior art, this application has the following advantages:

[0073] A data reading and writing method provided in an embodiment of the present application is applied to a logic management controller. The logic management controller communicates with a CPU and at least two extended memory controllers based on the CXL protocol. The logic management controller includes a request parsing module, an address decoding module, a request decomposition module, and a request allocation module. When the CPU needs to write target data to the extended memory (or the target data exists in the extended memory and the CPU needs to read the target data), the logic management controller receives a data write request (or data read request) sent by the CPU via the CXL IP; based on the received data write request (or data read request), the request parsing module parses the received data read / write request for the target data to obtain a local command; the address decoding module parses the local command to determine the location information for data reading and writing; the request decomposition module generates multiple write data sub-requests (or multiple read data sub-requests) based on the location information; the request allocation module sends the obtained multiple write data sub-requests (or multiple read data sub-requests) to each target extended memory controller currently used for data writing (or data reading); and each target extended memory controller performs a write operation (or a read operation) on the target data in parallel based on the received write data sub-requests (or read data sub-requests) to implement writing (or reading) of the target data. Therefore, this application introduces a logical management controller (LMC) that receives data read and write requests for target data issued by the CPU, splits the data read and write requests into multiple data read and write sub-requests, and distributes them to each target extended memory controller. The target extended memory controllers then execute read and write operations for the target data in parallel. This increases the bandwidth of the extended memory by executing read and write operations for data in parallel across multiple extended memories, thereby improving the CPU's access efficiency to the extended memory. At the same time, the LMC isolates the CPU from direct management of the extended memory, thereby increasing the security of the extended memory.

[0074] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

[0076] FIG1 is a flow chart of a data reading and writing method provided by some embodiments of the present application;

[0077] FIG2 is a diagram showing an existing memory expansion system architecture based on the CXL protocol;

[0078] FIG3 is an architecture diagram of a memory expansion system to which a data reading and writing method provided in some embodiments of the present application is applied;

[0079] FIG4 is a flowchart of data read and write request distribution in a data read and write method provided by some embodiments of the present application;

[0080] FIG5 is another flow chart of a data reading and writing method provided by some embodiments of the present application;

[0081] FIG6 is a schematic diagram of a data reading and writing system provided by some embodiments of the present application;

[0082] FIG7 is a schematic diagram of an electronic device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0083] Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0084] To facilitate understanding of the embodiments of this application, the following related professional terms are explained:

[0085] FPGA (Field Programmable Gate Array): Programmable logic device;

[0086] CXL (Compute Express Link): A new computing high-speed interconnect standard;

[0087] CXL IP (Compute Express Link intellectual property): The intellectual property core of the CXL protocol, which is a hardware module that implements the CXL protocol.

[0088] Before describing the present application, the background of the current prior art is described.

[0089] CXL (Compute Express Link) is an industry-adopted open standard based on the physical and electrical interface connections of the PCI Express (PCIe) specification. It includes three sub-protocols: CXL.io, CXL.cache, and CXL.mem. The CXL.mem protocol uses load and store commands to provide the host CPU with access to the memory of connected devices. The host CPU acts as the master device, and the CXL devices act as slaves, enabling memory expansion and pooling. This open standard provides a coherent cache interconnect for processors, memory expansion, and accelerators. In current FPGA-based CXL memory solutions, from the CPU's perspective, the MEMs of all channels are organized into a unified address space. Data is accessed sequentially on a channel-by-channel basis. This means that when a channel is accessed, other channels are idle, resulting in low access efficiency. If the CPU initiates a task request to extended memory through CXL, CXL will parse the request. Due to the characteristics of extended memory, row and column selection, refresh, and read latency are required. This latency cannot be further reduced due to hardware factors. Furthermore, CXL-based extended memory uses a unified address space on the CPU side: the first extended memory MEM1 occupies the address space BaseAddr+N1 (GB), the second extended memory MEM2 occupies the address space BaseAddr+N1 (GB, Gigabyte) + N2 (GB), and the third extended memory MEM3 occupies the address space BaseAddr+N1 (GB) + N2 (GB) + N3 (GB). Furthermore, because a CPU-initiated task request accesses a continuous range of addresses, if this address falls within a specific extended memory, the memory request reads the extended memory sequentially in address order until the request is completed. During this time, the other extended memories are idle and waiting, resulting in only one extended memory being accessible at a time. This reduces the bandwidth of the extended memory and reduces access efficiency. In view of this, the present application proposes a data read and write method. By introducing a logical management controller, the logical management controller receives a data read and write request for target data issued by the CPU, splits the data read and write request into multiple data read and write sub-requests, and distributes them to each target extended memory controller. The target extended memory controller then executes the read and write operations for the target data in parallel. In this way, the bandwidth of the extended memory is improved by executing the read and write operations for the data in parallel on multiple extended memories, thereby improving the efficiency of the CPU's access to the extended memory. At the same time, the logical management controller isolates the CPU from direct management of the extended memory, thereby increasing the security of the extended memory.

[0090] FIG1 is a flow chart of a data reading and writing method provided by some embodiments of the present application. As shown in FIG1 , the method is applied to a logic management controller, which communicates with a CPU and at least two extended memory controllers based on the CXL protocol. The logic management controller includes a request parsing module, an address decoding module, a request decomposition module, and a request allocation module. The method includes:

[0091] Step S1: parse the received data read and write request for target data through the request parsing module to obtain a local command.

[0092] Step S2: parsing the local command through the address decoding module to determine the location information for data reading and writing.

[0093] Step S3: The request decomposition module generates multiple data read and write sub-requests based on the location information.

[0094] Step S4: sending the multiple data read and write sub-requests to each target extended memory controller through the request allocation module.

[0095] Step S5: According to the multiple data read and write sub-requests, control each target extended memory controller to execute data read and write operations in parallel.

[0096] In some embodiments of the present application, as shown in FIG2 , FIG2 shows an existing memory expansion system architecture diagram based on the CXL protocol, and some embodiments of the present application provide a data reading and writing method applied to a memory expansion system architecture that adds a logic management controller on the basis of the existing memory expansion system architecture. As shown in FIG3 , the logic management controller is implemented by programming inside the programmable logic device in the board where the memory expansion system architecture is located, and the function of the logic management controller is realized by adding logic functions inside the programmable logic device through programming. The function of the logic management controller is a software function realized by the programmable logic device. The logic management controller is used to implement the steps related to the logic management controller in a data reading and writing method provided in an embodiment of the present application, wherein the programmable logic device includes but is not limited to FPGA. It should be understood that the logic management controller can also be a customized processor introduced into the board where the memory expansion system architecture is located to realize the function of the logic management controller.

[0097] In some embodiments of the present application, as shown in FIG3 , the logic management controller in the present application communicates with each extended memory controller based on the CXL protocol, and the logic management controller communicates with the CPU via a protocol implementation module (CXL IP) based on the CXL protocol. In the present application, the CPU performs memory expansion based on the CXL protocol, and the entire expansion link is connected based on the physical and electrical interfaces of the PCI Express (PCIe) specification. The memory expansion system includes three sub-protocols: CXL.io, CXL.cache, and CXL.mem. The CXL.mem protocol provides the CPU with access to connected devices (that is, access to extended memory) by using load commands and store commands, wherein the CPU acts as a master device and the CXL device acts as a slave device, thereby achieving memory expansion.

[0098] In some embodiments of the present application, when the CPU needs to perform corresponding read and write operations on a certain specific data, the certain specific data is the target data. At this time, the CPU will issue a data read and write request for the target data based on the CXL.mem protocol. At this time, the logical management controller will receive the data read and write request through the CXL IP, and generate multiple data read and write sub-requests based on the data read and write request to read and write the target data. After generating multiple data read and write sub-requests, the logical management controller will send the generated multiple data read and write sub-requests to multiple target extended memory controllers. Any one of the multiple data read and write sub-requests will only be sent to one target extended memory controller, and any one of the multiple target extended memory controllers will receive at least one data read and write sub-request. Among them, the target extended memory controller refers to the extended memory controller currently used to control the target data to perform corresponding read and write operations. There is a one-to-one correspondence between the extended memory controller and the extended memory, that is, one extended memory controller controls a corresponding extended memory. For example, the extended memory set for the CPU includes 5 extended memories a1 to a5, and correspondingly there are 5 extended memory controllers A1 to A5. When the extended memory controller currently used to control the target data to perform corresponding read and write operations is the extended memory controller A1 to A3, the extended memory controller A1 to A3 is the target extended memory controller.

[0099] In some embodiments of the present application, after each target extended memory controller receives a data read / write sub-request, the multiple target extended memory controllers execute corresponding data read / write operations in parallel based on the data read / write sub-requests received by themselves to realize reading and writing of target data.

[0100] Specifically, when the CPU needs to perform a corresponding write operation on a certain specific data, the certain specific data is the target data. At this time, the CPU will issue a write data request for the target data based on the CXL.mem protocol. At this time, the logical management controller will receive the write data request and, based on the write data request, generate multiple write data sub-requests to perform a write operation on the target data, and divide the target data into multiple data segments equal to the number of the multiple write data sub-requests. The write data sub-requests and the data segments have a one-to-one correspondence, that is, one write data sub-request is used to control the writing of a data segment corresponding to the write data sub-request. After generating multiple write data sub-requests, the logical management controller will send the generated multiple write data sub-requests to multiple target extended memory controllers. Any one of the multiple write data sub-requests will only be sent to one target extended memory controller, and any one of the multiple target extended memory controllers will receive at least one write data sub-request. After each target extended memory controller receives a write data sub-request, the multiple target extended memory controllers execute corresponding data write operations in parallel based on the write data sub-requests they received, thereby writing the target data. Thus, when the CPU needs to write target data, compared to the previous method of writing target data using only the bandwidth of a single extended memory, the method for improving extended memory provided by this application can simultaneously write target data using the bandwidth of multiple extended memories, thereby significantly improving the access bandwidth to the extended memory.

[0101] For example, based on a received write data request X for target data, three write data sub-requests x1, x2, and x3 are generated, and the target data Y is correspondingly divided into three data segments y1, y2, and y3. Write data sub-request x1 is determined as a write data sub-request for controlling the writing of data segment y1, write data sub-request x2 is determined as a write data sub-request for controlling the writing of data segment y2, and write data sub-request x3 is determined as a write data sub-request for controlling the writing of data segment y3. Write data sub-request x1 is sent to target extended memory controller A1, write data sub-request x2 is sent to target extended memory controller A2, and write data sub-request x3 is sent to target extended memory controller A3. At this time, the target extended memory controllers A1 to A3 execute write operations on data segments y1 to y3 in parallel based on the write data sub-requests they receive, thereby realizing the write operation on the target data Y. That is, the target extended memory controllers A1 to A3 will simultaneously execute write operations on the data segments based on the write data sub-requests they receive. At this time, the write operation is that the target extended memory controller A1 controls the data segment y1 to be written into its corresponding extended memory a1, the target extended memory controller A2 controls the data segment y2 to be written into its corresponding extended memory a2, and the target extended memory controller A3 controls the data segment y3 to be written into its corresponding extended memory a3. Compared with the previous method of only being able to write to one extended memory at a time based on a write data request, the present application can write to multiple extended memories at the same time based on the multiple write data sub-requests divided into by the write data request, thereby effectively improving the CPU's access efficiency to the extended memory.

[0102] Specifically, when the CPU needs to perform a corresponding read operation on a specific data, the specific data is the target data, wherein the target data belongs to the data written by a data reading and writing method provided by this application. At this time, the CPU will issue a read data request for the target data based on the CXL.mem protocol. At this time, the logical management controller will receive the read data request. Since the target data is the data written by a data reading and writing method previously provided by this application, the logical management controller in this application will record which extended memories the target data is written to, and the logical addresses corresponding to the specific physical addresses in these extended memories. At this time, the logical management controller will generate multiple read data sub-requests based on the recorded extended memories to which the target data is written and the logical addresses corresponding to the specific physical addresses in each extended memory to perform a read operation on the target data. After generating multiple read data sub-requests, the logical management controller will send the generated multiple read data sub-requests to the corresponding target extended memory controllers. Any one of the multiple read data sub-requests will only be sent to one target extended memory controller, and any one of the multiple target extended memory controllers will receive at least one read data sub-request. After each target extended memory controller receives a read data sub-request, the multiple target extended memory controllers execute corresponding data read operations in parallel based on the read data sub-requests they received, thereby reading the target data. Thus, when the CPU needs to read target data, compared to the previous method of only being able to read the target data using the bandwidth of a single extended memory, the method provided in this application can simultaneously read the target data using the bandwidth of multiple extended memories, thereby significantly improving the access bandwidth to the extended memory.

[0103] For example, based on a received read data request U for target data Y, three read data sub-requests u1, u2, and u3 are generated. Read data sub-request u1 is sent to target extended memory controller A1, read data sub-request u2 is sent to target extended memory controller A2, and read data sub-request u3 is sent to target extended memory controller A3. At this point, target extended memory controllers A1 to A3 concurrently execute read operations on data segments y1 to y3 based on the read data sub-requests they have received, thereby achieving read access to target data Y. That is, target extended memory controllers A1 to A3 simultaneously read data segments y1, y2, and y3 from their respective extended memories based on the read data sub-requests they have received, thereby achieving read access to target data Y. Compared with the previous method of only being able to read the target data in one extended memory at the same time based on a read data request, this application can divide the target data Y into multiple data fragments and store them in different extended memories. Then, based on the multiple read data sub-requests divided into by the read data request, the target data can be read in multiple extended memories at the same time, thereby effectively improving the CPU's access efficiency to the extended memory.

[0104] In some embodiments of the present application, the data read / write request sent by the CPU is a request packet, and the present application only requires the key data read / write location information when generating data read / write sub-requests. Therefore, the logic management controller in the present application includes at least a request parsing module, an address decoding module, a request decomposition module, and a request allocation module. The request parsing module in the logic management controller is used to perform packet parsing on the data read / write request sent by the CPU to obtain a corresponding local command. The local command refers to the specific data in the data read / write request obtained by parsing the data read / write request.

[0105] In some embodiments of the present application, the obtained local command includes a large number of fields, each representing different meanings. However, when generating a data read / write sub-request, the present application only requires the key data read / write location information. Therefore, after the request parsing module in the logic management controller performs packet parsing on the data read / write request to obtain the corresponding local command, the address decoding module in the logic management controller further performs command parsing on the local command to determine the data read / write location information from all fields in the local command.

[0106] In some embodiments of the present application, after the location information for data reading and writing is determined, a request allocation module in the logic management controller generates multiple data reading and writing sub-requests based on the location information.

[0107] A data reading and writing method provided in an embodiment of the present application is applied to a logic management controller. The logic management controller communicates with a CPU and at least two extended memory controllers based on the CXL protocol. The logic management controller includes a request parsing module, an address decoding module, a request decomposition module, and a request allocation module. When the CPU needs to write target data to the extended memory (or the target data exists in the extended memory and the CPU needs to read the target data), the logic management controller receives a data write request (or data read request) sent by the CPU via the CXL IP; based on the received data write request (or data read request), the request parsing module parses the received data read / write request for the target data to obtain a local command; the address decoding module parses the local command to determine the location information for data reading and writing; the request decomposition module generates multiple write data sub-requests (or multiple read data sub-requests) based on the location information; the request allocation module sends the obtained multiple write data sub-requests (or multiple read data sub-requests) to each target extended memory controller currently used for data writing (or data reading); and each target extended memory controller performs a write operation (or a read operation) on the target data in parallel based on the received write data sub-requests (or read data sub-requests) to implement writing (or reading) of the target data. Therefore, this application introduces a logical management controller (LMC) that receives data read and write requests for target data issued by the CPU, splits the data read and write requests into multiple data read and write sub-requests, and distributes them to each target extended memory controller. The target extended memory controllers then execute read and write operations for the target data in parallel. This increases the bandwidth of the extended memory by executing read and write operations for data in parallel across multiple extended memories, thereby improving the CPU's access efficiency to the extended memory. At the same time, the LMC isolates the CPU from direct management of the extended memory, thereby increasing the security of the extended memory.

[0108] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data read / write method. In this data read / write method, when the data read / write request is a write data sub-request, step S2 is: performing command parsing on the local command through the address decoding module to determine the logical starting address, data length, and data content for data writing.

[0109] In some embodiments of the present application, when the CPU needs to perform a corresponding write operation on target data, the present application generates multiple write data sub-requests based on a write data request issued by the CPU. The specific logical start address to which the target data is to be written, that is, the logical address from which the target data is to be written, as well as the data length of the target data and the specific data content of the target data, are required to be used in the write data request. Therefore, when the CPU needs to perform a corresponding write operation on the target data, one implementation of step S2 is as follows: the address decoding module in the logic management controller parses the data packet to obtain the corresponding local command, performs command parsing, and determines the logical start address to be written to the target data, the data length of the target data, and the specific data content of the target data from all fields in the local command.

[0110] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S3 may include steps S31 to S34:

[0111] Step S31: Determine the number of times data is written according to the data length in the location information.

[0112] Step S32: determining the target number of target extended memories for data writing according to the number of write times and the total number of extended memories.

[0113] In some embodiments of the present application, after storing target data in extended memory, to ensure that the CPU can subsequently read portions of the target data in parallel, the target data is divided into multiple small data segments, which are then stored in parallel in different extended memories. Accordingly, a corresponding write data subrequest is generated for each small data segment, i.e., one write data subrequest corresponds to each data segment.

[0114] Specifically, first, based on the data length of the target data to be written, the number of data writes required and the amount of target extended memory used to write the data segments of the target data are determined. This amount is the target amount of target extended memory. The longer the data length, the more data content the target data contains. To ensure that the subsequent CPU can also read part of the target data content in parallel, the present application divides the target data into more data segments and writes the data more times accordingly. To ensure access efficiency for parallel writing of data segments of the target data, the longer the data length, the more extended memory is involved in writing the data segments of the target data.

[0115] For example, the data content of the target data is z1 to z300, and the data length is 300. After the target data is stored in the extended memory, in order to ensure that when the CPU needs to read part of the data content of the target data (such as part of the data content z1 to z30), it can read the part of the data content in parallel, the target data is divided into 30 data fragments with a length of 10, that is, z1 to z10, z11 to z20, z21 to z30, ..., z291 to z300, a total of 30 fragments, and the 30 fragments are written to 3 extended memories in a dispersed manner, such as writing the 1st, 4th, ..., 3n+1th data fragments to the 1st extended memory, writing the 2nd, 5th, ..., 3n+2th data fragments to the 2nd extended memory, and writing the 3rd, 6th, ..., 3n+3th data fragments to the 3rd extended memory, where n is 0 to 9. When the CPU needs to read data z1 to z30 of the target data, it can read data z1 to z30 in parallel from the three extended memories. That is, the three extended memories will read data z1 to z3 in the first parallel read, then z4 to z6 in the second parallel read, and so on. In the tenth parallel read, the three extended memories will read data z28 to z30. Ultimately, all 30 data bytes of z1 to z30 will be read simultaneously using the total bandwidth of the three extended memories. As the target data becomes longer, the number of data segments will increase, and the corresponding write times will also increase.

[0116] Step S33: Determine each target extended memory for data writing according to the logical start address and the target quantity.

[0117] In some embodiments of the present application, the logical starting address and data length for writing the target data can be determined from the write data request issued by the CPU in step S2. The logical starting address indicates the logical address from which the CPU intends to start writing the target data and the data length of the target data to be written. Since there is a one-to-one mapping relationship between logical addresses and physical addresses of extended memory, the physical address of the extended memory corresponding to the logical starting address can be determined based on the logical starting address, and the extended memory to which the physical address belongs can be determined based on the physical address. After determining the extended memory to which the physical address belongs, the extended memory is determined as the first target extended memory for writing the data segment of the target data. Then, based on the determined target number, several extended memories are selected from all extended memories configured for the CPU as target extended memories for writing the data segment of the target data, thereby obtaining the target number of target extended memories. For example, if the determined target number is 3, after determining the first target extended memory, two more extended memories are selected from all extended memories configured for the CPU as target extended memories for writing the data segment of the target data.

[0118] Step S34: generating a plurality of write data sub-requests with positioning identifiers equal to the write times according to the write times and the target extended memories, wherein the positioning identifiers are used to determine the target extended memory controller to which the write data sub-requests are sent.

[0119] In some embodiments of the present application, after determining the write count and the target extended memory for writing the target data segment, multiple write data sub-requests with the same number and write count and location identifiers are generated. The location identifiers of the write data sub-requests are used to determine the target extended memory controller corresponding to the target extended memory to which the write data sub-request should be sent for performing the corresponding data write operation.

[0120] For example, the number of writes is determined to be 20, and the target extended memories are a1 and a2. Based on the determined number of writes and the target extended memories, 20 write data sub-requests q1 to q20 with positioning identifiers are generated. The write data sub-request q1 has a corresponding positioning identifier p1, the write data sub-request q2 has a corresponding positioning identifier p2,..., and the write data sub-request q20 has a corresponding positioning identifier p20. Based on the built-in logical algorithm, the logical management controller can determine the specific target extended memory corresponding to each positioning identifier. For example, based on the positioning identifier p1, it is determined that the target extended memory corresponding to the positioning identifier p1 is a1, so the write data sub-request q1 corresponding to the positioning identifier p1 is sent to the target extended memory controller A1 corresponding to the target extended memory a1; based on the positioning identifier p2, it is determined that the target extended memory corresponding to the positioning identifier p2 is a2, so the write data sub-request q2 corresponding to the positioning identifier p2 is sent to the target extended memory controller A2 corresponding to the target extended memory a2; based on the positioning identifier p3, it is determined that the target extended memory corresponding to the positioning identifier p3 is a1, so the write data sub-request q3 corresponding to the positioning identifier p3 is sent to the target extended memory controller A1 corresponding to the target extended memory a1; based on the positioning identifier p4, it is determined that the target extended memory corresponding to the positioning identifier p4 is a2, so the write data sub-request q4 corresponding to the positioning identifier p4 is sent to the target extended memory controller A2 corresponding to the target extended memory a2, and so on.

[0121] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S31 may include steps S311 to S312:

[0122] Step S311: Determine the single data writing amount according to the data length in the location information.

[0123] Step S312: Determine the number of data writes according to the data length in the location information and the single data write amount.

[0124] In some embodiments of the present application, one implementation method for determining the number of write times for target data is: obtaining a single data write amount of data writing, and obtaining the number of data write times by dividing the determined data length of the target data by the single data write amount.

[0125] In some embodiments of the present application, the single data write amount can be a fixed value pre-set by the logic management controller, such as 10, 50, 100, etc. At the same time, the value of the single data write amount can be determined based on the data length of the target data. An optional implementation method is: when the data length of the target data exceeds a certain set threshold, the single data write amount is determined to be a fixed value, and when the data length of the target data does not exceed a certain set threshold, the single data write amount is determined to be another fixed value. The advantage of determining the value of the single data write amount based on the data length of the target data is that for target data of any data size (that is, data length), when the CPU needs to read part of the data content of the target data, it can be read in parallel with the bandwidth of multiple extended memories at the same time, thereby effectively improving the access efficiency to the extended memory. For example, if the single data write amount is determined to be a fixed value (such as 50), when the data length of the target data is 500, when the CPU needs to read part of the data content of the target data (such as the part of the target data with a length of 200), it can be read in parallel with the bandwidth of multiple extended memories at the same time; but when the data length of the target data is only 50, when the CPU needs to read part of the data content of the target data (such as the part of the target data with a length of 20), since the single data write amount is 50, the target data will be written to one extended memory at a time, so the CPU can only read from the one extended memory for the part of the data with a length of 20, which will be detrimental to improving the access efficiency to the extended memory. If the value of the single data write amount is determined based on the data length of the target data, the above-mentioned problem of being detrimental to improving the access efficiency to the extended memory can be effectively avoided. For example, when the data length of the target data is 500, the corresponding single data write amount is determined to be 50 based on the data length of the target data. For this single data write amount, when the CPU needs to read part of the data content of the target data (such as part of the target data with a length of 200), it can be read in parallel with the bandwidth of multiple extended memories at the same time, thereby effectively improving the access efficiency to the extended memory; when the data length of the target data is 50, the corresponding single data write amount is determined to be 5 based on the data length of the target data. For this single data write amount, when the CPU needs to read part of the data content of the target data (such as part of the target data with a length of 20), it can be read in parallel with the bandwidth of multiple extended memories at the same time, thereby effectively improving the access efficiency to the extended memory.

[0126] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S32 may include steps S321 to S323:

[0127] Step S321: Determine the relationship between the number of write times and the total amount of extended memory.

[0128] In some embodiments of the present application, in order to improve the efficiency of access to the extended memory as much as possible, the present application determines the number of target extended memories used to write data segments of the target data based on the relationship between the determined number of writes and the total amount of extended memory configured for the CPU, that is, the target number of target extended memories.

[0129] Step S322: when the number of write times is greater than or equal to the total number, determining the target number of target extended memories for data writing to be the total number of all extended memories.

[0130] In some embodiments of the present application, when the determined number of writes is greater than or equal to the total number of extended memories configured for the CPU, even if all extended memories are used to write data segments of the target data, it is still impossible to complete the writing of all data contents of the target data at one time. At this time, in order to improve the access efficiency to the extended memory as much as possible, the present application determines all extended memories configured for the CPU as target extended memories when the determined number of writes is greater than or equal to the total number of extended memories configured for the CPU. At this time, the target number of target extended memories is equal to the total number of extended memories configured for the CPU.

[0131] Step S323: when the number of write times is less than the total number, determining the target number of target extended memories for data writing to be equal to the number of write times.

[0132] In some embodiments of the present application, to maximize the efficiency of accessing extended memory, if the determined number of writes is less than the total number of extended memories configured for the CPU, the present application determines the number of target extended memories used to write data segments of the target data to be equal to the number of writes. This allows all data segments of the target data to be written to the extended memories in parallel at once. This not only maximizes the efficiency of accessing the extended memories, but also effectively reduces the time required to write data. For example, if the determined number of writes is three and the total number of extended memories configured for the CPU is five, then three extended memories are selected as target extended memories. When writing the three data segments of the target data, the three target extended memories can simultaneously write to each corresponding data segment, thereby achieving parallel writing of the target data using the total bandwidth of the three extended memories.

[0133] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S33 may include steps S331 to S332:

[0134] Step S331: According to the logical start address, the extended memory corresponding to the logical start address is determined as the target extended memory.

[0135] In some embodiments of the present application, the logical starting address and data length for writing the target data can be determined from the write data request issued by the CPU in step S2. The physical address of the extended memory corresponding to the logical starting address is determined based on the logical starting address, and the extended memory to which the physical address belongs is determined based on the physical address. After determining the extended memory to which the physical address belongs, the extended memory is determined as the first target extended memory for writing the data segment of the target data.

[0136] Step S332: According to the idleness and target quantity of each extended memory, a plurality of extended memories ranked higher in idleness are determined as target extended memories to obtain the target quantity of target extended memories.

[0137] In some embodiments of the present application, in order to ensure that when the CPU subsequently sends a write data request, it can also perform parallel writing with the bandwidth of multiple extended memories at the same time, so as to effectively improve the access efficiency of the extended memory, the present application makes the remaining space in each extended memory as close as possible when writing data, thereby ensuring that when the CPU subsequently sends a write data request, all extended memories configured for the CPU are in a nearly available state, avoiding the situation where the space of one or some extended memories is full, resulting in the CPU being unable to perform parallel writing with the bandwidth of multiple extended memories at the same time when sending a write data request, or being unable to perform parallel writing with the bandwidth of a larger number of extended memories at the same time. Therefore, in order to achieve the purpose of making the remaining space in each extended memory as close as possible when writing data, the present application provides a preferred implementation method for determining subsequent target extended memories after determining the first target extended memory, specifically: determining the idleness of each extended memory other than the first target extended memory, and then determining the extended memory with the highest idleness as the target extended memory, until the number of all determined target extended memories reaches the target number. For example, the target number of target extended memories to be used is 5. After the first target extended memory is determined, the top 4 extended memories in terms of idleness among all extended memories configured for the CPU are determined as target extended memories.

[0138] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S34 may include steps S341 to S343:

[0139] Step S341: Determine the number of write data sub-requests corresponding to each target extended memory according to the number of writes and the target number.

[0140] In some embodiments of the present application, after determining the number of writes to be performed and the target number of target extended memories, all determined target extended memories participate in each parallel write process of the target data segments, thereby maximizing the access efficiency to the extended memory. This is because, when both the number of writes and the target number of target extended memories are determined, all determined target extended memories participate in each parallel write process of the target data segments, thereby maximizing the bandwidth achieved by each parallel write process, thereby maximizing the access efficiency to the extended memory. For example, if the number of writes is 30, the target data is divided into 30 data segments, and the target extended memories have 3 data segments. At this time, the three target extended memories write three data segments in parallel each time, and 10 parallel writes are performed to completely write the 30 data segments into the extended memory. At the same time, in each parallel write process, the three data segments are written in parallel at the maximum bandwidth, which is the sum of the bandwidths of the three target extended memories. Therefore, when the determined number of writes is an integer multiple of the determined target number, the present application determines the value obtained by dividing the determined number of writes by the determined target number as the number of write data sub-requests for each target extended memory. In this case, the number of write data sub-requests for each target extended memory is the same. For example, if the number of writes is 30 and the target number of target extended memories is 3, then the number of write data sub-requests corresponding to each target extended memory is 10. Since the present application subsequently distributes write data sub-requests based on the positioning identifiers of the actually generated write data sub-requests, it distributes one write data sub-request at a time to each target extended memory in the order of the positioning identifiers.For example, write data sub-requests include q1, q2, q3, q4, and q5, and target extended memories include a1, a2, and a3. The positioning identifier corresponding to q1 is p1, the positioning identifier corresponding to q2 is p2, the positioning identifier corresponding to q3 is p3, the positioning identifier corresponding to q4 is p4, and the positioning identifier corresponding to q5 is p5. When distributing write data sub-requests, the logic management controller distributes one write data sub-request to each target extended memory in sequence according to the order of the positioning identifiers. It knows that the write data sub-request q1 with the positioning identifier p1 needs to be sent to the target extended memory controller A1 corresponding to the first target extended memory a1; the positioning identifier needs to be The write data sub-request q2 identified as p2 is sent to the target extended memory controller A2 corresponding to the second target extended memory a2; the write data sub-request q3 identified as p3 needs to be sent to the target extended memory controller A3 corresponding to the third target extended memory a3; since there is no longer a sequentially increasing target extended memory a4 for the location identifier p4, it is now known that the write data sub-request q4 corresponding to the location identifier p4 needs to be sent to the target extended memory controller A1 corresponding to the first target extended memory a1; the write data sub-request q5 corresponding to the location identifier p5 needs to be sent to the target extended memory controller A2 corresponding to the second target extended memory a2. After the logical management controller knows the target extended memory to which each write data sub-request should be distributed based on the logic of sequentially distributing one write data sub-request to each target extended memory in the order of the location identifiers, it simultaneously sends multiple write data sub-requests belonging to the same target extended memory to the target extended memory controller corresponding to the target extended memory. Therefore, in the present application, if the determined number of writes is not an integer multiple of the determined target number, the determined number of writes is divided by the determined target data to obtain a value and a remainder. Based on the remainder, the number of write data sub-requests for the top multiple target extended memories with the same value as the remainder is determined as the value obtained by adding 1 to the value obtained by the division. For other target extended memories, the corresponding number of write data sub-requests is determined as the value obtained by the division. For example, if the determined number of writes is 32 and the determined target number of target extended memories is 3, the two are divided to obtain a value of 10 and a remainder of 2. Based on this result, the number of write data sub-requests corresponding to the first two target extended memories is determined to be 11, and the number of write data sub-requests for the last target extended memory is determined to be 10.

[0141] Step S342: according to the number of write data sub-requests corresponding to the target extended memory and the single data writing amount, a plurality of logical start addresses equal to the number of write data sub-requests corresponding to the target extended memory are determined in the target extended memory.

[0142] In some embodiments of the present application, since the implementation method for determining multiple physical start addresses corresponding to each target extended memory is the same, the determination of multiple physical start addresses corresponding to one target extended memory is taken as an example for description, and the specific description is as follows:

[0143] When writing any data segment of all data segments of the target data, the data segment is written at consecutive address bits. At the same time, when writing data, the extended memory writes data sequentially from the first physical address. Therefore, after determining the target extended memory for writing the data segment of the target data and the number of write data sub-requests corresponding to the target extended memory, the physical address of the first unwritten data is found in sequence in the target extended memory, and then the logical address corresponding to the physical address is determined as the first logical start address; then, starting from the first physical start address, after the physical address length corresponding to the data length of the single write data amount is separated, the logical address corresponding to the second physical start address is taken as the second logical start address; then, starting from the second physical start address, after the physical address length corresponding to the data length of the single write data amount is separated, the logical address corresponding to the third physical start address is taken as the third logical start address, and this cycle is repeated until a number of logical start addresses equal to the number of write data sub-requests corresponding to the target extended memory are obtained. For example, when the number of write data sub-requests corresponding to the target extended memory is 3, the physical address of the target extended memory includes physical addresses 1 to 500, and the amount of data written at a single time is 5 data lengths, it is first determined that no data has been written to the physical address of the target extended memory starting from physical address 101. At this time, the logical address corresponding to the physical address 101 of the target extended memory is determined as the first logical starting address corresponding to the target extended memory; then, after an interval of 5 data lengths of the amount of data written at a single time, the logical address corresponding to the physical address 106 of the target extended memory is determined as the second logical starting address corresponding to the target extended memory; then, after an interval of 5 data lengths of the amount of data written at a single time, the logical address corresponding to the physical address 111 of the target extended memory is determined as the third logical starting address corresponding to the target extended memory, thereby obtaining the 3 logical starting addresses corresponding to the target extended memory.

[0144] In some embodiments of the present application, through the same implementation as above, each target extended memory can obtain multiple logical start addresses corresponding to itself.

[0145] Step S343: Based on all the determined logical start addresses and the single data writing amount, a plurality of data writing sub-requests with positioning identifiers are generated, the number of which is the same as the number of writing times.

[0146] In some embodiments of the present application, since the method for determining the locator corresponding to any logical start address is the same, the method for determining the locator corresponding to a logical start address is used as an example for illustration. Specifically, the following steps are performed: first, the order of the target extended memory pointed to by the logical start address among all determined target extended memories is determined, and this order is determined as a first order, represented by Q1. Simultaneously, the order of the physical start address corresponding to the logical start address among the physical start addresses corresponding to each logical start address of the target extended memory pointed to by the logical start address is determined, and this order is determined as a second order, represented by Q2. Then, based on the first order (Q1), the second order (Q2), and the determined target quantity (represented by Q3), a locator Q corresponding to the logical start address is determined using the algorithm: Q = (Q2-1)*Q3+Q1. Thus, through the same method as above, a corresponding locator can be determined for each logical start address.

[0147] In some embodiments of the present application, after determining the location identifier corresponding to the logical starting address, a write data sub-request corresponding to the logical starting address is generated based on the logical starting address, the location identifier corresponding to the logical starting address, and the determined single data write amount. Thus, based on the same implementation, a corresponding write data sub-request can be determined for each logical starting address. Any write data sub-request will include a unique logical starting address, location identifier, and single data write amount.

[0148] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In this data reading and writing method, step S4 may include: sending the multiple write data sub-requests to their respective corresponding target extended memory controllers via a request allocation module based on the respective location identifiers of the multiple write data sub-requests.

[0149] In some embodiments of the present application, through the above steps S341 to S343, multiple write data sub-requests with positioning identifiers can be determined. As shown in Figure 4, according to the identification order of the positioning identifiers of the write data sub-requests, one write data sub-request at a time is distributed sequentially to each determined target extended memory in the order of the positioning identifiers. For example, write data sub-requests include q1 to q3n, and target extended memories include a1, a2, and a3. The positioning identifier corresponding to q1 is p1, the positioning identifier corresponding to q2 is p2, the positioning identifier corresponding to q3 is p3, ..., and the positioning identifier corresponding to q3n is p3n. When distributing write data sub-requests, the request allocation module in the logic management controller distributes one write data sub-request to each target extended memory in sequence according to the order of the positioning identifiers. It is known that the write data sub-request q1 with the positioning identifier p1 needs to be sent to the target extended memory controller A1 corresponding to the first target extended memory a1; the write data sub-request q2 with the positioning identifier p2 needs to be sent to the target extended memory controller A1 corresponding to the second target extended memory a1; the write data sub-request q3 with the positioning identifier p3 needs to be sent to the target extended memory controller A3 corresponding to the third target extended memory a3; and since there is no sequentially increasing target extended memory a4 for the positioning identifier p4, it is known that the write data sub-request q4 with the positioning identifier p4 needs to be sent to the target extended memory controller A1 corresponding to the first target extended memory a1. Send to the target extended memory controller A1 corresponding to the first target extended memory a1; the write data sub-request q5 corresponding to the positioning identifier p5 needs to be sent to the target extended memory controller A2 corresponding to the second target extended memory a2; the write data sub-request q5 corresponding to the positioning identifier p5 needs to be sent to the target extended memory controller A2 corresponding to the second target extended memory a2; the write data sub-request q6 corresponding to the positioning identifier p6 needs to be sent to the target extended memory controller A2 corresponding to the second target extended memory a2; ...; the write data sub-request q(3n-2) corresponding to the positioning identifier p(3n-2) needs to be sent to the target extended memory controller A1 corresponding to the first target extended memory a1; the write data sub-request q(3n-1) corresponding to the positioning identifier p(3n-1) needs to be sent to the target extended memory controller A2 corresponding to the second target extended memory a2; the write data sub-request q(3n) corresponding to the positioning identifier p(3n) needs to be sent to the target extended memory controller A3 corresponding to the third target extended memory a3. The logic management controller distributes one write data sub-request to each target extended memory in sequence based on the logic of the positioning identifier. After knowing the target extended memory to which each write data sub-request should be distributed, multiple write data sub-requests belonging to the same target extended memory are sent to the target extended memory controller corresponding to the target extended memory at the same time.

[0150] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S4 may include steps S41 to S42:

[0151] Step S41: sending the multiple write data sub-requests to the command queues of the corresponding target extended memory controllers respectively through the request allocation module according to the respective positioning identifiers of the multiple write data sub-requests.

[0152] In some embodiments of the present application, after the logical management controller determines the target extended memory controller to which each write data sub-request should be sent based on the positioning identifier of the write data sub-request, it sends each write data sub-request to the command queue of the corresponding target extended memory controller.

[0153] Step S42: After all write data sub-requests have been sent, each target extended memory controller is notified to read the write data sub-requests in its own command queue.

[0154] In some embodiments of the present application, after the request allocation module in the logical management controller completes the sending of all write data sub-requests, it notifies each target extended memory controller to read the write data sub-requests in its own command queue, so as to perform parallel write operations on the data segments of the target data based on the read write data sub-requests.

[0155] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, the method further includes:

[0156] Step S344: Divide the data content into a plurality of data segments whose number is the same as the number of write times according to the write times.

[0157] In some embodiments of the present application, based on the determined number of write times, the data content of the target data to be written is divided into a number of data segments equal to the number of write times. For example, if the determined number of write times is 30, the data content of the target data is divided into 30 segments.

[0158] Step S345: according to the determined target extended memories, the plurality of data segments are sequentially and cyclically stored in the respective buffer areas of the target extended memories.

[0159] In some embodiments of the present application, the present application divides a corresponding cache area for each extended memory, that is, there is a one-to-one correspondence between the cache area and the extended memory. According to the determined target extended memories, the multiple data fragments are stored in each target extended memory in a cyclic manner according to the order of the target extended memories. For example, when the target extended memory includes target extended memories a1, a2, and a3, and the data fragments include data fragments 1 to 8, data fragments 1, 4, and 7 are stored in the cache area corresponding to the target extended memory a1 in sequence, and data fragments 2, 5, and 8 are sent to the cache area corresponding to the target extended memory a2 in sequence, and data fragments 3 and 6 are sent to the cache area corresponding to the target extended memory a3 in sequence.

[0160] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S5 may include steps S51 to S52:

[0161] Step S51: controlling each target extended memory controller to obtain write data sub-requests in its own command queue in parallel.

[0162] In some embodiments of the present application, each target extended memory controller simultaneously retrieves one write data sub-request from its own command queue at a time. Multiple read data sub-requests sent to the same command queue have a sequential order, and a write data sub-request for writing earlier data segments to the extended memory is sent to the command queue first.

[0163] Step S52: According to the acquired write data sub-requests in the respective command queues, control the respective target extended memory controllers to execute write operations on the corresponding data segments in the respective corresponding buffer areas in parallel, so as to write the target data into the extended memory.

[0164] In some embodiments of the present application, each target extended memory controller obtains data segments from its own corresponding cache area in parallel and writes them into its own corresponding target extended memory based on the write data sub-requests in its own command queue. After completing one parallel write, each target extended memory controller obtains a new write data sub-request from its own command queue again at the same time, and based on the new write data sub-request in its own command queue, obtains new data segments from its own corresponding cache area in parallel and writes them into its own corresponding target extended memory again, until there are no more write data sub-requests in the command queues of all target extended memory controllers. The cache area of ​​each extended memory is provided by RAM (random-access memory) in the computing terminal, and the above-mentioned memory expansion system is part of the computing terminal.

[0165] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In this data reading and writing method, when the data reading and writing request is a read data sub-request, step S2 is: using the address decoding module to parse the local command and determine the logical starting address and data length for data reading.

[0166] In some embodiments of the present application, when the CPU needs to perform a corresponding read operation on the target data, the present application needs to use the logical starting address in the read data request and the data length of the target data in order to generate multiple read data sub-requests based on the read data request issued by the CPU. Therefore, when the CPU needs to perform a corresponding read operation on the target data, one implementation of the above-mentioned step S2 is: the address decoding module in the logic management controller parses the data packet to obtain the corresponding local command, and performs command parsing to determine the logical starting address for reading the target data and the data length of the target data from all fields in the local command. Since the target data is being read at this time, the specific data content of the target data is no longer involved.

[0167] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S3 may include steps S301 to S302:

[0168] Step S301: determining the first logical start address and the first data length of all data segments included in the data to be read according to the logical start address and the data length.

[0169] In some embodiments of the present application, when the CPU writes target data to the extended memory, it uses a data reading and writing method provided by the present application to write the target data. During this process, the logic management controller records the extended memories to which the CPU previously wrote each data segment of the target data, as well as the specific locations within each extended memory, and the order in which all data segments corresponding to the target data were formed. When the logic management controller subsequently receives a read request from the CPU for the target data, the logic management controller can determine, based on the previously recorded data information, the extended memories to which each data segment of the target data previously written by the CPU is located, as well as the specific locations within each extended memory, and the order in which all data segments corresponding to the target data were formed. This can thereby determine the first logical starting address and first data length of each data segment corresponding to the target data, as well as the order in which each data segment was formed. For example, a CPU previously wrote target data D. During the write, the CPU provided a logical start address and data length to be written. The target data D was divided into 30 data segments and then written into three extended memories. The logic management controller recorded the number of data segments into which the target data D with the logical start address and data length was divided, as well as the physical addresses at which these data segments were stored. Upon receiving another read data request from the CPU for the target data D, the read data request provided the same logical start address and data length as those provided by the CPU when previously writing the target data. The logic management controller can then determine, based on the logical start address and data length in the read data request, that the data to be read by the CPU is the target data D. Furthermore, based on the recorded data information, the logic management controller can determine the respective extended memories where the respective data segments of the target data previously written by the CPU are located, as well as the specific locations within the respective extended memories. This allows the controller to determine the first logical start address and first data length of each data segment corresponding to the target data. At the same time, since the logical management controller records how many data fragments the target data D is divided into and at which physical addresses these data fragments are stored, and there is a one-to-one correspondence between the physical address and the logical address, when the CPU receives a read data request for part of the data content of the target data D, based on the logical starting address and data length in the read data request and the data information recorded by the logical management controller, the specific part of the target data D that the CPU wants to read can also be determined, thereby determining the first logical starting address and first data length of all the data fragments included in the data to be read.

[0170] Step S302: Generate multiple data read sub-requests with positioning identifiers according to the first logical start addresses and data lengths of all data fragments, wherein the positioning identifier is used to determine the target extended memory controller to which the data read sub-requests are sent.

[0171] In some embodiments of the present application, after determining the first logical starting address and first data length of each of the data segments of the data to be read and the order of each when constituting the target data, a positioning identifier corresponding to the data segment is determined based on the order of the data segments when constituting the target data, and then a corresponding read data sub-request is generated based on the positioning identifier, first logical starting address, and first data length corresponding to the data segment. Based on the same implementation method, a corresponding read data sub-request can be obtained for each of all the data segments corresponding to the data to be read. The positioning identifier of the read data sub-request is used to determine the target extended memory controller corresponding to the target extended memory to which the read data sub-request should be sent to perform the corresponding data read operation.

[0172] For example, when writing target data, the target data is divided into 10 data segments, sequentially including data segments 1 through 10. This sequence is recorded by the logic management controller during the process of writing the target data to the extended memory. If the data to be read by the CPU is the target data, all data segments to be read are the 10 data segments. The first logical starting address and first data length corresponding to any of the 10 data segments are the same as the logical starting address and data length used when the data segment was previously written to the extended memory. For data segment n, the logic management controller records the sequence of the target data corresponding to data segment n as n, and determines the location identifier corresponding to data segment n as n, where n ranges from 1 to 10. Thus, for any of the data segments corresponding to the target data, the corresponding first logical starting address, first data length, and location identifier can be determined. Accordingly, based on the first logical starting address, first data length, and location identifier, a corresponding read data subrequest with a location identifier can be generated for the data segment.

[0173] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method, wherein the method further includes step S303: determining target extended memories for data reading based on the first logical starting addresses of all data fragments.

[0174] When the method further includes step S303, step S4 may be: sending the multiple read data sub-requests to their corresponding target extended memory controllers respectively through the request allocation module according to the respective positioning identifiers of the multiple read data sub-requests.

[0175] In some embodiments of the present application, after the logical management controller determines the first logical starting addresses of all data fragments involved in the data to be read, all extended memories corresponding to these first logical starting addresses can be determined based on the correspondence between the logical addresses and the physical addresses. All the corresponding extended memories are the target extended memories currently used to read the data.

[0176] In some embodiments of the present application, after each target extended memory for data reading is determined, each read data sub-request is sent to its corresponding target extended memory according to a location identifier of the read data sub-request.

[0177] For example, the CPU previously wrote a target data D, which was divided into 10 data segments and stored in three extended memories a1, a2, and a3. Extended memory a1 stores data segments 1, 4, 7, and 10, extended memory a2 stores data segments 2, 5, and 8, and extended memory a3 stores data segments 3, 6, and 9. When the logical start address and data length in the read data request currently initiated by the CPU indicate that the data to be read are data segments 2 to 4 of the target data D, the logical management controller performs a read operation based on the logical start address and data length in the read data request currently initiated by the CPU. Based on the length, it can be determined that the data that the CPU currently wants to read is data segments 2 to 4 of the target data D. At the same time, the logic management controller can determine the logical addresses of data segments 2, 3, and 4 based on the data information recorded before writing the target data D. The logical address that comes first in the logical address is the logical starting address of the data segment, and the specific extended memory where it is located can be determined. It can also be determined that the order of these three data segments in forming the target data D is the second, third, and fourth respectively. Based on this order, the three positioning identifiers can be determined as positioning identifier p2 (this positioning identifier is the same as the one before data segment 2). The first logical start address and the first data length of data segment 2 are used to generate a read data sub-request 1, a read data sub-request 2 is generated based on the positioning identifier p3 and the first logical start address and the first data length of data segment 3, and a read data sub-request 3 is generated based on the positioning identifier p4 and the first logical start address and the first data length of data segment 4. The logical management controller records the target extended memory to which the positioning identifier was sent when data was previously written, and the positioning identifier used in the newly generated read data sub-request for reading a specific data segment is the same as the positioning identifier used when writing data to the specific data segment before. Therefore, the request allocation module in the logical management controller can know which corresponding target extended memory controller the read data sub-request needs to be sent to based on the positioning identifier in the read data sub-request. Therefore, the request allocation module in the logical management controller can send each read data sub-request to its corresponding target extended memory controller based on the positioning identifier of the read data sub-request.

[0178] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In this data reading and writing method, based on the respective positioning identifiers of the multiple read data sub-requests, the multiple read data sub-requests are sent to their respective corresponding target extended memory controllers, which may include steps S401 to S402:

[0179] Step S401: sending the multiple data read sub-requests to the command queues of the corresponding target extended memory controllers respectively through a request allocation module according to the respective positioning identifiers of the multiple data read sub-requests.

[0180] In some embodiments of the present application, the request allocation module in the logical management controller determines the target extended memory controller to which each read data sub-request should be sent based on the positioning identifier of the read data sub-request, and then sends each read data sub-request to the command queue of the corresponding target extended memory controller.

[0181] Step S402: when all read data sub-requests have been sent, each target extended memory controller is notified to read the read data sub-requests in its own command queue.

[0182] In some embodiments of the present application, after the request allocation module in the logical management controller completes the sending of all read data sub-requests, it notifies each target extended memory controller to read the read data sub-requests in its own command queue, so that parallel read operations on the data segments are performed based on the read read data sub-requests.

[0183] In combination with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In the data reading and writing method, step S5 may include steps S501 to S504:

[0184] Step S501: controlling each target extended memory controller to concurrently obtain read data sub-requests in its own command queue.

[0185] In some embodiments of the present application, each target extended memory controller simultaneously obtains one read data sub-request from its own command queue each time.

[0186] Step S502: according to the acquired read data sub-requests in the respective command queues, control the respective target extended memory controllers to execute read operations on the respective corresponding target extended memories in parallel, and store the read data into the respective corresponding buffer areas.

[0187] In some embodiments of the present application, each target extended memory controller, based on a read data subrequest received in its own command queue, concurrently reads the data segments pointed to by the read data subrequest from its corresponding extended memory, and stores the read data segments in its corresponding cache. After completing one parallel read, each target extended memory controller concurrently retrieves a new read data subrequest from its own command queue, and based on the new read data subrequest received in its own command queue, concurrently reads the data segments pointed to by the read data subrequest from its corresponding extended memory, and stores the read data segments in its corresponding cache, until all target extended memory controllers no longer have read data subrequests in their command queues.

[0188] Step S503: When all data read operations are completed, all read data segments are sorted and packaged based on the order in which the read data segments constitute the target data to obtain the target data.

[0189] In some embodiments of the present application, multiple read data sub-requests sent to the same command queue have a priority order. Read data sub-requests that require reading earlier data segments are sent to the command queue earlier. Therefore, data segments read from the same extended memory cache also have a priority order. Because the logical management controller can determine the specific data segments to be read, and these data segments are stored in the corresponding caches after being read, and multiple data segments stored in the same cache have a priority order, the logical management controller can determine the priority order of all currently read data segments based on the caches where the data segments are stored and the priority order of the multiple data segments within the same cache. Based on this priority order, the logical management controller sorts and packages all read data segments to obtain the target data required by the CPU.

[0190] Step S504: Send the target data to the CPU.

[0191] In some embodiments of the present application, after all data segments are packaged to obtain target data, the obtained target data is sent to the CPU, wherein the packaged target data is preferably a completion packet of CXL.mem.

[0192] In conjunction with the above embodiments, in one implementation, some embodiments of the present application further provide a data reading and writing method. In this data reading and writing method, the method further includes: initializing a communication link between the CPU and the extended memory controller via the logic management controller; after completing the initialization of the communication link, the CPU reads the memory address and address length of all extended memories to enable subsequent data reading and writing by the CPU.

[0193] In some embodiments of the present application, the preparatory work before implementing the present method includes: the logical management controller communicates with the CPU and at least two extended memory controllers based on the CXL protocol, the CPU performs memory expansion based on the CXL protocol, and after the memory expansion is completed, initializes the communication link to enable the memory expansion system to operate normally.

[0194] In some embodiments of the present application, after completing the initialization of the communication link, the CPU reads the memory address and address length of all configured extended memories, so that the subsequent CPU can perform corresponding data read and write operations based on the memory address and address length.

[0195] In some embodiments of the present application, as shown in Figure 5, the CPU first initiates a data read and write request, and then the logic management controller parses the data read and write request. When it is determined that the data read and write request is a write data request, the write data request is divided into multiple write data sub-requests, and then based on the positioning identifiers of the write data sub-requests, the multiple write data sub-requests are sent to the command queues of their respective corresponding target extended memory controllers. After the sending is completed, each target extended memory controller obtains the write data sub-request from its respective command queue in parallel, and then writes the data fragments corresponding to the write data sub-requests obtained by itself in parallel to its respective target extended memory, thereby completing the data write operation. When it is determined that the data read / write request is a read data request, the read data request is divided into multiple read data sub-requests. Then, based on the location identifiers of the read data sub-requests, the multiple read data sub-requests are sent to the command queues of their respective target extended memory controllers. After the sending is completed, each target extended memory controller obtains the read data sub-requests from its respective command queues in parallel, and then reads the data segments corresponding to the obtained read data sub-requests from its respective target extended memory in parallel. After the data read operation is completed, all the read data segments are packaged in sequence and sent to the CPU. The data read / write method provided by this application can realize parallel data read / write operations on multiple extended memories, thereby improving the access efficiency of the extended memory. At the same time, the multiple data read / write sub-requests divided from a total data read / write request can be evenly distributed to each extended memory, thereby balancing the load of the extended memory. At the same time, by further increasing the number of extended memories, the bandwidth utilization of the extended memory can be further improved. In addition, the addition of a logical management controller realizes unified management of the address space of each extended memory, avoids the resource consumption caused by the CPU directly managing the extended memory, and plays an isolation role, ensuring data security.

[0196] Based on the same inventive concept, the second aspect of the present application provides a data reading and writing system. As shown in FIG6 , the system 600 includes:

[0197] Central processing unit (CPU) 601, logical management controller 602, extended memory controller 603 and extended memory 604. The logical management controller 602 includes a request parsing module 6021, an address decoding module 6022, a request decomposition module 6023, and a request allocation module 6024.

[0198] Central processing unit (CPU) 601, used to initiate data read and write requests for target data;

[0199] The request parsing module 6021 in the logic management controller 602 is used to parse the received data read and write requests for the target data to obtain local commands;

[0200] The address decoding module 6022 in the logic management controller 602 is used to parse local commands and determine the location information for data reading and writing;

[0201] The request decomposition module 6023 in the logic management controller 602 is used to generate multiple data read and write sub-requests based on the location information;

[0202] The request allocation module 6024 in the logical management controller 602 is used to send multiple data read and write sub-requests to each target extended memory controller;

[0203] Each target extended memory controller in the extended memory controller 603 is configured to control its corresponding target extended memory to execute corresponding data read and write operations in parallel according to the data read and write sub-requests it receives.

[0204] Optionally, the address decoding module 6022 includes:

[0205] The first address decoding module is used to determine the logical starting address, data length and data content for data writing by parsing the local command when the data read / write request is a data write sub-request.

[0206] Optionally, the request decomposition module 6023 includes:

[0207] A first data determination module, configured to determine a number of write times for data writing according to a data length in the location information;

[0208] a second data determining module, configured to determine a target number of target extended memories for data writing according to the number of writes and the total number of extended memories;

[0209] A target extended memory determination module is used to determine each target extended memory for data writing according to a logical start address and a target quantity;

[0210] The write data sub-request generation module is used to generate multiple write data sub-requests with positioning identifiers, the number of which is the same as the number of write times and each target extended memory, wherein the positioning identifier is used to determine the target extended memory controller to which the write data sub-request is sent.

[0211] Optional, target extended memory determination module, including:

[0212] A first target extended memory determining module is configured to determine, according to the logical start address, the extended memory corresponding to the logical start address as the target extended memory;

[0213] The second target extended memory determination module is configured to determine, according to the idleness and target quantity of each extended memory, a plurality of extended memories ranked with the highest idleness as target extended memories, so as to obtain a target quantity of target extended memories.

[0214] Optionally, a write data sub-request generation module includes:

[0215] A data write sub-request quantity determination module is used to determine the number of data write sub-requests corresponding to each target extended memory according to the number of writes and the target quantity;

[0216] a logic start address determination module, configured to determine, in the target extended memory, a plurality of logic start addresses equal to the number of write data sub-requests corresponding to the target extended memory and a single data write amount;

[0217] The write data sub-request generating sub-module is used to generate a plurality of write data sub-requests with positioning identifiers, the number of which is the same as the number of write times, according to all the determined logical starting addresses and the single data writing amount.

[0218] Optionally, the request allocation module 6024 includes:

[0219] The write data sub-request allocation module is used to send the multiple write data sub-requests to their corresponding target extended memory controllers according to their respective positioning identifiers.

[0220] Optionally, a write data sub-request allocation module includes:

[0221] a first write data sub-request allocation module, configured to send the plurality of write data sub-requests to the command queues of the respective corresponding target extended memory controllers according to the respective positioning identifiers of the plurality of write data sub-requests;

[0222] The second write data sub-request allocation module is used to notify each target extended memory controller to read the write data sub-requests in the respective command queues when all write data sub-requests are sent.

[0223] Optionally, the system 600 further includes:

[0224] A data segment division module is used to divide the data content into a plurality of data segments having the same number as the number of write times according to the number of write times;

[0225] The data segment cache module is used to store multiple data segments in sequence and cyclically in the cache areas of the respective target extended memories according to the determined target extended memories.

[0226] Optionally, the extended memory controller 603 includes:

[0227] The request acquisition module is used to obtain the write data sub-requests in the command queue in parallel;

[0228] The execution module is used to execute write operations on corresponding data fragments in the corresponding buffer area in parallel according to the write data sub-requests in the command queue obtained in parallel, so as to write the target data into the extended memory.

[0229] Optionally, the first data determination module includes:

[0230] A single data writing amount determination module is used to determine the single data writing amount according to the data length in the position information;

[0231] The write times determination module is used to determine the write times for data writing according to the data length in the position information and the amount of data written in a single time.

[0232] Optionally, the second data determination module includes:

[0233] a relationship comparison module, for determining a relationship between the number of write times and the total amount of extended memory;

[0234] a first target quantity determining module, configured to determine, when the number of write times is greater than or equal to the total number, the target quantity of the target extended memory for writing data as the total number of all extended memories;

[0235] The second target data determination module is configured to determine, when the number of write times is less than the total number, a target number of target extended memories for data writing to be equal to the number of write times.

[0236] Optional, address decoding module, including:

[0237] The second address decoding module is used to determine the logical starting address and data length for data reading by performing command parsing on the local command when the data read / write request is a data read sub-request.

[0238] Optionally, request a decomposition module, including:

[0239] a third data determination module, configured to determine, according to the logical start address and the data length, the first logical start address and the first data length of each of the data segments included in the data to be read;

[0240] The read data sub-request generation module is used to generate multiple read data sub-requests with positioning identifiers according to the first logical starting addresses and data lengths of all data fragments, wherein the positioning identifier is used to determine the target extended memory controller to which the read data sub-request is sent.

[0241] Optionally, the system 600 further includes:

[0242] a target extended memory determination submodule, configured to determine respective target extended memories for data reading according to respective first logical start addresses of all data fragments;

[0243] The request allocation module 6024 includes:

[0244] The read data sub-request allocation module is used to send the multiple read data sub-requests to their corresponding target extended memory controllers respectively according to their respective positioning identifiers.

[0245] Optionally, a read data sub-request allocation module includes:

[0246] a first read data sub-request allocation module, configured to send the plurality of read data sub-requests to the command queues of the respective corresponding target extended memory controllers according to the respective positioning identifiers of the plurality of read data sub-requests;

[0247] The second read data sub-request allocation module is used to notify each target extended memory controller to read the read data sub-requests in the respective command queues when all the read data sub-requests are sent.

[0248] Optionally, the extended memory controller 603 includes:

[0249] The request acquisition module is used to obtain read data sub-requests in each command queue in parallel;

[0250] an execution module, configured to control each target extended memory controller to execute a read operation on the corresponding target extended memory in parallel according to the read data sub-requests obtained in the respective command queues, and store the read data into the corresponding buffer areas;

[0251] The data synthesis module in the logic management controller is used to sort and package all the read data fragments based on the order in which the read data fragments compose the target data after completing all data read operations, obtain the target data, and send the target data to the CPU.

[0252] In some embodiments of the present application, as shown in FIG3 , FIG3 shows a hardware architecture diagram of a data reading and writing system provided by the present application. The main modules involved include a central processing unit (CPU) for initiating data reading and writing requests, a protocol implementation module (CXL IP) for implementing the CXL protocol, a logic management controller for implementing relevant steps in a data reading and writing method provided by the present application, and multiple extended memory controllers for controlling their respective extended memories to perform corresponding data reading and writing operations. The logical management controller includes at least four core modules: a request parsing module, which is used to parse data packets of data read and write requests initiated based on CXL.mem based on the CXL protocol to obtain the specific internal data content, that is, to obtain the corresponding local commands; an address parsing module and a request decomposition module, which are used to parse local commands to obtain the core data information in the local commands for generating a large number of data read and write sub-requests, and generate multiple data read and write sub-requests based on the obtained core data information; a request allocation module composed of the above-mentioned read data sub-request allocation module and write data sub-request allocation module, which is used to allocate the generated multiple data read and write sub-requests to the corresponding extended memory controller; and a data synthesis module, which is used to sort and package all read data fragments after completing all read data operations to obtain the target data that the CPU needs to read.

[0253] Based on the same inventive concept, in the third aspect of the embodiments of the present application, as shown in Figure 7, the present application provides an electronic device, which includes: a processor 701, a memory 702, and a computer program stored in the memory and running on the processor. When the computer program is executed by the processor, it implements the steps in the data reading and writing method of the first aspect of the present application.

[0254] Based on the same inventive concept, in the fourth aspect of the embodiments of the present application, the present application provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the data reading and writing method of the first aspect of the present application are implemented.

[0255] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing the computer program instructions on a computer, the process or function according to some embodiments of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer non-volatile readable storage medium, or transmitted from a computer non-volatile readable storage medium to another computer non-volatile readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode.

[0256] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0257] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0258] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A data reading and writing method, characterized in that: Applied to a logical management controller, the logical management controller communicates with a CPU and at least two extended memory controllers based on the CXL protocol, the logical management controller includes a request parsing module, an address decoding module, a request decomposition module, and a request allocation module, the method comprising: Parsing the received data read and write request for the target data by the request parsing module to obtain a local command; Parsing the local command by the address decoding module to determine the location information for data reading and writing; The request decomposition module generates a plurality of data read and write sub-requests based on the location information; Sending the multiple data read and write sub-requests to each target extended memory controller through the request allocation module; According to the multiple data read and write sub-requests, the target extended memory controllers are controlled to perform data read and write operations in parallel.

2. The data reading and writing method according to claim 1, wherein: In a case where the data read / write request is a data write sub-request, the address decoding module is used to parse the local command to determine the location information for data read / write, including: The local command is parsed by the address decoding module to determine the logical starting address, data length and data content for data writing.

3. The data reading and writing method according to claim 2, wherein: The request decomposition module generates a plurality of data read and write sub-requests based on the location information, including: Determining the number of write times for data writing according to the data length in the position information; Determining a target amount of target extended memory for data writing according to the number of write times and the total amount of extended memory; Determining each target extended memory for data writing according to the logical starting address and the target quantity; According to the write count and the target extended memories, a plurality of write data sub-requests with positioning identifiers, the same number as the write count, are generated, wherein the positioning identifier is used to determine the target extended memory controller to which the write data sub-request is sent.

4. The data reading and writing method according to claim 3, wherein: Determining, according to the logical start address and the target quantity, respective target extended memories for data writing, including: According to the logical starting address, determining the extended memory corresponding to the logical starting address as the target extended memory; According to the idleness of each extended memory and the target quantity, a plurality of extended memories with higher idleness are determined as target extended memories, so as to obtain the target quantity of target extended memories.

5. The data reading and writing method according to claim 3, characterized in that: Generating, according to the number of write times and the respective target extended memories, a plurality of write data sub-requests with positioning identifiers, the same number as the number of write times, including: Determining the number of write data sub-requests corresponding to each target extended memory according to the number of write times and the target number; determining, in the target extended memory, a plurality of logical start addresses equal to the number of write data sub-requests corresponding to the target extended memory and a single data write amount according to the number of write data sub-requests corresponding to the target extended memory; According to all the determined logical start addresses and the single data writing amount, a plurality of data writing sub-requests with positioning identifiers are generated, the number of which is the same as the number of writing times.

6. The data reading and writing method according to claim 3, characterized in that: The method includes sending the multiple data read and write sub-requests to each target extended memory controller through the request allocation module, including: The request allocation module sends the multiple write data sub-requests to their corresponding target extended memory controllers respectively according to the respective positioning identifiers of the multiple write data sub-requests.

7. The data reading and writing method according to claim 6, characterized in that: The method includes sending the plurality of write data sub-requests to their respective corresponding target extended memory controllers through the request allocation module according to the respective positioning identifiers of the plurality of write data sub-requests, including: sending the plurality of write data sub-requests to the command queues of the respective corresponding target extended memory controllers through the request allocation module according to the respective positioning identifiers of the plurality of write data sub-requests; When all write data sub-requests are sent, each target extended memory controller is notified to read the write data sub-requests in the respective command queues.

8. The data reading and writing method according to claim 3, characterized in that: The method further comprises: According to the number of write times, the data content is divided into a plurality of data segments whose number is the same as the number of write times; According to the determined target extended memories, the multiple data fragments are cyclically stored in the respective buffer areas of the target extended memories in sequence.

9. The data reading and writing method according to claim 8, characterized in that: Controlling the target extended memory controllers to perform data read and write operations in parallel according to the multiple data read and write sub-requests includes: Controlling each target extended memory controller to obtain write data sub-requests in the respective command queues in parallel; According to the acquired write data sub-requests in the respective command queues, the target extended memory controllers are controlled to perform write operations on the corresponding data segments in the corresponding cache areas in parallel.

10. The data reading and writing method according to claim 3, wherein: Determining the number of write times for data writing according to the data length in the location information includes: Determining a single data write amount according to the data length in the position information; The number of times data is written is determined according to the data length in the position information and the single data writing amount.

11. The data reading and writing method according to claim 3, wherein: Determining a target amount of target extended memory for writing data according to the number of writes and the total amount of extended memory includes: Determining the relationship between the number of writes and the total amount of extended memory; In a case where the number of write times is greater than or equal to the total number, determining the target number of target extended memories for data writing to be the total number of all extended memories; When the number of write times is less than the total number, the target number of target extended memories for data writing is determined to be equal to the number of write times.

12. The data reading and writing method according to claim 1, wherein: In a case where the data read / write request is a data read sub-request, the address decoding module performs command parsing on the local command to determine location information for data reading / writing, including: The local command is parsed by the address decoding module to determine the logical starting address and data length for data reading.

13. The data reading and writing method according to claim 12, characterized in that: The request decomposition module generates a plurality of data read and write sub-requests based on the location information, including: Determining, according to the logical starting address and the data length, first logical starting addresses and first data lengths of all data fragments included in the data to be read; A plurality of read data sub-requests with positioning identifiers are generated according to the first logical starting addresses and data lengths of all the data fragments, wherein the positioning identifier is used to determine the target extended memory controller to which the read data sub-requests are sent.

14. The data reading and writing method according to claim 13, wherein: The method further comprises: Determining target extended memories for data reading according to first logical start addresses of all data fragments; The step of sending the plurality of data read and write sub-requests to each target extended memory controller through the request allocation module includes: The request allocation module sends the multiple read data sub-requests to their corresponding target extended memory controllers respectively according to the respective positioning identifiers of the multiple read data sub-requests.

15. The data reading and writing method according to claim 14, characterized in that: The method includes sending the plurality of read data sub-requests to their respective corresponding target extended memory controllers through the request allocation module according to the respective positioning identifiers of the plurality of read data sub-requests, including: sending the plurality of read data sub-requests to the command queues of the respective corresponding target extended memory controllers through the request allocation module according to the respective positioning identifiers of the plurality of read data sub-requests; When all read data sub-requests are sent, each target extended memory controller is notified to read the read data sub-requests in the respective command queues.

16. The data reading and writing method according to claim 13, characterized in that: Controlling the target extended memory controllers to perform data read and write operations in parallel according to the multiple data read and write sub-requests includes: Control each target extended memory controller to obtain read data sub-requests in its own command queue in parallel; Controlling the target extended memory controllers to execute read operations on the corresponding target extended memories in parallel according to the obtained read data sub-requests in the respective command queues, and storing the read data in the corresponding buffer areas; After all data read operations are completed, all read data fragments are sorted and packaged based on the order in which the read data fragments form the target data to obtain the target data; The target data is sent to the CPU.

17. A data reading and writing system, characterized in that: The system includes: a CPU, a logic management controller, an extended memory controller and an extended memory, wherein the logic management controller includes a request parsing module, an address decoding module, a request decomposition module and a request allocation module; The CPU is configured to initiate a data read and write request for target data; The request parsing module is configured to parse the received data read and write request for the target data to obtain a local command; The address decoding module is configured to parse the local command and determine the location information for data reading and writing; The request decomposition module is configured to generate a plurality of data read and write sub-requests according to the location information; The request allocation module is configured to send the multiple data read and write sub-requests to each target extended memory controller; Each target extended memory controller in the extended memory controller is configured to control the corresponding target extended memory to perform corresponding data read and write operations in parallel according to the data read and write sub-requests received by the respective target extended memory controllers.

18. The data reading and writing system according to claim 17, characterized in that: The logic management controller includes: The data synthesis module is used to sort and package all the read data fragments based on the order in which the read data fragments compose the target data after all data reading operations are completed, obtain the target data, and send the target data to the CPU.

19. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and running on the processor, wherein when the computer program is executed by the processor, the steps in a data reading and writing method according to any one of claims 1 to 16 are implemented.

20. A computer-readable non-volatile storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the data reading and writing method according to any one of claims 1 to 16 are implemented.

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