LDPC code-based communication method and communication apparatus

Abstract

An LDPC code-based communication method and communication apparatus. Encoding or decoding can be performed on the basis of a first split sequence and a first LDPC storage matrix. The first split sequence is one sequence among a plurality of split sequences, and the first LDPC storage matrix is a matrix corresponding to the first split sequence among a plurality of LDPC storage matrices. The plurality of LDPC storage matrices are in one-to-one correspondence to the plurality of split sequences, one element among x elements corresponds to one row in the first LDPC storage matrix, the first split sequence θ comprises the x elements, and the value of an i-th element among the x elements is θ(i). According to the communication method, a plurality of sequences are designed on the basis of a split LDPC code, and optimal matrices supporting different code rates are generated on the basis of the plurality of split sequences, thereby mitigating the problem of non-optimum of decoding thresholds.

Description

Communication method and communication device based on LDPC code

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 5, 2024, with application number 202410168738.2 and application name “Communication method and communication device based on LDPC code”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. In current LDPC codes, when using the check matrix, the first X rows and Y columns of the check matrix are truncated. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. While the nested form of new radio (NR) LDPC codes can support flexible code rates, it cannot achieve uniformly optimal decoding thresholds for all code rates. In other words, each low-code rate expansion pursues the current local optimal decoding threshold, failing to achieve a global optimum. Summary of the Invention

[0004] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which can improve the problem of non-optimal decoding threshold.

[0005] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0006] The method includes: obtaining an information bit sequence; selecting a first split sequence θ from a plurality of split sequences, the first split sequence θ including x elements, where x is a positive integer; determining a first LDPC storage matrix corresponding to the first split sequence from a plurality of LDPC storage matrices based on the first split sequence, wherein the plurality of LDPC storage matrices correspond one-to-one to the plurality of split sequences, and one of the x elements corresponds to a row in the first LDPC storage matrix; performing LDPC encoding on the information bit sequence according to the first split sequence and the first LDPC storage matrix to obtain an LDPC codeword sequence; and transmitting the LDPC codeword sequence.

[0007] In the above technical solution, multiple split sequences correspond one-to-one to multiple storage matrices. Based on different split sequences and corresponding storage matrices, multiple optimal basis matrices (or check matrices) compatible with different code rates can be generated. In this way, the transmitting device can select a suitable split sequence based on the code rate required for encoding, thereby improving the current situation where it is impossible to achieve optimal decoding thresholds for each code rate.

[0008] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0009] The method includes: receiving an LDPC codeword sequence; performing LDPC decoding on the LDPC codeword sequence according to a first split sequence θ and a first LDPC storage matrix to obtain an information bit sequence, wherein the first split sequence is a sequence of multiple split sequences, and the first LDPC storage matrix is ​​a matrix corresponding to the first split sequence among multiple LDPC storage matrices, wherein the multiple LDPC storage matrices correspond one-to-one to the multiple split sequences, and the first split sequence θ includes x elements, x is a positive integer, and one element of the x elements corresponds to a row in the first LDPC storage matrix.

[0010] For the beneficial effects of the second aspect, please refer to the description of the first aspect and will not be repeated here.

[0011] In certain implementations of the first and second aspects, the remaining elements of the x elements except the first type of 0 elements are composed of t+1 groups of elements in sequence, the 0th group of elements includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, and the lth group of elements includes the position numbers of all elements in the 0th group to the l-1th group in the first split sequence, wherein the first type of 0 elements are all 0 elements after the first non-0 element in the x elements, and the second type of 0 elements are all 0 elements before the first non-0 element, 1≤l≤t, and l, t, and M are all positive integers.

[0012] In certain implementations of the first and second aspects, the x elements do not include the first type 0 element, the position number of the first element in the first split sequence is 1, and the elements of the first group include values ​​1 to M*2 l-1 .

[0013] In certain implementations of the first and second aspects, the remaining elements in the x elements except the first type of 0 elements include L+1 element sets, the 0th element set includes the 0th group of elements, the 0th group of elements includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, the nth element set includes the tth n-1 +1 group of elements to tth nGroup elements, where n = 1, t n-1 =0, and the first group of elements includes the position numbers of M zero elements in the first split sequence, the l+1th group of elements in each element set includes the lth group of elements and the M values ​​of the 2M values ​​corresponding to the position numbers of the M elements in the lth group of elements in the first split sequence, and the position numbers of one element and one element in the lth group of elements have and only have one included in the l+1th group of elements, wherein the first type of zero elements are all zero elements after the first non-zero element in the x element, and the second type of zero elements are all zero elements before the first non-zero element, t n-1 +1≤l<t n , 1≤n≤L, l, n, M, L are all positive integers.

[0014] In certain implementations of the first and second aspects, the ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 or the first index of row θ(i) plus or minus 2 or the first index of row θ(i) plus or minus 3 is U, wherein the value of the i-th element in the x elements is θ(i), 0<U<1, the first region is the region composed of the rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element in the x elements, row i is the row corresponding to any non-zero element from the first non-zero element to the last element in the x elements, the first index of row θ(i) is related to |N(θ(i))|, |N(θ(i))| is the number of 1s contained in the core column of the first LDPC storage matrix corresponding to row θ(i) or the number of 1s contained in all columns of the corresponding first LDPC storage matrix.

[0015] In certain implementations of the first and second aspects, U is equal to 1 / 2, or 1 / 3, or 2 / 3, or 1 / 4, or 3 / 4.

[0016] In certain implementations of the first and second aspects, the first index of row θ(i) is further related to δ i (θ(i)) and / or γ i (θ(i)) is related, where δ i (θ(i)) is the sum of the number of 1s in all rows in the first set that satisfy the first condition, γ i (θ(i)) is the number of rows in the first set that satisfy the first condition, where the first set includes rows θ(i)+1 to row i-1 in the first LDPC storage matrix, and the first condition is that the value of the kth element of the first split sequence corresponding to row k in the first set is θ(k)=θ(i).

[0017] In certain implementations of the first and second aspects, the first index of row θ(i) is equal to |N(θ(i))|, or the first index of row θ(i) is equal to |N(θ(i))|-δ i (θ(i))+γ i (θ(i)), or the first index of row θ(i) is equal to |N(θ(i))|-δ i (θ(i)).

[0018] In certain implementations of the first and second aspects, the ratio U of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus 1 or the first index of row θ(i) minus 1 is 1 / 2, the first region is a region consisting of the rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element in the x elements, row i is the row corresponding to any non-zero element from the first non-zero element to the last element in the x elements, the first index of row θ(i) is related to |N(θ(i))|, |N(θ(i))| is the number of 1s contained in the core column of the first LDPC storage matrix corresponding to row θ(i) or the number of 1s contained in all columns of the corresponding first LDPC storage matrix.

[0019] In certain implementations of the first and second aspects, the lth group of elements includes the i-th element θ(i) in the x elements, and the ratio of the row weight of row i in the first region of the first LDPC memory matrix to the first index of row θ(i) or the first index of row θ(i) plus 1 or the first index of row θ(i) minus 1 is or The first region is a region consisting of the rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element in the x elements, and the row i is the row corresponding to any non-zero element from the first non-zero element to the last element in the x elements. The first index of the row θ(i) is related to |N(θ(i))|, and |N(θ(i))| is the number of 1s in the core column of the first LDPC storage matrix corresponding to the row θ(i) or the number of 1s in all columns of the corresponding first LDPC storage matrix. If Then the elements included in the l+1th group of elements are numerical values ​​i, otherwise, the elements included in the l+1th group of elements are numerical values ​​θ(i).

[0020] In certain implementations of the first and second aspects, selecting a first split sequence from a plurality of split sequences includes: selecting a first split sequence from a plurality of split sequences based on the encoding code rate and a first corresponding relationship, wherein the first corresponding relationship is that a plurality of row number intervals correspond one-to-one to a plurality of split sequences, the row number threshold corresponding to each split sequence in the plurality of split sequences is included in the corresponding row number interval, the number of matrix rows x required for encoding is included in the row number interval corresponding to the first split sequence, and the number of matrix rows x required for encoding is determined based on the encoding code rate.

[0021] In certain implementations of the first and second aspects, the row number interval corresponding to the first split sequence is (a k ,b k ), the row number thresholds corresponding to the first split sequence are x1 to x1 in ascending order. n , then a k or b k is (x i +x i+1 ) / 2, (x i +x i+1 ) / 2, or or One of rounding up or rounding down, where 1≤i≤n-1, and i is an integer.

[0022] In certain implementations of the first and second aspects, the multiple row number intervals include 2 row number intervals, and the multiple splitting sequences include 2 splitting sequences, wherein one of the 2 row number intervals includes an interval less than a first threshold, and the other row number interval includes an interval greater than the first threshold.

[0023] In certain implementations of the first and second aspects, the multiple row number intervals are continuous row number intervals or discontinuous row number intervals.

[0024] When the row number range is continuous, the expression is concise and the screening principle is kept as simple as possible, reducing additional hardware complexity. When the row number range is discontinuous, it is more consistent with the optimal range of multiple sequences, and the optimal range of each sequence is itself discontinuous.

[0025] In certain implementations of the first and second aspects, any matrix among the multiple LDPC storage matrices includes a first region and a second region, wherein the multiple LDPC storage matrices correspond to the same second region, and the multiple LDPC storage matrices correspond to different first regions, wherein the first region of the first LDPC storage matrix is ​​a region consisting of rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element among the x elements, and the second region of the first LDPC storage matrix is ​​the region remaining in the first LDPC storage matrix except the first region.

[0026] In certain implementations of the first and second aspects, the second region corresponds to a first table, the first table indicates the edge relationship and translation value of the rows of the second region, multiple different first regions correspond to the second table, the second table includes multiple sub-tables, the multiple sub-tables correspond one-to-one to the multiple different first regions, each sub-table in the multiple sub-tables indicates the edge relationship of the rows of the corresponding first region and the identifier of the sub-table, and the identifier of the sub-table is associated with the identifier of the corresponding split sequence.

[0027] In a third aspect, a communication device is provided, configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0028] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0029] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0030] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to perform the method provided by any one of the above aspects or its implementation.

[0031] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0032] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0033] In a fifth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0034] In one implementation, the device further includes the memory.

[0035] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0036] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0037] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0038] In an eighth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0039] In a ninth aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0040] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0041] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0042] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0043] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of a network architecture applicable to an embodiment of the present application.

[0045] FIG2 is a schematic diagram of an LDPC check matrix H.

[0046] FIG3 is a Tanner graph of an LDPC check matrix H.

[0047] FIG4 is a schematic diagram of the structure of a check matrix.

[0048] FIG5 is a schematic diagram of the information transmission process.

[0049] Figure 6 is an example of traditional expansion and split expansion.

[0050] FIG7 is a schematic flowchart of a communication method 700 based on LDPC codes provided in this application.

[0051] FIG8 is a schematic diagram of the ratio U of child nodes to parent nodes proposed in this application.

[0052] FIG9 is a schematic diagram of splitting the first split sequence and the first LDPC storage matrix based on the form 1 proposed in this application.

[0053] FIG10 is a schematic diagram of a parent node splitting method proposed in this application.

[0054] FIG11 is a schematic diagram of splitting the first split sequence and the first LDPC storage matrix based on the second form proposed in this application.

[0055] FIG12 is a schematic diagram of another parent node splitting method proposed in this application.

[0056] FIG13 is a performance simulation diagram provided by an embodiment of the present application.

[0057] FIG14 is a schematic structural diagram of a device provided in an embodiment of the present application.

[0058] FIG15 is another schematic structural diagram of the device provided in an embodiment of the present application.

[0059] FIG16 is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0061] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various numerical numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. This application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the communication field, for example, it may include the Long Term Evolution (LTE) protocol, the NR protocol and related protocols used in future communication systems. This application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be construed as being preferred or advantageous over other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "a plurality" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0062] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0063] A communication system to which the embodiments of the present application can be applied is described below.

[0064] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0065] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0066] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of the present application. As shown in Figure 1, the embodiment of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0067] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0068] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0069] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0070] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0071] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, an URLLC (Ultra Reliable Low Latency Communication) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0072] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0073] 1. LDPC Code

[0074] LDPC codes are linear block codes that divide the information sequence to be encoded into groups of q bits. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits and the m parity bits are then combined to form a codeword of length n = q + m. The mapping from q information bits to codewords of length n is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0075] The LDPC parity check matrix H is a sparse matrix. The number of zero elements in H is far greater than the number of nonzero elements. In other words, the row weight (or column weight) of the parity check matrix is ​​much smaller than the number of elements in each row (or column) of the LDPC matrix. An LDPC code with an information bit sequence length equal to q and a code length equal to n can be uniquely determined by its parity check matrix H.

[0076] In 1981, Tanner represented the check matrix H using a graph. This type of graph is now called a Tanner graph, and there is a one-to-one correspondence between a Tanner graph and a check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is a check node, representing a check constraint. Each check node represents a check constraint. This is explained below with reference to Figures 2 and 3.

[0077] FIG2 is a schematic diagram of an LDPC check matrix H.

[0078] In Figure 2, {V i} represents the variable node (VN) set, {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 2, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0079] FIG3 is a Tanner graph of an LDPC check matrix H.

[0080] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle has one vertex in this group as both its starting and ending point, and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as its size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which in turn corresponds to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, which in turn corresponds to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. The connection between the check node and the variable node can also be described as: there is a connection or edge between the check node and the variable node. The edge relationship between the check node and the variable node can include two situations: the existence of an edge or the absence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes and edges connected end to end.

[0081] 2. QC-LDPC Code

[0082] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the parity check matrix H of the LDPC code will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by an exponential matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called QC blocks.

[0083] Based on the exponential matrix H b And the improvement value Z c (lifting size), the exponential matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0084] For example, the exponential matrix H of the QC-LDPC code b As shown below:

[0085] It can be seen that the exponential matrix H b The size of the exponential matrix H is 4 rows and 24 columns. b Each element in represents a Z c square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0086] For example, As shown below:

[0087] Optional, exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0088] For example, the above index matrix can be called a basegraph (BG).

[0089] For example, the BG may be a graph of the same size as the exponential matrix, but the BG is a graph in which positions greater than or equal to 0 in the exponential matrix are changed to 1, and positions -1 are changed to 0. The 1s in the BG are expanded into a cyclic shift matrix based on the corresponding exponential matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After the expansion is completed, a check matrix is ​​obtained.

[0090] Currently, NR LDPC codes involve multiple basegraph selections, with the standard storing two basegraphs: BG1 and BG2. BG2 is used when the message length is less than or equal to 292 characters, or when the message length is less than or equal to 3824 characters and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25. Otherwise, BG1 is used.

[0091] 3. Non-zero elements and zero elements

[0092] In the check matrix, a zero element indicates that there is no connection between the variable node and the check node, and a non-zero element indicates that there is a connection between the variable node and the check node.

[0093] In the LDPC index matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The circulant permutation matrix of the identity matrix of order , where the values ​​of the non-zero elements represent the circulant shift values ​​or offset values ​​(shifting value) relative to the identity matrix.

[0094] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the check matrix H shown in Figure 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, the exponential matrix H described above b In the , "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0095] For the convenience of description, "0" is used below to represent a zero element and "1" is used to represent a non-zero element.

[0096] 4. Column weight and row weight

[0097] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in that column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in that row. For example, as shown in Figure 2, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4.

[0098] It can be understood that the matrix involved in the description of row weight and column weight is the check matrix H.

[0099] 5. Structure of the check matrix

[0100] FIG4 is a schematic diagram of the structure of a check matrix.

[0101] As shown in Figure 4 (a), the parity check matrix may include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region may include parts A and B, as shown in Figure 4 (b). Part A corresponds to information bits (also known as information bits, systematic bits, etc.), and part B is a square matrix corresponding to core parity bits (also known as core check bits). The core check bits may be the check bits corresponding to the highest code rate, or may be checks with degrees greater than or equal to 2, or may be check nodes corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). The all-zero region may correspond to part C in Figure 4 (b), an all-zero matrix. The incremental redundancy region may correspond to part D in Figure 4 (b). The raptor-like region may correspond to part E in Figure 4 (b), a unit matrix corresponding to the parity bits for low-rate extension.

[0102] The parity check matrix of the LDPC code shown in Figure 4 employs a "raptor-like" structure, allowing for gradual expansion to lower code rates using a high-rate core matrix. In practice, as shown in Figure 4 (a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the matrix area used also expands.

[0103] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0104] 6. Information column and check column

[0105] The columns of the LDPC basis matrix consist of information columns and check columns.

[0106] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0107] Parity column: Corresponds to the parity bit (or check digit). It can include a core parity column and an extended parity column. The core parity column corresponds to part B, and the extended parity column corresponds to part C or part E. The extended parity column is also called a raptor-like column. The extended parity column corresponds to the extended node.

[0108] 7. Expand verification rows and expand areas

[0109] Extended validation row: the row corresponding to the raptor-like column.

[0110] Extension region: can include extended check rows and all rows of the LDPC basis matrix.

[0111] 8. Core rows, core columns, core matrices, and core check columns

[0112] Core rows: The core rows of the LDPC matrix are the rows corresponding to the core parity bits. In other words, the core rows are the rows corresponding to the high-rate region, or the rows corresponding to Part A, Part B, or Part C.

[0113] Core columns: This includes all information columns and all core check columns. In other words, core columns are the columns corresponding to the high bitrate area, or the columns corresponding to part A + part B.

[0114] Kernel Matrix: This is the matrix region consisting of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix, or the portion consisting of Part A and Part B.

[0115] Core parity column: The N columns after the information column in the LDPC basis matrix, where N is equal to the number of rows corresponding to the core row. For example, the information column is 1 to K b column, the core check column is K b +1 to K b +N columns.

[0116] 9. Information transmission process

[0117] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 5 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 5.

[0118] 10. Storage matrix: The scale is the same as the LDPC base matrix. The connection relationship and translation values ​​it represents are similar to the base matrix, but there is correlation between its rows. Based on this correlation, different low-code rate expansion methods may exist.

[0119] It is understood that the storage matrix is ​​a predefined or pre-stored matrix, and the storage matrix may also be referred to as an LDPC storage matrix or an LDPC matrix or a matrix. This application does not specifically limit the name of the storage matrix.

[0120] 11. Code length, message length, and code rate

[0121] The information length is the length of the information bit sequence to be sent (i.e. the number of bits contained). This length can be the length of the payload information bits, or the length of the payload information bits after adding the cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0122] The code length refers to the length of the codeword sequence after the information bit sequence to be sent is encoded.

[0123] The code rate refers to the ratio of the length of the information bit sequence to be sent to the length of the encoded codeword sequence.

[0124] Optionally, the above three values ​​may be pre-configured by higher layer signaling, a media access control (MAC) layer, or a downlink physical layer signal, and may also be directly obtained or calculated by the transceiver. For example, the code length may be determined by the frame structure, number of layers, and modulation scheme of the coded and transmitted information bit sequence, or may be given in a modulation and coding scheme (MCS) table.

[0125] 12. Traditional expansion and split expansion

[0126] Traditional expansion: also known as normal expansion, refers to a low-code rate expansion method based on the traditional method. In this method, the rows of the storage matrix are read as the rows of the LDPC basis matrix.

[0127] Split-and-expand: Unlike traditional expansion, this approach uses a row of the storage matrix as a newly added row of the LDPC base matrix. The newly added row is then used to eliminate a row in the LDPC base matrix preceding the newly added row. The eliminated row and the newly added row are orthogonal, excluding the expanded nodes. Alternatively, the eliminated row is split into the newly added row and the eliminated row; or, the eliminated row and the newly added row are orthogonal, excluding the expanded nodes; or, the eliminated row contains all rows in the newly added row except for the expanded check nodes. The eliminated row can correspond to the parent node, and the newly added row, or the eliminated row, can correspond to the child node.

[0128] Figure 6 shows an example of traditional expansion and split expansion. Figure 6 takes the split expansion of row 2 as an example.

[0129] Figure 6(a) is the matrix before expansion. Figure 6(b) is the matrix after adding a row. The process from Figure 6(a) to Figure 6(b) is a traditional expansion. Figure 6(c) is the matrix after eliminating row 2 using the added row. The process from Figure 6(a) to Figure 6(b) and then to Figure 6(c) is a splitting expansion. The eliminated row and the newly added row are orthogonal, except for the last column.

[0130] As mentioned above, when using the parity check matrix in practice, as shown in Figure 4(a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. Although the nested form of NR LDPC codes can support flexible code rates, it cannot achieve optimal decoding thresholds for all code rates (for example, BG1 prioritizes high code rates, at the expense of performance at medium and low code rates). In other words, each low-code rate expansion pursues the current local optimal decoding threshold, and cannot achieve a global optimality.

[0131] In view of this, the present application provides a communication method and a communication device of LDPC code, which can effectively solve the above technical problems.

[0132] The following describes the method embodiments of the present application.

[0133] Figure 7 is a schematic flow chart of a communication method 700 based on LDPC codes provided in this application. This method 700 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or receiving device itself, or to a device that supports the transmitting device or receiving device to implement the function. For ease of description, the following description will uniformly use the transmitting device and receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device. This method 700 can include the following steps.

[0134] S701: A transmitting device obtains an information bit sequence.

[0135] That is, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0136] For example, the transmitting device obtains the information bit sequence including: the transmitting device performs source encoding on the source symbols to generate the information bit sequence; or, the transmitting device obtains the information bit sequence including: the transmitting device receives the information bit sequence from other communication devices.

[0137] S702: The transmitting end device selects a first split sequence θ from multiple split sequences.

[0138] The first split sequence θ includes x elements, and the value of the i-th element in the x elements is θ(i), where x is a positive integer. For ease of description, the position numbers of the elements in the first split sequence are counted starting from 1 in this application. Therefore, the i-th element indicates that the position number of the element in the first split sequence is i.

[0139] For example, the multiple split sequences may be sequences stored in the transmitting device or sequences predefined by a protocol.

[0140] How the transmitting device selects the first split sequence from multiple split sequences is not described here in detail and will be described in detail later.

[0141] S703: The transmitting end device determines, based on the first split sequence, a first LDPC storage matrix corresponding to the first split sequence from a plurality of LDPC storage matrices, where the plurality of LDPC storage matrices correspond one-to-one to the plurality of split matrices.

[0142] One of the x elements in the first split sequence corresponds to a row in the first LDPC memory matrix. It can be understood that the rows of the first LDPC memory matrix correspond one-to-one to the elements in the first split sequence, so the number of rows in the first LDPC memory matrix is ​​equal to the length of the first split sequence.

[0143] For example, the multiple LDPC storage matrices may be matrices stored in the transmitting device or matrices predefined by a protocol.

[0144] In the present application, an LDPC base matrix can be obtained based on the first LDPC storage matrix and the first split sequence. The LDPC base matrix is ​​used to perform LDPC encoding on the information bit sequence, that is, the LDPC base matrix is ​​the matrix actually used by the transmitter when performing LDPC encoding. In the process of obtaining the LDPC base matrix, the transmitter device reads the x rows corresponding to the x elements included in the first split sequence from the first LDPC storage matrix according to the x elements. The expansion method of the row corresponding to each element in the x elements is related to the value of the element. The expansion method can be split expansion or traditional expansion. The description of split expansion and traditional expansion can be referred to above and will not be described in detail here.

[0145] For example, the value of the element θ(i) in the first split sequence can be the first character or a positive integer, and the first character is not equal to any positive integer. When the value of θ(i) is a positive integer, the θ(i) is less than i, that is, the value of θ(i) is less than the row number of the current row. The value of the element θ(i) in the first split sequence represents the expansion method of the first LDPC storage matrix. For example, when θ(i) is a positive integer, it means that the i-th row is split and expanded, that is, the i-th row needs to split and expand the θ(i)-th row, where the θ(i)-th row is equivalent to the parent node of the i-th row, and the i-th row is equivalent to the child node of the θ(i)-th row; when θ(i) is the first character, it means that the i-th row is expanded normally.

[0146] For ease of description, the rows of the matrices involved in this application are all counted from row 1, and the columns are all counted from column 1, that is, the first character in this application can be 0. If the rows of the matrix are counted from row 0 and / or the columns are counted from column 0, that is, the first character cannot be 0, and can be other characters, such as -1, -2, etc. The first character can be a number, a letter, or a symbol, etc., which is not limited in this application.

[0147] As an example, in the process of obtaining the LDPC base matrix, the transmitting end device can select the corresponding rows in the first LDPC storage matrix from the first element to the x-th element in sequence for expansion based on the x elements included in the first split sequence. The transmitting end device determines the expansion method of the i-th row based on the value θ(i) of the i-th element being the first character or a positive integer. For example, the fifth element θ(5) in the first split sequence is 3, and the fifth row in the first LDPC storage matrix needs to split and expand the third row, wherein the third row is equivalent to the parent node of the fifth row, and the fifth row is equivalent to the child node of the third row, or the third row can also be called the parent node row of the fifth row, and the fifth row is the child node row of the third row.

[0148] For example, the sequence form of any of the multiple split sequences may be form one or form two. For ease of description, the first split sequence is taken as an example to describe the sequence forms one and two.

[0149] Form 1

[0150] The remaining elements of the x elements of the first split sequence except the first type of 0 elements are composed of t+1 groups of elements in sequence, the 0th group of elements includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, and the lth group of elements includes the position numbers of all elements in the 0th group to the l-1th group in the first split sequence, where 1≤l≤t, and l, t, and M are all positive integers.

[0151] In this application, the first type of 0 elements are all 0 elements after the first non-0 element among the x elements, and the second type of 0 elements are all 0 elements before the first non-0 element among the x elements. The details will not be repeated later.

[0152] It can be understood that the rows corresponding to the second type of 0 elements are core rows.

[0153] It can be understood that the t+1 group of elements in the above-mentioned first split sequence can be obtained after t+1 rounds of splitting. For ease of description, the calculation here starts from the 0th round of splitting. The 0th round of splitting corresponds to the 0th group of elements. The 1st group of elements corresponding to the 1st round of splitting includes the position sequence number of the 0th group of elements in the first split sequence. The 2nd round of splitting corresponds to the position sequence number of all elements included in the 0th group of elements and the 1st group of elements in the first split sequence. The 3rd round of splitting corresponds to the position sequence number of all elements included in the 0th group of elements, the 1st group of elements, and the 2nd group of elements in the first split sequence, and so on. No further details are given here.

[0154] It can also be understood that if the x elements do not include the first type of 0 elements, then the x elements of the first split sequence are composed of t+1 groups of elements in sequence, the 0th group of elements includes the above M 0 elements, the lth group of elements includes values ​​1 to M*2 l-1 In this application, the split sequence with this feature may also be referred to as a complete split sequence.

[0155] For example, the first split sequence is a complete split sequence obtained after 3 (i.e., t+1=3) rounds of splitting, M=5, then the 0th group of elements obtained after the 0th round of splitting is M=5 0 elements, the first group of elements obtained after the 1st round of splitting includes permutations from 1 to 5, for example, {2,4,1,3,5}, the second group of elements obtained after the second round of splitting includes permutations from 1 to 10, for example, {2,4,6,7,8,10,1,3,5,9}, then the first split sequence finally obtained by splitting is {0,0,0,0,0,2,4,1,3,5,2,4,6,7,8,10,1,3,5,9}.

[0156] Form 2

[0157] The remaining elements of the x elements of the first split sequence except the first type of 0 elements include L+1 element sets, the 0th element set includes the 0th group element, the 0th group element includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, and the nth element set includes the tth n-1 +1 group of elements to tth n Group elements, where n = 1, t n-1= 0, and the first group of elements includes the position numbers of M 0 elements in the first split sequence, the l+1th group of elements in each element set includes the lth group of elements and the M values ​​of the 2M values ​​corresponding to the position numbers of the M elements in the lth group of elements in the first split sequence, and the position numbers of one element and one element in the lth group of elements have only one included in the l+1th group of elements, t n-1 +1≤l<t n , 1≤n≤L, l, n, M, L are all positive integers.

[0158] In Example 1, the first element set includes elements from group 1 to group t1, and the second element set includes elements from group t1+1 to group t2. Then, the t1+1th element set includes the position numbers of the 0th element set and any M elements from the 1st element set in the first split sequence. The third element set includes elements from group t2+1 ​​to group t3. Then, the t2+1th element set includes the 0th element set and any M elements from the remaining elements in the 1st element set excluding the t1+1th element set. This is analogous and will not be repeated here.

[0159] Example 2: The first element set includes elements from group 1 to group t1, and the second element set includes elements from group t1+1 to group t2. Then the t1+1 element set includes the position numbers of all elements in the 0th element set and the first element set in the first split sequence. Without loss of generality, the tth element of the nth (n is not equal to 1)th element set is n-1 The +1 group of elements includes the position numbers of all elements in the 0th element set to the n-1th element set in the first split sequence.

[0160] For example, the x elements in the first split sequence can be obtained through multiple rounds of splitting. For ease of description, the calculation starts from the 0th round of splitting. The 0th round of splitting corresponds to the 0th group of elements. The 1st group of elements corresponding to the 1st round of splitting includes the permutation of the position numbers of the 0th group of elements in the first split sequence. The 2nd group of elements corresponding to the 2nd round of splitting includes the 1st group of elements and M elements in the 1st group of elements, and M values ​​in the 2M values ​​corresponding to the position numbers in the first split sequence, and one element A in the 1st group of elements and one and only one position number of element A are included in the 2nd group of elements. The 3rd group of elements corresponding to the 3rd round of splitting includes the 2nd group of elements and M values ​​in the 2M values ​​corresponding to the position numbers in the first split sequence of M elements in the 2nd group of elements, and one element B in the 2nd group of elements and one and only one position number of element B are included in the 3rd group of elements. Afterwards, if based on Example 1, the 4th group of elements corresponding to the 4th round of splitting may include the position numbers of any M elements from the 0th group of elements to the 3rd group of elements in the first splitting sequence, or, based on Example 2, the 4th group of elements corresponding to the 4th round of splitting may include the position numbers of all M elements from the 0th group of elements to the 3rd group of elements in the first splitting sequence.

[0161] It can be understood that the x elements include the 0th element set, the 1st element set, and the 2nd element set, where the 0th element set includes the 0th group of elements, the 1st element set includes the 1st to 3rd group of elements, and the 2nd element set includes the 4th group of elements. It should be noted that the 2nd element set may include multiple groups of elements, and the 4th group of elements is the first group of elements in the 2nd element set.

[0162] For example, the first split sequence is a complete split sequence obtained after 4 (i.e., t+1=4) rounds of splitting, M=5, then the 0th group of elements obtained after the 0th round of splitting is M=5 0 elements, and the first group of elements obtained after the 1st round of splitting includes permutations from 1 to 5, for example {2,4,1,3,5}. In the second round of splitting, it is necessary to select 5 values ​​from the first group of elements {2,4,1,3,5} and the position numbers of the first group of elements in the first split sequence {6,7,8,9,10}, and only one value between 2 and 6 can appear in the second round of splitting. Similarly, only one value in each pair of 4 and 7, 1 and 8, 9 and 3, 10 and 5 can appear in the second round. For example, the second group of elements obtained after the second round of splitting includes {4,6,1,10,3}. Similarly, in the third round of splitting, 5 values ​​need to be selected from the second group of elements {4,6,1,10,3} and the position numbers of the second group of elements in the first split sequence {11,12,13,14,15}, and only one value between 4 and 11 can appear in the third round of splitting. Similarly, only one value in each pair of 6 and 12, 1 and 13, 10 and 14, and 3 and 15 can appear in the third round. For example, the third group of elements obtained after the third round of splitting includes {6,11,3,13,14}, and the first split sequence finally obtained by splitting is {0,0,0,0,0,2,4,1,3,5,4,6,1,10,3,6,11,3,13,14}.

[0163] Optionally, the sequence form of the first split sequence may also be form three, which is a mixture of form one and form two, that is, some splitting rounds are split into form one, and some splitting rounds are split into form two.

[0164] The above introduces the possible sequence forms of the split sequence. The following introduces the matrix characteristics of multiple LDPC storage matrices.

[0165] Any of the multiple LDPC memory matrices corresponding to the multiple split sequences includes a first region and a second region, wherein the multiple LDPC matrices correspond to the same second region and the multiple LDPC matrices correspond to different first regions. The first region of the first LDPC memory matrix is ​​a region consisting of rows of the first LDPC memory matrix corresponding to the first non-zero element to the last element among the x elements, and the second region of the first LDPC memory matrix is ​​a region remaining in the first LDPC memory matrix excluding the first region.

[0166] Optionally, the first region may be the extended region defined above, and the second region may be the remaining region in the first LDPC storage matrix except the first region.

[0167] Optionally, the second region can be defined in the following ways: the first region is the remaining region in the first LDPC storage matrix except the second region. For example, the second region can be obtained by dividing the matrix into blocks, and the second region is a region composed of part A and part B (i.e., the core matrix defined above); or, the second region is determined by a code rate threshold, that is, there is a code rate threshold, and the matrix region corresponding to a code rate greater than / equal to the code rate threshold is the second region, for example, the code rate threshold is 22 / 24, or 44 / 47, or 948 / 1024; or, the second region is obtained based on a matrix row number threshold, and the matrix region corresponding to a row number less than or equal to the threshold is the second region. For example, the second region can be the region corresponding to 1 to 3 rows, or 1 to 4 rows, or 1 to 5 rows, that is, the corresponding row number thresholds are 3, 4, or 5, respectively.

[0168] Taking the first LPDC storage matrix as an example, the characteristics of the first LPDC storage matrix are described by row i (i.e., row i) in the first region of the first LPDC storage matrix and its parent node row θ(i). It can be understood that row i represents the i-th row in the first LDPC storage matrix, which is included in the first region of the first LPDC storage matrix, and the parent node row θ(i) represents the θ(i)-th row stored in the first LDPC storage matrix.

[0169] Wherein, the ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 or the first index of row θ(i) plus or minus 2 or the first index of row θ(i) plus or minus 3 is U, where 0<U<1, row i is the row corresponding to any non-zero element from the first non-zero element to the last element of x elements, and the first index of row θ(i) is associated with |N(θ(i))|, which is the number of 1s in the core column of the first LDPC storage matrix corresponding to row θ(i), or the number of 1s in all columns associated with the first LDPC storage matrix.

[0170] For example, Wherein, y is a positive integer greater than 1, x=1 or x=y-1. For example, U is equal to 1 / 2, or 1 / 3, or 2 / 3, or 1 / 4, or 3 / 4.

[0171] Optionally, the first index of row θ(i) is also related to δ i (θ(i)) and / or γ i (θ(i)) is related, where δ i (θ(i)) is the sum of the number of 1s in the corresponding core columns of all rows in the first set that satisfy the first condition, γ i(θ(i)) is the number of rows in the first set that satisfy the first condition, where the first set includes rows θ(i)+1 to row i-1 in the first LDPC storage matrix, and the first condition is that the value of the kth element of the first split sequence corresponding to row k in the first set is θ(k)=θ(i).

[0172] Several possible definitions of the first index of row θ(i) are given below as examples.

[0173] Definition 1: The first index of a row θ(i) is equal to |N(θ(i))|.

[0174] Definition 2: The first index of row θ(i) is equal to |N(θ(i))|-δ i (θ(i))+γ i (θ(i)).

[0175] Definition 3: The first index of row θ(i) is equal to |N(θ(i))|-δ i (θ(i)).

[0176] It is understood that Definition 1 is applicable to the solution corresponding to the case where the sequence form of the first split sequence is Form 1, which will not be described in detail here. Detailed description will be given later.

[0177] The comparison value U is illustrated below with reference to FIG8 . FIG8 exemplifies the first 12 rows of the first LDPC memory matrix, corresponding to the first 12 elements of the first split sequence {0, 0, 0, 0, 3, 4, 2, 1, 1, 3, 2, 4}. Based on Definition 2 or Definition 3 above, the ratio of the row weight of row i in the solid-line box to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 or the first index of row θ(i) plus or minus 2 or the first index of row θ(i) plus or minus 3 is U = 1 / 3, and the ratio of the row weight of row i in the dashed-line box to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 or the first index of row θ(i) plus or minus 2 or the first index of row θ(i) plus or minus 3 is U = 1 / 2.

[0178] For example, take row 6 in the first region of the first LDPC memory matrix as an example (i.e., row 2 in the solid box), the row weight of row 6 is 13, and the first index based on the definition of 2 rows θ(6)=4 is |N(θ(i))|-δ i (θ(i))+γ i (θ(i))=40-0+0=40, U=13 / (40-1)=1 / 3.

[0179] For example, take row 12 in the first region of the first LDPC memory matrix as an example (i.e., the last row in the dotted box), the row weight of row 12 is 13, and the first index based on the definition of 2 rows θ(12)=4 is |N(θ(i))|-δi (θ(i))+γ i (θ(i))=40-13+1=28, U=13 / (28-2)=1 / 2.

[0180] The above describes the possible sequence forms of the split sequence and the matrix characteristics of multiple LDPC storage matrices. The following describes the matrix characteristics for sequence form one and sequence form two.

[0181] Based on the above sequence form 1, if the first index of row θ(i) is defined by Definition 2 or Definition 3, then the ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 is U = 1 / 2.

[0182] Based on the above sequence form 1, if the first index of row θ(i) is defined by Definition 1, then the ratio of the row weight of row i in the first region of the first LDPC memory matrix to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 is U=1 / 2 k , where k is a positive integer, for example, k is the current splitting round number.

[0183] An example is provided with reference to Figure 9. M = 4, the first 8 elements of the first split sequence are {0, 0, 0, 0, 4, 3, 2, 1}, the number of 1s in rows 1 through 4 of the first 8 rows of the first LDPC storage matrix is ​​40 (or an integer close to 40), in the first round of splitting, the first group of elements of the first split sequence includes {4, 3, 2, 1}, and the ratio of the row weight of row j1 to the first index of row θ(j1) in the first LDPC storage matrix is ​​U = 1 / 2, where 5 ≤ j1 ≤ 8. That is, the number of 1s in rows 5 through 8 of the first LDPC storage matrix is ​​20 (or an integer close to 20). Then, the fifth element θ(5)=4 in the first splitting sequence indicates that the fifth row needs to be split and expanded on the fourth row. Similarly, the sixth element θ(6)=3 in the first splitting sequence indicates that the sixth row needs to be split and expanded on the third row. The seventh element θ(7)=2 in the first splitting sequence indicates that the seventh row needs to be split and expanded on the second row. The eighth element θ(8)=1 in the first splitting sequence indicates that the eighth row needs to be split and expanded on the first row. For the specific splitting process, see Figure 9.

[0184] This is illustrated with reference to Figure 10. Assume that in the current splitting round, a parent node includes 15 1s. Child node #1 splits and expands the parent node. Since U = 1 / 2, child node #1 includes 8 1s, and the parent node includes 7 1s after the split. In the next splitting round, child node #2 splits and expands child node #1. Since U = 1 / 2, the row corresponding to child node #2 includes 4 1s, and child node #1 includes 4 1s after the split. Similarly, child node #3 splits and expands the parent node after the split. Since U = 1 / 2, the row corresponding to child node #3 includes 4 1s, and child node #2 includes 3 1s after the split.

[0185] Based on the above sequence form 2, for the lth group of elements in any element set after the 0th element set among the x elements (for example, the nth element set), they all have the following characteristics: the lth group of elements includes the i-th element θ(i) among the x elements, and the ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus 1 or the first index of row θ(i) minus 1 is or

[0186] For example, n-1 +1=2,t n =4, then when l=2, the corresponding U=1 / 4 or U=3 / 4, when l=3, the corresponding U=1 / 3 or U=2 / 3, and when l=4, the corresponding U=1 / 2.

[0187] It is understandable that if (ie, greater than 1 / 2), the elements included in the l+1th group of elements are values ​​i; otherwise, the elements included in the l+1th group of elements are values ​​θ(i).

[0188] An example is given in conjunction with Figure 11. M=4, the first 12 elements of the first split sequence are {0,0,0,0,3,4,2,1,1,3,2,4}, the number of 1s in the 1st to 4th rows of the first LDPC storage matrix is ​​equal to 40 (or an integer close to 40), in the first round of splitting, the first group of elements of the first split sequence includes {3,4,2,1}, the ratio of the row weight of row j1 in the first LDPC storage matrix to the first index of row θ(j1) is U=1 / 3, 5≤j1≤8, that is, the number of 1s in the 5th to 8th rows of the first LDPC storage matrix is ​​13 (or an integer close to 13), then the 5th row in the first split sequence is 13 (or an integer close to 13). The first element θ(5)=3 indicates that the 5th row needs to split and expand the 3rd row. Similarly, the 6th element θ(6)=4 in the first split sequence indicates that the 6th row needs to split and expand the 4th row. The 7th element θ(7)=2 in the first split sequence indicates that the 7th row needs to split and expand the 2nd row. The 8th element θ(8)=1 in the first split sequence indicates that the 8th row needs to split the 1st row. For the specific splitting process, see (a) to (d) in Figure 11. Since U=1 / 3<1 / 2 in the first round of splitting, the second group of elements in the first split sequence includes 4 of the first group of elements. Elements, that is, the second group of elements includes {1,3,2,4}. In the second round of splitting, the ratio of the row weight of row j2 in the first LDPC storage matrix to the first index of row θ(j2) is U=1 / 2, 9≤j2≤12, that is, the number of 1s in the 9th to 12th rows of the first LDPC storage matrix is ​​1 / 2 of the number of 1s in the {1,3,2,4}th row after splitting, 26 (or an integer close to 26), that is, 13 (or an integer close to 13). Then the 9th element θ(9)=1 in the first split sequence means that the 9th row needs to split and expand the 1st row. Similarly, the 10th element θ(1 0)=3 means that the 10th row needs to split and expand the 3rd row, the 11th element θ(11)=2 in the first splitting sequence means that the 11th row needs to split and expand the 2nd row, and the 12th element θ(8)=4 in the first splitting sequence means that the 12th row needs to split and expand the 4th row. For the specific splitting process, please refer to (e) to (h) in Figure 11. It can be seen that after multiple rounds of splitting, the weight of each row i in (h) in Figure 11 is the same, or differs by 1. Then the splitting can be stopped or continued until the required first LDPC storage matrix and the corresponding first splitting sequence are obtained.

[0189] Let's use Figure 12 as an example. As shown in Figure 12 (a), suppose that in the current splitting round, a parent node contains 15 1s. Child node #1 splits and expands the parent node, and U = 1 / 3. Then, child node #1 contains 5 1s, and the parent node contains 10 1s after the split. In the next splitting round, child node #2 splits and expands the parent node after the split. Since U = 1 / 3, the row corresponding to child node #2 contains 5 1s, and the parent node contains 5 1s after two splits. As shown in Figure 12 (b), suppose that in the current splitting round, a parent node contains 15 1s. Child node #1 splits and expands the parent node, and U = 1 / 3. Then, child node #1 contains 10 1s, and the parent node contains 5 1s after the split. In the next splitting round, child node #2 splits and expands the parent node after the split. Since U = 1 / 3, the row corresponding to child node #2 contains 5 1s, and the parent node contains 5 1s after the split.

[0190] In one possible implementation, the rows in (h) of FIG11 can continue to be split, and any M (M=4) rows in (h) of FIG11 are regarded as the original rows to be split, and the above splitting operation is repeated until the selected M rows and the rows introduced in the splitting process are split into rows with the same i weight, or a difference of 1; then, any M (M=4) rows are selected from the remaining rows in (h) of FIG11 except the 4 rows selected last time as the original rows to be split, and the above splitting operation is repeated until the M rows selected this time and the rows introduced in the splitting process are split into rows with the same i weight, or a difference of 1; then, the 4 rows remaining after the last two selections in (h) of FIG11 are regarded as the original rows to be split, and the above splitting operation is repeated until the selected M rows and the rows introduced in the splitting process are split into rows with the same i weight, or a difference of 1.

[0191] In another possible implementation, the rows in (h) in Figure 11 can continue to be split, and the rows in (h) in Figure 11 are regarded as the original rows that need to be split (i.e., M=12), and the above splitting operation is repeated until the 12 rows and the rows introduced in the splitting process are split into rows with the same row weight or a difference of 1 for each row i. After that, the splitting can be stopped or continued until the required first LDPC storage matrix and the corresponding first splitting sequence are obtained.

[0192] S704: The transmitting end device performs LDPC encoding on the information bit sequence according to the first split sequence and the first LDPC storage matrix to obtain an LDPC codeword sequence.

[0193] It can be understood that the transmitting device can determine the LDPC base matrix according to the first LDPC storage matrix and the first split sequence, and use the LDPC base matrix to perform LDPC encoding on the information bit sequence to obtain an LDPC codeword sequence.

[0194] S705: The transmitting device sends an LDPC codeword sequence to the receiving device. Correspondingly, the receiving device receives the LDPC codeword sequence from the transmitting device.

[0195] It should be noted that since the LDPC codeword sequence may introduce channel noise signals during the transmission process, the LDPC codeword sequence output or sent by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0196] S706: The receiving end device decodes the LDPC codeword sequence according to the first split sequence and the first LDPC storage matrix.

[0197] The LDCP base matrix used by the receiving device for decoding is the same as the LDCP base matrix used by the transmitting device for encoding, and is determined based on the first split sequence and the first LDPC storage matrix. The relevant characteristics of the LDPC storage matrix and the indicator sequence can be specifically referred to the description on the transmitting device side and will not be described in detail here.

[0198] In one possible implementation, the receiving end and the transmitting end select a first split sequence from multiple split sequences using the same method and then determine a first LDPC memory matrix based on the first split sequence. The method for selecting the first split sequence from multiple split sequences will be described in detail later and will not be elaborated on here.

[0199] In another possible implementation, after selecting the first splitting sequence, the transmitting device sends information about the selected first splitting sequence and / or first LDPC storage matrix to the receiving end, and the receiving end determines the first splitting sequence and the first LDPC storage matrix according to the indicated information.

[0200] The above is a detailed introduction to the communication method based on LDPC codes proposed in this application. The above scheme is based on the design of multiple sequences based on split-LDPC codes, and the optimal matrix design compatible with different code rates through multiple split sequences is used to improve the problem of non-optimal decoding threshold.

[0201] In S702 above, it is described that a first split sequence θ can be selected from multiple split sequences before encoding and decoding. The following describes in detail how to select the first split sequence from multiple split sequences.

[0202] Optionally, different splitting sequences may correspond to different scenarios, and the transmitting device selects a required splitting sequence according to different scenarios.

[0203] Optionally, the protocol contains a predefined table that includes multiple encoding rates R and multiple split sequences, with each rate R corresponding to each split sequence. Optionally, the table also includes multiple matrix row numbers x required for encoding (or the number of matrix rows corresponding to the code length), with each row number x corresponding to each encoding rate R. The transmitting device can then filter based on the rate in the predefined table or by the number of rows.

[0204] Among them, the encoding rate R and the number of matrix rows x required for encoding can satisfy formula (1): Wherein, P is the number of puncturing columns, and K is the length of the information bit sequence to be sent (or called information length). For example, K can be the length of the payload information bits, or the length of the payload information bits after adding CRC check bits.

[0205] For ease of description, the following describes multiple matrix row numbers x required for encoding and multiple splitting sequences according to the number of rows.

[0206] In a specific implementation, the sending end can select a first split sequence from multiple split sequences based on the number of matrix rows x required for encoding and a first corresponding relationship, wherein the first corresponding relationship is that multiple row number intervals correspond one-to-one to multiple split sequences, the row number threshold corresponding to each split sequence in the multiple split sequences is included in the corresponding row number interval, and x is included in the row number interval corresponding to the first split sequence.

[0207] For example, if the maximum number of rows corresponding to the first region of multiple split sequences is M, the row number interval {1,2,…,M} is divided into intervals (a1,b1), (a2,b2),…, (a k ,b k )…, the above intervals correspond to the split sequences θ1, θ2, …θ k ,..., where θ t The corresponding row number threshold is (a t ,b t ). The transmitter can filter the sequence based on the number of matrix rows x required for encoding. If it is in the interval (a t ,b t ), then filter θ t It can be understood that the row number threshold can also be used to obtain the corresponding bit rate threshold based on formula (1).

[0208] It can be understood that the sequences corresponding to different intervals can be the same or different, and this application does not impose any limitation on this.

[0209] It is also understood that the multiple row number intervals can be continuous or discontinuous. When the row number intervals are continuous, the screening method is concise, the screening principle is kept as simple as possible, and additional hardware complexity is reduced. When the row number intervals are discontinuous, it is more consistent with the dominant intervals of multiple sequences, and the optimal interval of each sequence is inherently discontinuous.

[0210] The row number threshold corresponding to the sequence of form 1 can be defined as the number of all elements from the 0th group element to the i-th group element in the first split sequence. The i-th group element is any group of elements in the first split sequence. The row number threshold can be M, 2M..., 2 t M.

[0211] The row number threshold corresponding to the sequence of form 2 can be defined as the number of all elements from the 0th group element to the ith group element in the first split sequence, where the row weights of the first LDPC storage matrix corresponding to all elements from the 0th group element to the ith group element are the same after splitting, or differ by 1. It can be understood that (a1, b1), (a2, b2), ..., (a k ,b k )…, multiple intervals can be non-overlapping. The last value in interval #1 and the first value in interval #2 can be the same or different. Interval #1 and interval #2 are adjacent intervals, and interval #1 comes before interval #2. For example, (a1, b1) can be (1, 5), and (a2, b2) can be (5, 11); or (a1, b1) can be (1, 5), and (a2, b2) can be (7, 11).

[0212] For example, the endpoints of the above intervals can be determined in the following way. k The corresponding at least one row number threshold is x i , sort them in ascending order as x1, x2, ..., then the interval endpoint a k or b k is (x i +x i+1 ) / 2, or or Or the above values ​​are rounded up or down. The advantage of this implementation is that it can maximize the division according to the dominant interval of each sequence, ensuring that the sequence is used in the optimal interval of each sequence and also in intervals with relatively small differences in the number of rows and bit rates. This is a principle based on "distance division".

[0213] In another specific implementation, when the number of matrix rows x required for encoding is greater than or less than a certain threshold (i.e., independent of the fixed interval endpoints described above), a single sequence is used. For example, multiple split sequences are θ1 and θ2. When the number of rows is greater than the predetermined threshold, θ2 is selected; when the number of rows is less than the predetermined threshold, θ1 is selected. When the number of rows is equal to the threshold, either θ1 or θ2 can be selected. This implementation has the advantage of simplicity and uses a single sequence across most bitrate ranges.

[0214] In another specific implementation, except for at least one interval corresponding to a split sequence, the remaining intervals all correspond to the same split sequence. For example, (a1, b1] and (a2, b2] correspond to θ1 and θ2 respectively, and all other intervals correspond to θ3.

[0215] The above describes in detail how to select a suitable split sequence from multiple split sequences. The following describes a standard storage method for possible multiple Split-LDPC sequences.

[0216] Standard storage contents include:

[0217] (1) Multiple split sequences are identified by sequence IDs.

[0218] (2) A first table (table 1) indicates the edge relationships and shifting values ​​(SV) of the rows of the second region of the plurality of split sequences. It can be understood that the first table is a common table corresponding to the plurality of split sequences.

[0219] (3) Multiple different first regions correspond to a second table (table2), the second table including multiple sub-tables, each of the multiple sub-tables corresponding to the multiple different first regions, each of the multiple sub-tables indicating an edge relationship between rows of the corresponding first region and an identifier of the sub-table, the identifier of the sub-table being associated with an identifier of the corresponding split sequence. For example, the association may be that the identifier of the sub-table is the same as the identifier of the corresponding split sequence.

[0220] Then, based on the above-mentioned standard storage content, S703 determines the first LDPC storage matrix corresponding to the first split sequence based on the first split sequence, including: selecting the first sub-table corresponding to the first split sequence from multiple sub-tables of the second table; determining the first LDPC storage matrix based on the connection relationship, translation value, and edge relationship of the rows of the second area indicated by the first table and the first sub-table.

[0221] The following is an example of standard storage content.

[0222] (1) The stored multiple splits are divided into two split sequences, and the two split sequences include sequence #0 and sequence #1, wherein the sequence ID of sequence #1 is 0, and the sequence ID of sequence #1 is 1. The elements contained in the two sequences are shown in Table 1.

[0223] Table 1

[0224] (2) The first table stored is shown in Table 2.

[0225] Table 2

[0226] (3) The second table is stored as shown in Table 3. The subtable corresponding to ID=0 corresponds to split sequence #0, and the subtable corresponding to ID=1 corresponds to split sequence #1. It can be understood that the dominant intervals of split sequences with different IDs are different. The dominant interval corresponding to the sequence with ID=0 is row number 9 or row number 19; the dominant interval corresponding to the sequence with ID=1 is row number 14.

[0227] Table 3

[0228] Based on the above description, a possible encoding process includes the following steps.

[0229] (1) The transmitting end device determines a first split sequence among multiple split sequences according to the scenario and / or the information length and / or the rate matching code length (or the code rate).

[0230] (2) The transmitting end device selects a first sub-table with the same ID as the first split sequence from the multiple sub-tables in the second table according to the ID of the first split sequence.

[0231] (3) The transmitter obtains a base matrix based on the connection relationship and translation value of the rows in the first table, the connection relationship of the rows in the first sub-table, and the first split sequence, and then completes the construction of the check matrix H based on the base matrix.

[0232] (4) The transmitting device encodes the bit sequence to be transmitted according to the check matrix H. When there are more base images, the stored content increases accordingly. The content provided in the embodiments of the present application may be storage content and encoding process only for a specific scenario (such as eMBB+ scenario, high throughput scenario, peak rate scenario, etc.), or it may be storage content and encoding process applicable to multiple communication scenarios defined by the protocol (such as URLLC scenario, etc.).

[0233] FIG13 is a performance simulation diagram of two different split sequences based on the method proposed in this application. The horizontal axis of FIG13 is the coding rate, and the vertical axis is the block error rate (BLER) at 10 -2 It can be seen that different split sequences and expansion methods have their own advantages and disadvantages in different bitrate ranges. Using multiple sequences can always use the optimal matrix degree distribution in each bitrate range, thereby achieving universal performance gains.

[0234] The above describes in detail the method embodiment provided by the present application in conjunction with Figures 7 to 13 , and the following describes the device embodiment of the present application in conjunction with Figures 14 to 16 .

[0235] It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 14 to 16 include hardware structures and / or software modules corresponding to the functions. Those skilled in the art should readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0236] Figures 14 and 15 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0237] As shown in FIG. 14 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0238] When apparatus 10 is used to implement the functions of a transmitting device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as step 705, and processing unit 12 is used to execute the processing steps of the transmitting device, such as steps 701 to 704. When apparatus 10 is used to implement the functions of a receiving device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as step 705, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 706.

[0239] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0240] As shown in FIG15 , apparatus 20 includes a processing circuit 21. Processing circuit 21 is coupled to a memory 23, which is used to store instructions. When apparatus 20 is used to implement the method described above, processing circuit 21 is used to execute the instructions in memory 23 to implement the functions of processing unit 12 described above.

[0241] Optionally, the device 20 further includes a memory 23 .

[0242] Optionally, the apparatus 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It will be appreciated that the transceiver circuit 22 can be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0243] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0244] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and accordingly, the transceiver circuit may be an input / output interface.

[0245] Exemplarily, when apparatus 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to the transmitting device or the receiving device by other devices; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to other devices by the transmitting device or the receiving device.

[0246] 16 is a schematic diagram of a chip system 30 according to an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0247] The logic circuit 31 may be a processing circuit in the chip system 30. The logic circuit 31 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 30 can implement the methods and functions of the various embodiments of the present application. The input / output interface 32 may be an input / output circuit in the chip system 30, outputting information processed by the chip system 30 or inputting data or signaling information to be processed into the chip system 30 for processing.

[0248] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0249] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0250] The present application also provides a communication device, comprising a processing circuit coupled to a memory, the memory being used to store computer programs or instructions and / or data, and the processing circuit being used to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processing circuits. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processing circuit or provided separately.

[0251] The present application also provides a chip including a processing circuit coupled to a memory, the memory being configured to store computer programs or instructions, and the processing circuit being configured to execute the computer programs or instructions stored in the memory to implement the methods performed by the transmitting or receiving device in each of the above method embodiments. The memory may be located within the chip or independently of the chip, external to the chip, without limitation herein.

[0252] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0253] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0254] The present application also provides a communication system, which includes at least one of the transmitting end device or the receiving end device in the above embodiments.

[0255] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0256] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0257] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting device or a receiving device. Of course, the processor and storage medium can also be present in a transmitting device or a receiving device as discrete components.

[0258] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0259] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0260] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: obtaining an information bit sequence; Selecting a first split sequence θ from a plurality of split sequences, where the first split sequence θ includes x elements, where x is a positive integer; Determining, based on the first split sequence, a first LDPC storage matrix corresponding to the first split sequence from a plurality of LDPC storage matrices, wherein the plurality of LDPC storage matrices correspond one-to-one to the plurality of split sequences, and one element of the x elements corresponds to a row in the first LDPC storage matrix; Performing LDPC encoding on the information bit sequence according to the first split sequence and the first LDPC storage matrix to obtain an LDPC codeword sequence; The LDPC codeword sequence is sent.

2. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Receive an LDPC codeword sequence; According to a first split sequence θ and a first LDPC storage matrix, LDPC decoding is performed on the LDPC codeword sequence to obtain an information bit sequence, wherein the first split sequence is a sequence of multiple split sequences, and the first LDPC storage matrix is a matrix corresponding to the first split sequence among multiple LDPC storage matrices, wherein the multiple LDPC storage matrices have a one-to-one correspondence with the multiple split sequences, and the first split sequence θ includes x elements, where x is a positive integer, and one of the x elements corresponds to a row in the first LDPC storage matrix.

3. The method according to claim 1 or 2, characterized in that The remaining elements of the x elements except the first type of 0 elements are composed of t+1 groups of elements in sequence, the 0th group of elements includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, and the lth group of elements includes the position numbers of all elements in the 0th group to the l-1th group in the first split sequence, wherein the first type of 0 elements are all 0 elements after the first non-0 element in the x elements, and the second type of 0 elements are all 0 elements before the first non-0 element, 1≤l≤t, and l, t, and M are all positive integers.

4. The method according to claim 3, characterized in that The x elements do not include the first type 0 element, the position number of the first element in the first split sequence is 1, and the lth group of elements includes values 1 to M*2 l-1 .

5. The method according to claim 1 or 2, characterized in that The remaining elements in the x elements except the first type of 0 elements include L+1 element sets, the 0th element set includes the 0th group of elements, the 0th group of elements includes M 0 elements, the M 0 elements are the second type of 0 elements in the x elements, the nth element set includes the tth n-1 +1 group of elements to tth n Group elements, where n = 1, t n-1 =0, and the first group of elements includes the position numbers of the M zero elements in the first split sequence, the l+1th group of elements in each element set includes the lth group of elements and the M values of the 2M values corresponding to the position numbers of the M elements in the lth group of elements in the first split sequence, and one of the elements in the lth group of elements and the position number of the one element has only one included in the l+1th group of elements, wherein the first type of zero elements are all zero elements after the first non-zero element in the x element, and the second type of zero elements are all zero elements before the first non-zero element, t n-1 +1≤l<t n , 1≤n≤L, and l, n, M, and L are all positive integers.

6. The method according to any one of claims 1 to 5, characterized in that The ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus or minus 1 or the first index of row θ(i) plus or minus 2 or the first index of row θ(i) plus or minus 3 is U, wherein θ(i) is the value of the i-th element in the x elements, 0<U<1, the first region is the region composed of the rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element in the x elements, the row i is the row corresponding to any non-zero element from the first non-zero element to the last element in the x elements, the first index of the row θ(i) is related to |N(θ(i))|, and |N(θ(i))| is the number of 1s contained in the core column of the first LDPC storage matrix corresponding to the row θ(i) or the number of 1s contained in all columns of the corresponding first LDPC storage matrix.

7. The method according to claim 6, characterized in that The U is equal to 1 / 2, or 1 / 3, or 2 / 3, or 1 / 4, or 3 / 4.

8. The method according to claim 6 or 7, characterized in that The first index of the row θ(i) is also related to δ i (θ(i)) and / or γ i (θ(i)) related, where the δ i (θ(i)) is the sum of the number of 1s contained in the corresponding core columns of all rows in the first set that meet the first condition, and the γ i (θ(i)) is the number of rows in the first set that satisfy the first condition, where the first set includes rows θ(i)+1 to row i-1 in the first LDPC storage matrix, and the first condition is that the value θ(k)=θ(i) of the kth element of the first split sequence corresponding to row k in the first set.

9. The method according to claim 8, characterized in that The first index of the row θ(i) is equal to |N(θ(i))|, or, The first index of the row θ(i) is equal to |N(θ(i))|-δ i (θ(i))+γ i (θ(i)), or, The first index of the row θ(i) is equal to |N(θ(i))|-δ i (θ(i)).

10. The method according to any one of claims 3, 4, 6 to 9, characterized in that The ratio U of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus 1 or the first index of row θ(i) minus 1 is 1 / 2, θ(i) is the value of the i-th element in the x elements, the first region is the region composed of the rows of the first LDPC storage matrix corresponding to the first non-0 element to the last element in the x elements, the row i is the row corresponding to any non-0 element from the first non-0 element to the last element in the x elements, the first index of the row θ(i) is related to |N(θ(i))|, and |N(θ(i))| is the number of 1s contained in the core column of the first LDPC storage matrix corresponding to the row θ(i), or the number of 1s contained in all columns of the corresponding first LDPC storage matrix.

11. The method according to any one of claims 5 to 9, characterized in that The lth group of elements includes the i-th element in the x elements, the value of the i-th element is θ(i), and the ratio of the row weight of row i in the first region of the first LDPC storage matrix to the first index of row θ(i) or the first index of row θ(i) plus 1 or the first index of row θ(i) minus 1 is or The first region is a region consisting of rows of the first LDPC storage matrix corresponding to the first non-0 element to the last element of the x elements, the row i is a row corresponding to any non-0 element from the first non-0 element to the last element of the x elements, the first index of the row θ(i) is related to |N(θ(i))|, and the |N(θ(i))| is the number of 1s contained in the core column of the first LDPC storage matrix corresponding to the row θ(i) or the number of 1s contained in all columns of the corresponding first LDPC storage matrix, In t n-1 +1≤l<t n In this case, if Then the elements included in the l+1th group of elements are numerical values i, otherwise, the elements included in the l+1th group of elements are numerical values θ(i).

12. The method according to any one of claims 1 to 11, characterized in that The selecting a first split sequence from a plurality of split sequences includes: The first split sequence is selected from the multiple split sequences based on the encoding bit rate and a first corresponding relationship, wherein the first corresponding relationship is that multiple row number intervals correspond one-to-one to the multiple split sequences, the row number threshold corresponding to each split sequence in the multiple split sequences is included in the corresponding row number interval, the number of matrix rows x required for encoding is included in the row number interval corresponding to the first split sequence, and the number of matrix rows x required for encoding is determined based on the encoding bit rate.

13. The method according to claim 12, characterized in that The row number interval corresponding to the first split sequence is (a k ,b k ), the row number thresholds corresponding to the first split sequence are x1 to x1 in descending order. n , then a k or b k is (x i +x i+1 ) / 2, (x i +x i+1 ) / 2, or or One of rounding up or rounding down, where 1≤i≤n-1, and i is an integer.

14. The method according to claim 12, characterized in that The multiple row number intervals include 2 row number intervals, and the multiple splitting sequences include 2 splitting sequences, wherein one of the two row number intervals includes an interval smaller than a first threshold, and the other row number interval includes an interval larger than the first threshold.

15. The method according to claim 12, characterized in that The multiple line number intervals are continuous line number intervals or discontinuous line number intervals.

16. The method according to any one of claims 1 to 15, characterized in that Any matrix among the multiple LDPC storage matrices includes a first region and a second region, wherein the multiple LDPC storage matrices correspond to the same second region, and the multiple LDPC storage matrices correspond to different first regions, wherein the first region of the first LDPC storage matrix is a region consisting of rows of the first LDPC storage matrix corresponding to the first non-zero element to the last element of the x elements, and the second region of the first LDPC storage matrix is the region remaining in the first LDPC storage matrix except the first region.

17. The method according to claim 16, characterized in that The second area corresponds to a first table, and the first table indicates the edge relationship and translation value of the rows in the second area. The multiple different first regions correspond to a second table, the second table includes multiple sub-tables, the multiple sub-tables correspond one-to-one to the multiple different first regions, each sub-table in the multiple sub-tables indicates the edge relationship of the rows of the corresponding first region and the identifier of the sub-table, and the identifier of the sub-table is associated with the identifier of the corresponding split sequence.

18. A communication device, characterized in that: The method comprises modules or units for executing the method according to any one of claims 1 to 17.

19. A communication device, characterized in that: The method comprises a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method according to any one of claims 1 to 17 through a logic circuit or executing code instructions.

20. The communication device according to claim 19, wherein The communication device is a chip or a chip system.

21. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction. When the computer program or instruction is executed by the communication device, the method according to any one of claims 1 to 17 is implemented.

22. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 17.

23. A communication system, characterized in that: include: A sending end device for executing the method according to any one of claims 1, 3 to 17; A receiving device for executing the method according to any one of claims 2 to 17.

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