Encoding method and related product

Abstract

An encoding method and a related product. The method comprises: obtaining a first check matrix, and encoding a first source bit on the basis of the first check matrix, so as to obtain a first encoded bit; segmenting the first encoded bit on the basis of the first check matrix, so as to obtain at least one second encoded bit; and encoding at least one third encoded bit on the basis of the first check matrix, so as to obtain at least one fourth encoded bit, wherein the at least one second encoded bit includes the at least one third encoded bit. In the solution of the present application, the first source bit is encoded to obtain the first encoded bit, the first encoded bit is segmented, encoded bits obtained by means of segmentation are then encoded, and an information bit and a first check bit of the first encoded bit are both used as information bits and are then encoded, so that the flexibility of design of a first check matrix is improved, and the efficiency of encoding is improved, thereby improving the performance of encoding.

Description

Coding methods and related products

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 8, 2024, with application number 202410177326.5 and invention name “Encoding Method and Related Products”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a coding method and related products. Background Art

[0003] With the sixth generation (6 th With the advent of the fifth generation (6G) mobile communications, real-time high data rate applications such as extended reality (XR), mixed reality (MR), and immersive services have emerged. These emerging services have put forward higher requirements for the peak throughput and area efficiency of codecs, with peak rates even required to reach TeraBytes per second (Tbps). At the same time, the power consumption of decoders is required to be further reduced. Obviously, the fifth generation (5G) th The low-density parity check code (LDPC) and polar code used in 5G (first-generation, 5G) mobile communications cannot meet these extremely high requirements. Therefore, for the next generation of chip channel coding and decoding, technological breakthroughs are needed in two main areas: high-throughput, low-power coding and decoding, and high-reliability coding and decoding. Through new coding designs and low-complexity decoding designs, the goals of the future 6G standard can be achieved.

[0004] Product codes have the potential to achieve high-throughput and low-power encoding and decoding; however, their performance still has much room for improvement.

[0005] Therefore, how to improve encoding performance is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a coding method and related products to improve coding performance.

[0007] In a first aspect, a coding method is provided, comprising: obtaining a first check matrix, encoding first source bits according to the first check matrix to obtain first coding bits; segmenting the first coding bits according to the first check matrix to obtain at least one second coding bit; and encoding at least one third coding bit according to the first check matrix to obtain at least one fourth coding bit, wherein the at least one second coding bit includes the at least one third coding bit.

[0008] In this aspect, by encoding the first source bit to obtain the first coded bit, segmenting the first coded bit, and then encoding the segmented coded bit, the first check matrix used is flexibly designed, which improves the coding efficiency and thus improves the coding performance.

[0009] In combination with the first aspect, in a possible implementation, before segmenting the first coded bits according to the first check matrix, the method also includes: adjusting the length of the first coded bits to obtain adjusted first coded bits; segmenting the first coded bits according to the first check matrix includes: segmenting the adjusted first coded bits according to the first check matrix.

[0010] In this implementation, in order to make the lengths of multiple second coded bits uniform when the first coded bits are subsequently segmented, the length of the first coded bits may be adjusted before the first coded bits are segmented to obtain adjusted first coded bits.

[0011] In combination with the first aspect, in another possible implementation, adjusting the length of the first coded bits includes: filling bits at the beginning, end, and / or middle of the first coded bits.

[0012] In combination with the first aspect, in another possible implementation, before encoding the first source bit according to the first check matrix, the method also includes: adjusting the length of the first source bit to obtain the adjusted first source bit; encoding the first source bit according to the first check matrix includes: encoding the adjusted first source bit according to the first check matrix.

[0013] In this implementation, in order to make the lengths of multiple second coded bits uniform when the first coded bits are subsequently segmented, the length of the first source bits may be adjusted before encoding the first source bits to obtain adjusted first source bits.

[0014] In combination with the first aspect, in another possible implementation, adjusting the length of the first information source bits includes: filling bits at the beginning, end, and / or middle of the first information source bits.

[0015] In combination with the first aspect, in another possible implementation, the first coded bits include information bits and first check bits after encoding the first source bits; the second coded bits include part / all of the information bits and / or part / all of the first check bits.

[0016] In this implementation, all first check bits can be attached to the end of the information bits and then evenly segmented. In this way, the first check bits are all located in the later segments. The format of the obtained second coded bits is as follows:

[0017] In one example, the second coded bits include partial bits of the information bits.

[0018] In another example, the second coded bits include all bits of the information bits.

[0019] In yet another example, the second coded bits include partial bits of the first parity bits.

[0020] In yet another example, the second coded bits include all bits of the first parity bits.

[0021] In yet another example, the second coded bits include partial bits of the information bits and partial bits of the first parity bits.

[0022] In yet another example, the second coded bits include partial bits of the information bits and all bits of the first parity bits.

[0023] First, the first parity bit is evenly divided into k1 segments, and the information bits are also evenly divided into k1 segments, so that the first parity bit is evenly placed at the end of each information bit segment. The format of the obtained second coded bit is as follows:

[0024] In one example, the second coded bits include all the information bits and part of the first check bits.

[0025] In another example, the second coded bits include all bits of the information bits and all bits of the first parity bits.

[0026] In yet another example, the second coded bits include partial bits of the information bits and partial bits of the first parity bits.

[0027] In yet another example, the second coded bits include all bits of the information bits and part of the first parity bits.

[0028] In combination with the first aspect, in another possible implementation, the first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is ​​used to encode the first source bits, and the at least one second check sub-matrix is ​​used to encode the at least one third coded bit.

[0029] In combination with the first aspect, in another possible implementation, the value of at least one second element at the tail of one of the at least one first check submatrices is 0, and the position of the at least one second element corresponds to the at least one first element at the tail of one of the at least one second check submatrixes.

[0030] In this implementation, the matrix characteristics can support flexible redundant bit generation when encoding at least one third coded bit, so that the encoding can support flexible rate adaptation and incremental redundancy hybrid automatic repeat request.

[0031] With reference to the first aspect, in yet another possible implementation, one first syndrome matrix among the at least one first syndrome matrix is ​​obtained by coupling all first syndrome matrices within a first sliding window length.

[0032] In this implementation, a first check sub-matrix in at least one first check matrix is ​​obtained by coupling at least one first check sub-matrix within a first sliding window length, thereby simplifying encoding, reducing hardware complexity, and making decoding more suitable for serial processing. Subsequent coded bits can more easily utilize decoding information of preceding coded bits.

[0033] In combination with the first aspect, in another possible implementation, encoding the first source bit according to the first check matrix to obtain the first coded bit includes: segmenting the first source bit according to the at least one first check matrix to obtain at least one second source bit; encoding the at least one second source bit according to the at least one first check matrix to obtain at least one fifth coded bit; and determining the first coded bit based on the at least one fifth coded bit.

[0034] In this implementation, in order to ensure that the length of at least one second source bit obtained when the adjusted first source bit is subsequently segmented is the same, the length of the first source bit may be adjusted before the first source bit is segmented to obtain the adjusted first source bit.

[0035] With reference to the first aspect, in yet another possible implementation, one of the at least one second syndrome matrix is ​​obtained by coupling all second syndrome matrices within a second sliding window length.

[0036] In this implementation, the second extended matrix can be flexibly trimmed (for example, flexible rate mainly requires different numbers of matrix rows, and the second extended matrix supports trimming from top to bottom to the required size according to different needs without affecting the encoding output). This flexible trimming is an existing 5G technology, and this implementation uses this technology to couple multiple coding bits, so that the encoding result can also support flexible rate changes.

[0037] In combination with the first aspect, in another possible implementation, one of the at least one second check submatrixes includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second check submatrix is ​​aligned with the top of the second extension matrix of the previous second check submatrix of the second check submatrix.

[0038] In combination with the first aspect, in another possible implementation, the method further includes: determining at least one sixth coded bit based on the at least one fourth coded bit.

[0039] In a second aspect, a coding apparatus is provided for implementing the coding method of the first aspect or any one of the implementations of the first aspect. The apparatus may be a transmitting device, a module (e.g., a processor, a chip, or a chip system) applied to the transmitting device, or a logical node, a logical module, or software capable of implementing all or part of the functions of the transmitting device.

[0040] In a possible implementation, the encoding device in the second aspect includes a unit for respectively executing the method in the first aspect or any one implementation of the first aspect.

[0041] Exemplarily, the device includes: an acquisition unit for obtaining a first check matrix; a coding unit for encoding a first source bit according to the first check matrix to obtain a first coded bit; the coding unit is also used to segment the first coded bit according to the first check matrix to obtain at least one second coded bit; and the coding unit is also used to encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit, the at least one second coded bit including the at least one third coded bit.

[0042] Optionally, the device also includes: a first adjustment unit, used to adjust the length of the first coding bit before the coding unit segments the first coding bit according to the first check matrix to obtain the adjusted first coding bit; and the coding unit is also used to segment the adjusted first coding bit according to the first check matrix.

[0043] Optionally, the first adjustment unit is configured to fill bits at the beginning, end and / or middle position of the first coded bits.

[0044] Optionally, the device also includes: a second adjustment unit, used to adjust the length of the first source bit before the encoding unit encodes the first source bit according to the first check matrix to obtain the adjusted first source bit; and the encoding unit is also used to encode the adjusted first source bit according to the first check matrix.

[0045] Optionally, the second adjustment unit is configured to fill bits at the beginning, end and / or middle position of the first source bits.

[0046] Optionally, the first coded bits include information bits and first check bits obtained by encoding the source bits; the second coded bits include part / all of the information bits and / or part / all of the first check bits.

[0047] Optionally, the first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is ​​used to encode the first source bits, and the at least one second check sub-matrix is ​​used to encode the at least one third coded bit.

[0048] Optionally, a value of at least one second element at the tail of one of the at least one first check submatrices is 0, and a position of the at least one second element corresponds to at least one first element at the tail of one of the at least one second check submatrixes.

[0049] Optionally, one first syndrome matrix among the at least one first syndrome matrix is ​​obtained by coupling all first syndrome matrices within the first sliding window length.

[0050] Optionally, the encoding unit is further used to segment the first source bit according to the at least one first check matrix to obtain at least one second source bit; the encoding unit is further used to encode the at least one second source bit according to the at least one first check matrix to obtain at least one fifth coded bit; and the encoding unit is further used to determine the first coded bit based on the at least one fifth coded bit.

[0051] Optionally, one second syndrome matrix in the at least one second syndrome matrix is ​​obtained by coupling all second syndrome matrices within the second sliding window length.

[0052] Optionally, one of the at least one second check submatrix includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second check submatrix is ​​aligned with a top portion of a second extension matrix of a previous second check submatrix of the second check submatrix.

[0053] Optionally, the apparatus further includes: a determining unit, configured to determine at least one sixth coded bit based on the at least one fourth coded bit.

[0054] In another possible implementation, the encoding device in the second aspect includes a processor coupled to a memory; the processor is configured to enable the device to perform the corresponding functions in the above-mentioned encoding method. The memory is coupled to the processor and stores the necessary programs (instructions) and / or data for the device. Optionally, the encoding device may further include a communication interface for enabling communication between the device and other network elements. Optionally, the memory may be located inside or outside the encoding device.

[0055] In another possible implementation, the encoding device in the second aspect includes a processor and a transceiver, the processor being coupled to the transceiver, and the processor being used to execute a computer program or instruction to control the transceiver to receive and send information; when the processor executes the computer program or instruction, the processor is also used to implement the above method through a logic circuit or by executing code instructions. The transceiver may be a transceiver, a transceiver circuit, or an input / output interface, configured to receive signals from encoding devices other than the encoding device and transmit them to the processor, or to send signals from the processor to encoding devices other than the encoding device. When the encoding device is a chip, the transceiver is a transceiver circuit or an input / output interface.

[0056] When the encoding device in the second aspect is a chip, the sending unit may be an output unit, such as an output circuit or a communication interface; the receiving unit may be an input unit, such as an input circuit or a communication interface. When the encoding device is a terminal device, the sending unit may be a transmitter or a transmitter; and the receiving unit may be a receiver or a receiver.

[0057] In a third aspect, a computer-readable storage medium is provided, wherein a computer program or instruction is stored in the computer-readable storage medium. When the computer program or instruction is executed, the methods described in the above aspects are implemented.

[0058] In a fourth aspect, a computer program product comprising instructions is provided, which, when executed on an encoding device, causes the encoding device to execute the methods described in the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic diagram of a communication scenario;

[0060] FIG2 is a schematic diagram of a product code sending bits;

[0061] FIG3 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0062] FIG4 is a flow chart of another encoding method provided in an embodiment of the present application;

[0063] FIG5 is a schematic diagram of an encoding process according to an embodiment of the present application;

[0064] FIG6 is a schematic diagram of a first parity check matrix according to an embodiment of the present application;

[0065] FIG7 is a schematic diagram of an equal-division encoding scheme according to an embodiment of the present application;

[0066] FIG8 is a schematic diagram of an interleaved coding scheme according to an embodiment of the present application;

[0067] FIG9 is a schematic diagram of a flow chart of another encoding method provided in an embodiment of the present application;

[0068] FIG10 is a schematic diagram of another encoding process according to an embodiment of the present application;

[0069] FIG11 is a schematic diagram of another first parity check matrix according to an embodiment of the present application;

[0070] FIG12 is a schematic diagram of another first parity check matrix according to an embodiment of the present application;

[0071] FIG13 is a schematic diagram of a second syndrome matrix according to an embodiment of the present application;

[0072] FIG14 is a schematic diagram of another first parity check matrix according to an embodiment of the present application;

[0073] FIG15 is a schematic diagram of another first parity check matrix according to an embodiment of the present application;

[0074] FIG16 is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0075] FIG17 is a schematic structural diagram of another encoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] The solution of this application is further described below with reference to the accompanying drawings.

[0077] Figure 1 shows a schematic diagram of a possible, non-limiting communication system. As shown in Figure 1 , communication system 1000 includes a radio access network (RAN) 100 and a core network (CN) 200. Communication system 1000 may also include the Internet 300. RAN 100 includes at least one RAN node (e.g., 110a and 110b in Figure 1 , collectively referred to as 110) and at least one terminal device (e.g., 120a-120j in Figure 1 , collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1 ). Terminal device 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wiredly connected to core network 200. The core network devices in core network 200 and RAN node 110 in RAN 100 may be separate physical devices, or they may be a single physical device that integrates core network logical functions and radio access network logical functions.

[0078] The RAN 100 may be a cellular system related to the Third Generation Partnership Project (3GPP), such as a 4G or 5G mobile communication system, or a future-oriented evolutionary system (such as a 6G mobile communication system). The RAN 100 may also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN 100 may also be a communication system that integrates two or more of the above systems.

[0079] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and facilitates wireless access for terminal devices. Multiple RAN nodes 110 in communication system 1000 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal device 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminal device 120j accessing RAN 100 via network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal device. RAN node 110 and terminal device 120 are sometimes referred to as coding devices. For example, network elements 110a and 110b in Figure 1 can be understood as coding devices with base station functionality, and network elements 120a-120j can be understood as coding devices with terminal device functionality.

[0080] In one possible scenario, a RAN node may be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a next-generation base station in a sixth-generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system. A RAN node may be a macro base station (such as 110a in Figure 1 ), a micro base station or an indoor station (such as 110b in Figure 1 ), a relay node or a donor node, or a wireless controller in a CRAN scenario. Alternatively, a RAN node may be a server, a wearable device, a vehicle, or an onboard device. For example, the access network device in vehicle-to-everything (V2X) technology may be a roadside unit (RSU).

[0081] In another possible scenario, multiple RAN nodes assist terminal devices in achieving wireless access, and different RAN nodes respectively implement part of the functions of the base station. For example, the RAN node can be a centralized unit (CU), a distributed unit (DU), a centralized unit-control plane (CU-CP), a centralized unit-user plane (CU-UP), or a radio unit (RU). The CU and DU can be set separately, or they can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0082] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, CU may also be called an open-centralized unit (opern-CU, O-CU), DU may also be called an open-distributed unit (opern-distributed unit, O-DU), CU-CP may also be called an open-centralized unit-control plane (open-central unit-control plane, O-CU-CP), CU-UP may also be called an open-centralized unit-user plane (open-central unit-user plane, O-CU-UP), and RU may also be called an open-radio unit (open-radio unit, O-RU). For convenience of description, this application uses CU, CU-CP, CU-UP, DU and RU as examples for description. Any of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0083] Terminal devices may also be referred to as terminals, user equipment (UE), mobile stations, mobile terminal devices, etc. Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IOT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grid, smart furniture, smart office, smart wearable, smart transportation, smart city, etc. Terminal devices can be mobile phones, tablet computers, computers with wireless transceiver functions, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc. The embodiments of the present application do not limit the device form of the terminal device.

[0084] The communication between the access network device and the terminal device follows a certain protocol layer structure. The protocol layer may include a control plane protocol layer and a user plane protocol layer. The control plane protocol layer may include at least one of the following: a radio resource control (RRC) layer, a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, a media access control (MAC) layer, or a physical (PHY) layer. The user plane protocol layer may include at least one of the following: a service data adaptation protocol (SDAP) layer, a PDCP layer, an RLC layer, a MAC layer, or a physical layer.

[0085] Base stations and terminal devices can be fixed or mobile. They can be deployed on land, indoors or outdoors, handheld or vehicle-mounted; on water; or on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of base stations and terminal devices.

[0086] The roles of base stations and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile base station. To terminal devices 120j accessing the wireless access network 100 via 120i, terminal device 120i is a base station. However, to base station 110a, 120i is a terminal device, meaning that communication between 110a and 120i occurs via a wireless air interface protocol. Of course, communication between 110a and 120i can also occur via a base station-to-base station interface protocol. In this case, 120i is also a base station relative to 110a. Therefore, base stations and terminal devices can be collectively referred to as encoding devices. 110a and 110b in Figure 1 can be referred to as encoding devices with base station functionality, and 120a-120j in Figure 1 can be referred to as encoding devices with terminal functionality.

[0087] In the embodiments of the present application, a base station is also referred to as an access network device. The device used to implement the functions of the access network device can be the access network device; it can also be a device that can support the access network device in implementing the functions, such as a chip system, a hardware circuit, a software module, or a hardware circuit and a software module. The device can be installed in the access network device or used in conjunction with the access network device. In the embodiments of the present application, only the device used to implement the functions of the access network device is used as an example, and the embodiments of the present application are not limited to the solutions of the embodiments of the present application.

[0088] It is understandable that the present application can be applied to access network equipment or terminal equipment.

[0089] It should be understood that the number and type of each device in the communication system shown in Figure 1 are for illustration only, and the present application is not limited to this. In actual applications, the communication system may also include more terminal devices, more access network devices, and other network elements, such as core network devices, and / or network elements for implementing artificial intelligence functions.

[0090] It is understandable that all or part of the functions implemented by one or more of the terminal equipment, access network equipment, core network equipment, or network elements for implementing artificial intelligence functions can be virtualized, that is, implemented by one or more of the proprietary processors or general-purpose processors and the corresponding software modules. Among them, since the terminal equipment and the access network equipment involve interfaces for air interface transmission, the transceiver functions of the interfaces can be implemented by hardware. Core network equipment, such as operation administration and maintenance (OAM) network elements, can be virtualized. Optionally, one or more functions of the virtualized terminal equipment, access network equipment, core network equipment, or network elements for implementing artificial intelligence functions can be implemented by cloud devices, such as cloud devices in over the top (OTT) systems.

[0091] Channel coding is one of the most core technologies in wireless communications. The complete channel coding process includes adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Error correction coding is the most critical component. Its purpose is to ensure that the receiver can automatically correct errors that occur during data transmission by minimizing redundancy overhead. For a given bit error rate (BER), the lower the overhead required, the higher the coding efficiency. Traditional channel coding and decoding generally include linear block codes (such as Hamming codes, Gray codes, error-correcting codes (Bose–Chaudhuri–Hocquenghem (BCH) codes, Reed–Solomon (RS) codes), convolutional codes, and concatenated codes. These codes have different characteristics and performance, and are suitable for different scenarios.

[0092] In the third generation (3 rd generation, 3G) and fourth generation (4 thIn 4G (first-generation) mobile communication systems, concatenated (Turbo) codes, a codec technology defined by the 3GPP standard, are convolutional codes with excellent performance, very close to the Shannon limit. In the 5G mobile communication era, data transmission rates are orders of magnitude higher than those of 4G. Turbo codes, based on serial processing, struggle to effectively support such high-speed data transmission. At the same time, the 5G era has also seen the emergence of more diverse service application scenarios and new requirements for channel coding. For example, massive machine type communication (mMTC) scenarios require smaller data packets, while ultra-reliable low-latency communications (URLLC) scenarios have stringent requirements for encoding and decoding latency and low bit error rates. Therefore, based on the key channel coding requirements of the three major 5G application scenarios, LDPC and Polar codes were ultimately adopted in the 5G standard. Compared to traditional linear block codes and convolutional codes, both codes offer superior performance, very close to the Shannon limit. However, they differ in their applicable scenarios and codec complexity.

[0093] With the advent of 6G, real-time, high-data-rate applications such as XR, MR, and immersive services are emerging commercially. These emerging services place higher demands on peak throughput and area efficiency for codecs, with peak rates reaching even terabits per second, while also requiring further reductions in decoder power consumption. 5G's LDPC and Polar codes clearly cannot meet these extremely demanding requirements. Therefore, for next-generation chip channel codecs, technological breakthroughs are needed in two key areas: high-throughput, low-power codecs, and high-reliability codecs. These breakthroughs will enable the achievement of the future 6G standard through innovative coding and low-complexity decoding designs.

[0094] Aiming for the future 6G standard, product codes have the potential to achieve high-throughput, low-power encoding and decoding. The main idea is that long codes can be constructed using product codes, and upon reception, the highly complex long code can be decoded and converted into multiple shorter component codes for decoding. The main benefits of product codes are reflected in the following two aspects: First, long codes can be constructed without significantly increasing the complexity, and the resulting long codes have better error correction performance than short codes of the same code rate. Second, compared with directly constructing long codes using a single parity check matrix, the decoding complexity (e.g., the number of iterations) of the component codes can be significantly reduced at the same operating point, resulting in higher throughput. Therefore, product codes can be used as an alternative code type for achieving high-throughput, low-power encoding and decoding.

[0095] A two-dimensional product code consists of two component codes and The two-step encoding is often completed by encoding the row component and the column component. When constructing the product code, algebraic codes are often used as component codes. and This type of product code has been widely used.

[0096] Figure 2 shows a schematic diagram of a product code sending bits. For example, consider a binary linear code with code length, information bit length, and the shortest distance (n1, k1, d1) and (n2,k2,d2) binary linear code A two-dimensional product code can be constructed as follows: Arrange the information bits of length k1k2 into a matrix C1 of k1×k2; for each row of C1, Encode and get the matrix C2 of k1×n2; for each column of C2, according to Encode and get the matrix C of n1×n2, which is a matrix composed of and A two-dimensional product code word of length n1n2 is determined, and the code rate of the product code word is k1k2 / n1n2.

[0097] However, the structure of the check matrix of the LDPC-SPC code generated by the above method is relatively fixed, and the performance of the code still has much room for improvement.

[0098] In view of this, the present application provides a coding scheme, which encodes the first source bit to obtain the first coding bit, segments the first coding bit, and then encodes the segmented coding bit. The first check matrix used is flexibly designed, improves the coding efficiency, and thus improves the coding performance.

[0099] The technical solution provided in the embodiment of the present application can be applied to channel coding / decoding between communication devices. Channel coding / decoding between communication devices may include: channel coding / decoding between network devices and terminal devices, channel coding / decoding between network devices and network devices, and channel coding / decoding between terminal devices and terminal devices. Among them, in the embodiment of the present application, the term "channel coding and decoding" can also be referred to as "coding", and the term "coding" can also be described as "channel coding and decoding", "network coding", "external code", and "source-channel joint coding and decoding". The term "coding structure" can also be referred to as "coding", "code type", and "code design", and the term "coding structure" can also be described as "concatenated code", "layered code", "coupled code", "external code", "sliding window code", "product code", and "staircase code".

[0100] Based on the above communication system, the encoding method provided by the embodiment of the present application will be described below:

[0101] As shown in Figure 3, a flowchart of an encoding method provided in an embodiment of the present application is provided. The method is applied to an encoding device, which is any transmitting device, such as a network device or a terminal device. Exemplarily, the method may include the following steps:

[0102] S301. Obtain a first check matrix, and encode first source bits according to the first check matrix to obtain first coded bits.

[0103] Before encoding, the encoding device obtains a first parity check matrix. The encoding device may obtain the first parity check matrix from its own memory or from other devices or equipment.

[0104] After obtaining the first check matrix, the encoding device encodes the first information source bits according to the first check matrix to obtain first coded bits.

[0105] Exemplarily, the encoding device may encode the first source bits according to all or part of the first check matrix to obtain first coded bits.

[0106] S302. Segment the first coded bits according to the first check matrix to obtain at least one second coded bit.

[0107] After obtaining the first coded bit, the coding device further segments the first coded bit according to the first check matrix to obtain at least one second coded bit.

[0108] The length of at least one second coded bit obtained by segmentation may be the same or different.

[0109] S303. Encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit.

[0110] After obtaining at least one second coded bit in segments, the coding device encodes at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit.

[0111] The at least one second coded bit includes at least one third coded bit, that is, the at least one third coded bit is part or all of the at least one second coded bit.

[0112] Existing encoding devices rigidly use LDPC codes and single-bit parity check (SPC) codes, resulting in a fixed structure, high redundancy, and difficulty adjusting the code rate. This embodiment first encodes a first source bit to obtain a first coded bit; then segments the first coded bit and encodes at least one third coded bit obtained from the segmentation. This provides structural flexibility and improves coding flexibility.

[0113] According to a coding method provided in an embodiment of the present application, a first source bit is encoded to obtain a first coding bit, the first coding bit is segmented, and the segmented coding bit is then encoded. The first check matrix used is flexibly designed, which improves coding efficiency and thus improves coding performance.

[0114] In the above embodiment, the length of at least one second coding bit obtained by segmentation can be the same or different. When the length of at least one second coding bit is the same, it is necessary to adjust the length of the first source bit or the first coding bit to be divisible; when the length of at least one second coding bit is different, but the length of at least one second coding bit is set, for example, the lengths of the three second coding bits are set to A, B, and C, it is necessary to adjust the length of the first source bit or the first coding bit so that the lengths of the three second coding bits are A, B, and C. The following description is based on the case where the length of at least one second coding bit is the same:

[0115] As shown in Figure 4, it is a flowchart of another encoding method provided in an embodiment of the present application. Exemplarily, the method may include the following steps:

[0116] S401. Adjust the length of the first signal source bits to obtain adjusted first signal source bits.

[0117] In order to ensure that the lengths of multiple second coded bits obtained when the first coded bits are subsequently segmented are the same, the length of the first source bits may be adjusted before encoding the first source bits to obtain adjusted first source bits.

[0118] As shown in FIG5 , a schematic diagram of an encoding process according to an embodiment of the present application is shown. The length of the first source bit u' is A' bits, which is divided into c coded bits for coupling. The total length of the adjusted first source bit u is A gt =A′+A p .

[0119] Among them, A p There are two ways to do this:

[0120] One way is to fill A′ with bits at the beginning, end and / or middle of the first source bit (for example, p 0), where in, It is understood that making A′ divisible by c is a way to achieve uniform and unified segmentation in the future, and this application does not limit this processing method.

[0121] Another way is to fix A p =0, that is, no processing is performed.

[0122] S402. Obtain a first check matrix, and encode the adjusted first source bits according to the first check matrix to obtain first coded bits.

[0123] After length adjustment is performed on the first information source bits and before encoding the adjusted first information source bits, the encoding device obtains a first check matrix.

[0124] Exemplarily, the encoding apparatus may obtain the first check matrix from its own memory, or obtain the first check matrix from other apparatuses or devices.

[0125] As shown in FIG6 , a schematic diagram of a first check matrix according to an embodiment of the present application is shown. The first check matrix includes at least one first check sub-matrix (H global =[H global,0 H global,1 …H global,c-1 ], FIG6 illustrates that the first check matrix includes c first check sub-matrices) and at least one second check sub-matrix (H local =[H local,0 H local,1 …H local,c -1], FIG6 illustrates that the first parity check matrix includes c second parity sub-matrices).

[0126] The at least one first check sub-matrix has r rows, A′ lt The at least one first check sub-matrix is ​​used to encode the adjusted first signal source bit. For example, the adjusted first signal source bit is linearly block-coded according to the at least one first check sub-matrix to obtain the first coded bit u g0 , the code length before encoding (i.e. the first source bit after adjustment) is A gt , after encoding (i.e. the first encoding bit), the code length is A′ lt =A gt +r.

[0127] S403. Adjust the length of the first coding bit to obtain the adjusted first coding bit.

[0128] In order to ensure that the lengths of multiple second coded bits obtained when the first coded bits are subsequently segmented are the same, the length of the first coded bits may be adjusted before the first coded bits are segmented to obtain adjusted first coded bits.

[0129] Still referring to FIG5, the first coded bit u g0 The code length is Al lt , if A′′t Cannot be divided by c, then in u g0 Fill bits at the beginning, end and / or middle of the p 0), where If A′ lt If it is divisible by c, no addition is made. p = 0. The adjusted sequence (i.e. the adjusted first coded bit) is recorded as u g , length A lt =A′ lt +c p .in, Indicates A′ lt / c rounds down.

[0130] It is understood that both step S403 and step S401 are for the purpose of enabling subsequent uniform and unified segmentation. Length adjustment may be performed before and / or after encoding the first source bits, i.e., only step S401, only step S403, or both step S403 and step S401 may be performed, and this application does not impose any limitation thereto.

[0131] S404. Segment the adjusted first coded bits according to the first check matrix to obtain at least one second coded bit.

[0132] After the encoding device adjusts the length of the first coded bit, the first coded bit u after adjustment is coded according to the first check matrix. g Segmentation is performed to obtain at least one second coded bit, wherein the first coded bit includes an information bit and a first check bit obtained by encoding the adjusted first source bit.

[0133] There are two ways to segment:

[0134] One way is to use u g Divide into c equal segments, each segment is called u l,i (i=0,1,…,c-1), length is A l =A lt / c.

[0135] As shown in FIG7 , it is a schematic diagram of an equal-division coding scheme according to an embodiment of the present application. The total length of the first source bit u is A gt =c(n0-m0)-r, using at least one first check matrix (H global =[H global,0 H global,1 …H global,c-1 ]) Encode the first source bit (or the first source bit after length adjustment) to obtain a first coded bit. The first coded bit u g0 The code length is A′lt =c(n0-m o The first coded bit (or the first coded bit after length adjustment) is segmented to obtain at least one second coded bit.

[0136] As can be seen from Figure 7, all the first check bits are attached to the end of the information bits and then evenly segmented. In this way, the first check bits are all located in the later segments. The format of the obtained second coded bits is as follows:

[0137] In one example, the second coded bits include partial bits of the information bits.

[0138] In another example, the second coded bits include all bits of the information bits.

[0139] In yet another example, the second coded bits include partial bits of the first parity bits.

[0140] In yet another example, the second coded bits include all bits of the first parity bits.

[0141] In yet another example, the second coded bits include partial bits of the information bits and partial bits of the first parity bits.

[0142] In yet another example, the second coded bits include partial bits of the information bits and all bits of the first parity bits.

[0143] The code length of at least one second coding bit is c(n0-m0).

[0144] Another way is to use u g Interleave, the interleaver length is A lt , then divide the interleaved sequence into c segments, each segment is denoted as u l,i (i=0,1,…,c-1), length is A l =A lt / c.

[0145] As shown in FIG8 , a schematic diagram of an interleaved coding scheme according to an embodiment of the present application is shown. First, the first parity bit is evenly divided into k1 segments, and the information bit is also evenly divided into k1 segments, so that the first parity bit is evenly placed at the end of each information bit segment. The format of the obtained second coded bit is as follows:

[0146] In one example, the second coded bits include all the information bits and part of the first check bits.

[0147] In another example, the second coded bits include all bits of the information bits and all bits of the first parity bits.

[0148] In yet another example, the second coded bits include partial bits of the information bits and partial bits of the first parity bits.

[0149] In yet another example, the second coded bits include all bits of the information bits and part of the first parity bits.

[0150] S405. Encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit.

[0151] After segmenting the adjusted first coded bits to obtain at least one second coded bit, encoding the at least one third coded bit according to the first parity check matrix to obtain at least one fourth coded bit, wherein the fourth coded bit includes an information bit and a second parity check bit.

[0152] Specifically, according to at least one second syndrome matrix (H local =[H local,0 H local,1 ...H local,c-1 ]) Encode the at least one third coded bit to obtain at least one fourth coded bit. The at least one second coded bit includes the at least one third coded bit, i.e., the at least one third coded bit is part or all of the at least one second coded bit.

[0153] For example, u l,i (i=0,1,…,c-1) is encoded by linear block code, and A before encoding l bits, the encoded sequence (i.e. the fourth encoded bit) is recorded as x l,i Number of bits n0 = A l +m0.

[0154] Exemplarily, the code rate of the second syndrome matrix can be flexibly changed.

[0155] Still referring to FIG6, the total length of the adjusted first source bit u is After encoding the adjusted first source bit according to the first parity check matrix to obtain the first coded bit, the length of the first coded bit is adjusted, and the adjusted first coded bit is segmented to obtain at least one second coded bit, and at least one third coded bit is encoded according to the first parity check matrix. The length of each second coded bit obtained after segmentation is A l =n0-m0, at least one third coded bit is encoded to obtain at least one fourth coded bit, and the length of each fourth coded bit is n0.

[0156] As can be seen in Figure 6, in at least one first check sub-matrix and at least one second check sub-matrix, at the position corresponding to at least one first element at the tail of the second check sub-matrix, the value of at least one second element at the tail of the first check sub-matrix is ​​zero. This matrix feature can support flexible redundancy bit generation when encoding at least one third coded bit, so that the encoding can support flexible code rate adaptation and incremental redundancy hybrid automatic repeat request (IR-HARQ). This matrix structure feature is only an example and is not limited in this application.

[0157] S406. Determine at least one sixth coded bit based on the at least one fourth coded bit.

[0158] Still referring to FIG5, for example, x l,i Concatenate in the order of i=0,1,…c-1 to get the sequence x l , with a length of n0c.

[0159] According to a coding method provided in an embodiment of the present application, a first source bit is encoded to obtain a first coded bit, and the first coded bit is segmented, and then the segmented coded bit is encoded, and the information bit and the first check bit of the first coded bit are both encoded as information bits, thereby improving the flexibility of the design of the first check matrix, improving the coding efficiency, and thus improving the coding performance; and when encoding the segmented coded bits, flexible code rate adaptation and IR-HARQ retransmission are supported.

[0160] The above embodiment illustrates that linear block coding can be used for encoding. The following embodiment will describe that at least one first check sub-matrix of a sliding window structure can be used to encode the first source bits (or the first source bits after length adjustment) to further improve the encoding performance.

[0161] As shown in Figure 9, a flow chart of another encoding method provided in an embodiment of the present application is provided. Exemplarily, the method may include the following steps:

[0162] S901. Adjust the length of the first signal source bits to obtain adjusted first signal source bits.

[0163] In order to ensure that the length of at least one second source bit segment obtained when the adjusted first source bit is subsequently segmented is the same, the length of the first source bit may be adjusted before segmenting the first source bit to obtain the adjusted first source bit.

[0164] As shown in FIG10 , another encoding process diagram of an embodiment of the present application is shown. The length of the first source bit u' is A' bits, which is divided into c coded bits for coupling. The total length of the adjusted first source bit u is A gt =A′+A p .

[0165] The specific implementation of adjusting the length of the first source bit may refer to step S401 of the embodiment shown in FIG4 , and will not be described in detail here.

[0166] S902. Obtain a first check matrix, and segment the adjusted first signal source bits according to at least one first check sub-matrix to obtain at least one second signal source bit.

[0167] Before encoding, the encoding device obtains a first parity check matrix. The encoding device may obtain the first parity check matrix from its own memory or from other devices or equipment.

[0168] In this embodiment, the first check matrix includes at least one first check matrix and at least one second check matrix. The encoding device segments the adjusted first signal source bits according to the at least one first check matrix to obtain at least one second signal source bit.

[0169] Still referring to Figure 10, the length A gt The sequence (i.e. the first source bit after length adjustment) u is divided into c segments, each segment is denoted as u i (i=0,1,…,c-1), the length of each segment is n0-m0-r.

[0170] S903. Encode at least one second source bit in sequence according to at least one first check sub-matrix to obtain at least one fifth coded bit.

[0171] In this embodiment, one first syndrome matrix in the at least one first syndrome matrix is ​​obtained by coupling all first syndrome matrices within the first sliding window length.

[0172] At least one second information source bit is encoded according to at least one first check sub-matrix to obtain at least one fifth coded bit.

[0173] For example, let the length of the first sliding window be L, then:

[0174] According to the first syndrome matrix H global,0 Encode the second information bit u0 to obtain x g,0 ;

[0175] According to the first syndrome matrix H global,0 ,H global,1 Encode the second information bit u1 to obtain xg,1 ;

[0176] …

[0177] According to the first syndrome matrix H global,j - L+1 ,H global,j - L+2 ,…,H global,j For the second information bit u j Encode to get x g,j (j≥L).

[0178] Among them, for each first check sub-matrix H global,j , the submatrix has r′ rows and (n0-m0) columns.

[0179] When r is divisible by c, r′ can be taken as r / c, that is, each local coding matrix obtains r / c check bits.

[0180] When r cannot be divided by c, a value distribution scheme is: the value of r′ in the first c-1 blocks is in Indicates rounding up, the r′ value of the last block is

[0181] The following are two examples of the first check matrix:

[0182] As shown in FIG11 , it is a schematic diagram of another first check matrix according to an embodiment of the present application. The first check matrix includes at least one first check sub-matrix (H globql =[H gllbal,0 H global,1 …H global,c-1 ]) and at least one second check matrix (H local =[H local,0 H local,1 ...H local,c-1 In this embodiment, the second syndrome matrix may still refer to the above description; the first syndrome matrix is ​​based on at least one first syndrome matrix within the first sliding window length, and its first sliding window length L=2, then:

[0183] According to the first syndrome matrix H global,0 Encode the second information bit u0 to obtain x g,0 ;

[0184] According to the first syndrome matrix H global,j-1 ,H global,j For the second information bit u j Encode to get x g,j (1≤j≤c-1).

[0185] It can be understood that the blocks marked as 0 in FIG11 and the unmarked blank positions are all matrices of all 0s.

[0186] It can be seen that from the first syndrome matrix H global,1 Initially, the two first check sub-matrices have a coupling relationship. This is reflected in at least one first check sub-matrix, each H global,j The matrix is ​​divided into three equal parts from top to bottom, the upper part is in the same row as the previous first syndrome matrix, and the left side of the lower part is all 0. gloobal,1 For example, the two first check sub-matrices (H global,0 、H global,1 ) have a coupling relationship. This is reflected in the global,1 The matrix is ​​divided into three equal parts from top to bottom, the upper part and the lower part, and the upper part is connected to the previous first check sub-matrix (H global,0 、H global,1 ) In the same row, the lower left side is all 0s.

[0187] As shown in FIG12 , it is a schematic diagram of another first check matrix according to an embodiment of the present application. The first check matrix includes at least one first check sub-matrix (H global =[H global,0 H global,1 …H global,c-1 ]) and at least one second syndrome matrix

[0188] (H local =[H local,0 H local,1 …H local,c -1]). In this embodiment, the second syndrome matrix may still refer to the above description; one of the at least one first syndrome matrix is ​​based on all first syndrome matrices within the first sliding window length, and its first sliding window length L=3, then:

[0189] According to the first syndrome matrix H global,0 Encode the second information bit u0 to obtain x g,0 ;

[0190] According to the first syndrome matrix H global,0 ,H global,1 Encode the second information bit u1 to obtain x g,1 ;

[0191] According to the first syndrome matrix H global,j-2 ,H global,j-1 ,H global,j For the second information bit u j Encode to get x g,j (2≤j≤c-1).

[0192] It can be seen that from the first syndrome matrix H global,2 Initially, the three first check sub-matrices have a coupling relationship. This is reflected in at least one first check sub-matrix, each H global,j The matrix is ​​divided into three equal parts from top to bottom: upper, middle, and lower. The upper part is in the same row as the first two first syndrome matrices, the middle part is in the same row as the previous syndrome matrix, and the left side of the lower part is all 0. For example, with H global,2 For example, the three first check sub-matrices (H global,0 、H global,1 、H global,2 ) have a coupling relationship. This is reflected in the global,2 The matrix is ​​divided into three equal parts from top to bottom: upper, middle and lower parts. The upper part is connected with the first two first check sub-matrices (H global,0 、H global,1 ) in the same row, the middle part is the same as the previous check matrix (H global,1 ) In the same row, the lower left side is all 0s.

[0193] S904. Determine a first coded bit according to at least one fifth coded bit.

[0194] Exemplarily, after the encoding device encodes at least one second source bit to obtain at least one fifth encoded bit, it can cascade the at least one fifth encoded bit to obtain the first encoded bit.

[0195] Still referring to FIG10, the encoding device converts x g,j (j=0,1,…,c-1) are arranged in order, and u is obtained. g0 .

[0196] S905. Adjust the length of the first coding bit to obtain the adjusted first coding bit.

[0197] S906. Segment the adjusted first coded bits according to the first check matrix to obtain at least one second coded bit.

[0198] S907. Encode at least one third coded bit according to at least one second syndrome matrix to obtain at least one fourth coded bit.

[0199] S908. Determine at least one sixth coded bit based on the at least one fourth coded bit.

[0200] The specific implementation of the above steps S905-S908 can refer to steps S403-S406 of the embodiment shown in FIG4 , and will not be repeated here.

[0201] According to an encoding method provided by an embodiment of the present application, a first source bit is encoded to obtain a first coded bit, the first coded bit is segmented, and the segmented coded bit is encoded. The first parity check matrix used in the encoding method has a flexible design, which improves coding efficiency and thus improves coding performance. In the first parity check matrix, the first parity check matrix is ​​based on at least one first parity check matrix within a first sliding window length, making encoding simpler, reducing hardware complexity, and making decoding more suitable for serial processing. Subsequent coded bits can more easily utilize decoding information of preceding coded bits.

[0202] The above embodiment describes a first parity check matrix including at least one first parity check matrix and at least one second parity check matrix. In one case, when encoding is performed using the at least one first parity check matrix and the at least one second parity check matrix, both can be encoded using linear block codes. In another case, when encoding is performed using the at least one first parity check matrix, one of the at least one first parity check matrix is ​​based on all first parity check matrices within a first sliding window length, and when encoding is performed using the at least one second parity check matrix, the at least one second parity check matrix can be encoded using a linear block code.

[0203] The following embodiment will describe that when encoding is performed using at least one second syndrome matrix, one second syndrome matrix in the at least one second syndrome matrix may also be obtained by coupling all second syndrome matrices within the second sliding window length.

[0204] The second check sub-matrix is ​​the base matrix of QC-LDPC. As shown in FIG13 , it is a schematic diagram of the second check sub-matrix of the embodiment of the present application. The second check sub-matrix includes the core matrix H core , all-zero matrix H zero , the first expansion matrix H extend1 , diagonal matrix H diag and the second expansion matrix H extend2 .

[0205] Among them, H zero :with H core The same number of rows, located in H core on the right side.

[0206] H extend1 : The row weight (the number of 1s in each row) is smaller than H core The matrix elements are more sparse.

[0207] H diag : Only diagonal elements are '1'. This matrix primarily supports flexible bit rate implementation of LDPC codes and is cropped from the upper left corner to the lower right according to different bit rate requirements.

[0208] H extend2There are two implementation methods. Method 1 is a matrix with smaller row weight, and its characteristics are consistent with the first extended matrix. Method 2 is an all-zero matrix.

[0209] In this embodiment, when encoding at least one third coded bit according to at least one second check sub-matrix to obtain at least one fourth coded bit, the second check sub-matrix adopts a sliding window structure, that is, one second check sub-matrix in the at least one second check sub-matrix is ​​based on all second check sub-matrices within the second sliding window length.

[0210] Different from the embodiment shown in FIG3 or FIG4, when the source bits (or the source bits after length adjustment) are encoded by linear block code, each u l,i The LDPC coding of (i=0, 1, ..., c-1) can be performed independently, where the LDPC coding of each fourth coded bit is related to the current third coded bit and several previous third coded bits.

[0211] The encoding process adopts a sliding window structure, and the length of the second sliding window is L, then:

[0212] u l,0 By H local,0 Perform LDPC code encoding to obtain;

[0213] u l,1 By H local,1 , H local,0 Perform LDPC code encoding to obtain;

[0214] …

[0215] u l,j By H local,j-L+1 , H local,j-L+2 ,H local,j It is obtained by LDPC code encoding.

[0216] The number of check bits obtained after encoding each third coded bit is m0, and the encoding results are recorded as u l,0 (i=0,1,…,c-1).

[0217] The following are two examples of the first check matrix:

[0218] FIG14 is a schematic diagram of another first check matrix according to an embodiment of the present application. In the first check matrix, when at least one first check sub-matrix is ​​used to encode the first signal source bit (or the first signal source bit after length adjustment, or at least one second signal source bit), it is still divided into c non-zero blocks, and the information bit length of each block is A. gt / c(Assume A gt can be divided by c, if A gtIf it is not divisible by c, it is divided into c-1 Blocks and 1 Each non-zero block in the first check sub-matrix has a length of n0-m0 and a number of rows of r. The first check sub-matrix corresponds to the column where the information bits of the second check sub-matrix are located. That is, the result obtained by encoding with the first check sub-matrix is ​​used as the information bit for the next encoding.

[0219] When at least one second syndrome matrix is ​​used to encode at least one third coded bit, the coupling relationship is that the core matrix of the second syndrome matrix is ​​aligned with the top of the second extended matrix of the previous second syndrome matrix of the second syndrome matrix, so that when different LDPC codes are used for sliding window coding, H diag The second sliding window length in FIG14 is L=2, that is, the current coding result is only related to the information bit of the current third coding bit, the information bit of the previous coding result, and the check bit of the previous coding result (optional, if H extend2 If it is an all-zero matrix, it does not include ).

[0220] Figure 15 is a schematic diagram of another first parity check matrix according to an embodiment of the present application. In this first parity check matrix, when encoding is performed using at least one first parity check matrix and at least one second parity check matrix, both employ a sliding window LDPC code. When encoding using at least one first parity check matrix and at least one second parity check matrix with a sliding window structure, reference can be made to the descriptions above for each.

[0221] With the solution of this embodiment, the second extended matrix can be flexibly trimmed (for example, the flexible rate mainly requires different numbers of matrix rows, and the second extended matrix supports trimming from top to bottom to the required size according to different needs without affecting the encoding output result). This flexible trimming is an existing technology for 5G. This implementation uses this technology for coupling multiple coding bits, so that the encoding result can also support flexible rate changes.

[0222] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the sending end device. Accordingly, the embodiment of the present application also provides an encoding device, which is used to implement the various methods described above. The encoding device can be the sending end device in the above method embodiment, or a component that can be used for the sending end device. It can be understood that in order to implement the above functions, the encoding device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a computer software-driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0223] In the embodiment of the present application, the functional modules of the encoding device can be divided according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.

[0224] Based on the same concept of the above encoding method, this application also provides the following encoding device:

[0225] FIG16 is a schematic diagram of the structure of an encoding device provided in an embodiment of the present application. The encoding device 1600 includes:

[0226] The acquisition unit 161 is used to obtain a first check matrix; the encoding unit 162 is used to encode the first source bit according to the first check matrix to obtain a first coded bit; the encoding unit 162 is also used to segment the first coded bit according to the first check matrix to obtain at least one second coded bit; and the encoding unit 162 is also used to encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit, wherein the at least one second coded bit includes the at least one third coded bit.

[0227] Optionally, the device also includes (indicated by dotted lines in Figure 16): a first adjustment unit 164, which is used to adjust the length of the first coding bit before the coding unit segments the first coding bit according to the first check matrix to obtain the adjusted first coding bit; and the coding unit 162, which is also used to segment the adjusted first coding bit according to the first check matrix.

[0228] Optionally, the first adjustment unit 164 is configured to fill bits at the beginning, end and / or middle of the first coded bits.

[0229] Optionally, the device also includes (indicated by dotted lines in Figure 16): a second adjustment unit 165, which is used to adjust the length of the first source bit before the encoding unit encodes the first source bit according to the first check matrix to obtain the adjusted first source bit; and the encoding unit 162 is also used to encode the adjusted first source bit according to the first check matrix.

[0230] Optionally, the second adjustment unit 165 is configured to fill bits at the beginning, end and / or middle of the first source bits.

[0231] Optionally, the first coded bits include information bits and first check bits obtained by encoding the source bits; the second coded bits include part / all of the information bits and / or part / all of the first check bits.

[0232] Optionally, the first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is ​​used to encode the first source bits, and the at least one second check sub-matrix is ​​used to encode the at least one third coded bit.

[0233] Optionally, a value of at least one second element at the tail of one of the at least one first check submatrices is 0, and a position of the at least one second element corresponds to at least one first element at the tail of one of the at least one second check submatrixes.

[0234] Optionally, one first syndrome matrix among the at least one first syndrome matrix is ​​obtained by coupling all first syndrome matrices within the first sliding window length.

[0235] Optionally, the encoding unit 162 is further used to segment the first source bit according to the at least one first check matrix to obtain at least one second source bit; the encoding unit 162 is further used to encode the at least one second source bit according to the at least one first check matrix to obtain at least one fifth coded bit; and the encoding unit 162 is further used to determine the first coded bit based on the at least one fifth coded bit.

[0236] Optionally, one second syndrome matrix in the at least one second syndrome matrix is ​​obtained by coupling all second syndrome matrices within the second sliding window length.

[0237] Optionally, one of the at least one second check submatrix includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second check submatrix is ​​aligned with a top portion of a second extension matrix of a previous second check submatrix of the second check submatrix.

[0238] Optionally, the apparatus further includes (indicated by dotted lines in FIG16 ): a determination unit 163 configured to determine at least one sixth coding bit based on the at least one fourth coding bit.

[0239] The division of modules in this application is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the examples of this application may be integrated into a single processor, exist physically as separate modules, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in either hardware or software functional modules.

[0240] For the specific implementation of the above-mentioned units, please refer to the relevant descriptions in the embodiments shown in Figures 3, 4 and 9.

[0241] As shown in Figure 17, it is a structural diagram of another encoding device provided in an embodiment of the present application, and the encoding device 1700 includes a processor 1701. Optionally, the encoding device 1700 may further include an interface circuit 1702 (indicated by a dotted line in Figure 17), and the processor 1701 and the interface circuit 1702 are coupled to each other. It is understandable that the interface circuit 1702 can be a transceiver or an input and output interface. Optionally, the encoding device 1700 may further include a memory 1703 (indicated by a dotted line in Figure 17), and the memory 1703 is used to store instructions executed by the processor 1701, or to store input data required for the processor 1701 to run the instructions, or to store data generated after the processor 1701 runs the instructions.

[0242] In which, processor 1701 is used to perform the following operations: obtain a first check matrix; encode a first source bit according to the first check matrix to obtain a first coded bit; segment the first coded bit according to the first check matrix to obtain at least one second coded bit; and encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit, where the at least one second coded bit includes the at least one third coded bit.

[0243] Optionally, the processor 1701 is further used to perform the following operations: before segmenting the first coded bits according to the first check matrix, adjusting the length of the first coded bits to obtain adjusted first coded bits; and segmenting the adjusted first coded bits according to the first check matrix.

[0244] Optionally, the processor 1701 performs the operation of adjusting the length of the first coded bits to obtain adjusted first coded bits, including: filling bits at the beginning, end and / or middle position of the first coded bits.

[0245] Optionally, the processor 1701 is further used to perform the following operations: before encoding the first source bit according to the first check matrix, adjust the length of the first source bit to obtain the adjusted first source bit; and encode the adjusted first source bit according to the first check matrix.

[0246] Optionally, the processor 1701 performs the operation of adjusting the length of the first information source bits to obtain adjusted first information source bits, including filling bits at the beginning, end and / or middle position of the first information source bits.

[0247] Optionally, the first coded bits include information bits and first check bits obtained by encoding the source bits; the second coded bits include part / all of the information bits and / or part / all of the first check bits.

[0248] Optionally, the first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is ​​used to encode the first source bits, and the at least one second check sub-matrix is ​​used to encode the at least one third coded bit.

[0249] Optionally, a value of at least one second element at the tail of one of the at least one first check submatrices is 0, and a position of the at least one second element corresponds to at least one first element at the tail of one of the at least one second check submatrixes.

[0250] Optionally, one first syndrome matrix among the at least one first syndrome matrix is ​​obtained by coupling all first syndrome matrices within the first sliding window length.

[0251] Optionally, the processor 1701 is further used to perform the following operations: segmenting the first source bit according to the at least one first check matrix to obtain at least one second source bit; encoding the at least one second source bit according to the at least one first check matrix to obtain at least one fifth coded bit; and determining the first coded bit based on the at least one fifth coded bit.

[0252] Optionally, the second syndrome matrix in the at least one second syndrome matrix is ​​obtained by coupling all second syndrome matrices within the second sliding window length.

[0253] Optionally, one of the at least one second check submatrix includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second check submatrix is ​​aligned with a top portion of a second extension matrix of a previous second check submatrix of the second check submatrix.

[0254] Optionally, the processor 1701 is further configured to perform the following operation: determine at least one sixth coded bit according to the at least one fourth coded bit.

[0255] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0256] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program or instruction is stored. When the computer program or instruction is executed, the method in the above embodiment is implemented.

[0257] An embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the above embodiment.

[0258] The present application also provides a circuit, which is coupled to a memory and is used to execute the method shown in the above embodiment. The circuit may include a chip circuit.

[0259] An embodiment of the present application also provides a chip device, including a processor, for calling a computer program or computer instruction stored in the memory so that the processor executes the method provided in any one of the embodiments shown in Figures 3, 4, and 9 above.

[0260] In one possible implementation, the input of the chip device corresponds to the receiving operation in any one of the embodiments shown in Figures 3, 4, and 9 above, and the output of the chip device corresponds to the sending operation in any one of the embodiments shown in Figures 3, 4, and 9 above.

[0261] Optionally, the processor is coupled to the memory via an interface.

[0262] Optionally, the chip device further includes a memory, in which computer programs or computer instructions are stored.

[0263] It should be noted that the above units or one or more of the units can be implemented by software, hardware, or a combination of the two. When any of the above units or units is implemented by software, the software exists in the form of computer program instructions and is stored in a memory, and a processor can be used to execute the program instructions and implement the above method flow.

[0264] In this application, a processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in this application. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in this application may be directly executed by a hardware processor, or by a combination of hardware and software modules within the processor.

[0265] When the above units or units are implemented in hardware, the hardware can be any one or any combination of a CPU, a microprocessor, a digital signal processing (DSP) chip, a microcontroller unit (MCU), an artificial intelligence processor, an ASIC, a SoC, an FPGA, a PLD, a dedicated digital circuit, a hardware accelerator or a non-integrated discrete device, which can run the necessary software or not rely on the software to execute the above method flow.

[0266] Optionally, an embodiment of the present application further provides a chip system, comprising: at least one processor and an interface, wherein the at least one processor is coupled to a memory via the interface, and when the at least one processor executes a computer program or instruction in the memory, the chip system executes the method in any of the above method embodiments. Optionally, the chip system may be composed of a chip, or may include a chip and other discrete devices, which is not specifically limited in the embodiments of the present application.

[0267] The memory in the present application may also be a circuit or any other device capable of implementing a storage function for storing program instructions and / or data. A memory is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. For example, the memory may be a non-volatile memory, such as a digital versatile disc (DVD), a hard disk drive (HDD), or a solid-state drive (SSD), or a volatile memory, such as a random-access memory (RAM).

[0268] It is understood that, in this application, "indication" can include direct indication, indirect indication, explicit indication, and implicit indication. When describing a certain indication information as indicating A, it can be understood that the indication information carries A, directly indicates A, or indirectly indicates A. In this application, the information indicated by the indication information is referred to as the information to be indicated. In the specific implementation process, there are many ways to indicate the information to be indicated. For example, but not limited to, the information to be indicated can be directly indicated, such as the information to be indicated itself or an index of the information to be indicated, or it can be indirectly indicated by indicating other information, where there is an association between the other information and the information to be indicated. It is also possible to indicate only a part of the information to be indicated, while the rest of the information to be indicated is known or agreed in advance. For example, it is also possible to indicate specific information by using a pre-agreed (e.g., protocol-specified) order of arrangement of various information, thereby reducing the indication overhead to a certain extent. The information to be indicated can be sent as a whole or divided into multiple sub-information and sent separately, and the sending period and / or sending time of these sub-information can be the same or different. The specific sending method is not limited in this application. The sending period and / or sending timing of these sub-information may be predefined, for example, predefined according to a protocol, or may be configured by the transmitting end device by sending configuration information to the receiving end device.

[0269] The at least one (item) involved in this application indicates one (item) or more (items). More than one (item) refers to two (items) or more than two (items). "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In addition, it should be understood that although the terms first, second, etc. may be used to describe each object in this application, these objects should not be limited to these terms. These terms are only used to distinguish each object from each other.

[0270] The terms "including" and "having" mentioned above and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any method or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other methods or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way.

[0271] A network element in a communication system can send a signal to another network element or receive a signal from another network element. The signal may include information, signaling, or data, etc. The network element can also be replaced by an entity, a network entity, a device, a terminal device, a communication module, a node, a communication node, etc. The present application uses the network element as an example for description. For example, the communication system may include at least one terminal device and at least one network device. The network device can send a downlink signal to the terminal device, and / or the terminal device can send an uplink signal to the network device. In addition, it can be understood that if the communication system includes multiple terminal devices, the multiple terminal devices can also send signals to each other, that is, the signal sending network element and the signal receiving network element can both be terminal devices.

[0272] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0273] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0274] It is understood that the various numbers used in the embodiments of this application are merely for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the sequence numbers of the above-mentioned processes does not necessarily imply a specific order of execution; the order of execution of the processes should be determined by their functions and inherent logic.

[0275] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0276] The components in the device of the embodiment of the present application can be merged, divided, or deleted according to actual needs. Those skilled in the art can combine or combine the different embodiments and features of the different embodiments described in this specification.

[0277] In this application, under the premise of no logical contradiction, the examples can reference each other, for example, the methods and / or terms between method embodiments can reference each other, for example, the functions and / or terms between device embodiments can reference each other, for example, the functions and / or terms between device examples and method examples can reference each other.

Claims

1. A coding method, characterized in that: The method comprises: Obtaining a first check matrix, and encoding first source bits according to the first check matrix to obtain first coded bits; Segmenting the first coded bits according to the first check matrix to obtain at least one second coded bit; At least one third coded bit is encoded according to the first check matrix to obtain at least one fourth coded bit, where the at least one second coded bit includes the at least one third coded bit.

2. The method according to claim 1, wherein Before segmenting the first coded bits according to the first check matrix, the method further includes: Adjusting the length of the first coding bits to obtain adjusted first coding bits; The segmenting the first coded bits according to the first check matrix includes: The adjusted first coded bits are segmented according to the first check matrix.

3. The method according to claim 2, wherein The adjusting the length of the first coding bits includes: Bits are filled at the beginning, end and / or middle position of the first coded bits.

4. The method according to any one of claims 1 to 3, wherein Before encoding the first source bits according to the first check matrix, the method further includes: Adjusting the length of the first information source bits to obtain adjusted first information source bits; The encoding of the first source bits according to the first check matrix includes: The adjusted first source bits are encoded according to the first check matrix.

5. The method according to claim 4, wherein The adjusting the length of the first information source bits includes: Fill bits at the beginning, end and / or middle of the first source bits.

6. The method according to any one of claims 1 to 5, wherein The first coded bits include information bits and first check bits obtained by encoding the first source bits; The second coded bits include part / all of the information bits and / or part / all of the first check bits.

7. The method according to any one of claims 1 to 6, wherein The first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is used to encode the first source bits, and the at least one second check sub-matrix is used to encode the at least one third coded bit.

8. The method according to claim 7, wherein A value of at least one second element at the tail of one of the at least one first check submatrix is 0, and a position of the at least one second element corresponds to at least one first element at the tail of one of the at least one second check submatrix.

9. The method according to claim 7, wherein One first syndrome matrix among the at least one first syndrome matrix is obtained by coupling all first syndrome matrices within the first sliding window length.

10. The method according to claim 9, wherein The encoding of the first source bit according to the first check matrix to obtain the first coded bit includes: Segmenting the first information source bits according to the at least one first check sub-matrix to obtain at least one second information source bit; Encoding the at least one second information source bit according to the at least one first check submatrix to obtain at least one fifth coded bit; The first coded bit is determined based on the at least one fifth coded bit.

11. The method according to claim 7, wherein One second syndrome matrix in the at least one second syndrome matrix is obtained by coupling all second syndrome matrices within the second sliding window length.

12. The method according to claim 11, wherein One of the at least one second syndrome matrixes includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second syndrome matrix is aligned with a top of a second extension matrix of an upper second syndrome matrix of the second syndrome matrix.

13. The method according to any one of claims 1 to 12, wherein The method further comprises: At least one sixth coded bit is determined based on the at least one fourth coded bit.

14. An encoding device, characterized in that: The device comprises: an acquiring unit, configured to obtain a first check matrix; an encoding unit, configured to encode first source bits according to the first check matrix to obtain first coded bits; The encoding unit is further configured to segment the first coded bits according to the first check matrix to obtain at least one second coded bit; The encoding unit is further configured to encode at least one third coded bit according to the first check matrix to obtain at least one fourth coded bit, where the at least one second coded bit includes the at least one third coded bit.

15. The device according to claim 14, wherein The device further comprises: a first adjustment unit, configured to adjust the length of the first coded bits before the encoding unit segments the first coded bits according to the first check matrix, to obtain adjusted first coded bits; The encoding unit is further configured to segment the adjusted first coded bits according to the first check matrix.

16. The device according to claim 15, characterized in that The first adjustment unit is configured to fill bits at the beginning, end and / or middle of the first coded bits.

17. The device according to any one of claims 14 to 16, characterized in that The device further comprises: a second adjustment unit, configured to adjust the length of the first information source bits before the encoding unit encodes the first information source bits according to the first check matrix to obtain adjusted first information source bits; The encoding unit is further configured to encode the adjusted first signal source bits according to the first check matrix.

18. The device according to claim 17, wherein The second adjustment unit is configured to fill bits at the beginning, end and / or middle of the first source bits.

19. The device according to any one of claims 14 to 18, characterized in that The first coded bits include information bits and first check bits obtained by encoding the first source bits; The second coded bits include part / all of the information bits and / or part / all of the first check bits.

20. The device according to any one of claims 14 to 19, characterized in that The first check matrix includes at least one first check sub-matrix and at least one second check sub-matrix, the at least one first check sub-matrix is used to encode the first source bits, and the at least one second check sub-matrix is used to encode the at least one third coded bit.

21. The device according to claim 20, characterized in that A value of at least one second element at the tail of one of the at least one first check submatrix is 0, and a position of the at least one second element corresponds to at least one first element at the tail of one of the at least one second check submatrix.

22. The device according to claim 20, wherein One first syndrome matrix among the at least one first syndrome matrix is obtained by coupling all first syndrome matrices within the first sliding window length.

23. The device according to claim 22, characterized in that: The encoding unit is further configured to segment the first information source bits according to the at least one first check sub-matrix to obtain at least one second information source bit; The encoding unit is further configured to encode the at least one second information source bit according to the at least one first check sub-matrix to obtain at least one fifth coded bit; The encoding unit is configured to determine the first encoding bit based on the at least one fifth encoding bit.

24. The device according to claim 20, wherein One second syndrome matrix in the at least one second syndrome matrix is obtained by coupling all second syndrome matrices within the second sliding window length.

25. The device according to claim 24, wherein One of the at least one second syndrome matrixes includes a core matrix, an all-zero matrix, a first extension matrix, a diagonal matrix, and a second extension matrix, and the core matrix of the second syndrome matrix is aligned with a top of a second extension matrix of an upper second syndrome matrix of the second syndrome matrix.

26. The device according to any one of claims 14 to 25, characterized in that The device further comprises: A determining unit is configured to determine at least one sixth coded bit based on the at least one fourth coded bit.

27. An encoding device, characterized in that The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 13 when executing the computer program.

28. A chip, characterized in that: The chip is used to execute the method according to any one of claims 1 to 13.

29. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction. When the computer program or instruction is executed by the encoding device, the method according to any one of claims 1 to 13 is implemented.

30. A computer program product comprising instructions, characterized in that When the instruction is executed on a coding device, the coding device is caused to perform the method according to any one of claims 1 to 13.

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