NTT circuit, NTT method, and electronic device

Abstract

The present application provides an NTT circuit, an NTT method, and an electronic device. The NTT circuit comprises a first storage module, a first operation module, a first rotation module, and a second storage module. The first storage module is configured to store J4 pieces of first data. The J4 pieces of first data is divided into J2 first data arrays. Each first data array comprises J×J pieces of first data. J is a positive integer. The first operation module is configured to execute an NTT operation on the basis of each first data array to obtain a first operation result. The first rotation module is configured to transform the first operation result on the basis of a first rotation factor to obtain a first transformation result. The first transformation result comprises J×J pieces of second data. The second storage module is configured to store J4 pieces of second data corresponding to the J2 first data arrays. By means of the present application, the computing resources required by an NTT operation are reduced, and power consumption is reduced.

Description

NTT circuits, NTT methods, and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 5, 2024, with application number 202410168541.9 and application name “NTT circuit, NTT method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a number theoretic transform (NTT) circuit, an NTT method, and an electronic device. Background Art

[0003] In the process of Zero Knowledge Proof (ZKP), a hardware architecture based on NTT can be used. NTT makes the calculation speed of ZKP faster. The amount of data used by NTT in ZKP is usually large. Especially in some specific application scenarios, the amount of data involved in NTT calculation may reach 2 20 scale.

[0004] However, in NTT operations, as the scale of processed data increases, the required computing resources and storage bandwidth will also increase. Therefore, how to reduce the computing resources and storage bandwidth of NTT operations is an urgent problem to be solved. Summary of the Invention

[0005] This application proposes an NTT circuit, an NTT method, and an electronic device, thereby reducing the computing resources and storage bandwidth required for NTT operations.

[0006] In a first aspect, the present application provides an NTT circuit. The NTT circuit includes a first storage module, a first operation module, a first rotation module, and a second storage module. The first storage module is configured to store J 4 The first data. 4 The first data is divided into J 2 First data arrays. Each first data array includes J×J first data. J is a positive integer.

[0007] The first operation module is configured to perform an NTT operation based on each first data array to obtain a first operation result. The first rotation module is configured to transform the first operation result according to the first rotation factor to obtain a first transformation result. The first transformation result includes J×J second data. The second storage module is configured to store the first transformation result with J 2 The first data array corresponds to J 4 The second data.

[0008] In some possible implementations, the first storage module may include J 3 A first-in-first-out (FIFO) memory. Each first FIFO memory is configured to store J 4 Each data array includes J first data. 3 J×J first data in J first FIFO memories in a FIFO memory.

[0009] In some possible implementations, the first operation module may include a plurality of butterfly transformation units. The plurality of butterfly transformation units are cascade-connected and configured to perform an NTT operation on J×J first data in each data array.

[0010] In some possible implementations, the number of the plurality of butterfly transformation units may be log2J.

[0011] In some possible implementations, each of the first plurality of butterfly transformation units may include a FIFO buffer. In two adjacent butterfly transformation units among the plurality of butterfly transformation units, the depth of the FIFO buffer of the previous butterfly transformation unit is twice the depth of the FIFO buffer of the next butterfly transformation unit.

[0012] In some possible implementations, multiple butterfly transform units 21 form a pipeline architecture to implement NTT based on a frequency decimation algorithm.

[0013] In some possible implementations, the first operation module further includes at least one of a unit root generation unit, a first counter, a second counter, and a storage unit;

[0014] The unit root generation unit is used to generate the unit roots required for NTT calculation, and the generated unit roots are input to each butterfly transformation unit;

[0015] A first counter, used for initializing the pipeline architecture;

[0016] a second counter, used for delay control of a first butterfly transformation unit among the plurality of butterfly transformation units;

[0017] The storage unit is used to store the intermediate data generated when the first operation module performs the NTT operation.

[0018] In some possible implementations, the storage space size of the storage unit is equal to J×J.

[0019] In some possible implementations, the NTT circuit may further include a third storage module, a second operation module, a second rotation module, and a fourth storage module. The third storage module is configured to store J4 Second data. 4 The second data is divided into J 2 The second data array includes J×J second data. The second operation module is configured to perform an NTT operation based on each second data array to obtain a second operation result. The second rotation module is configured to transform the second operation result according to the second rotation factor to obtain a second transformation result. The second transformation result includes J×J third data. The fourth storage module is configured to store the data corresponding to J 2 The second data array corresponds to J 4 The third data.

[0020] In a second aspect, the present application provides an NTT method. The method comprises: storing J in a first storage module 4 The first data, among which J 4 The first data is divided into J 2 First data arrays, each first data array includes J×J first data, where J is a positive integer; based on each first data array, performing NTT operation in a first operation module to obtain a first operation result; transforming the first operation result in the first rotation module according to a first rotation factor to obtain a first transformation result, wherein the first transformation result includes J×J second data; storing the first transformation result in the second storage module with the J 2 The first data array corresponds to J 4 The second data.

[0021] In some possible implementations, the first operation module may include multiple butterfly transformation units, which are cascade-connected.

[0022] In some possible implementations, the number of the plurality of butterfly transformation units may be log2J.

[0023] In some possible implementations, each of the first plurality of butterfly transformation units may include a FIFO buffer. In two adjacent butterfly transformation units among the plurality of butterfly transformation units, the depth of the FIFO buffer of the previous butterfly transformation unit is twice the depth of the FIFO buffer of the next butterfly transformation unit.

[0024] In some possible implementations, the above method may further include: storing J in a third storage module 4 Second data, where J 4 The second data is divided into J 2second data arrays, each of which includes J×J second data; performing an NTT operation in a second operation module based on each second data array to obtain a second operation result; transforming the second operation result in the second rotation module according to a second rotation factor to obtain a second transformation result, wherein the second transformation result includes J×J third data; storing the J×J third data in a fourth storage module. 2 The second data array corresponds to J 4 The third data.

[0025] In a third aspect, the present application provides an electronic device, which includes the NTT circuit as described in the first aspect and possible implementations thereof.

[0026] According to this application, when it is necessary to 4 When NTT calculation is performed on the first data, J 4 The first data is divided into J 2 First data arrays are generated, each of which includes J×J first data. Then, an NTT operation is performed on each first data array. In this way, the computing resources and power consumption required for the NTT operation can be significantly reduced.

[0027] Furthermore, by adopting multiple butterfly transform units connected in cascade, the number of butterfly transform units required can be reduced from log2J 4 By using cascaded butterfly transform units to implement a pipelined architecture, one piece of data can be read and written during each clock cycle. Compared to parallel input and output methods, the required transmission bandwidth is significantly reduced.

[0028] In addition, FIFO memories are provided in the plurality of butterfly transform units for caching the input data. The maximum depth of the FIFO in the butterfly transform unit is J / 2, and the number of clock cycles required to complete the initial pipeline filling is J. 4 Compared with NTT calculation based on the first data, the solution of the present application requires less waiting time before calculation.

[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0031] FIG1 is a schematic structural diagram of an NTT circuit provided in an embodiment of the present application;

[0032] FIG2 is a schematic structural diagram of a first storage module in the NTT circuit of FIG1 ;

[0033] 3 is a schematic diagram of a first FIFO memory storing first data in a first storage module according to an embodiment of the present application;

[0034] 4 is a schematic diagram of a second FIFO memory storing first data in a first storage module according to an embodiment of the present application;

[0035] FIG5 is a schematic structural diagram of the first operation module in the NTT circuit of FIG1 ;

[0036] 6A to 6C are schematic structural diagrams of a butterfly transformation unit according to an embodiment of the present application;

[0037] FIG7 is a schematic structural diagram of the second storage module in the NTT circuit of FIG1 ;

[0038] 8 is a schematic diagram of a third FIFO memory storing second data in a second storage module according to an embodiment of the present application;

[0039] 9 is a schematic diagram of a fourth FIFO memory storing NTT data in the second storage module of an embodiment of the present application;

[0040] FIG10 is a schematic structural diagram of another NTT circuit provided in an embodiment of the present application;

[0041] FIG11 is a schematic structural diagram of another NTT circuit provided in an embodiment of the present application;

[0042] FIG12 is a schematic flow chart of an NTT method provided in an embodiment of the present application;

[0043] FIG13 is a flow chart of another NTT method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of devices consistent with certain aspects of the present application, as detailed in the appended claims.

[0045] FIG1 is a schematic diagram of the structure of an NTT circuit provided in an embodiment of the present application. As shown in FIG1 , the NTT circuit 1 includes a first storage module 10 , a first operation module 20 , a first rotation module 30 , and a second storage module 40 .

[0046] The first storage module 10 is used to store first data. The first data is data to be subjected to NTT operation. The first data can be input from the outside into the NTT circuit 1 and stored in the first storage module 10.

[0047] The amount of the first data stored in the first storage module 10 may be N. Here, N is a positive integer. In some embodiments, N may be equal to J 4 Here, J is a positive integer. In practical applications, the value of N can be very large, for example, the order of N can be ten thousand, one hundred thousand, one million, ten million, etc.

[0048] FIG2 is a schematic diagram of the structure of the first storage module in the NTT circuit of FIG1. ​​As shown in FIG2, the first storage module 10 includes a first FIFO memory 11. The first FIFO memory 11 can be used to store the first data. The number of the first FIFO memories 11 can be equal to J 3 The depth of each first FIFO memory 11 may be J. In other words, each first FIFO memory 11 may be used to store J first data.

[0049] It is understandable that the multiple first FIFO memories 11 can be implemented by different storage locations in a storage device (for example, RAM), or can be implemented by different storage devices respectively, and the embodiment of the present application does not make any specific limitation on this.

[0050] FIG3 is a schematic diagram of a first FIFO memory storing first data in a first storage module of an embodiment of the present application. 3 The first FIFO memories 11 can be represented as F1[0], F1[1], ..., F1[J 3 -1]. Here, 0, 1, ..., J 3 -1 is the index value of each first FIFO memory 11.

[0051] J 3 The first FIFO memory 11 can be divided into J 2 First FIFO groups. Each first FIFO group may include J first FIFO memories 11. In one example, starting from the first first FIFO memory 11, J consecutive first FIFO memories 11 may constitute a first FIFO group. Thus, J first FIFO memories 11 with index values ​​0 to (J-1) may constitute a first FIFO group, J first FIFO memories 11 with index values ​​J to (2J-1) may constitute a first FIFO group, and so on.

[0052] Each first FIFO group may include J first FIFO memories 11, and the depth of each first FIFO memory 11 may be J. Each first FIFO group may store J×J first data. The J×J first data stored in each first FIFO group may constitute a first data array. 4 The first data can be divided into J 2 First data arrays are formed. Each first data array includes J×J first data.

[0053] 2 , the first storage module 10 of the embodiment of the present application may further include a second FIFO memory 12. The second FIFO memory 12 may be provided before the first FIFO memory 11. More specifically, the output of the second FIFO memory 12 may serve as the input of the first FIFO memory 11.

[0054] The second FIFO memory 12 can be used to store the first data. The number of the second FIFO memories 12 can be equal to J. The depth of each second FIFO memory 12 can be J 3 In other words, each second FIFO memory 12 can be used to store J 3 The first data.

[0055] It is understandable that the multiple second FIFO memories 12 can be implemented by different storage locations in a storage device (for example, RAM), or can be implemented by different storage devices respectively, and the embodiment of the present application does not make any specific limitation on this.

[0056] FIG4 is a schematic diagram illustrating a second FIFO memory storing first data in a first storage module according to an embodiment of the present application. As shown in FIG4 , J second FIFO memories 12 can be represented as F2[0], F2[1], ..., F2[J-1], respectively. Here, 0, 1, ..., and J-1 are index values ​​of each second FIFO memory 12, respectively.

[0057] With J in each second FIFO memory 12 3 The first data is a row, and the J first data at the same position of the J second FIFO memories 12 is a column, so a size of J 3 ×J matrix. Each element in this matrix is ​​J 4 Similarly, the J first data in each first FIFO memory 11 are a row, and the J 3 J at the same position of the first FIFO memory 11 3 The first data is a column, and a J×J 3 Each element in this matrix is ​​J 4One of the first data.

[0058] Based on Figures 3 and 4, it can be seen that J 3 The matrix of the first data formed by the J first FIFO memories 11 is the transposed matrix of the matrix of the first data formed by the J second FIFO memories 12. In other words, the first data is output from the J second FIFO memories 12 and stored in the J 3 The process in the first FIFO memory 11 implements the transposition operation of the matrix of the first data.

[0059] 2, the first storage module 10 of the embodiment of the present application may further include a memory 13. The memory 13 may be provided before the second FIFO memory 12. More specifically, the output of the memory 13 may be used as the input of the second FIFO memory 12. The memory 13 may be used to store J 4 The first data.

[0060] In some embodiments, the memory 13 may store the first data in a one-dimensional sequence. 4 The first data may be stored in sequence at consecutive addresses of the memory 13 .

[0061] The size of the storage space of the memory 13 may be greater than or equal to the amount of the first data. In an example, the size of the storage space of the memory 13 may be equal to J 4 In one example, the size of the storage space of the memory 13 may be larger than J 4 .

[0062] The memory 13 may be dedicated to storing the first data. In this case, the first data may be stored in the memory 13 at address 0 to address (J 4 The addressing address of each first data in the memory 13 can be used as the index value of the data.

[0063] In some embodiments, the first data may be written in advance into the memory 13. In some embodiments, the first data may be input into the first storage module 10 and stored in the memory 13.

[0064] In some embodiments, the memory 13 may be a random access memory (RAM). For example, the memory 13 may be a static RAM. Of course, the memory 13 may also be other types of memory, which is not specifically limited in the embodiments of the present application.

[0065] In some embodiments, the first storage module 10 may include a memory 13, a second FIFO memory 12, and a first FIFO memory 11. The memory 13 stores first data. The first data can be read from the memory 13 and input into the second FIFO memory 12. The J second FIFO memories 12 store the first data in a matrix. Thereafter, the first data can be read from the second FIFO memory 12 and input into the first FIFO memory 11. 3 The first FIFO memory 11 stores the first data in a matrix form. The matrix of the first data is transposed during the process of being read from the second FIFO memory 12 and stored in the first FIFO memory 11.

[0066] In some embodiments, the first storage module may include a memory 13 and a first FIFO memory 11. The memory 13 stores first data. The first data may be read from the memory 13 and input into the first FIFO memory 11. 3 The first FIFO memories 11 store first data in a matrix manner.

[0067] In some embodiments, the first storage module may include a first FIFO memory 11. The first data may be directly input into the first FIFO memory 11 from outside the NTT circuit 1. 3 The first FIFO memories 11 store first data in a matrix manner.

[0068] Figure 5 is a schematic diagram of the structure of the first operation module in the NTT circuit of Figure 1. As shown in Figure 5, the first operation module 20 may include multiple butterfly transformation units 21. The multiple butterfly transformation units 21 are used to perform NTT operations on J×J first data in each data array.

[0069] Multiple butterfly transform units 21 are connected in cascade, that is, the output of the butterfly transform unit 21 of the previous stage can be used as the input of the butterfly transform unit 21 of the next stage.

[0070] The J×J first data may be respectively input to the butterfly transform unit 21 at the highest level. More specifically, the J×J first data may be input to the butterfly transform unit 21 at the highest level in batches at different times.

[0071] Among the plurality of butterfly transformation units 21 , each butterfly transformation unit 21 , except for the butterfly transformation unit 21 at the highest level, may receive an output from the butterfly transformation unit 21 at the previous stage.

[0072] Among the plurality of butterfly transform units 21 , each butterfly transform unit 21 may perform an operation based on input data and output an operation result.

[0073] In some embodiments, the number of butterfly transform units 21 may be equal to log2 J. In other words, a plurality of butterfly transform units 21 are connected in cascade to form a log2 J stage.

[0074] 6A to 6C are schematic structural diagrams of a butterfly transformation unit according to an embodiment of the present application.

[0075] FIG6A illustrates the structure of the highest-level butterfly transform unit 21. In FIG6A , the butterfly transform unit 21 may include a butterfly operation circuit 611 and a FIFO buffer 612. FIFO buffer 612 includes a FIFO buffer 612A and a FIFO buffer 612B. FIFO buffer 612A may be used to buffer first data input to the butterfly transform unit 21. The butterfly operation circuit 611 may be used to perform an NTT operation on the first data from the FIFO buffer 612A. FIFO buffer 612B may be used to buffer a portion of the operation results from the butterfly operation circuit 611. In some embodiments, the depth of FIFO buffer 612A may be equal to J / 2.

[0076] FIG6B shows the structure of the butterfly transformation unit 21 at the middle stage. In FIG6B , the butterfly transformation unit 21 may include a butterfly operation circuit 621 and a FIFO buffer 622. The FIFO buffer 622 includes a FIFO buffer 622A and a FIFO buffer 622B. The FIFO buffer 622A may be used to cache the operation result from the butterfly transformation unit 21 of the previous stage. The butterfly operation circuit 621 may be used to perform an NTT operation on the first data and the operation result from the FIFO buffer 622A. The FIFO buffer 622B may be used to cache part of the operation result from the butterfly operation circuit 621. In some embodiments, the depth of the FIFO buffer 622 may be equal to J / 2. k Here, k may be a positive integer. In some embodiments, the value of k increases by 1 for each subsequent level of the butterfly transform unit 21. In other words, the depth of the FIFO buffer 622 of the previous level butterfly transform unit 21 may be twice the depth of the FIFO buffer 622 of the subsequent level butterfly transform unit 21. Specifically, the depth of the FIFO buffer 622 in the butterfly transform unit 21 located after the highest level butterfly transform unit 21 may be equal to J / 2 2 , the depth of the FIFO buffer 622 in the butterfly transform unit 21 of the next level can be equal to J / 2 3 , and so on.

[0077] FIG6C illustrates the structure of a butterfly transform unit 21 at the first stage. In FIG6A , the butterfly transform unit 21 may include a butterfly operation circuit 631 and a FIFO buffer 632. The FIFO buffer 632 includes a FIFO buffer 632A and a FIFO buffer 632B. FIFO buffer 632A can be used to buffer the operation results from the butterfly transform unit 21 at the previous stage. The butterfly operation circuit 631 can be used to perform an NTT operation on the first data from the FIFO buffer 632A and the operation results from the butterfly transform unit 21 at the previous stage. FIFO buffer 632B can be used to buffer a portion of the operation results from the butterfly operation circuit 631. In some embodiments, the depth of the FIFO buffer 632 can be equal to 1. In one example, as shown in FIG6C , the FIFO buffer 632 (including the FIFO buffers 632A and 632B) in the first-stage butterfly transform unit 21 can be implemented by a flip-flop. The flip-flop can be, for example, a D flip-flop.

[0078] The above multiple butterfly transform units 21 can form a pipeline architecture to implement NTT based on the frequency decimation algorithm (DIF).

[0079] 5 , the first operation module 20 may further include at least one of the following: a unit root generation unit 22 , a first counter 23 , a second counter 24 , and a storage unit 25 .

[0080] The unit root generation unit 22 may be used to generate the unit roots required for NTT calculation and the generated unit roots may be input to each butterfly transformation unit 21 .

[0081] The first counter 23 can be used to initialize the pipeline architecture. The second counter 24 can be used to control the delay of the first butterfly conversion unit 21. Based on the first counter 23 and the second counter 24, the logic control of multiple butterfly conversion units 21 can be implemented.

[0082] The storage unit 25 may be used to store intermediate data when the first operation module 20 performs the NTT operation. In some embodiments, the size of the storage space of the storage unit 25 may be equal to J×J.

[0083] In some embodiments, the first operation result obtained by the NTT operation on the J×J first data may include J×J NTT data.

[0084] The first rotation module 30 is configured to transform the first operation result according to the first rotation factor to obtain a first transformation result. Specifically, the first rotation module 30 may transform J×J NTT data in the first operation result respectively to obtain J×J second data.

[0085] The second storage module 40 is used to store J 4 The second data. 4 The second data may correspond to J 2 Each data array may correspond to the J stored in the second storage module 40. 2 The second data.

[0086] FIG7 is a schematic diagram of the structure of the second storage module in the NTT circuit of FIG1. ​​As shown in FIG7, the second storage module 40 may include a third FIFO memory 41. The third FIFO memory 41 may be used to store the second data. The number of the third FIFO memories 41 may be equal to J. The depth of each third FIFO memory 41 may be J 3 In other words, each third FIFO memory 41 can be used to store J 3 The first data.

[0087] It is understandable that the multiple third FIFO memories 41 can be implemented by different storage locations in a storage device (for example, RAM), or can be implemented by different storage devices respectively, and the embodiment of the present application does not make any specific limitation on this.

[0088] FIG8 is a schematic diagram illustrating a third FIFO memory storing second data in a second storage module according to an embodiment of the present application. As shown in FIG8 , J third FIFO memories 41 can be represented as F3[0], F3[1], ..., F3[J-1], respectively. Here, 0, 1, ..., and J-1 are index values ​​of each third FIFO memory 41, respectively.

[0089] 7, the second storage module 40 may further include a fourth FIFO memory 42. The fourth FIFO memory 42 may be used to store NTT data (ie, the operation result output by the first operation module 20). The number of the fourth FIFO memory 42 may be equal to J 3 The depth of each fourth FIFO memory 42 may be J. In other words, each fourth FIFO memory 42 may be used to store J NTT data.

[0090] It is understandable that the multiple fourth FIFO memories 42 can be implemented by different storage locations in a storage device (for example, RAM), or can be implemented by different storage devices respectively, and the embodiment of the present application does not make any specific limitation on this.

[0091] FIG9 is a schematic diagram of a fourth FIFO memory storing NTT data in the second storage module of an embodiment of the present application. As shown in FIG9 , J 3The fourth FIFO memories 42 can be represented as F4[0], F4[1], ..., F4[J 3 -1]. Here, 0, 1, ..., J 3 −1 is the index value of each fourth FIFO memory 42 .

[0092] J 3 The fourth FIFO memory 42 can be divided into J 2 Each fourth FIFO group may include J fourth FIFO memories 42. In one example, starting from the first fourth FIFO memory 42, J consecutive fourth FIFO memories 42 may constitute a fourth FIFO group. Thus, J fourth FIFO memories 42 with index values ​​0 to (J-1) may constitute a fourth FIFO group, J fourth FIFO memories 42 with index values ​​J to (2J-1) may constitute a fourth FIFO group, and so on.

[0093] Each fourth FIFO group may include J fourth FIFO memories 42, and the depth of each fourth FIFO memory 42 may be J. Each fourth FIFO group may store J×J NTT data. The J×J NTT data stored in each fourth FIFO group may constitute an NTT data array. 4 NTT data can be divided into J 2 NTT data arrays. Each NTT data array includes J×J NTT data.

[0094] In some embodiments, the fourth FIFO memory 42 may be provided before the first rotation module 30, and the third FIFO memory 41 may be provided after the first rotation module 30. In this case, the NTT data from the first operation module 20 may be stored in the fourth FIFO memory 42. Thereafter, the first rotation module 30 may transform the NTT data from the fourth FIFO memory 42 according to the rotation factor to obtain the second data. The second data is stored in the third FIFO memory 41. Based on FIG3 and FIG4 , it can be seen that the matrix of the second data formed by J third FIFO memories 41 is J 3 The fourth FIFO memory 42 is a transposed matrix of the NTT data matrix (the matrix elements are transformed by the rotation factors).

[0095] 7, the second storage module 40 may further include a memory 43. The memory 43 may be provided after the third FIFO memory 41. More specifically, the output of the third FIFO memory 41 may be used as the input of the memory 43. The memory 43 may be used to store J 4 The second data.

[0096] In some embodiments, the memory 43 may store the second data in a one-dimensional sequence. 4 The second data may be stored in sequence at consecutive addresses of the memory 43 .

[0097] In some embodiments, the memory 43 may be a random access memory (RAM) or other types of memory, which is not specifically limited in the embodiments of the present application.

[0098] In some embodiments, the second storage module 10 may include a third FIFO memory 41, a fourth FIFO memory 42, and a memory 43. The NTT data from the first operation module 20 may be stored in the fourth FIFO memory 42 in a matrix format. Subsequently, the NTT data may be read from the fourth FIFO memory 42 and input to the first rotation module 30 for transformation. Next, the second data obtained through the transformation may be stored in the third FIFO memory 41 in a matrix format. Finally, the second data in the third FIFO memory 41 may be input to the memory 43 and stored as a one-dimensional sequence.

[0099] In some embodiments, the second storage module 40 may include a memory 43 and a third FIFO memory 41. The NTT data from the first operation module 20 may be directly input into the first rotation module 30 for transformation. Next, the second data obtained by the transformation may be stored in a matrix in the third FIFO memory 41. Finally, the second data in the third FIFO memory 41 may be input into the memory 43 and stored in a one-dimensional sequence.

[0100] In some embodiments, the second storage module 40 may include a third FIFO memory 41. The NTT data from the first operation module 20 may be directly input to the first rotation module 30 for transformation. Next, the second data obtained by the transformation may be stored in the third FIFO memory 41 in a matrix manner.

[0101] In the NTT circuit 1 shown in FIG1 , the first storage module 10 and the second storage module 40 can be independent of each other. It is understood that in some embodiments, the first storage module 10 and the second storage module 40 can be the same storage module. For example, the first storage module 10 can be reused as the second storage module.

[0102] For example, the first FIFO memory 11, the second FIFO memory 12, and the memory 13 in the first storage module 10 have the same configuration as the third FIFO memory 42, the fourth FIFO memory 41, and the memory 43 in the second storage module 40, respectively. Therefore, after all the first data are input into the first operation module 20, the first storage module 10 may no longer store the first data, but may be used as a fourth storage module to store intermediate data and / or second data.

[0103] Figure 10 is a schematic diagram of the structure of another NTT circuit provided in an embodiment of the present application. Compared to the NTT circuit 1 shown in Figure 1, the NTT circuit 1 in Figure 10 may include a first storage module 10, a first operation module 20, and a first rotation module 30. The first storage module 10 is used to store first data. The first operation module 20 is used to perform an NTT operation on J×J first data from the first storage module 10. The first rotation module 30 is used to transform the result of the NTT operation. The J×J second data obtained after the transformation can be input into the first storage module 10.

[0104] In some embodiments, the first operation module 20 obtains J by performing NTT operation. 4 The NTT data can be input into the first FIFO memory 11 for storage. The NTT data in the first FIFO memory 11 can be input into the first rotation module 30 for transformation. 4 The second data may be input to the second FIFO memory 12 for storage. Thereafter, the second data may be input to the memory 13 by the second FIFO memory 12 and stored in a one-dimensional sequence.

[0105] It should be noted that, in some cases, the NTT circuit 1 in the embodiments of the present application may include a control circuit (not shown) that can be used to control the operation of various modules, units, circuits, etc. in the NTT circuit 1.

[0106] In some embodiments, the control circuit may be a controller that generates necessary control signals to ensure that data flows and is processed in the circuit according to a predetermined sequence and conditions.

[0107] Figure 11 is a schematic diagram of the structure of another NTT circuit provided by an embodiment of the present application. As shown in Figure 11, the NTT circuit 1 may include a first storage module 10, a first operation module 20, a first rotation module 30, a second storage module 40, a third storage module 50, a second operation module 60, a second rotation module 70, and a fourth storage module 80.

[0108] The first storage module 10, the first operation module 20, the first rotation module 30, and the second storage module 40 in the NTT circuit 1 shown in Figure 11 are the same as the first storage module 10, the first operation module 20, the first rotation module 30, and the second storage module 40 in the NTT circuit 1 in Figures 1 and 10, and are not repeated here.

[0109] The third storage module 50 is used to store J 4 Here, J 4 The second data can be divided into J 2 Each second data array may include J×J second data.

[0110] The second operation module 60 is configured to perform an NTT operation based on each second data array to obtain a second operation result.

[0111] The second rotation module 70 is configured to transform the second operation result according to the second rotation factor to obtain a second transformation result. The second transformation result may include J×J third data.

[0112] The fourth storage module 80 is used to store 2 The second data array corresponds to J 4 The third data.

[0113] It should be noted that the specific implementations of the third storage module 50, the second operation module 60, the second rotation module 70, and the fourth storage module 80 in the NTT circuit 1 shown in Figure 11 are similar to the first storage module 10, the first operation module 20, the first rotation module 30, and the second storage module 40, respectively, and therefore are not further described here.

[0114] FIG12 is a flow chart of an NTT method provided in an embodiment of the present application. The NTT method can be applied to the NTT circuit shown in FIG1 .

[0115] As shown in FIG. 12 , the NTT method according to the embodiment of the present application may include steps S1201 to S1204 .

[0116] In step S1201, J is stored in the first storage module 10. 4 The first data.

[0117] In this step, J 4 (ie, N) first data are stored in the first storage module 10 in a predetermined manner.

[0118] In some embodiments, step S1201 may include three sub-steps.

[0119] In the first sub-step, J 4The first data is stored in the memory 13. In the memory 13, J 4 The first data may be stored in a one-dimensional sequence.

[0120] In the second sub-step, J 4 The first data are taken out from the memory 13 and input into J second FIFO memories 12. Thus, each second FIFO memory 12 can store J 3 The first data.

[0121] In one example, the pseudo code for implementing the second sub-step is as follows:

[0122] Algorithm 1: Mapping of memory to first FIFO memory

[0123] 1:mm is ram array and F2 is fifo array and rd_address is read address in ram array / / Define mm as RAM array, F2 as FIFO array, rd_address as read address in RAM array

[0124] 2:N is NTT point number and I is and J is / / Define N as the number of NTT points, I as J is

[0125] 3:for u:=0to J-1do / / u's value range is 0 to J-1

[0126] 4:for i:=0to J-1do / / the value range of i is 0 to J-1

[0127] 5:for j:=0to J-1do / / the value range of j is 0 to J-1

[0128] 6:for k:=0to J-1do / / The value range of k is 0 to J-1

[0129] 7: / / Traverse u, i, j, k and calculate the corresponding address rd_address[u]

[0130] 8: F2[u][I×i+J×j+k]=mm[rd_address[u]] / / Write the first data at address rd_address[u] in the memory to the position I×i+J×j+k in the second FIFO memory 12 with index u

[0131] 9:end

[0132] 10:end

[0133] 11:end

[0134] 12:end

[0135] By using the above algorithm 1, the location where the first data at each address in the memory 13 should be stored in the second FIFO memory 12 can be calculated based on u, i, j, and k. The distribution of the first data in the J second FIFO memories 12 is shown in Figure 4. In Figure 3, the number in each box represents the storage address of the first data at that location in the memory 13.

[0136] In the third sub-step, J 4 The first data are input from the J second FIFO memories 12 to the J3 first FIFO memories 11. In this way, each first FIFO memory 11 can store J first data.

[0137] In this sub-step, the J in each second FIFO memory 12 can be 3 The first data are taken out in sequence and stored in J 3 At the same position of the first FIFO memory 11.

[0138] First data in J 3 The distribution of the first FIFO memory 11 is shown in Figure 3. In Figure 4, the number in each box is used to represent the storage address of the first data at that position in the memory 13.

[0139] It can be understood that the third sub-step realizes the J×J structure of the first data in the J second FIFO memories 12. 3 Matrix to J 3 The J 3 The transpose of the ×J matrix.

[0140] J 3 The first FIFO memory 11 can constitute J 2 Each first FIFO group may include J first FIFO memories 11.

[0141] Exemplarily, the J first FIFO groups may include:

[0142] Group 0: F[0], F[1], F[2], ..., F[J-1];

[0143] Group 1: F[J], F[J+1], F[J+2], ..., F[2J-1];

[0144] …

[0145] No. J 2 -1 Group: F[(J 2 -1)J]、F[(J 2 -1)J+1], F[(J+-1)J+2],…, F[(J 2 -1)J+(J-1)].

[0146] In step S1202 , an NTT operation is performed in the first operation module 20 based on each first data array.

[0147] Here, each first data array includes J×J first data. The first data in each first data array is obtained from a first FIFO group.

[0148] In some embodiments, a J-point NTT operation may be performed in the first operation module 20. The J-point NTT operation refers to performing an NTT operation on a number J of first data. In one embodiment, the J first data in each first FIFO memory 11 may serve as input data for the J-point NTT operation.

[0149] In some embodiments, step S1202 may include four sub-steps.

[0150] In the first sub-step, J first data in the first FIFO memory 11 are input into the first operation module 20 to perform a J-point NTT operation.

[0151] Specifically, J first data from one first FIFO memory 11 may be input to a butterfly operation unit 21 at the highest level among the plurality of butterfly operation units 21 , thereby implementing an NTT operation.

[0152] In the second sub-step, each operation result of the NTT operation is multiplied by a twiddle factor to obtain intermediate data, and the intermediate data is written into the storage unit 25 .

[0153] In some embodiments, the rotation factor can be used to transform each result of the NTT operation. In one example, the rotation factor in this step can be recorded as

[0154] In some embodiments, the intermediate data may be written into the storage unit 25 in row-major order. More specifically, the intermediate data corresponding to the NTT operation of J first data of one first FIFO memory 11 may be stored in a row in the storage unit 25. The intermediate data corresponding to the NTT operation of the first data of different first FIFO memories 11 may be stored in different rows in the storage unit 25.

[0155] It is understandable that different rows in the storage unit 25 can be distinguished physically or logically, and the embodiments of the present application do not specifically limit this.

[0156] For J first FIFO memories 11 in a FIFO group, the above first sub-step and second sub-step may be repeated to obtain J×J intermediate data and store them in the storage unit 25 .

[0157] In some embodiments, the number of storage units 25 may be one or more. In one example, the number of storage units 25 may be equal to 1. In one example, the number of storage units 25 may be greater than 1. In this case, the intermediate data obtained based on different first data arrays may be stored in different storage units 25. For example, the number of storage units 25 may be equal to 2. At this time, of the two storage units 25, one storage unit 25 may be used to store the intermediate data obtained based on the first data array in the first FIFO group with an odd index value, and the other storage unit 25 may be used to store the intermediate data obtained based on the first data array in the first FIFO group with an even index value. It is understandable that the number of storage units 25 and the corresponding relationship between the storage units 25 and each first data array can be set as needed, and the embodiments of the present application do not specifically limit this.

[0158] In the third sub-step, the J×J intermediate data in the storage unit 25 are input to the butterfly operation unit 21 at the highest level among the multiple butterfly operation units 21 to perform a J-point NTT operation.

[0159] Specifically, the J intermediate data in the storage unit 25 can be read in columns to perform a J-point NTT operation. By repeating this step, the J-point NTT operation can be completed on the J×J intermediate data, thereby obtaining J×J NTT data.

[0160] In the fourth sub-step, the first operation result is output.

[0161] Here, after each J-point NTT operation of J intermediate data is completed, the obtained NTT data can be output. In this way, for each first data array, a first operation result is finally output. The first operation result includes J×J NTT data.

[0162] In some embodiments, the NTT data may be output to the fourth FIFO memory 42 of the second storage module 40. 3 The distribution manner in the fourth FIFO memory 42 is shown in FIG9 .

[0163] It can be understood that, through the above four sub-steps, the NTT operation for a group of first data arrays can be realized. Then, repeating the above steps for different first data arrays can realize the NTT operation for all first data arrays (ie, J 4 NTT operation of the first data).

[0164] In step S1203, the first operation result is transformed in the first rotation module according to the first rotation factor.

[0165] Here, the first operation result may be taken out from the fourth FIFO memory 42 , and the NTT data may be transformed in the first rotation module to obtain a first transformation result.

[0166] The first transformation result may include J×J second data. 2 The first data array can be obtained by 4 The second data.

[0167] In one example, the pseudo code for implementing step S1203 is as follows:

[0168] Algorithm 2: For J 4 Rotation transformation of NTT data

[0169] 1:ω I is I-th root of unity andω N is N-th root of unit and F3 is fifo array and F4 is fifo array / / define ω I is the first-order unit root, ω N is the Nth root of unity, F3 is a FIFO array, and F4 is a FIFO array

[0170] 2:N is NTT point number and I is and J is / / Define N as the number of NTT points, I as J is

[0171] 3:interger variable row,col,rowTimescol,twiddle and row is log2I bits wide and col is log2I bits wide and rowTimescol is log2N bits / / Define integer variables row, col, rowTimescol, twiddle, row has log2I bits, col has log2I bits, rowTimescol has log2N bits

[0172] 4:function mult is modular multiplication / / Define function mult as modular multiplication

[0173] 5:for i:=0to J-1do / / the value range of i is 0 to J-1

[0174] 6: for j: = 0 to J-1 do / / j's value range is 0 to J-1

[0175] 7:for k:=0to J-1do / / The value range of k is 0 to J-1

[0176] 8:for l:=0to J-1do / / The value range of l is 0 to J-1

[0177] 9:row=64×i+j / / Define the value of row

[0178] 10:col=64×l+k / / define the value of col

[0179] 11:rowTimescol=row×col / / Define the value of rowTimescol

[0180] 12: / / Define the first rotation factor twiddle by and The modular multiplication operation between

[0181] 13: F3[l][I×i+J×j+k]=mul(F4[I×i+J×j+k][l],twiddle) / / defines that the second data at row l, column I×i+J×j+k in the third FIFO memory 41 is obtained by performing a modular multiplication operation between the NTT data at row I×i+J×j+k, column l in the fourth FIFO memory 42 and the corresponding first twiddle factor.

[0182] 14:end

[0183] 15:end

[0184] 16:end

[0185] 17:end

[0186] Through the above algorithm 2, not only can each NTT data in the fourth FIFO memory 42 be transformed according to the first rotation factor, but also the position of the second data obtained by transforming the NTT data in the third FIFO memory 41 can be determined.

[0187] In some embodiments, the first rotation factor may be equal to and Of course, the first rotation factor can also be obtained in other ways or use other values, which is not specifically limited in this embodiment of the present application.

[0188] In step S1204, J is stored in the second storage module 40. 4 The second data.

[0189] Specifically, after obtaining J×J second data of the first transformation result, these second data can be stored in J third FIFO memories 41 of the second storage module 40. Each third FIFO memory 41 can store J 3 The second data.

[0190] In some embodiments, step S1204 may include two sub-steps.

[0191] In the first sub-step, the second data in the third FIFO memory 41 is rearranged.

[0192] Here, the second data at the same address in the J third FIFO memories 41 can be read out from the third FIFO memories 41 and rearranged, and the rearranged second data can be written back to the J third FIFO memories 41 .

[0193] In one example, the pseudo code for implementing the first sub-step is as follows:

[0194] Algorithm 3: Rearrangement

[0195] 1:F3 is fifo array and v is a fifo of depth J and stages is fifo array and N is NTT point number and I is and J is / / Define F3 as a FIFO array, v as a FIFO with a depth equal to J, stages as a FIFO array, N as the number of points of the NTT, and I as J as

[0196] 2: function xor_permute_spatial implements data rearrangement in a size of J / / Define the function xor_permute_spatial to rearrange data in units of J

[0197] 3: for i := 0 to J - 1 do / / The value range of i is from 0 to J - 1

[0198] 4: for j := 0 to J - 1 do / / The value range of j is from 0 to J - 1

[0199] 5: for k := 0 to J - 1 do / / The value range of k is from 0 to J - 1

[0200] 6: for l := 0 to J - 1 do / / The value range of l is from 0 to J - 1

[0201] 7: v[l] = F3[l][I * i + J * j + k] / / Define that the l-th data in the FIFO v is the second data at the l-th row and the I * i + J * j + k-th column in the third FIFO memory 41

[0202] 8: end

[0203] 9: stages[0] = v / / Define that the data in the 0-th row of the FIFO array stages comes from the FIFO v

[0204] 10: for m := 0 to log2J do / / The value range of m is from 0 to log2J

[0205] 11: for n := 0 to J do / / The value range of n is from 0 to J

[0206] 12: stages[m + 1][n] = stages[m][i[m]? n ^ (1 << m) : j] / / Define that the data at the n-th column of the (m + 1)-th row in the FIFO array stages is obtained by rearranging the data in the m-th row.

[0207] 13: end

[0208] 14: v = stages[log2J]

[0209] 15: end

[0210] 16:for u:=0to J-1do / / The value range of u is 0 to J-1

[0211] 17:F3[l][I×i+J×j+k]=v[u]

[0212] 18:end

[0213] 19:end

[0214] 20:end

[0215] 21:end

[0216] Specifically, the rearrangement method implemented by the pseudocode on line 12 in the above rearrangement algorithm can be as follows: determine whether the m-th bit data of i is 1; if it is 1, the data at the m+1-th row and n-th column in stages comes from the m-th row and n^2m-th column (^ represents an exclusive OR operation); if it is not 1, the data at the m+1-th row and n-th column in stages comes from the m-th row and j-th column.

[0217] In the second sub-step, the second data are output to the memory 43 .

[0218] In this sub-step, the second data may be read out from the third FIFO memory 41 and stored in the memory 43 .

[0219] In some embodiments, J 4 The second data may be stored in the memory 43 in the form of a one-dimensional sequence.

[0220] Algorithm 4: Third FIFO memory to memory mapping

[0221] 1:mm is ram array and F3 is fifo array and wr_address is write address in ram array / / Define mm as RAM array, F3 as FIFO array, wr_address as write address in RAM array

[0222] 2:N is NTT point number and I is and J is / / Define N as the number of NTT points, I as J is

[0223] 3:for u:=0to J-1do / / u's value range is 0 to J-1

[0224] 4:for i:=0to J-1do / / the value range of i is 0 to J-1

[0225] 5:for j:=0to J-1do / / the value range of j is 0 to J-1

[0226] 6:for k:=0to J-1do / / The value range of k is 0 to J-1

[0227] 7: / / Traverse u, i, j, k and calculate the corresponding address wr_address[u]

[0228] 8: mm[wr_address[u]] = F3[u][I×i+J×j+k] / / write the second data at position I×i+J×j+k in the third FIFO memory 43 with index value u to the address wr_address[u] in the memory

[0229] 9:end

[0230] 10:end

[0231] 11:end

[0232] 12:end

[0233] Through the above algorithm 4, the location where each second data in the third FIFO memory 41 should be stored in the memory 43 can be calculated according to u, i, j, and k.

[0234] It should be noted that during the execution of steps S1203 and S1204 above, the NTT data and / or the second data may be stored in the second storage module 40. In some embodiments, the NTT circuit 1 may not include the second storage module 40. In this case, the NTT data and / or the second data may be stored in the first storage module 10.

[0235] FIG13 is a flow chart of another NTT method provided in an embodiment of the present application. The NTT method can be applied to the NTT circuit 1 shown in FIG10 .

[0236] As shown in FIG. 13 , the method of the embodiment of the present application may include steps S1301 to S1308 .

[0237] Steps S1301 to S1304 in the NTT method shown in FIG13 are the same as steps S1201 to S1204 in FIG13 , and are not described in detail here.

[0238] In step S1305, J is stored in the third storage module 50. 4 Second data.4 The second data is divided into J 2 Second data arrays. Each second data array includes J×J second data.

[0239] In step S1306, based on each second data array, NTT operation is performed in the second operation module 60 to obtain a second operation result. The second operation result corresponding to each second data array includes J×J NTT data.

[0240] In step S1307, the second operation result is transformed in the second rotation module 70 according to the second rotation factor to obtain a second transformation result. The second transformation result corresponding to each second data array includes J×J third data.

[0241] In step S1308, J is stored in the fourth storage module 80. 2 The second data array corresponds to J 4 The third data.

[0242] It should be noted that the specific implementation of steps S1305 to S1308 is substantially the same as that of steps S1301 to S1304. Therefore, in the following, only the differences between steps S1305 to S1308 are described, and the same contents are not repeated.

[0243] In some embodiments, the second rotation factor may have a fixed value. In one example, the value of the second rotation factor may be equal to 1.

[0244] Based on the same inventive concept, an embodiment of the present application provides an electronic device. The electronic device may include any NTT circuit described in the embodiment of the present application.

[0245] According to the solution of the embodiment of the present application, when N=J 4 When NTT calculation is performed on the first data, J 4 The first data is divided into J 2 First data arrays are prepared, each of which includes J×J first data. A J-point NTT operation is then performed on each first data array. Based on the recursion of the J-point NTT operation on each first data array, an N-point NTT operation is ultimately implemented. Compared to the log2N-stage full-pipeline architecture of the N-point NTT operation, the number of butterfly transform units used in the J-point NTT operation is reduced to log2J. Since the butterfly transform unit occupies most of the area of ​​the entire NTT circuit, reducing the number of butterfly transform units can significantly reduce the number of computing resources in the NTT circuit, thereby reducing the area of ​​the NTT circuit.

[0246] In the actual test, the clock frequency is set to 500 MHz, and the scale of the NTT operation (ie, the value of N) is 213. The specific test results are shown in Table 1.

[0247] Table 1: Comparison of NTT computing performance

[0248] It can be seen from Table 1 that, at a unit throughput, the number of logic resources occupied by the solution of the embodiment of the present application is reduced by about 5%, and the power consumption is reduced by about 31%.

[0249] Furthermore, by using cascaded butterfly transform units to implement a pipeline architecture, one piece of data can be read and written in each clock cycle, significantly reducing the required transmission bandwidth compared to parallel input and output methods.

[0250] In addition, FIFO memories are provided in the plurality of butterfly transform units for caching the input data. The maximum depth of the FIFO in the butterfly transform unit is J / 2, and the number of clock cycles required to complete the initial pipeline filling is J. 4 Compared with the NTT calculation of the first data, the solution of the present application requires less waiting time before calculation. For example, the delay caused by the NTT circuit of the embodiment of the present application to implement N-point NTT calculation is: L butterfly Indicates the number of clock cycles required for the butterfly transform unit to perform calculations. multi Identifies the number of clock cycles required to perform a modular multiplication operation.

[0251] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0252] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A number theory transform NTT circuit, characterized in that: The NTT circuit includes: The first storage module is configured to store J 4 First data, wherein the J 4 The first data is divided into J 2 first data arrays, each first data array includes J×J first data, where J is a positive integer; a first operation module configured to perform an NTT operation based on each of the first data arrays to obtain a first operation result; a first rotation module configured to transform the first operation result according to a first rotation factor to obtain a first transformation result, wherein the first transformation result includes J×J second data; The second storage module is configured to store the J 2 The first data array corresponds to J 4 The second data.

2. The NTT circuit according to claim 1, characterized in that The first storage module includes: J 3 A first first-in-first-out FIFO memory, wherein each first FIFO memory is configured to store the J 4 J first data among the first data; Wherein, each of the data arrays includes the J 3 J×J first data in J first FIFO memories in a FIFO memory.

3. The NTT circuit according to claim 1, wherein: The first operation module includes: A plurality of butterfly transform units are provided, wherein the plurality of butterfly transform units are connected in cascade, and the plurality of butterfly transform units are used to perform an NTT operation on J×J first data in each data array.

4. The NTT circuit according to claim 3, characterized in that The number of the plurality of butterfly transformation units is log2J.

5. The NTT circuit according to claim 3, characterized in that: The plurality of butterfly transformation units each include a FIFO buffer; Among the two adjacent butterfly transformation units among the plurality of butterfly transformation units, the depth of the FIFO buffer of the previous butterfly transformation unit is twice the depth of the FIFO buffer of the next butterfly transformation unit.

6. The NTT circuit according to claim 5, characterized in that: The plurality of butterfly transform units 21 form a pipeline architecture to implement NTT based on a frequency decimation algorithm.

7. The NTT circuit according to claim 6, characterized in that The first operation module further includes at least one of a unit root generation unit, a first counter, a second counter, and a storage unit; The unit root generating unit is used to generate the unit root required for NTT calculation, and the generated unit root is input to each of the butterfly transformation units; The first counter is used for initializing the pipeline architecture; The second counter is used for delay control of the first butterfly transformation unit among the plurality of butterfly transformation units; The storage unit is used to store intermediate data generated when the first operation module performs NTT operation.

8. The NTT circuit according to claim 7, characterized in that: The storage space size of the storage unit is equal to J×J.

9. The NTT circuit according to any one of claims 1 to 8, characterized in that: The NTT circuit further includes: The third storage module is configured to store J 4 Second data, wherein the J 4 The second data are divided into J2 second data arrays, each second data array includes J×J second data; a second operation module configured to perform an NTT operation based on each second data array to obtain a second operation result; a second rotation module configured to transform the second operation result according to a second rotation factor to obtain a second transformation result, wherein the second transformation result includes J×J third data; The fourth storage module is configured to store the J 2 The second data array corresponds to J 4 The third data.

10. A number theoretic transformation (NTT) method, characterized in that: The method comprises: Store J in the first storage module 4 First data, wherein the J 4 The first data is divided into J 2 first data arrays, each first data array includes J×J first data, where J is a positive integer; Based on each of the first data arrays, performing an NTT operation in a first operation module to obtain a first operation result; transforming the first operation result in a first rotation module according to a first rotation factor to obtain a first transformation result, wherein the first transformation result includes J×J second data; The second storage module stores the J 2 The first data array corresponds to J 4 The second data.

11. The method according to claim 10, characterized in that The first operation module includes a plurality of butterfly transformation units, and the plurality of butterfly transformation units are connected in cascade.

12. The method according to claim 11, characterized in that The number of the plurality of butterfly transformation units is log2J.

13. The method according to claim 11, characterized in that The first plurality of butterfly transformation units each include a FIFO buffer; Among the two adjacent butterfly transformation units among the plurality of butterfly transformation units, the depth of the FIFO buffer of the previous butterfly transformation unit is twice the depth of the FIFO buffer of the next butterfly transformation unit.

14. The method according to any one of claims 10 to 13, characterized in that The method further comprises: Store J in the third storage module 4 Second data, wherein the J 4 The second data is divided into J 2 second data arrays, each second data array including J×J second data; Based on each of the second data arrays, performing an NTT operation in a second operation module to obtain a second operation result; transforming the second operation result in a second rotation module according to a second rotation factor to obtain a second transformation result, wherein the second transformation result includes J×J third data; The fourth storage module stores the J 2 The second data array corresponds to J 4 The third data.

15. An electronic device, characterized in that: The electronic device includes the NTT circuit according to any one of claims 1 to 9.

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