Register allocation method and electronic device

Abstract

The present application discloses a register allocation method and an electronic device. The method comprises: an electronic device may acquire a plurality of instructions, the plurality of instructions comprising at least one first instruction and at least one second instruction, the first instruction operating consecutive registers, and the at least one second instruction being an instruction other than the at least one first instruction among the plurality of instructions; allocating, to an i-th parameter in the first instruction, a target register corresponding to the i-th parameter, the first instruction comprising n parameters, n being a positive integer greater than 1, i being a positive integer not greater than n, and each parameter among the n parameters uniquely corresponding to a target register; and, after allocating the register to the parameter in the at least one first instruction, allocating a register to a parameter in at least one second instruction. According to the method, the number of move instructions generated in the process of allocating the register to the parameter in the first instruction (i.e., a range instruction) is reduced, so that the volume of an application installation package generated on the basis of the first instruction is reduced.

Description

Register allocation method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 7, 2024, with application number 202410175852.8, and priority to the Chinese patent application entitled “A Register Allocation Method and Electronic Device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of terminal technology, and in particular to a register allocation method and an electronic device. Background Art

[0003] Computer files are generally stored in binary format. With the increasing demand for compatibility between different programming languages ​​and architectures, virtual machine technology has emerged, such as Oracle's Java Virtual Machine (JVM) and Google's Android Runtime (ART). Existing virtual machine compilers convert application source code into a binary file (also known as a bytecode file). A virtual machine is an executable program on a smart device (such as a mobile phone, smartwatch, or tablet). It takes a bytecode file as input and executes the instructions contained in it.

[0004] Among the instructions in bytecode files, many require contiguous registers as operands. These instructions are called range instructions (range instructions for short). The number of bytecode instructions directly affects the size of the application installation package and the performance of the application on the terminal. Currently, when registers are allocated to range instructions, the operands used are unconditionally copied to temporary contiguous registers using move instructions. This results in an excessive number of bytecode instructions, which in turn leads to a large application installation package. Summary of the Invention

[0005] The present application discloses a register allocation method and an electronic device, which can reduce the number of move instructions generated in the process of allocating registers to parameters in a range instruction, thereby avoiding an excessively large size of an application installation package generated based on the range instruction.

[0006] The present application is introduced below from different aspects. It should be understood that the implementation methods and beneficial effects of the following different aspects can be referenced to each other.

[0007] In a first aspect, the present application discloses a register allocation method, which may include: obtaining multiple instructions, the multiple instructions including at least one first instruction and at least one second instruction; the first instruction operates on consecutive registers; the at least one second instruction is an instruction in the multiple instructions other than the at least one first instruction; allocating a target register corresponding to the i-th parameter to the i-th parameter in the first instruction, the first instruction including n parameters, n is a positive integer greater than 1, i is a positive integer not greater than n, and each of the n parameters uniquely corresponds to a target register; after allocating registers to the parameters in the at least one first instruction, allocating registers to the parameters in the at least one second instruction.

[0008] The embodiment of the present application preferentially allocates registers to the parameters in the first instruction among multiple instructions, and then allocates registers to the parameters in the instructions other than the first instruction among the multiple instructions (i.e., the second instruction mentioned above), so that the optional range of registers to which the parameters of the first instruction can be allocated is larger, and the operation of copying the parameters in the first instruction from the original register to other registers can be reduced, that is, the number of copy instructions (which can be called move instructions) generated thereby is reduced, thereby reducing the size of the application installation package generated based on the above multiple instructions.

[0009] In some embodiments of the present application, the above-mentioned instructions can be called bytecode instructions, and the above-mentioned multiple instructions can be intermediate representations (IR) obtained by parsing the source code of the application; the meaning of the first instruction operating on consecutive registers can be: the first instruction is an instruction with consecutive registers as operands; the first instruction can also be called a range instruction, and the above-mentioned second instruction can be called a non-range instruction.

[0010] In combination with the first aspect, in a possible implementation, the method further includes: when traversing the first instruction, determining the allocated registers corresponding to the parameters in the n parameters and the registers to which the parameters are not allocated in the pending registers; the pending registers are registers that can be allocated by multiple instructions; based on the allocated registers corresponding to the parameters in the n parameters and the registers to which the parameters are not allocated in the pending registers, determining the target registers corresponding to the n parameters; wherein the target register corresponding to the i-th parameter is the register to which the parameters are not allocated, or the target register corresponding to the i-th parameter is the allocated register corresponding to the i-th parameter.

[0011] In an embodiment of the present application, when traversing the first instruction, the target register corresponding to the parameter in the first instruction can be determined based on the current allocation of registers to be processed and the current allocation of parameters in the first instruction. This method can avoid the problem of excessively large move instructions caused by unconditionally using move instructions to copy the used operands to temporary continuous registers, and can reduce the number of move instructions.

[0012] The allocation status of the currently processed registers may specifically refer to whether each register in the pending registers has been assigned parameters after traversing the previous first instruction. Registers that have been assigned parameters may be called active registers. The currently active registers may be represented by an active set, which may include the numbers and values ​​of the active registers. It should be understood that if the first instruction is the first instruction traversed, then the currently processed registers may be in an initial state, e.g., each register in the pending registers has not been assigned parameters and is therefore not an active register.

[0013] In an embodiment of the present application, if the target register corresponding to the i-th parameter is a register to which no parameter is assigned, there are two cases: the first case is that the i-th parameter is a parameter to which no register is assigned, then no move instruction needs to be generated for the parameter; the second case is that the i-th parameter is a parameter to which a register has been assigned, then, assuming that the register assigned to the i-th parameter is different from its target register, then a move instruction corresponding to the i-th parameter needs to be generated; assuming that the register assigned to the i-th parameter is the same as its target register, then no move instruction needs to be generated. If the target register corresponding to the i-th parameter is the assigned register corresponding to the i-th parameter, then no move instruction needs to be generated. In this method, compared to unconditionally using the move instruction, it is possible to avoid generating move instructions in the above-mentioned multiple cases, thereby reducing the number of generated move instructions.

[0014] In combination with the first aspect, in a possible implementation, the above-mentioned determining the target registers corresponding to the n parameters based on the allocated registers corresponding to the parameters in the n parameters and the registers to be processed that are not allocated parameters includes: when traversing the first instruction, determining a first set from the registers to be processed, the first set is used to indicate at least one first register, and the target registers corresponding to the first registers all satisfy: the target registers corresponding to the first registers are continuous registers, the target registers corresponding to the first registers have a one-to-one correspondence with the n parameters, and the target register corresponding to the i-th parameter is a register to which no parameter is allocated or an allocated register corresponding to the i-th parameter; determining a first starting register from the first set, each register in the first set uniquely corresponds to a first value, the first value corresponding to the first starting register is the smallest of the first values ​​corresponding to at least one first register, the first value is the number of first parameters in the n parameters, the first parameter is a parameter of the allocated register, and the allocated register corresponding to the first parameter is different from the target register corresponding to the parameter; the first starting register is the target register corresponding to the first parameter executed in the first instruction; wherein the target register corresponding to the first starting register is the target register corresponding to the n parameters.

[0015] In an embodiment of the present application, the above-mentioned first set ensures that the parameters of unallocated registers will only be allocated to unallocated registers, and not to registers to which other parameters have been allocated. This can avoid the generation of move instructions when the parameters of unallocated registers are allocated to registers to which other parameters have been allocated, thereby reducing the number of move instructions.

[0016] In some embodiments of the present application, the above-mentioned first set can be a set P (or a set of starting registers), and the set P is a set of first register (also called starting register) number values ​​x; the first register can be called a starting register or a starting register, and the first starting register can also be called a target starting register; the above-mentioned first parameter can be called a conflict parameter, and the above-mentioned first value can be the number of conflict parameters.

[0017] Optionally, when traversing the first instruction, the parameter positions of the parameters in the first instruction can be numbered according to the execution order of the parameters in the first instruction. The parameter position of the first executed parameter can be the first parameter position (such as the parameter position can be represented as parameter position i=0). Since the first starting register is the target register corresponding to the first executed parameter in the first instruction, the first starting register is the target register corresponding to the parameter at parameter position i=0. Since the parameter positions in the first instruction correspond to the parameters one-to-one, the above-mentioned first numerical value can also be the number of parameter positions of the conflicting parameters.

[0018] For example, when traversing the first instruction, a set L(x) corresponding to each first register x in set P can be constructed. L(x) is the set of parameter positions i in set Q where x+i≠yi, where set Q is the set of parameter positions i of the parameters of the allocated registers in the range instruction. x+i≠yi means that the allocated register yi of the parameter of the allocated register is different from the target register x+i of the parameter, and the parameter corresponding to parameter position i is a conflicting parameter. Therefore, the absolute value of L(x) |L(x)| is the number of parameter positions of the conflicting parameters corresponding to the first register x, that is, the first value corresponding to the first register x. Furthermore, the first register corresponding to the number x that minimizes the number of elements in L(x), that is, the smallest |L(x)|, is determined as the first starting register.

[0019] In combination with the first aspect, in a possible implementation, the method further includes: based on the target register corresponding to the first starting register, assigning the target register corresponding to the j-th parameter to the j-th parameter in the first instruction, j is a positive integer not greater than n, the j-th parameter is a parameter to which a register is not assigned among the n parameters, and the target register corresponding to the first register includes the target register corresponding to the j-th parameter.

[0020] In an embodiment of the present application, after determining the first starting register of the first instruction, the target register corresponding to each parameter in the first instruction (i.e., the target register corresponding to the first starting register) can be determined; then, the target register corresponding to the parameter is assigned to the parameter in the first instruction that is not assigned a register. Because the above first set ensures that parameters of unassigned registers are only assigned to unassigned registers, this method can avoid the generation of move instructions when parameters of unassigned registers are assigned to registers that have other assigned parameters, thereby reducing the number of move instructions.

[0021] In combination with the first aspect, in a possible implementation, the parameters of the allocated registers among the n parameters include the kth parameter, where k is a positive integer not greater than n. The method further includes: when the target register corresponding to the kth parameter and the allocated register corresponding to the kth parameter are different, generating a third instruction corresponding to the kth parameter, and the third instruction corresponding to the kth parameter is used to copy the kth parameter from the allocated register corresponding to the kth parameter to the target register corresponding to the kth parameter.

[0022] In some embodiments of the present application, the third instruction may also be called a move instruction.

[0023] For example, for a parameter of an allocated register (such as the kth parameter mentioned above), assuming that the parameter position of the parameter is i, the allocated register yi of the parameter is different from the target register x+i, and the allocated register yi needs to be copied to the target register x+i. The third instruction corresponding to the parameter that can be generated (i.e., the move instruction) can be: Mov x+i,yi.

[0024] In combination with the first aspect, in one possible implementation, the n parameters include m second parameters, the second parameters are parameters to which registers are not allocated, and m is an integer greater than 1 and not greater than n; the first parameter to which a register is allocated among the m second parameters is parameter j, and the method further includes: generating a third instruction corresponding to the p-th parameter, the p-th parameter being a parameter other than parameter j among the m second parameters, p being a positive integer not greater than m, and each of the n parameters uniquely corresponding to a target register; the third instruction corresponding to the p-th parameter is used to copy parameter j from the target register corresponding to parameter j to the target register corresponding to the p-th parameter.

[0025] In some embodiments of the present application, the second parameter may also be referred to as a repeat parameter. For example, for a repeat parameter that does not have a register assigned to it (such as the second parameter described above), the repeat parameter may first be assigned to the target register x+j corresponding to the first parameter position j; then, the repeat parameter (such as the parameter j described above) needs to be copied from the target register x+j at the first parameter position j to the target register x+i corresponding to the repeat parameter's non-first parameter position i (such as the parameter position where the p-th parameter is located). The move instruction generated for the parameter position i may be: Mov x+i,x+j.

[0026] In one implementation, for the case of repeated parameters with unallocated registers (such as the second parameter mentioned above), Repeated(i) corresponding to each parameter except parameter j in the m second parameters can be constructed, Repeated(i) = minimal j, where i is the parameter position of each parameter except parameter j in the m second parameters, and minimal j is the parameter position of parameter j; and then, a move instruction corresponding to each parameter except parameter j in the m second parameters is generated.

[0027] In combination with the first aspect, in a possible implementation, the parameters in the above-mentioned first instruction may include the above-mentioned conflicting parameters and repeated parameters, and the move instruction generated for the first instruction may include the above-mentioned move instruction generated for the conflicting parameters and the above-mentioned move instruction generated for the repeated parameters.

[0028] In combination with the first aspect, in one possible implementation, registers are assigned to parameters in at least one second instruction, including: constructing a second set for the qth parameter in at least one second instruction, the second set being used to indicate a second register, and the second register satisfying: the second register is a register to which parameters have been assigned or a register in a third instruction corresponding to parameters in multiple instructions, and the active interval of the second register intersects with the active interval of the qth parameter; selecting a third register from the registers to be processed except the registers in the second set; and assigning the qth parameter to the third register.

[0029] In the embodiment of the present application, registers can be allocated to the parameters in the first instruction before the parameters in the second instruction are allocated to registers, thereby ensuring the normal execution of the register allocation of the parameters in the second instruction.

[0030] In some embodiments of the present application, the second set may be set A, the elements of which are the numerical numbers of the target registers to which the parameters of the unallocated registers are to be allocated, such as the numerical number x+i of the target register to which the parameters of the unallocated register at parameter position i are to be allocated.

[0031] In combination with the first aspect, in a possible implementation, multiple instructions are a first intermediate expression IR obtained by parsing the source code of the first application. The method also includes: adding a third instruction corresponding to the parameters in the multiple instructions to the first IR to obtain a second IR; based on the second IR, generating a bytecode file of the first application, and the bytecode file of the first application is used to run the first application.

[0032] The embodiment of the present application can reduce the number of move instructions in the IR corresponding to the first application, thereby reducing the size of the application installation package of the first application.

[0033] In a second aspect, the present application provides an electronic device. The electronic device may include a memory and a processor. The memory may be used to store a computer program. The processor may be used to invoke the computer program, causing the electronic device to execute the first aspect or any possible implementation of the first aspect.

[0034] In a third aspect, the present application provides a computer program product comprising instructions, which, when run on an electronic device, enables the electronic device to execute the first aspect or any possible implementation of the first aspect.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium comprising instructions. When the instructions are executed on an electronic device, the electronic device is caused to perform the first aspect or any possible implementation of the first aspect. The technical effects achieved by the above-mentioned various aspects can be referenced to each other or to the beneficial effects of the method embodiments shown below, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1A is a schematic diagram of a compilation process provided in an embodiment of the present application;

[0037] FIG1B is a schematic diagram of another compilation process provided in an embodiment of the present application;

[0038] FIG1C is a schematic diagram of a virtual machine executing instructions in a bytecode file provided by an embodiment of the present application;

[0039] FIG2A is a schematic diagram of an active interval after parameter sorting to be allocated provided in an embodiment of the present application;

[0040] FIG2B is a schematic diagram of a register state after parameter allocation provided by an embodiment of the present application;

[0041] FIG3A is a schematic diagram of the system architecture of a register allocation system provided in an embodiment of the present application;

[0042] FIG3B is a schematic diagram of an application scenario exemplarily provided in an embodiment of the present application;

[0043] FIG4A is a flow chart of a register allocation method exemplarily provided in an embodiment of the present application;

[0044] FIG4B is a flow chart of another register allocation method exemplarily provided in an embodiment of the present application;

[0045] FIG4C is a schematic diagram of a process for determining a target start register according to an embodiment of the present application;

[0046] FIG5 is a schematic diagram of an active interval after parameter sorting before unallocated registers provided by an embodiment of the present application;

[0047] FIG6 is a schematic diagram of a first allocation flow of registers provided in an embodiment of the present application;

[0048] FIG7 is a schematic diagram of an active interval after the first allocation provided by an embodiment of the present application;

[0049] FIG8 is a schematic flow chart of a method for second allocation provided in an embodiment of the present application;

[0050] FIG9 is a schematic diagram of an active interval after the second allocation provided by an embodiment of the present application;

[0051] FIG10 is a schematic diagram of a third allocation process according to an embodiment of the present application;

[0052] FIG11 is a schematic diagram of an active interval after the third allocation provided by an embodiment of the present application;

[0053] FIG12 is a schematic diagram of an active interval when a parameter other than a range instruction exists, provided by an embodiment of the present application;

[0054] FIG13 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0056] In the description of this application, words such as "first" and "second" are used only to distinguish different objects and do not limit the quantity or execution order. Moreover, words such as "first" and "second" do not necessarily mean different. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to the process, method, product, or device.

[0057] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one (item)", "the following one (item) or more (items)" or similar expressions refer to any combination of these items, including any combination of single or plural items (items). For example, at least one item (item) of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a, b, and c. Among them, a, b, and c can be single or multiple.

[0058] In the description of this application, words such as "exemplary" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described in this application as "exemplary," "for example," or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete way.

[0059] It should be understood that in the description of this application, the terms "when," "if," and "if" all refer to the device performing a corresponding action under certain objective circumstances. They do not limit the time, do not require the device to perform a judgment action during implementation, and do not imply any other limitations. Specifically, "the device performing a corresponding action under certain objective circumstances" includes: the device performing the corresponding action under certain objective circumstances can perform the corresponding action only if the objective circumstances are met; or the device performing the corresponding action can perform the corresponding action only if the objective circumstances and other circumstances are met.

[0060] The term "simultaneously" in this application may be understood as at the same time point, within a period of time, or within the same cycle, and may be understood in conjunction with the context.

[0061] Elements used in the singular herein are intended to mean "one or more" rather than "one and only one" unless specifically stated otherwise.

[0062] Additionally, the terms "system" and "network" are often used interchangeably herein.

[0063] It should be understood that in the various embodiments of the present application, "A corresponds to B," "A corresponds to B," "A corresponds to B," or similar expressions indicate that B is associated with A and B can be determined based on A. Determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0064] In order to facilitate understanding of the technical solutions of the embodiments of the present application, a brief introduction to the relevant technologies and terms of the present application is first given.

[0065] 1. range instruction

[0066] The range instruction differs from a regular instruction in that it operates on consecutive registers. Therefore, you only need to specify the number of operands and the register number of the first operand, without having to specify each register number. The range instruction is useful when the instruction has more than four parameters, effectively reducing instruction length.

[0067] The basic structure of the range instruction includes: the instruction code (opcode), the number of operands (numArgs), and the register number of the first operand (firstReg), indicating that this instruction uses registers firstReg, firstReg+1, ..., firstReg+numArgs-1 as operands.

[0068] Taking the dex bytecode instruction set of the Android virtual machine as an example, there are two main range instructions:

[0069] (1) Instructions for constructing an array (filled-new-array.range), such as instructions generated based on int[]arr={1,2,3,4,5,6} in the source code;

[0070] (2) Function call instructions for all scenarios, such as invoke-virtual.range for virtual function calls, invoke-super.range for parent class method calls, invoke-direct.range for static method calls, etc.

[0071] Since the range instruction requires the registers of the operands to be continuous, during the register allocation stage of the compilation process, whenever a range instruction is encountered, a move instruction must be executed for each operand corresponding to the range instruction to temporarily copy the operands (such as parameters) to continuous registers. This will generate a large number of move instructions, which will significantly increase the number of bytecode instructions.

[0072] 2. Compile

[0073] Compilation refers to the conversion or translation of one file (source file or source code) into another file (target file).

[0074] As shown in Figure 1A, the compilation process is divided into the following four steps:

[0075] (1) Parsing (parser:) parses the source file into an intermediate representation IR, which can also be called an intermediate representation;

[0076] (2) Optimization: various optimizations are performed on IR, such as dead code elimination, loop unrolling, function inlining, code sinking, etc.

[0077] (3) Register allocation: Allocate registers for parameters in IR;

[0078] (4) Emitter: Generates the target file according to the format of the target file after optimizing the IR.

[0079] Exemplarily, the source file may be the source code of the application, the target file may be a bytecode file, and the virtual machine compiler may compile the source code of the application into a bytecode file. Figures 1B and 1C exemplarily illustrate the contents of a portion of the source code and a portion of the bytecode file. As shown in Figure 1B , the virtual machine compiler may convert the source code of the application into a binary file (i.e., a bytecode file); the virtual machine is an executable program on a smart terminal (such as a mobile phone, smart watch, tablet, etc.), as shown in Figure 1C , the virtual machine takes the bytecode file as input and executes the instructions in the bytecode file.

[0080] Currently, the most commonly used register allocation algorithm is the linear scan algorithm. This algorithm first numbers the instructions in the intermediate representation (IR) in a certain order, where the instructions in the intermediate representation (IR) include range instructions and non-range instructions. A live interval is set for each parameter in each instruction. The live interval of a parameter [i, j] is the instruction number from the beginning to the end of the parameter's use, where i is the number of the first instruction that uses the parameter and j is the number of the last instruction that uses the parameter. The algorithm's flow is as follows:

[0081] S101: Sort the active intervals of the parameters to be assigned in ascending order based on the starting number i of the active interval of each parameter. That is, the smaller the starting number i of the active interval of the parameter, the higher the ranking of the active interval of the parameter.

[0082] Figure 2A illustrates the sorted active intervals of parameters a, b, c, d, e, and f to be assigned. The instruction numbers are ordered from left to right, with nine instructions listed in sequence. Gray rectangles represent active intervals, and the active intervals of parameters are in ascending order from top to bottom. That is, the smaller the starting number i of the parameter's active interval, the higher the ranking of the parameter's active interval.

[0083] As shown in Figure 2A, the active interval of parameter a is [1,7], that is, the starting number of parameter a is 1, and the starting number is the first number in ascending order. Therefore, the active interval of parameter a is ranked first and is arranged in the first row from top to bottom in Figure 2A; the active interval of parameter b is [2,7], that is, the starting number of the active interval of parameter b is 2, and the starting number is the second number in ascending order. Therefore, the active interval of parameter b is ranked second and is arranged in the second row from top to bottom in Figure 2A; and so on.

[0084] S102: Based on the active interval of the parameter, allocate registers to each parameter in sequence according to the order.

[0085] For example, the active intervals shown in FIG2A can be scanned, and free registers can be allocated to the active interval of each parameter in order, and the registers of the allocated parameters can be added to the active set; if the end point of the active interval of a parameter in the current active set is less than or equal to the starting point of the current active interval, it indicates that the parameter is no longer active. At this time, the register of the parameter is removed from the active set, that is, the register allocated to the parameter is released.

[0086] Taking Figure 2A as an example, each time one interval is scanned, the process of the linear scanning algorithm is as follows:

[0087] Step a: Add a to the active set and assign register v1 to a. Now active = {a(v1)};

[0088] Step b: Add b to the active set and assign register v2 to b. Now active = {a(v1), b(v2)};

[0089] Step c: Add c to the active set and assign register v3 to c. Now active = {a(v1), b(v2), c(v3)};

[0090] Step d: Add d to the active set and assign register v4 to d. Now active = {a(v1), b(v2), c(v3), d(v4)}.

[0091] Step e: Since the end point of c is less than or equal to the starting point of e, c is inactive. Remove c from the active set, freeing register v3. At the same time, add e to the active set. At this point, active = {a(v1), b(v2), d(v4), e(v3)};

[0092] Step f: Since the end points of a, b, and d are smaller than the starting point of f, remove a, b, and d from the active set, freeing registers v1, v2, and v4. At the same time, add f to the active set. At this point, avtive = {e(v3), f(v1)};

[0093] Step g: The traversal ends, and each parameter is assigned to the corresponding register.

[0094] Figure 2B exemplarily shows the registers assigned to parameters a, b, c, d, e, and f. As shown in Figure 2B, the register assigned to parameter a is register v1, the register assigned to parameter b is register v2, the register assigned to parameter c is register v3, the register assigned to parameter d is register v4, the register assigned to parameter e is register v3, and the register assigned to parameter f is register v1.

[0095] Existing register allocation technology does not take into account the optimization of range instructions. Therefore, when encountering a range instruction, it will unconditionally use move instructions to copy the operands to temporary continuous registers. For example, when targeting FunctionCall(a,b,c,d,e,f), the compiler will generate a corresponding move instruction for each parameter. For example, the move instructions corresponding to each parameter are: move-objetv0,v6; move-objetv1,v7; move-objetv2,v8; move-objetv3,v9; move-objetv4,v10; move-objetv5,v11. It can be seen that variables a to f are already stored in the continuous registers v6 to v11, but at this time the compiler will still use move instructions to reassign a to f to the continuous registers v0 to v5, resulting in unnecessary move instructions.

[0096] It should be understood that too many move instructions will significantly increase the size of the bytecode file and the installation package volume, affecting the user's willingness to download, install and update the application. The larger the installation package size, the weaker the user's willingness; in addition, too many unnecessary move instructions will degrade performance.

[0097] The present application provides a register allocation method and electronic device, which reduces unnecessary move instructions by preferentially allocating registers to range instructions.

[0098] The present application can also determine the target register corresponding to each parameter in the range instruction from the pending registers based on the register allocation of the parameters in the range instruction and the allocation of the pending registers, with the number of differences between the target register corresponding to each parameter and the registers already allocated for that parameter being the smallest among all pending registers. This method can minimize the number of move instructions generated for the range instruction.

[0099] This application also provides an optimization solution for scenarios where there are identical parameters in multiple range instructions, such as scenarios where multiple range instructions include foo(a,b,c) and bar(c,b,a), thereby reducing the number of move instructions in such conflicting scenarios. For example, the parameters a, b, and c in foo(a,b,c) are assigned to consecutive registers v0, v1, and v2 respectively; when assigning parameters to bar(c,b,a), the three parameters are assigned registers v2, v1, and v0 respectively. At this time, the registers assigned to the parameters in bar(c,b,a) are non-continuous, and a move is required, which is a conflicting scenario. The embodiment of this application can determine the situation where the assigned registers have the least conflict with the target registers. For details, see below (such as step S4042 below), thereby generating the least number of move instructions. For example, in the above scenario of foo(a,b,c) and bar(c,b,a), only two move instructions (i.e., mov v3v1 and mov v4v0) are required.

[0100] The electronic device may specifically be an electronic device with a compilation function, such as a compiler, a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc. Exemplary embodiments of the electronic device include but are not limited to a computer equipped with Portable electronic devices and desktop computers running Linux or other operating systems, etc.

[0101] The following uses an electronic device as a compiler as an example to introduce the system and application scenarios of the register allocation method provided in this application.

[0102] Please refer to FIG3A , which is a schematic diagram of the system architecture of a register allocation system provided in an embodiment of the present application.

[0103] As shown in Figure 3A, the system architecture may include a compiler 301 and a terminal device 302. The compiler 301 is used to compile source code into a bytecode file; and the terminal device 302 is used to execute the bytecode file.

[0104] In the present application, the compiler can parse the source code into IR; perform various optimizations on the IR, such as dead code elimination, loop unrolling, function inlining, code sinking, etc.; allocate registers for the parameters in the IR, which may specifically include prioritizing register allocation for the range instruction. The specific process can be seen in the embodiments shown in Figures 4A to 12 below; and then, generate a bytecode file according to the format of the target file using the IR obtained by allocating registers.

[0105] FIG3B is a schematic diagram of an application scenario exemplarily provided in an embodiment of the present application.

[0106] As shown in Figure 3B, the application developer compiles the application source code into a bytecode file through a compiler 301, packages the bytecode file and other files (such as images, text, audio, video, etc.) into an application installation package, and then publishes the application installation package to the application platform. For example, the source code of the first application can be compiled by the compiler 301 to obtain the bytecode file of the first application; the application installation package obtained based on the bytecode file of the first application is the application installation package of the first application. Then, the user downloads the application installation package on the application platform, and the terminal device 302 parses the bytecode file from the installation package and starts the virtual machine to execute the bytecode file, thereby completing the startup and operation of the application. For example, the user downloads the application installation package of the first application on the application platform, and the terminal device 302 parses the bytecode file of the first application from the installation package and starts the virtual machine to execute the bytecode file, thereby obtaining the execution result of the first application.

[0107] The register allocation method provided in this application can be applied to the register allocation stage in the compilation process of a compiler (such as the register allocation stage in FIG. 1A ).

[0108] Next, the overall process of the register allocation method provided by this application is introduced with reference to FIG. 4A .

[0109] As shown in the figure below, the method shown in FIG4A can be applied to the register allocation stage.

[0110] S401: The compiler numbers N instructions in the order of execution to obtain numbers of the N instructions, where the N instructions include range instructions and non-range instructions, and N is a positive integer.

[0111] The N instructions include at least one range instruction and at least one non-range instruction.

[0112] In some embodiments, the electronic device can parse the source file into an intermediate expression form IR; perform various optimizations on the IR, such as dead code elimination, loop expansion, function inlining, code sinking, etc., to obtain an optimized intermediate expression form, which includes the above-mentioned N instructions.

[0113] In other embodiments, the electronic device may parse the source file into an intermediate expression form, where the intermediate expression form includes the N instructions mentioned above.

[0114] Optionally, the source file may be source code of an application.

[0115] S402: The compiler generates active ranges of parameters in the N instructions based on the numbers of the N instructions.

[0116] Among them, at least one instruction among the N instructions includes at least one parameter. It should be understood that the instructions among the N instructions may include parameters or may not include parameters; the parameters among the N instructions above refer to all parameters in the N instructions.

[0117] In some embodiments, the compiler may generate an active range for each parameter in the N instructions, and obtain an active range for each parameter in all the parameters in the N instructions.

[0118] Optionally, if a parameter appears in multiple positions in N instructions, the active interval of the parameter may be generated only once.

[0119] The live interval of a parameter is the instruction number from the start of use to the end of use of the parameter. For example, as shown in FIG2A , the instruction numbers for using parameter a are 1 to 7, and the live interval of parameter a is [1, 7].

[0120] S403: The compiler sorts the active intervals of the parameters in the N instructions to obtain sorted active intervals.

[0121] In some embodiments, the compiler may sort the active intervals of a parameter in the order of the instruction number of the instruction that starts using the parameter (i.e., the first instruction that uses the parameter), and the earlier the instruction number of the instruction that starts using the parameter, the earlier the active interval of the parameter is sorted. For example, if the order of the instruction numbers is in ascending order from small to large, then the order of the active intervals may also be in ascending order from small to large, and the smaller the value, the earlier the order; assuming that the order is from top to bottom in the figure, then the order from front to back can be reflected in the figure as from top to bottom.

[0122] For example, the active interval of a parameter is denoted as [i, j]. The compiler can sort the active intervals of the parameters in N instructions in ascending order based on the starting number i of the active intervals of the parameters. Taking Figure 2A as an example, the starting number i of parameter a is 1, the starting number i of parameter b is 2, the starting number i of parameter c is 3, and the starting number i of parameter d is 4. Then the order of the active intervals of the parameters is active interval of parameter a, active interval of parameter b, active interval of parameter c, and active interval of parameter d, which is the order of the active intervals of the parameters from top to bottom in Figure 2A.

[0123] S404: The compiler allocates registers to the parameters of the range instruction in the N instructions based on the sorted active ranges.

[0124] In some embodiments, the compiler may first scan the range instruction during the register allocation phase and preferentially allocate registers to the parameters of the range instruction.

[0125] Optionally, when N instructions include multiple range instructions, the compiler may allocate registers for the parameters in the range in sequence according to the execution order of the range instructions. For example, the range instructions in the N instructions include funcA(a,b,c,d), funcB(d,a,b,e), and funcC(f,e,f,e), and the execution order of these three range instructions is funcA(a,b,c,d), funcB(d,a,b,e), and funcC(f,e,f,e). Then, the compiler may first allocate registers for funcA(a,b,c,d), then allocate registers for funcB(d,a,b,e), and finally allocate registers for funcC(f,e,f,e).

[0126] For example, assume that for any range instruction, such as bar(arg0, arg1, ..., argN), where arg0, arg1, ..., argN are the parameters in the range instruction and y0-yN are the registers allocated for the parameters, when the instruction is traversed, the status of registers yi (i = 0-N) may be unallocated (undefined) or allocated (active). It is necessary to find a suitable starting register number x that minimizes the number of move instructions.

[0127] In one implementation, the compiler may sequentially execute steps S4041 to S4044 on all range instructions as shown in FIG4B . The following description will be made using an example of traversing a range instruction.

[0128] S4041: Based on the sorted active interval, update the registers in the original active set to obtain the current active set. The current active set is used to indicate the registers to which parameters have been allocated when traversing the current range instruction.

[0129] Among them, the original active set is the active set obtained after traversing the previous range instruction, and the registers indicated by the original active set are the registers that have been assigned parameters when traversing the previous range instruction; the current active set is used to indicate the current active registers, and the current active registers are the registers corresponding to the parameters in the active range when traversing the range instruction currently.

[0130] In one implementation, the compiler can determine whether the parameters corresponding to the registers in the original active set are still in the active range for the currently traversed range instruction based on the sorted active range. If the parameters are still in the active range for the currently traversed range instruction, the registers assigned to the parameters are still active registers; if the parameters are not in the active range for the currently traversed range instruction, the registers assigned to the parameters are inactive registers; the inactive registers are removed from the original active set to obtain the current active set.

[0131] Exemplarily, the active set after traversing the previous range instruction is active = {0, 1, 2, 3}, where 0, 1, 2, and 3 are the identifiers of four registers (such as the number values ​​of the registers); assuming that the next range instruction is the current range instruction, then, when targeting the current range instruction, the compiler can determine whether the parameters in the original active set are still in the active interval based on the active interval of the parameters in the original active set when targeting the current range instruction. If the parameters are still in the active interval when targeting the current range instruction, the register assigned to the parameters is still the active register; if the parameters are not in the active interval when targeting the current range instruction, the register assigned to the parameters is the inactive register; if the parameters of the register corresponding to 2 are not in the active interval when targeting the current range instruction, 2 is removed from the active set, and the current active set is active = {0, 1, 3}.

[0132] S4042: Based on the current active set, determine the target start register number so that the number of move instructions is minimized.

[0133] Exemplarily, as shown in FIG4C , the specific implementation of step S4042 may include the following steps S1 to S4 .

[0134] Step S1: Determine the parameters of the allocated registers and the parameters of the unallocated registers in the range instruction.

[0135] In one implementation, a set Q and a set QC may be constructed based on whether registers are allocated to parameters in a range instruction. Set Q is the set of parameter positions i for parameters that have been allocated registers (referred to as allocated parameters) in the range instruction; and set QC is the set of parameter positions i for parameters that have not been allocated registers in the range instruction.

[0136] It should be understood that the range instruction may include parameters that are allocated registers and / or parameters that are unallocated registers.

[0137] In this application, the set Q can also be expressed as: Q = {i|yi is not undefined}; the set QC can also be expressed as: QC = {i|yi is undefined}. Where yi is the allocated register corresponding to parameter position i, Q = {i|yi is not undefined} means that the register yi corresponding to parameter position i in the set Q is not unallocated, that is, the parameter allocated register corresponding to parameter position i is yi; QC = {i|yi is undefined} means that the register yi corresponding to parameter position i in the set QC is unallocated, that is, the parameter corresponding to parameter position i is not allocated a register.

[0138] Step S2: Determine a set of start registers, where the target registers corresponding to the start registers satisfy the following conditions: the target registers corresponding to the start registers correspond one-to-one to each parameter position in the range instruction, and the target registers corresponding to each parameter position in the range instruction are either the registers that have been allocated to the parameter position or the registers that have not been allocated parameters.

[0139] In some embodiments, a set P of starting registers is constructed, where set P is a set of starting register number values ​​x, where x needs to satisfy a preset condition: x+i=yi, or x+i is the number value of an unassigned register, yi is the number value of the register assigned to parameter position i, and x+i is the number value x+i of the target register corresponding to parameter position i when x is the starting register.

[0140] It should be understood that if no parameter is assigned to register x+i, register x+i is an unassigned register. Furthermore, the relationship between a register number and its numerical value is as follows: if the register number is vp, then the register numerical value x=p, where p is a positive number. For example, if p is 1, i.e., the register number is v1, then the register numerical value x=1. In this application, register vp and register p may refer to the same register.

[0141] In some embodiments, the compiler may determine registers to be processed, which may be all registers in the compiler or a portion of registers determined based on a current active set. For example, the range of the portion of registers may be: the register number to be processed is greater than or equal to the minimum register number N in the current active set (N is the number of parameters, and if the result is less than 0, it starts at 0), and less than or equal to the maximum register number + 1 in the current active set, or 0 if the active set is empty. A judgment is performed on each register to determine whether, when the register to be processed is the starting register, the target register corresponding to the starting register satisfies the above-mentioned preset conditions. The target register corresponding to the starting register refers to: assuming that there are a parameters of the range instruction, the target register is the starting register and a-1 consecutive registers after the starting register. For example, if the starting register is v1 and there are a range instructions, the target registers are the a registers from v1 to v2 to va. If the register to be processed satisfies the above-mentioned preset conditions, the register to be processed is determined to be a starting register in set P. If the register to be processed does not satisfy the above-mentioned preset conditions, it is determined that the register to be processed is not the starting register in set P.

[0142] In this application, the set P can also be expressed as: P = {x|for each i in {0,….,N}, either x+i = yi, or x+i is not active}, where {0,….,N} refers to all parameter positions in the range instruction; not active means that the target register x+i is an unassigned register.

[0143] Step S3: Determine the number of conflicting parameters corresponding to each start register in the set P, where the conflicting parameters are parameters whose allocated registers of the parameters allocated registers in the range instruction are different from the target registers of the parameters.

[0144] In some embodiments, a set L(x) can be constructed, where L(x) is the set of parameter positions i in set Q where x+i≠yi, i.e., conflicting scenarios. Here, x is the number of a register in set P; set Q is the set of parameter positions i for parameters assigned registers in a range instruction; and x+i≠yi means that the assigned register yi of the parameter assigned register is different from the target register x+i of the parameter, and the parameter corresponding to parameter position i is a conflicting parameter.

[0145] It should be understood that the number of parameter positions i in L(x) is the number of conflicting parameters. Assuming that conflicting parameters appear repeatedly in the range instruction, then x+i≠yi also occurs at different positions. In this case, the parameters at different positions are considered different conflicting parameters. For example, if parameter a in the range instruction has x+i≠yi at parameter position i=1, and parameter a in the range instruction also has x+i≠yi at parameter position i=2, then they are considered two conflicting parameters.

[0146] In this application, the set L(x) can also be expressed as: L(x) = {i in Q|x+i! = yi}, which means that: L(x) is the set of parameter position i, parameter position i is an element in the set Q (i.e., the parameter at parameter position i has an allocated register yi), and the target register x+i corresponding to parameter position i is not equal to the allocated register yi. It can be understood that based on L(x), a move instruction can be generated to copy the parameter in the allocated register yi to the target register x+i, as detailed in step S7.

[0147] Step S4: Determine the start register with the least number of conflicting parameters in the set of start registers as the target start register.

[0148] In some embodiments, when constructing set P and set L(x), the target starting register number is found in set P so that the number of elements in L(x) is minimized, i.e., the conflict is minimized. The number of elements in L(x) is the number of conflicting parameters.

[0149] S4043: Determine a move instruction based on the target register corresponding to the target start register and the allocated registers for each parameter position in the range instruction.

[0150] Among them, the allocated register of the parameter position refers to the register that has been allocated to the parameter at the parameter position before traversing the current range instruction; the target register corresponding to the target start register has a one-to-one correspondence with the parameter position in the range instruction.

[0151] In some embodiments, for a parameter of an allocated register, if the allocated register yi of the parameter (i.e., the allocated register of the parameter at parameter position i) is different from the target register x+i, a move instruction corresponding to the parameter can be generated, and the move instruction is used to copy the allocated register yi to the target register x+i.

[0152] Optionally, when the range instruction includes a repeated parameter of an unassigned register, a move instruction corresponding to the repeated parameter needs to be generated. It should be understood that for a repeated parameter of an unassigned register, the repeated parameter will first be placed in the target register x+j corresponding to the first parameter position j; then, for the other non-j parameter positions i of the repeated parameter, a move instruction corresponding to the parameter position i needs to be generated, and the move instruction is used to copy the repeated parameter from the target register x+j of the first parameter position j to the target register x+i corresponding to the non-first parameter position i of the repeated parameter. It should be noted that the number of other non-j parameter positions i of the repeated parameter is the number of move instructions that need to be generated for the repeated parameter.

[0153] Optionally, after generating the move instruction, the move instruction may be added to the overflow fill attribute (SpillFill) of the current IR.

[0154] Exemplarily, the execution process of step S4043 may include the following steps S5 to S9.

[0155] Step S5: For the repeated parameters in the range instruction, determine the first parameter position and non-first parameter positions where the repeated parameters are located. Different parameter positions where the repeated parameters are located correspond to different target registers. The target register corresponding to the first parameter position is the first target register assigned to the repeated parameter when traversing the range instruction.

[0156] In some embodiments, the value of parameter position i is determined according to the execution order of the parameters in the range instruction, and the value of parameter position i decreases as the execution order of the parameters increases. For ease of description, the values ​​of the parameter positions in this application are all set according to the above-mentioned value-taking rules; it should be understood that in other embodiments of this application, the value of parameter position i is determined according to other rules, such as the value of parameter position i increases as the execution order of the parameters increases, and this application does not limit this.

[0157] In one implementation, for the case of repeated parameters, Repeated(i) is constructed, and the parameter position minimal j with the smallest value of the repeated parameter before the parameter position i of the repeated parameter is recorded, and it is recorded as Repeated(i)=minimal j.

[0158] Among them, a repeated parameter refers to a parameter that appears in at least two parameter positions in the range instruction; Repeated(i) is used to indicate that the repeated parameter at parameter position i appears before parameter position i.

[0159] Exemplarily, for each parameter, it can be determined whether the parameter is a repeated parameter; if the parameter is not a repeated parameter, Repeated(i) corresponding to the parameter position i of the parameter = undefined; if the parameter is a repeated parameter, the parameter position where the repeated parameter first appears in the range instruction is parameter position minimal j, the parameter position i in the range instruction that is not the first to appear the repeated parameter corresponds to Repeated(i) = minimal j, and the parameter position minimal j corresponds to Repeated(minimal j) = undefined.

[0160] In this application, Repeated(i) can also be expressed as: Repeated(i)=minimal j

[0161] It should be understood that Repeated(i) = undefined corresponds to two situations: the first situation is: the parameter corresponding to the parameter position i is not a repeated parameter; the second situation is: the parameter corresponding to the parameter position i is a repeated parameter, when the parameter position is the first position where the repeated parameter is located.

[0162] ​It should be noted that the number of repeated parameters in the range instruction can be more than 2, such as 3, 4, etc., that is, the same parameter is used in more than two parameter positions in the range instruction. Therefore, the above formula is "minimal j", and there may be other j positions before the parameter position i that are the repeated parameter. For example, the range instruction is funcD(a,b,a,d,a), and the repeated parameter in funcD(a,b,a,d,a) is a, minimal j is 0 (i.e., parameter a first appears at parameter position 0 in funcD(a,b,a,d,a)), Repeated(2) = 0 for parameter position 2, which is the second appearance of parameter a in funcD(a,b,a,d,a), and Repeated(4) = 0 for parameter position 4, which is the third appearance of parameter a in funcD(a,b,a,d,a). Repeated(i) = undefined for other parameter positions i, such as Repeated(0) = undefined for parameter position 0, which is the first appearance of parameter a in funcD(a,b,a,d,a); Repeated(1) = undefined for parameter position 1 of parameter a in funcD(a,b,a,d,a); and Repeated(3) = undefined for parameter position 3 of parameter d in funcD(a,b,a,d,a).

[0163] Step S6: For the repeated parameter to which no register is allocated, determine the target register that is not the first one to which the repeated parameter is allocated when traversing the range instruction.

[0164] In some embodiments, for each repeated parameter to which a register is not allocated in a range instruction, the first parameter position to which the repeated parameter is allocated and the parameter position not to which the repeated parameter is allocated when traversing the range instruction can be determined. The target register corresponding to the first parameter position to which the repeated parameter is allocated is the first target register to which the repeated parameter is allocated when traversing the range instruction, and the target register corresponding to the parameter position not to which the repeated parameter is allocated is the target register not to which the repeated parameter is allocated when traversing the range instruction.

[0165] In one implementation, a set R and a set RC may be constructed.

[0166] Among them, the set R includes the parameter position i in the set QC where Repeated(i) is undefined, the i in the set R is the parameter position i of the parameter of the range instruction that is not allocated a register, and the parameter at the parameter position i is not the non-first parameter position of the repeated parameter (that is, the parameter position of the non-repeated parameter and / or the first parameter position of the repeated parameter); the set RC includes the parameter position i of the repeated parameter of the unallocated register that is not the first allocated register, that is, the set RC is the parameter position i in the set QC except the set R.

[0167] It should be understood that the set of parameter positions of parameters of unallocated registers (i.e., set QC) is subtracted from the set of parameter positions of non-repeated parameters and / or the first parameter position of repeated parameters in the parameter positions of parameters of unallocated registers by the range instruction (i.e., set R), thereby obtaining the set of parameter positions of repeated parameters of unallocated registers that are not the first allocated register (i.e., set RC).

[0168] The set QC is the set of parameter positions i of the parameters of the range instruction that are not assigned registers.

[0169] In this application, the set R can also be expressed as: R = {i in QC|Repeated(i)is undefined}, that is, the parameter position i in the set R is the parameter position i in the set QC that satisfies Repeated(i)is undefined; the set R can also be expressed as: RC = QC–R, that is, the set RC is the set of parameter positions obtained by subtracting the parameter positions in the set R from the parameter positions in the set QC.

[0170] Step S7: For the parameter of the allocated register, if the allocated register of the parameter is different from the target register of the parameter, a move instruction corresponding to the parameter is generated, and the move instruction is used to copy the parameter of the allocated register to the target register.

[0171] It should be understood that step S7 is for the parameter of the allocated register. If the allocated register yi of the parameter is different from the target register x+i, the allocated register yi needs to be copied to the target register x+i.

[0172] In one implementation, for each element in L(x) (i.e., parameter position i to be moved), a move instruction corresponding to parameter position i can be generated based on the allocated register yi corresponding to parameter position i and the target register x+i. This move instruction is used to copy the parameter of the allocated register yi (i.e., the parameter at parameter position i) to the target register x+i, where x in L(x) is the target starting register. It can be understood that the number of each element in L(x) is equal to the number of move instructions generated, that is, for each element in L(x), a corresponding move instruction is generated.

[0173] In this application, the above-mentioned move instructions generated based on L(x) can be represented by the first set. Exemplarily, the first set can be represented as: MoveListInQ(x) = {Mov x+i,yi|i in L(x)}, where x is the target start register, yi is the allocated register for parameter position i in L(x), and x+i is the target register corresponding to parameter position i; Mov x+i,yi means: copy the parameter on register yi (i.e., the parameter corresponding to parameter position i) to the target register x+i.

[0174] Step S8: For the repeated parameter that is not assigned a register, generate a move instruction corresponding to the repeated parameter, which is used to copy the repeated parameter from the first target register assigned the repeated parameter when traversing the range instruction to a target register that is not the first target register assigned the repeated parameter.

[0175] It should be understood that step S8 is for repeated parameters that have not been assigned registers. Since the repeated parameters will first be assigned to the target register x+j corresponding to the first parameter position j; therefore, the repeated parameters need to be copied from the target register x+j of the first parameter position j to the target register x+i corresponding to the non-first parameter position i where the repeated parameter is located.

[0176] In one implementation, a second set can be constructed based on the set RC and Repeated(i), the second set including move instructions corresponding to repeated parameters of unallocated registers. Exemplarily, i in the set RC is the non-first parameter position i of the repeated parameter of the unallocated register; based on Repeated(i)=j, the first parameter position j of the repeated parameter is determined; and for parameter position i, a move instruction can be generated, the move instruction being used to copy the repeated parameter from the target register x+j corresponding to the first parameter position j to the target register x+i.

[0177] In the present application, the second set can be expressed as: MoveListInRepeated(x) = {Mov x+i,x+j|i in RC and j = Repeated(i)}, the parameters at parameter position i and parameter position j are repeated parameters, j is the first parameter position of the repeated parameter in the range instruction, i is the non-first parameter position of the repeated parameter in the range instruction, and the move instruction is: copy the parameter on the target register x+j to the target register x+i.

[0178] Step S9: Add the move instructions generated in steps S7 and S8 to the IR, which includes the above N instructions and the move instructions.

[0179] In one implementation, based on the above-mentioned first set and second set, all move instructions generated by traversing the range instruction (which can be called the third set) can be obtained; the move instructions in the third set are added to the SpillFill of the current IR.

[0180] In the present application, the third set can be expressed as: MoveList(x)=MoveListInQ(x)U MoveListInRepeated(x), that is, the third set is the union of the first set and the second set.

[0181] S4044: Based on the target register determined by the target start register, registers are allocated to parameters that have not been allocated registers.

[0182] In some embodiments, a target register x+i may be assigned to the parameter corresponding to parameter position i in a set R of unallocated registers and added to the active set. The set R is the parameter positions of non-duplicate parameters and / or the first parameter position of duplicate parameters in the parameters of the unallocated registers.

[0183] In the present application, the registers allocated to the parameters that are not allocated registers can be represented as a set A={x+i|i in R}, where the elements in the set A are the target registers x+i to be allocated to each parameter position i.

[0184] It should be understood that there are two types of parameters for allocated registers: one is that the allocated register is the target register and does not require re-allocation of registers or move; the other is that the allocated register is not the target register and does not require re-allocation of registers, but requires move, and a move instruction has been generated through step S4043. In addition, the non-first parameter position of the repeated parameter in the parameters of the unallocated registers is allocated registers through move. Therefore, the present application only needs to allocate registers to the parameter positions of the non-repeated parameters and / or the first parameter position of the repeated parameters in the parameters of the unallocated registers. This method can reduce the number of generated move instructions and avoid the bytecode file from being too large.

[0185] S405: After the compiler allocates registers to the parameters of the range instruction, it allocates registers to the parameters of the non-range instruction.

[0186] In some embodiments, after register allocation for range instructions is completed, registers are allocated for parameters of non-range instructions.

[0187] For example, for each unassigned parameter in a non-range instruction, a set A is constructed. The registers indicated by set A satisfy the following conditions: the register indicated by set A is a register that has been assigned a parameter and whose active range intersects with the active range of the current parameter; or the register indicated by set A is a register in SpillFill (i.e., a register in a move instruction) and whose active range intersects with the active range of the current parameter. Then, registers outside set A are selected for allocation.

[0188] It should be noted that registers that have already been allocated in the active interval cannot be allocated, that is, registers in SpillFill cannot be selected.

[0189] S403 is the focus of the present invention. The present invention provides an efficient register allocation algorithm for range instructions, which can effectively reduce the number of move instructions generated by range instructions.

[0190] The following is a detailed description of a register allocation method provided in an embodiment of the present application.

[0191] In an embodiment of the present application, an example is provided in which there are only three range instructions in the IR, and in the order of instruction execution, these three range instructions are funcA(a, b, c, d), funcB(d, a, b, e), and funcC(f, e, f, e).

[0192] It should be understood that, for ease of description, the range function examples in the embodiments of this application all have four parameters. The positional order of the parameters in the range instruction is the order in which the parameters are executed. For example, in funcA(a, b, c, d), the first parameter executed is parameter a, and parameter a is located in the first position, that is, parameter position i = 0. In other embodiments of this application, the number of parameters in the range function can be greater than four, and the parameters in different range functions can be different or the same, and this application does not limit this. The process of obtaining the IR can be referred to the relevant content above and will not be repeated here.

[0193] Figure 5 illustrates the active ranges after the parameters in funcA(a,b,c,d), funcB(d,a,b,e), and funcC(f,e,f,e) are sorted. The specific sorting process can be seen in steps S401 through S403 above. It should be understood that for ease of explanation, the range instruction has also been added to Figure 5. Here, funcA(a,b,c,d) is the fifth instruction in the execution order, i.e., instruction numbered 5; funcB(d,a,b,e) is the seventh instruction in the execution order, i.e., instruction numbered 7; and funcC(f,e,f,e) is the ninth instruction in the execution order, i.e., instruction numbered 9.

[0194] It should be understood that in the initial state, no registers are allocated and the active set is empty. Next, we begin traversing the range instructions in the order in which they are executed. For example, the first range instruction traversed is funcA(a, b, c, d). In this embodiment of the application, allocating registers for the parameters in funcA (a, b, c, d) is referred to as the first allocation. Please refer to Figure 6, which is a schematic diagram of the allocation flow for the first allocation of registers provided in this embodiment of the application. As shown in Figure 6, the following steps are included:

[0195] (1) Traverse funcA(a,b,c,d)

[0196] Initial state when traversing funcA(a,b,c,d): No registers in the compiler are allocated, and no registers are allocated to the parameters in funcA(a,b,c,d), as shown in Table 1.

[0197] Table 1 exemplarily shows the locations of parameters in funcA(a, b, c, d) and the registers to which the parameters are allocated.

[0198] Table 1

[0199] Among them, "i" in Table 1 is the parameter position of the parameter in funcA(a,b,c,d), such as the parameter position of parameter a in funcA(a,b,c,d) is "0"; "yi" in Table 1 is the register number assigned to the parameter corresponding to parameter position i or the status of the parameter corresponding to parameter position i, and "-" is used to indicate that the status of the parameter corresponding to parameter position i is undefined, that is, no register is assigned. For example, the second column is used to indicate that the parameter a corresponding to parameter position i=0 is not assigned a register.

[0200] S601: Based on the active range of the parameters in funcA(a,b,c,d), remove inactive registers from active{}.

[0201] It should be understood that in the initial state, no register is allocated and the active set is empty, so active = {} obtained after executing S601.

[0202] S602: For funcA(a, b, c, d), find the starting register number that meets the preset conditions so that the number of move instructions is minimized.

[0203] Exemplarily, step S602 includes the following steps S6021 to S6024.

[0204] S6021: For funcA(a,b,c,d), construct set Q and set QC, where set Q includes the parameter positions of the parameters of the allocated registers in funcA(a,b,c,d); set QC includes the parameter positions of the parameters of the unallocated registers in funcA(a,b,c,d).

[0205] It should be understood that funcA(a, b, c, d) is the first range instruction traversed. At this time, no registers have been allocated, so Q is empty, that is, Q = {}, QC = {0, 1, 2, 3}.

[0206] In this application, the set Q can also be expressed as: Q = {i|yi is not undefined}; the set QC can also be expressed as: QC = {i|yi is undefined}.

[0207] S6022: Based on active{}, construct a set P, where the set P is the value range of the starting register number. The target register corresponding to the starting register in the set P meets the preset condition. The preset condition is that the target register is an unassigned register, or the target register of the parameter is an assigned register of the parameter.

[0208] Optionally, P can also be expressed as: P = {x|for each i in{0,….,N},either x+i=yi,or x+i is not active}, where x is the starting register number, i is the parameter position in funcA(a,b,c,d), and yi is the register number assigned to i; P is the set of range starting register numbers x, and for each i belonging to 0~N, N is the maximum parameter position in funcA(a,b,c,d), the following conditions A and B need to be met, where condition A is: x+i is exactly equal to yi, that is, register x+i is the register assigned to i; condition B is: x+i is an unassigned register.

[0209] Table 2-1 illustrates the target registers x+i (i.e., x+0, x+1, x+2, and x+3) when traversing funcA(a,b,c,d) with the starting register number x being 0, 1, 2, 3, 4, and i being 0, 1, 2, or 3. The "-" in Table 2-1 indicates that the target register x+i is not assigned a parameter. As shown in Table 2-1, when traversing funcA(a,b,c,d) with the starting register x being 0, 1, 2, 3, or 4, the target registers (x+0, x+1, x+2, and x+3) are all unassigned. To facilitate comparison of whether the assigned register yi at parameter position i is the target register x+i, Table 2-2 illustrates the target register yi at parameter position i.

[0210] Table 2-1

[0211] Table 2-2

[0212] In the embodiment of the present application, since no registers are allocated when traversing funcA(a, b, c, d), no matter what value x takes, x+i is inactive (registers with no parameters allocated), so at this time: P = {0, 1, 2, 3, 4, 5...}. It should be understood that the embodiment of the present application exemplifies the example of the starting register number x being 0, 1, 2, 3, 4..., and it should be understood that the embodiment of the present application can also only detect the target register x+i (i.e., x+0, x+1, x+2, and x+3) corresponding to the four registers x being 0, 1, 2, 3, and 4, and the present application does not limit this.

[0213] It should be understood that for each parameter in the range instruction, such as arg0 to argN, assuming that the register number assigned to the starting parameter arg0 is x (i.e., the starting register number is x), then the corresponding parameters of registers x+1, x+2, x+3, etc. are arg1, arg2, arg3, etc., respectively. Assuming that i is any value from 0 to N, and yi is not assigned or is exactly equal to the value of x+i, then the parameters arg0 to argN can be directly assigned to the registers numbered x, x+1, x+2, x+3, etc. in sequence without conflict. P is such a set of x.

[0214] S6023: Find the starting register number x in the set P that minimizes |L(x)|, where L(x) is the set of parameter positions i in the set Q where the target register x+i is different from the allocated register yi when the starting register is x. The target register corresponding to the starting register x corresponds one-to-one to the parameter position in funcA(a,b,c,d).

[0215] The parameter positions of the assigned parameters in funcA(a, b, c, d) are the set Q mentioned above. In other words, L(x) can be expressed as: L(x) = {i in Q|x + i! = yi}.

[0216] In some embodiments, the compiler can construct a set L(x) corresponding to each register x in set P, where L(x) is the set of parameter positions of conflicting parameters in funcA(a, b, c, d) when x is used as the starting register. The compiler then finds the x in set P that minimizes |L(x)|, and the x that minimizes |L(x)| is the target starting register. In other words, the target starting register is the register in set P that generates the fewest conflicting parameters when used as the starting register, and the conflicting parameters are parameters for which the allocated registers corresponding to the allocated parameters in funcA(a, b, c, d) differ from the target register when the target starting register is used as the starting register.

[0217] It should be understood that the absolute value of the set L(x) refers to the number of elements in the set L(x), and the elements in the set L(x) are the parameter positions i of the conflicting parameters; the conflicting parameters are the parameters for which the allocated registers corresponding to the allocated parameters in funcA(a,b,c,d) are different from the target registers when x is used as the starting register.

[0218] In the embodiment of the present application, since Q is empty when traversing funcA(a, b, c, d), L(x) is also empty (that is, 0). When L(x) is the same, the register x with the smallest number among all the registers to be processed can be taken as the target starting register, that is, the number value x of the target starting register is 0, that is, the target register is the register numbered v0.

[0219] It should be understood that after finding a starting set P that meets the conditions, we need to find the x that generates the least move instructions from P. For the assigned register number i, if x + i != yi, that is, the registers at parameter position i are non-contiguous, a move instruction needs to be generated.

[0220] S6024: Construct Repeated(i) corresponding to funcA(a,b,c,d).

[0221] In the embodiment of the present application, it can be seen from Table 1 that there is no repeated parameter, so for i=0, 1, 2, 3, Repeated(i) is undefined.

[0222] In this application, Repeated(i) can be expressed as: Repeated(i)=minimal j

[0223] S603: Generate move instructions corresponding to conflicting parameters and duplicate parameters of unallocated registers respectively.

[0224] Optionally, add this to the IR after generating the move instruction.

[0225] S6031: Based on the set QC and Repeated(i), construct the set R and the set RC.

[0226] In the present application, the set R can be expressed as: R = {i in QC | Repeated(i) is undefined}; the set R can also be expressed as: RC = QC - R.

[0227] In the embodiment of the present application, the parameter positions of the unallocated registers in funcA(a, b, c, d) are QC = {0, 1, 2, 3}, and Repeated(i) is undefined. Then, R = {i in QC|Repeated(i) is undefined} = {0, 1, 2, 3}; the set RC = QC–R = {}.

[0228] In the embodiment of the present application, QC={0, 1, 2, 3}, R={0, 1, 2, 3}, and RC={}.

[0229] S6032: Generate a move instruction based on the set L(x), Repeated(i), set RC, the allocated registers of the parameters in funcA(a,b,c,d), and the target register corresponding to funcA(a,b,c,d). ​

[0230] Exemplarily, S6032 may include the following three steps:

[0231] S1: Construct MoveListInQ(x), MoveListInQ(x) = {Mov x+i,yi|i in L(x)}, where x is the number of the target starting register, that is, the x that minimizes |L(x)|.

[0232] In this embodiment of the present application, the value of x that minimizes |L(x)| is found to be 0 in step S6023, i.e., MoveListInQ(0) is constructed. If x = 0, i in L(x) satisfies x + i ≠ yi, i.e., yi is not at the corresponding x + parameter position i, then a move instruction is generated to move yi to x + i. Since L(0) corresponding to funcA(a, b, c, d) is empty (i.e., L(0) = 0), no move instruction is generated.

[0233] S2: Construct MoveListInRepeated(x), MoveListInRepeated(x)={Mov x+i,x+j|i in RC and j=Repeated(i)}.

[0234] If Repeated(i) for the parameter at position i is non-empty (i.e., not undefined), then the same parameter exists at a position before that position and has been assigned a register. In this case, simply move the parameter to that position. Since Repeated(i) for the parameters in funcA(a, b, c, d) is all undefined (i.e., empty), and RC = {}, no move instruction is generated.

[0235] S3: Based on MoveListInQ(x) and MoveListInRepeated(x), MoveList(x) is obtained. MoveList(x) is the union of the above two sets.

[0236] In the embodiment of the present application, since L(x) and RC are both empty, there is no need to generate a move instruction.

[0237] S604: Based on the set R, allocate registers to the parameter positions of funcA(a, b, c, d) that have not been allocated registers.

[0238] In an embodiment of the present application, the compiler can construct a set A for funcA(a,b,c,d), where A is the register number to which parameters need to be assigned. Since in the initial state funcA(a,b,c,d) has no parameters assigned and no registers have been assigned parameters, the parameters in funcA(a,b,c,d) all need to be assigned registers. Step S6023 has determined that the target register number value is 0, that is, the target register of the first parameter a executed in funcA(a,b,c,d) is 0. In the execution order, the target register number values ​​corresponding to other parameters are 1, 2, and 3, respectively, that is, A={0,1,2,3}; the registers in A are added to active{}, at this time active={0,1,2,3}; the target registers are assigned to the corresponding parameters; and the final allocation result is obtained.

[0239] For example, the final allocation result may be shown in Table 3.

[0240] Table 3

[0241] In this embodiment of the present application, register allocation for traversing funcA(a, b, c, d) can be called the first allocation. No Move occurs in the first allocation. As shown in Table 3, registers numbered v0, v1, v2, and v3 are allocated registers. The register numbers are added to the active set, resulting in active = {0, 1, 2, 3}.

[0242] For example, the active interval obtained after allocation can be shown in FIG7 , where registers have been allocated to parameters a, b, c, and d. Next, registers are allocated for the parameters of funcB.

[0243] Please refer to Figure 8, which is a flow chart of a second allocation method provided by an embodiment of the present application. As shown in Figure 8, the method may include the following steps:

[0244] (2) Traverse funcB(d,a,b,e)

[0245] As shown in Figure 7, the initial state when traversing funcB(d,a,b,e) is that the parameters a, b, and d have been allocated registers.

[0246] Table 4 shows the locations of the parameters in funcB(d, a, b, e) and the registers to which the parameters are allocated.

[0247] Table 4

[0248] Among them, "i" in Table 4 is the parameter position (i.e., parameter position) of the parameter in funcB(d,a,b,e), such as the parameter position of parameter d in funcB(d,a,b,e) is "0"; "yi" in Table 4 is the register number assigned to the parameter at position i or the status of the parameter at position i, and "-" is used to indicate that the status of the parameter at position i is undefined, that is, the register is not assigned. For example, the second column is used to indicate that the register number assigned to parameter d corresponding to parameter position i=0 is v3, and the last column is used to indicate that the status of parameter e corresponding to parameter position i=3 is an unassigned register.

[0249] S801: Based on the active range of the parameters in funcB(d,a,b,e), remove inactive registers from active{}.

[0250] For example, after traversing funcA(a, b, c, d), the active set obtained is active = {0, 1, 2, 3}. The allocated active interval is shown in Figure 7. It can be seen that since the register numbered v2 is in an inactive state when traversing funcB(d, a, b, e), the inactive register is the register numbered v2. After removing the inactive register v2 from the active set, the active set can be obtained, including registers numbered v0, v1 and v3, that is, active = {0, 1, 3}.

[0251] S802: For funcB(d, a, b, e), find the starting register number that meets the preset conditions so that the number of move instructions is minimized.

[0252] Exemplarily, step S602 includes the following steps S8021 to S8024.

[0253] S8021: For funcB(d,a,b,e), construct set Q and set QC, where set Q includes the parameter positions of the parameters of the allocated registers in funcB(d,a,b,e); set QC includes the parameter positions of the parameters of the unallocated registers in funcB(d,a,b,e).

[0254] Since the parameters d, a, b have been assigned registers when traversing funcB(d, a, b, e), the sets of Q and QC are: Q = {0, 1, 2}, QC = {3}.

[0255] S8022: Based on active{}, construct a set P, where the set P is a value range of the starting register number. The target register corresponding to the starting register in the set P meets a preset condition. The preset condition is that the target register is an unassigned register, or the target register of the parameter is an assigned register of the parameter.

[0256] In some embodiments, the compiler may first determine the starting register and determine the target register corresponding to each parameter; and perform a judgment on the target register corresponding to each parameter. First, it is determined whether the target register is an unassigned register. If so, the target register satisfies the preset condition; if not, it is determined whether the target register of the parameter is an assigned register of the parameter. If so, the target register satisfies the preset condition; if not, the target register does not satisfy the preset condition.

[0257] Table 5-1 shows the target register x+i (i.e., x+0, x+1, x+2, and x+3) when the starting register x is 0, 1, 2, 3, 4, ... and i is 0, 1, 2, 3 during traversal of funcB(d, a, b, e). The "-" in Table 5-1 indicates that no parameter is assigned to the target register x+i. The values ​​in Table 5-1 indicate the number of the target register x+i when the target register x+i is a register to which parameters have been assigned. The values ​​in bold indicate that the target register x+i is not register yi, but a register to which other parameters have been assigned.

[0258] To facilitate the comparison of whether the target register x+i is allocated and whether it is the register yi allocated to the parameter position i, Table 5-2 shows the situation of the parameter position i and the register yi corresponding to i in funcB(d,a,b,e).

[0259] Take the second row in Table 5-1 as an example to introduce Table 5-1. For example, in the second row and second column, when the starting register x is 0 and i is 0, the value number of the target register x+0 corresponding to the parameter position i=0 is 0. Referring to Table 5-2, it can be seen that the register v0 with the value number 0 is the register assigned to the parameter position 1, and is not the register y0 (i.e., v3) assigned to the parameter position i=0, that is, x+0≠y0. Therefore, the value number 0 of the target register x+0 is filled in the second row and second column in Table 5-1 and is bolded; for example, in the second row and third column, when the starting register x is 0 and i is 1, the target register x+1 corresponding to the parameter position i=1 The numerical number is 1, see Table 5-2, it can be seen that the register v1 with the numerical number 1 is the register allocated to parameter position 1, and is not the register y1 (i.e., v0) allocated to parameter position i=1, that is, x+1≠y1. Therefore, the numerical number 1 of the target register x+1 is filled in the second column of the second row in Table 5-1 and is highlighted in bold; for example, in the second column of the second row, when the starting register x is 0 and i is 2, the numerical number of the target register x+2 corresponding to parameter position i=2 is 2. See Table 5-2, it can be seen that the register v2 with the numerical number 2 is an unassigned register. Therefore, "-" is filled in the second column of the second row in Table 5-1.

[0260] Table 5-1

[0261] Table 5-2

[0262] In some embodiments, the target registers can be judged in order from small to large according to the register number value. When it is determined that there is a target register among the target registers corresponding to the starting register that does not meet the preset conditions, it can be considered that the target register corresponding to the starting register does not meet the preset conditions. As shown in Table 5-1, when x=0, the target register corresponding to the starting register in set P does not meet the preset condition, because the target register with the smallest number x+0≠y0 and x+0 is the active register; when x=1, the target register corresponding to the starting register in set P does not meet the preset condition, because the target register with the smallest number x+0≠y0 and x+0 is the active register; when x=2, the target register corresponding to the starting register in set P does not meet the preset condition, because when judging that the target register with the smallest number meets the preset condition, when judging the next target register with the number x+1, it is determined that x+1≠y1 and x+0 is the active register; when x=3, the target register corresponding to the starting register in set P meets the preset condition, because x+0=y0 and x+1, x+2, and x+3 are not assigned parameters (i.e., undefined); when the number x≥4 in set P, the target register corresponding to the starting register meets the preset condition, because x+0, x+1, x+2, and x+3 are not assigned parameters (i.e., undefined).

[0263] In the embodiment of the present application, since active = {0, 1, 3} and the order of allocating registers in the embodiment of the present application is according to the number, the target register corresponding to the starting register when the number value x≥4 in the set P meets the preset conditions.

[0264] Therefore, at this time: P = {3, 4, 5...}.

[0265] S8023: Find the starting register number x in the set P that minimizes |L(x)|, where L(x) is the set of parameter positions i in the set Q where the target register x+i is different from the allocated register yi when the starting register is x. The target register corresponding to the starting register x has a one-to-one correspondence with the parameter positions in funcB(d, a, b, e).

[0266] That is, a target starting register is determined in set P. The target starting register is the register in set P that generates the least number of conflicting parameters when used as the starting register. The conflicting parameters are parameters that are different between the allocated registers and the target registers when the target starting register is used as the starting register and the allocated parameters in funcB(d, a, b, e).

[0267] In some embodiments, for funcB(d, a, b, e), a set L(x) can be constructed, and x can be found in the set P such that |L(x)| is minimized.

[0268] Wherein, the set L(x) is the set of parameter positions i of conflicting parameters in funcB(d,a,b,e) when x is the starting register; |L(x)| is the number of conflicting parameters in parameter position i; and the conflicting parameters are the parameters for which the allocated registers corresponding to the allocated parameters in funcB(d,a,b,e) when x is the starting register are different from the target registers.

[0269] The parameter positions of the allocated parameters in funcB(d, a, b, e) are the set Q. Then, L(x) can be expressed as: L(x) = {i in Q|x+i! = yi}. In the embodiment of the present application, Q = {0, 1, 2}.

[0270] Table 6-1 shows the numerical values ​​of the target register x+i corresponding to parameter position i in the set Q when Q={0, 1, 2} (i.e., i=0, 1, 2) and the set P={3, 4, 5...} (i.e., x=3, 4, 5...). For example, the second row shows the numerical values ​​of the target register corresponding to parameter position i in Q when x=3. For example, the 3 in the second row and second column indicates that the register number of register x+0 corresponding to parameter position i=0 in Q is 3, the 4 in the second row and third column indicates that the register number of register x+1 corresponding to parameter position i=1 in Q is 4, and the 5 in the second row and fourth column indicates that the register number of register x+2 corresponding to parameter position i=2 in Q is 5.

[0271] Table 6-1 uses bold values ​​to indicate the number of the target register that is different from the original register of the parameter. For example, in the second row, the register number of the target register x+1 corresponding to parameter position i=1 is 4 (i.e., x+1 is v4). Referring to Table 6-2, it can be seen that the register y1 corresponding to parameter position i=1 is v3. Therefore, since x+1≠y1, the 4 in the second row and third column of Table 6-1 is indicated by bold.

[0272] To facilitate comparison of whether the target register x+i is the register yi allocated to parameter position i, Table 6-2 shows the situation of register yi corresponding to parameter position i in set Q.

[0273] Table 6-1

[0274] Table 6-2

[0275] As shown in Table 6-1, when x=3, the parameters corresponding to the two elements 1 and 2 in the Q set are conflicting parameters; when x=4, the parameters corresponding to the three elements 0, 1, and 2 in the Q set are conflicting parameters; when x=4, the parameters corresponding to the three elements 0, 1, and 2 in the Q set are conflicting parameters; when x≥6, the parameters corresponding to the three elements 0, 1, and 2 in the Q set are conflicting parameters.

[0276] In the embodiment of the present application, the maximum number of registers to which parameters have been assigned in funcB(d, a, b, e) is v3 and the number of assigned parameters is 3. Since the numbers of the target registers corresponding to the starting registers with number values ​​x≥4 are all greater than v3, the three registers to which parameters have been assigned in funcB(d, a, b, e) are all different from the target registers corresponding to the starting registers with number values ​​x≥4, that is, the number of conflicts corresponding to the target registers corresponding to the starting registers with number values ​​x≥4 is all 3, and |L(x)| = 3. Therefore, in the embodiment of the present application, when determining that the maximum number of registers to which parameters have been assigned in funcB(d, a, b, e) is v3 and the number of assigned parameters is 3, since |L(x)| corresponding to the starting registers with number values ​​x≥4 is 3, it is not necessary to calculate the cases of x≥4 one by one.

[0277] Then, we can get that when x=3, L(3)={1,2}, and at this time |L(x)|=2 is the minimum.

[0278] S8024: Construct Repeated(i) corresponding to funcB(d,a,b,e).

[0279] In the embodiment of the present application, it can be seen from Table 4 that there is no repeated parameter, so for i=0, 1, 2, 3, Repeated(i) is undefined.

[0280] S803: Move instructions corresponding to conflicting parameters and duplicate parameters of unassigned registers.

[0281] In some embodiments, a move instruction may be generated and added to the IR.

[0282] S8031: Based on the set QC and Repeated(i), construct the set R and the set RC.

[0283] In the embodiment of the present application, the parameter position of the unallocated register in funcB(d, a, b, e) is QC={3}, and Repeated(i) is undefined, then R={i in QC|Repeated(i)is undefined}={3}; the set RC=QC–R={}.

[0284] S8032: Generate a move instruction based on the set L(x) corresponding to funcB(d,a,b,e), Repeated(i), set RC, the allocated registers of the parameters in funcB(d,a,b,e), and the target register.

[0285] Exemplarily, S8032 may include the following three steps:

[0286] S1: Construct MoveListInQ(x).

[0287] In the embodiment of the present application, the target starting register x=3, and MoveListInQ(3) is constructed.

[0288] Since L(3) = {1,2}, that is, when the starting register is x = 3, the parameters corresponding to the two elements at parameter positions 1 and 2 in the Q set are conflicting parameters (a, b). The original register of a is v0, and the original register of b is v1. When the starting register is x = 3, the target register corresponding to a is v4, and the target register corresponding to b is v5. Therefore, the following two move instructions are generated for parameters a and b respectively:

[0289] Move v4, v0; Move v5, v1.

[0290] Move v4, v0 moves parameter a from register v0 to register v4, and Move v5, v1 moves parameter b from register v1 to register v5.

[0291] MoveListInQ(3)={Move v4, v0; Move v5, v1}.

[0292] S2: Construct MoveListInRepeated(x). In this case, there is no repeated parameter, so MoveListInRepeated(x) is empty {}.

[0293] S3: Based on MoveListInQ(x) and MoveListInRepeated(x), MoveList(x) is obtained. MoveList(x) is the union of the above two sets.

[0294] The final move instruction is the union of the above two sets, namely: Move v4, v0; Move v5, v1.

[0295] S804: Based on the set R, allocate registers to the parameter positions of funcB(d, a, b, e) that have not been allocated registers.

[0296] In an embodiment of the present application, the compiler can construct a set A for funcB(d, a, b, e), where A is the register number to which parameters need to be allocated, A = {6} (because x = 3, R = {3}); add the registers in A to active{}, at this time active = {0, 1, 3, 6}; allocate the registers to the corresponding parameters; and obtain the final allocation result.

[0297] For example, the final distribution results are shown in Table 7:

[0298] Table 7

[0299] In the embodiment of the present application, register allocation for traversing funcB(d, a, b, e) can be called the second allocation, generating two move instructions. At this time, active = {0, 1, 3, 6}.

[0300] Table 4 shows the register allocation before traversing funcB(d,a,b,e), and Table 8-1 shows the register allocation after traversing funcB(d,a,b,e). Two move instructions are generated, namely Move v4, v0; Move v5, v1. That is to say, funcB(d,a,b,e) can use the consecutive registers shown in Table 8-2 when calling.

[0301] Table 8-1

[0302] Table 8-2

[0303] After traversing funcB(d, a, b, e), the allocated active range is shown in Figure 9, where a' and b' are temporary variables generated by the move command, occupying register v4 and register v5, respectively, at instruction number 7. Assuming that in step S803 above, the generated move instruction is added to the IR, such as adding the generated move instruction to SpillFill in the IR, then register v4 and register v5 are the registers in SpillFill. It should be understood that when allocating registers for parameters in non-range instructions, registers in SpillFill that intersect with the active range of the parameter cannot be allocated.

[0304] As shown in Figure 9, you can see that registers have been allocated to parameters a, b, c, d, and e. Next, registers are allocated for the parameters of funcC.

[0305] Please refer to Figure 10, which is a schematic diagram of a third allocation process provided by an embodiment of the present application. As shown in Figure 10, the register allocation method may include the following steps:

[0306] (3) Traverse funcC(f,e,f,e)

[0307] Initial state when traversing funcC(f,e,f,e): parameter e in funcC(f,e,f,e) has been assigned to register v6.

[0308] Table 9 exemplarily shows the locations of parameters in funcC(f,e,f,e) and the registers to which the parameters are allocated.

[0309] Table 9

[0310] Among them, "i" in Table 9 is the parameter position (i.e., parameter position) of the parameter in funcC(f,e,f,e), such as the parameter position of parameter f in funcC(f,e,f,e) is "0"; "yi" in Table 9 is the register number assigned to the parameter corresponding to parameter position i or the status of the parameter corresponding to parameter position i, and "-" is used to indicate that the status of the parameter at position i is undefined, that is, an unassigned register. For example, the second column is used to indicate that the status of parameter f corresponding to parameter position i=0 is an unassigned register; the third column is used to indicate that parameter e corresponding to parameter position i=1 is an unassigned register.

[0311] S1001: Based on the active range of the parameters in funcC(f,e,f,e), remove inactive registers from active{}.

[0312] For example, after traversing funcB(d, a, b, e), the active set obtained is active = {0, 1, 3, 6}. The allocated active interval is shown in FIG9 . It can be seen that since the registers numbered v0, v1, and v3 are in an inactive state when traversing funcC(f, e, f, e), the inactive registers are the registers numbered v0, v1, and v3. After removing the inactive registers from the active set, the active set includes the registers numbered v0, v1, and v3, that is, 0, 1, and 3 are removed from active{}, and active = {6}.

[0313] S1002: Find a starting register number that meets a preset condition so as to minimize the number of move instructions.

[0314] S10021: For funcC(f,e,f,e), construct set Q and set QC, where set Q includes the parameter positions of parameters of allocated registers in funcC(f,e,f,e); set QC includes the parameter positions of parameters of unallocated registers in funcC(f,e,f,e).

[0315] Since the parameter e has been allocated a register when traversing funcC(f,e,f,e), the sets of Q and QC are: Q = {1,3}, QC = {0,2}.

[0316] S10022: Based on active{}, construct a set P, which is the value range of the starting register number. The target register corresponding to the starting register in the set P meets the preset condition. The preset condition is that the target register is an unassigned register, or the target register of the parameter is an assigned register of the parameter.

[0317] Table 10-1 shows the target register x+i (i.e., x+0, x+1, x+2, and x+3) when the starting register x is 0, 1, 2, 3, and i is 0, 1, 2, and 3 during traversal of funcC(f,e,f,e). The "-" in Table 10-1 indicates that no parameter is assigned to the target register x+i. The numerical values ​​in Table 10-1 indicate the number of the target register x+i when the target register x+i is an assigned register. The numerical values ​​in bold indicate that the target register x+i is not register yi, but is a register to which other parameters have been assigned.

[0318] To facilitate comparison of whether the target register x+i is allocated and whether it is the register yi allocated to parameter position i, Table 10-2 shows the situation of parameter position i and the register yi corresponding to i in funcC(f,e,f,e).

[0319] Taking the "-" in the second row and second column of Table 10-1 as an example, when the starting register x is 0 and i is 0, the value number of the target register x+0 corresponding to the parameter position i=0 is 0 (that is, register v0). Referring to Table 10-2, it can be seen that register v0 is an unassigned register. Therefore, "-" is filled in the second row and second column of Table 10-1.

[0320] Taking "6" in the fifth row and fifth column in Table 10-1 as an example, when the starting register x is 3 and i is 3, the register number value is x+3=6. In Table 10-2, the register number value is 6 (that is, register v6). Register v6 is an allocated register, so "6" is filled in the fifth row and fifth column. Since the allocated register corresponding to the parameter position i=3 is v6, that is, x+3=y3, the "6" in the fifth row and fifth column is not indicated in bold.

[0321] Taking the bold "6" in the fourth column of the sixth row in Table 10-1 as an example, the starting register x is 4 and i is 2, and the corresponding target register number value is 4+2=6. In Table 10-2, the register number value is 6 (that is, register v6). Register v6 is an allocated register, so "6" is filled in the fourth column of the sixth row. Since no register is allocated at the parameter position i=2 (that is, y3=undefined), that is, x+2≠y3, the "6" in the fourth column of the sixth row is bold.

[0322] Table 10-1

[0323] Table 10-2

[0324] So at this time: P = {0, 1, 2, 3, 5, 7, 8...}.

[0325] S10023: Find the starting register number x in the set P that minimizes |L(x)|, where L(x) is the set of parameter positions i in the set Q where the target register x+i is different from the allocated register yi when the starting register is x. The target register corresponding to the starting register x has a one-to-one correspondence with the parameter positions in funcC(f,e,f,e).

[0326] In some embodiments, for funcC(f,e,f,e), a set L(x) can be constructed, and x can be found in the set P such that |L(x)| is minimized.

[0327] The parameter positions of the allocated parameters in funcC(f,e,f,e) are the above set Q, Q = {1,3}. Then, L(x) can be expressed as: L(x) = {i in Q|x+i! = yi}.

[0328] Table 11-1 shows the numerical values ​​of the target register x+i corresponding to parameter position i in the set Q when Q = {1, 3} (i.e., i = 1, 3) and the set P = {0, 1, 2, 3, 5, 7, 8...} (i.e., x = 0, 1, 2, 3, 5, 7, 8...). For example, the second row shows the numerical values ​​of the target register corresponding to parameter position i in Q when x = 0. For example, the 1 in the second row and second column indicates that the register x+1 corresponding to parameter position i = 1 in Q has a numerical value of 1, and the 3 in the second row and third column indicates that the register x+3 corresponding to parameter position i = 3 in Q has a numerical value of 3.

[0329] Table 11-1 uses bold values ​​to indicate the number of the target register that is different from the original register of the parameter. For example, in the second row, the register number of the target register x+1 corresponding to parameter position i=1 is 4 (i.e., x+1 is v4). Referring to Table 11-2, it can be seen that the register y1 corresponding to parameter position i=1 is v3. Therefore, since x+1≠y1, the 4 in the second row and third column of Table 11-1 is indicated by bold.

[0330] To facilitate comparison of whether the target register x+i is the register yi allocated to parameter position i, Table 11-2 shows the situation of register yi corresponding to parameter position i in set Q.

[0331] Table 11-1

[0332] Table 11-2

[0333] As shown in Table 11-1, when x=3, L(3)={1}, at which time |L(x)| is the smallest; when x=5, L(5)={3}, at which time |L(x)| is the smallest.

[0334] Optionally, when there are multiple x that minimize |L(x)|, an x ​​can be randomly selected from the multiple x, or the x with the smallest value can be selected from the multiple x.

[0335] The embodiment of the present application is described by taking the example of selecting the x with the smallest value (ie, x=3) from multiple xs.

[0336] S10024: Construct Repeated(i) corresponding to funcC(f,e,f,e).

[0337] In one implementation, for each parameter at parameter position i in funcC(f,e,f,e), a forward search may be performed to find a parameter that is repeated with the parameter at the parameter position i. Based on the search result, Repeated(i) corresponding to each parameter position i is determined to obtain Repeated(i) corresponding to funcC(f,e,f,e).

[0338] As shown in Table 9, the parameter position i=0 corresponds to the parameter f, because the parameter position i=0 is the first parameter position, so there cannot be a parameter that repeats f before the parameter position i=0, so Repeated(0) is undefined; the parameter position i=1 corresponds to the parameter e, because the parameter position before the parameter position i=1 only has the parameter f, that is, there is no parameter that repeats e, so Repeated(1) is undefined; the parameter position i=2 corresponds to the parameter f, because the parameter f exists in the parameter position i=0 before the parameter position i=2, so Repeated(2)=0; the parameter position i=3 corresponds to the parameter e, because the parameter e exists in the parameter position i=1 before the parameter position i=3, so Repeated(3)=1; then, it can be obtained that the Repeated(i) corresponding to funcC(f,e,f,e) includes Repeated(2)=0, Repeated(3)=1, and both Repeated(0) and Repeated(1) are undefined.

[0339] Table 12 shows the situation of Repeated(i) corresponding to funcC(f,e,f,e).

[0340] Table 12

[0341] In the embodiment of the present application, as shown in Table 12, Repeated(2)=0, Repeated(3)=1, and Repeated(0) and Repeated(1) are both undefined.

[0342] S1003: Generate move instructions corresponding to conflicting parameters and duplicate parameters of unallocated registers respectively.

[0343] In some embodiments, the move instruction may be added to the IR after it is generated.

[0344] S10031: Based on the set QC and Repeated(i), construct the set R and the set RC.

[0345] In the embodiment of the present application, QC={0,2}, Repeated(0) is undefined, Repeated(2)=0, then, R={0}; RC=QC-R={2}.

[0346] S10032: Generate a move instruction based on the set L(x) corresponding to funcC(f,e,f,e), Repeated(i), set RC, the allocated registers of the parameters in funcC(f,e,f,e), and the target register.

[0347] Exemplarily, S10032 may include the following three steps:

[0348] S1: Construct MoveListInQ(x).

[0349] In the embodiment of the present application, the value of x that minimizes |L(x)| is 3, that is, MoveListInQ(3) is constructed.

[0350] Since L(3)={1}, the allocated register for parameter position i=1 is v6 and the target register is v4, so for parameter position i=1, a move instruction is generated: Move v4, v6.

[0351] S2: Construct MoveListInRepeated(x).

[0352] In the embodiment of the present application, the repeated parameters are parameter f and parameter e; RC = {2}, that is, parameter position i = 2 is the repeated parameter position; Repeated (2) = 0, generating the following move instruction:

[0353] Move v5, v3.

[0354] S3: Based on MoveListInQ(x) and MoveListInRepeated(x), MoveList(x) is obtained. MoveList(x) is the union of the above two sets.

[0355] In the embodiment of the present application, the final move instruction is the union of the above two sets, that is, MoveList(x) includes:

[0356] Move v4, v6; Move v5, v3.

[0357] S1004: Based on the set R, allocate registers to the parameter positions in funcC(f,e,f,e) that have not been allocated registers.

[0358] In an embodiment of the present application, the compiler can construct a set A for funcC(f,e,f,e), where A is the register number to which parameters need to be allocated, A={3} (because x=3, R={0}); add the registers in A to active{}; allocate the registers to the corresponding parameters; and obtain the final allocation result.

[0359] For example, the final allocation result may be shown in Table 13.

[0360] Table 13

[0361] In the embodiment of the present application, the register allocation of traversing funcC(f, e, f, e) can be called the third allocation. The third allocation generates two move instructions. At this time, active = {3, 6}.

[0362] Table 9 shows the register allocation before traversing funcC(f,e,f,e), and Table 14-1 shows the register allocation after traversing funcC(f,e,f,e). Two move instructions are generated: Move v4, v6; Move v5, v3. That is, funcC(f,e,f,e) can use the consecutive registers shown in Table 14-2 when calling it.

[0363] Table 14-1

[0364] Table 14-2

[0365] At this point, all range instructions have been allocated. The active range after allocation is shown in Figure 11. It can be seen that the parameters in funcA(a,b,c,d), funcB(d,a,b,e), and funcC(f,e,f,e) have all been allocated registers. Next, registers are allocated for non-range instructions.

[0366] (4) Allocate registers for instructions other than range instructions (i.e., non-range instructions).

[0367] In some embodiments, after the range instruction allocation is completed, register allocation of parameters of non-range instructions (which may be called regular parameters) may be performed.

[0368] Assume that x is a parameter outside the range instruction, and its active range is shown in the horizontal area in Figure 12, that is, [6,8]. Then, for parameter x, we can establish set A, which is the registers that intersect with the active range of parameter x. As shown in Figure 12, the active ranges of the registers assigned to the parameters (register v0, register v1, register v3, register v6) intersect with the active range of the current parameter, and the active ranges of the registers in SpillFill (register v4, register v5) intersect with the active range of the current parameter. Then, the set A corresponding to parameter x includes the above registers v0, register v1, register v3, register v4, register v5, and register v6. A register outside set A is selected as the target register for parameter x. For example, parameter x is ultimately assigned register v2.

[0369] In the prior art, registers are often assigned to instruction parameters according to the order in which they are executed, and move instructions are used to copy operands to consecutive registers before using the range instruction, resulting in a large number of move instructions. However, the present embodiment prioritizes assigning consecutive registers to the range instruction, which can reduce move instructions, resulting in fewer instructions in the bytecode file, better performance, and a smaller application installation package.

[0370] Please refer to FIG13 , which is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

[0371] As shown in Figure 13, the electronic device provided in the embodiment of the present application can be used to implement the method described in the above method embodiment, and reference can be made to the description in the above method embodiment. The electronic device can be a compiler, or a chip therein. Exemplarily, the electronic device includes one or more processors 1301 and a transceiver 1302. The electronic device may further include a memory 1303. In one implementation, the electronic device also includes input and output devices, such as a display screen and a keyboard (not shown in Figure 13).

[0372] The processor 1301 is used to control the entire electronic device, execute software programs, and process data from the software programs. The memory 1303 is primarily used to store software programs and data. The transceiver 1302 may include a control circuit and an antenna. The control circuit is primarily used to convert baseband signals into radio frequency signals and process the radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as a touch screen, display, and keyboard, are primarily used to receive user input and output data to the user.

[0373] When the electronic device is powered on, the processor 1301 can read the software program in the memory 1303, interpret and execute the instructions of the software program, and process the data of the software program. The processor 1301, the transceiver 1302, and the memory 1303 can be connected via a communication bus.

[0374] In one implementation, the processor 1301 may store instructions, which may be computer programs. The computer programs, when executed on the processor 1301, may cause the electronic device to perform the methods described in the above method embodiments. The computer programs may be embedded in the processor 1301, in which case the processor 1301 may be implemented by hardware.

[0375] In one implementation, the electronic device may include a circuit that can implement the functions of sending, receiving, or communicating in the aforementioned method embodiments. The processor and transceiver described in this application can be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit (RFIC), a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (nMetal-oxide-semiconductor, NMOS), P-channel metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (bipolar junction transistor, BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0376] It is understandable that the electronic device shown in the embodiment of the present application may also have more components than those shown in FIG13 , and the embodiment of the present application does not limit this.

[0377] An embodiment of the present application further provides a register allocation system, which includes an electronic device (such as a compiler), which can be used to execute the method in any of the aforementioned method embodiments.

[0378] In addition, the present application also provides a computer program, which is used to implement the operations and / or processing performed by an electronic device (such as a compiler) in the method provided by the present application.

[0379] The present application also provides a computer-readable storage medium, which stores computer code. When the computer code runs on a computer, it enables the computer to execute the operations and / or processing performed by an electronic device (such as a compiler) in the method provided by the present application.

[0380] The present application also provides a computer program product, which includes computer code or computer program. When the computer code or computer program runs on a computer, the operations and / or processing performed by an electronic device (such as a compiler) in the method provided by the present application are executed.

[0381] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0382] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected based on actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0383] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0384] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0385] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A register allocation method, characterized in that: The method comprises: Obtaining a plurality of instructions, the plurality of instructions including at least one first instruction and at least one second instruction; the first instruction operates on consecutive registers; the at least one second instruction is an instruction in the plurality of instructions other than the at least one first instruction; allocating a target register corresponding to an i-th parameter in the first instruction to an i-th parameter, where the first instruction includes n parameters, where n is a positive integer greater than 1, and i is a positive integer not greater than n, and each of the n parameters uniquely corresponds to a target register; After registers are assigned to the parameters in the at least one first instruction, registers are assigned to the parameters in the at least one second instruction.

2. The method according to claim 1, characterized in that The method further comprises: When traversing the first instruction, determining the allocated registers corresponding to the parameters among the n parameters and the registers to be processed that are not allocated with parameters; the registers to be processed are registers that can be allocated by the multiple instructions; Determine target registers corresponding to the n parameters based on allocated registers corresponding to the parameters in the n parameters and registers to which parameters are not allocated in the registers to be processed; wherein the target register corresponding to the i-th parameter is the register to which parameters are not allocated, or the target register corresponding to the i-th parameter is the allocated register corresponding to the i-th parameter.

3. The method according to claim 2, characterized in that The determining, based on the allocated registers corresponding to the parameters in the n parameters and the registers to be processed that are not allocated with parameters, the target registers corresponding to the n parameters includes: When traversing the first instruction, determining a first set from the registers to be processed, the first set being used to indicate at least one first register, and the target registers corresponding to the first registers all satisfying: the target registers corresponding to the first registers are consecutive registers, the target registers corresponding to the first registers have a one-to-one correspondence with the n parameters, and the target register corresponding to the i-th parameter is the register to which the parameter is not allocated or the allocated register corresponding to the i-th parameter; Determining a first starting register from the first set, each register in the first set uniquely corresponds to a first value, the first value corresponding to the first starting register being the smallest of the first values corresponding to the at least one first register, the first value being the number of first parameters in the n parameters, the first parameters being parameters of allocated registers, the allocated registers corresponding to the first parameters being different from the target registers corresponding to the parameters; and the first starting register being the target register corresponding to the first parameter executed in the first instruction; The target register corresponding to the first starting register is the target register corresponding to the n parameters.

4. The method according to claim 3, characterized in that The method further comprises: Based on the target register corresponding to the first starting register, the target register corresponding to the j-th parameter is assigned to the j-th parameter in the first instruction, where j is a positive integer not greater than n, the j-th parameter is a parameter of the n parameters to which a register is not assigned, and the target register corresponding to the first register includes the target register corresponding to the j-th parameter.

5. The method according to claim 3 or 4, characterized in that The parameter of the n parameters to which the register has been allocated includes the kth parameter, where k is a positive integer not greater than n, and the method further includes: When the target register corresponding to the kth parameter and the allocated register corresponding to the kth parameter are different, a third instruction corresponding to the kth parameter is generated, and the third instruction corresponding to the kth parameter is used to copy the kth parameter from the allocated register corresponding to the kth parameter to the target register corresponding to the kth parameter.

6. The method according to any one of claims 2 to 5, characterized in that The n parameters include m second parameters, where the second parameters are parameters of unassigned registers, and m is an integer greater than 1 and not greater than n; The first parameter of the allocated register among the m second parameters is parameter j, and the method further includes: Generate a third instruction corresponding to a p-th parameter, where the p-th parameter is a parameter among the m second parameters other than the parameter j, p is a positive integer not greater than m, and each of the n parameters uniquely corresponds to a target register; the third instruction corresponding to the p-th parameter is used to copy the parameter j from the target register corresponding to the parameter j to the target register corresponding to the p-th parameter.

7. The method according to any one of claims 2 to 6, characterized in that Allocating registers to the parameters in the at least one second instruction includes: For the qth parameter in the at least one second instruction, construct a second set, where the second set is used to indicate a second register, where the second register satisfies: the second register is a register to which a parameter has been allocated or a register in a third instruction corresponding to the parameters in the multiple instructions, and an active interval of the second register intersects with an active interval of the qth parameter; Selecting a third register from the registers to be processed excluding the second set; Allocate the qth parameter to the third register.

8. The method according to claim 5 or 6, characterized in that The plurality of instructions are a first intermediate representation (IR) obtained by parsing source code of the first application, and the method further includes: Adding a third instruction corresponding to the parameters in the plurality of instructions to the first IR to obtain a second IR; Based on the second IR, a bytecode file of the first application is generated, and the bytecode file of the first application is used to run the first application.

9. An electronic device, characterized in that: The electronic device includes one or more processors and one or more memories; wherein the one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, and the computer program code includes computer instructions, and when the one or more processors execute the computer instructions, the electronic device executes the method as described in any one of claims 1-8.

10. A computer program product comprising instructions, characterized in that When the computer program product is run on an electronic device, the electronic device is enabled to perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on an electronic device, the electronic device is caused to execute the method according to any one of claims 1 to 8.

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