P-i-n component and method for the production thereof

Abstract

The invention relates to an electronic component having a useful layer consisting of a compound semiconductor, said useful layer being spread out in a planar manner above a substrate (1) of the component and comprising, when the layer is viewed from above, an n-doped region (9), a p-doped region (10) and an intrinsically conductive region (8) that separates the p-doped region (10) from the n-doped region (9). The invention also relates to a method for producing an electronic component, wherein a layer system having two walls (2a, 2b) is provided on the layer system, wherein the two walls (2a, 2b) are arranged partially opposite one another and are spaced apart from one another, and semiconductor material is deposited on the layer system parallel to the two walls (2a, 2b) and at the same time a first dopant (Si) is deposited from one side obliquely with respect to the first wall (2a) and at the same time a second dopant (C) is deposited obliquely with respect to the second wall from the other side, specifically in such a way that the deposition in one working step produces an n-doped region (9), a p-doped region (10) and an intrinsically conductive region (8) that separates the p-doped region (10) from the n-doped region (9).

Description

[0001] Pin - component and method for manufacturing

[0002] Description

[0003] The invention relates to an electronic component and a method for producing the electronic component.

[0004] An electronic component can comprise one or more layers or regions of semiconducting materials. Semiconducting materials can be at least partially doped. For example, a semiconducting layer can be p- or n-doped to change the electrical conductivity of the semiconductor. By doping a region, the electrical conductivity of the doped region of a semiconducting material can be greatly increased or greatly reduced, for example, to create an electrical contact or an electrically insulating region.

[0005] Examples of electronic components are a field-effect transistor, a diode, or a photodetector. Between a p-doped and an n-doped region in such a component, there can be a lightly doped region or an undoped region with intrinsic conductivity, thus separating the p-doped region from the n-doped region. Such a component is referred to as a pin component. An example of a silicon-based photodetector is known from the document DE 10 2023 111 694 A1. The production of the photodetector known from the document DE 10 2023 111 694 A1 comprises the application of masks and ion implantation in order to dope desired regions. However, ion implantation can create defects in the semiconductor material and thus reduce the performance of the component. Undesired defects can, under certain conditions, be reduced by heating.However, this induces diffusion processes that can damage the component in other ways.

[0006] Doping by ion implantation can be avoided by using a layered structure. Layers of a pin component are then produced one after the other and stacked on top of each other. A first doped layer can therefore be applied to a substrate or a layer system. An intrinsically conductive layer can be applied to the first doped layer. A second doped layer can be applied to the intrinsically conductive layer. With such a structure, it is necessary for operation to electrically contact the doped layers. For this purpose, it may be necessary to create access through the second doped layer and through the intrinsically conductive layer in order to be able to electrically contact the first doped layer through the access.Such an electrically conductive contact not only requires increased manufacturing effort, but also creates negative shadowing effects, thus impairing performance. If the intrinsically conductive layer is to be irradiated with light to create a light-sensitive component, translucent materials must be applied to at least one side of the intrinsically conductive layer. This limits the choice of materials. A suitable passivation is also not possible with such a vertical structure.

[0007] For selective deposition, walls can be used to utilize the shadow cast by a wall. Corresponding methods for producing electronic components are known from the publications EP 0 201 713 A1, US 2022 / 0238781 A1, EP 1 355 359 A1, DE 696 15 628 T2, and US 2022 / 0149261 A1.

[0008] The object of the invention is to further develop an electronic component and a method for manufacturing the component. In particular, an electronic pin component is to be further developed.

[0009] The object of the invention can be achieved by an electronic component having the features of the first claim and by a method having the features of the dependent claim. The dependent claims relate to advantageous embodiments.

[0010] To achieve this goal, an electronic component may comprise a layer which, for ease of differentiation, will also be referred to as the wear layer. The wear layer may consist of a compound semiconductor. When viewed from above, the wear layer may contain a p-doped region. This p-doped region then extends from the underside of the wear layer to the top side of the wear layer. When viewed from above, the wear layer may contain an n-doped region. This n-doped region then extends from the underside of the wear layer to the top side of the wear layer. The n-doped region may be directly adjacent to the p-doped region. In this case, it may be a diode with a pn junction. The diode may be a light-emitting diode. When viewed from above, the wear layer may contain an intrinsically conductive region which separates the p-doped region from the n-doped region.The intrinsically conductive region then extends from the underside of the wear layer to the top side of the wear layer. The wear layer can be applied directly to the top side of a substrate. However, one or more other layers, also referred to as intermediate layers, can also have been applied to the top side of the substrate beforehand. The wear layer can then be applied to the top side of the last applied intermediate layer.

[0011] A region called a p-doped region does not have any additional n-type doping. A region called an n-doped region does not have any additional p-type doping.

[0012] Doping in a region can be determined using various methods, such as Rutherford backscattering spectrometry, photoluminescence spectroscopy (PL spectroscopy), or mass spectroscopy. For example, atoms can be released from regions of the wear layer by sputtering, and the resulting released atoms can be analyzed to determine doping.

[0013] A layer is a compound semiconductor spread out over a surface above a substrate. The substrate is therefore located beneath the top side of the layer. The wear layer comprises only one compound semiconductor. Regions within the wear layer therefore differ at most in terms of doping. The wear layer generally runs parallel to the top side of the substrate. The wear layer is generally flat and is therefore located in exactly one plane above the top side of the substrate. There can also be several wear layers above a substrate. For example, the efficiencies of solar cells or detectors can be improved by having several wear layers. One wear layer then differs from the other in terms of the material. There is therefore a first compound semiconductor in the first wear layer, which differs from a second compound semiconductor in the second wear layer.

[0014] The term "substrate" refers to the component of the part that supports the other components of the part. During manufacturing, the other components are applied to the substrate.

[0015] The wear layer can in particular be produced in a single work step, even if it comprises the aforementioned p-doped region, the aforementioned n-doped region and the aforementioned intrinsically conductive region, or consists of these three regions. The wear layer consists of these three regions if the wear layer has no other regions. However, if the component is produced using a particularly suitable process, there will also be other regions of the wear layer, which can, for example, be both p-doped and n-doped. Such regions of the wear layer can border both the p-doped region and the n-doped region, for example, border them laterally. A region that is both p-doped and n-doped is then primarily present for manufacturing reasons. Such a region could, under certain circumstances, be of some use for reasons of electronic insulation in the component.As a rule, such electronic isolation by a layer region that is both p- and n-doped is fundamentally unnecessary.

[0016] The provision of a compound semiconductor makes it possible to provide a deposition process that avoids the need for ion implantation to create doped regions. It also eliminates the need to apply a mask to the top of the wear layer for doping, allowing only a portion of the wear layer to be doped.

[0017] Doped regions can be directly electrically contacted on top of the wear layer. This eliminates the need to create access to a lower doped layer. The component can therefore have an electrical contact on top of the wear layer that directly contacts the p-doped region. The component can therefore have an electrical contact on top of the wear layer that directly contacts the n-doped region. An electrical contact is electrically conductive. An electrical contact can be made of metal. The two electrical contacts are spaced apart and thus electrically separated from each other.

[0018] To achieve a particularly high-performance component, the metal is preferably selected based on the doped region. The metal used to contact the p-doped region is then different from the metal used to contact the n-doped region. Metals can also be selected in such a way that a passivating material for the intrinsically conductive region, such as zinc selenide, cannot grow on the top surface.

[0019] A compound semiconductor is a semiconductor material consisting of two or more chemical compounds of different chemical elements. An example of a compound semiconductor is a III-V compound semiconductor. A III-V compound semiconductor consists of elements from the chemical main group III (earth metals / boron group) and V (nitrogen-phosphorus group), the combination of which causes the electrical conductivity of semiconductors and / or determines the fundamental optoelectronic properties of the semiconductor. III-V compound semiconductors enable high efficiencies.

[0020] Therefore, the wear layer preferably consists of a III-V compound semiconductor.

[0021] The III-V compound semiconductor preferably comprises gallium (Ga) and arsenide (As) to create a high-performance component. The III-V compound semiconductor preferably comprises indium (In) or aluminum (Al) to create a high-performance component.

[0022] Because the intrinsically conductive region extends to the top of the wear layer and there are doped regions adjacent to it, the component can be a particularly high-performance light-sensitive component, such as a photodetector. While a transparent layer can be applied to the intrinsically conductive region, it is not necessary to apply a doped, semiconducting, transparent layer to the intrinsically conductive region, which can have a negative impact on performance if the component is intended to be a light-sensitive component. It is also not necessary to apply a metal layer.

[0023] A light-sensitive component is a component designed to operate when light hits the intrinsically conductive region. The light-sensitive component responds to the intrinsically conductive region, for example, by generating an electric current.

[0024] The p-doped region of the wear layer can be coated with an electrical contact made of metal, for example, platinum (Pt). The metal with the platinum then forms an electrical contact that directly contacts the p-doped region. The metal with the platinum can also comprise titanium, for example, in order to be able to make particularly effective electrical contact with the p-doped region. Platinum may have been selected because zinc selenide cannot grow on platinum. A first metal, such as titanium, can be deposited first. After that, a metal such as platinum can be deposited. A layer of platinum is then located on a layer of titanium.

[0025] Preferably, a passivating layer is or will be applied to the intrinsically conductive region. The provision of platinum makes it particularly easy to apply such a passivating layer, since there are suitable materials that cannot be deposited on the metal containing platinum. Another example of a metal with which a passivating layer cannot be deposited is aluminum.

[0026] The component's performance can be improved by applying a passivating material to the intrinsically conductive layer. A suitable material for this purpose can be a II-VI compound semiconductor. Zinc selenide (ZnSe) is a particularly suitable II-VI compound semiconductor, which, among other things, cannot be deposited, or at least only with difficulty, on a platinum-containing metal. Zinc selenide has a particularly good passivating effect and is transparent. The intrinsically conductive region can therefore be coated with zinc selenide to create a particularly high-performance, light-sensitive component.

[0027] The n-doped region of the wear layer can be coated with aluminum (Al) and / or indium (In) to provide a particularly high-performance metal electrical contact for the n-doped region.

[0028] A first wall or a first trench can be laterally adjacent to the p-doped region and, if applicable, to the intrinsic region of the electronic component. A second wall or a second trench can be laterally adjacent to the n-doped region and, if applicable, to the intrinsic region of the electronic component. The two walls can be arranged diagonally opposite one another. The intrinsic region, if present, can be located between the first and second walls or the first and second trench. The two walls or the two trenches, if present, can be directly opposite one another only in the intrinsically conductive region and otherwise diagonally opposite one another. By providing the walls, the wear layer can be produced in just one work step. The walls can be etched away following production. Therefore, trenches can be present instead of walls.

[0029] Additional manufacturing advantages arise if another wall protrudes at an angle from one end of the first wall - if present - for example in the intrinsically conductive region. The first wall can enclose an angle with the other wall, which can be a 90° angle, for example, to enable particularly practical production. However, the angle can also be more than 70° and / or less than 110°, for example. The first wall can form an L-shape with the other wall. If the two walls have been etched away, then trenches can be present instead of walls. Additional manufacturing advantages arise if another wall protrudes at an angle from one end of the second wall - if present - for example in the intrinsically conductive region. The second wall can enclose a right angle with the other wall, i.e. a 90° angle, to enable particularly practical production.However, the angle can also be, for example, more than 70° and / or less than 110°. The second wall can form an L-shape with the other wall. If the two walls were etched away, trenches may be present instead of walls.

[0030] The two further walls can be arranged directly opposite or almost directly opposite each other if a pn junction or a junction with a very narrow intrinsic region is to be produced in one work step.

[0031] If the wear layer of the electronic component is manufactured in a single step using walls, the wear layer can be strip-shaped and / or flat. If the wear layer of the electronic component is manufactured in a single step using walls, for example, using a first wall, a second wall, and walls protruding from it, the wear layer can only be straight. Each region adjoining the intrinsic region is then the same width as the intrinsic region. The wear layer then has no bends.

[0032] However, it is also possible that a preferred manufacturing process results in the wear layer having bends. Starting at a front end of the wear layer, the wear layer can initially bend in a first direction and thus flow into the intrinsically conductive region. Behind the intrinsically conductive region, the wear layer can then bend in a second, opposite direction. The course of the wear layer can be rotationally symmetrical, specifically in the case of a 180° rotation.

[0033] It is possible for the aforementioned region, which is both p-doped and n-doped, to laterally border the p-doped region or the n-doped region. Depending on the manufacturing process, for example, the wear layer can therefore be angular or curved. A region that borders the p-doped region and can be both p-doped and n-doped can extend to one side. Another region that borders the n-doped region and can be both p-doped and n-doped can extend to another side. Starting from one end of the wear layer, the wear layer can therefore first pivot to the right and later pivot in the opposite direction, to the left. However, starting from one end of the wear layer, the wear layer can also conversely first pivot to the left and later pivot to the right.

[0034] An intermediate layer can be present between the wear layer and the substrate. The intermediate layer can act as a buffer layer and / or as an electronically insulating layer to improve the properties of the component. If, for example, the material of the intermediate layer is selected to have an electronically insulating effect, this can prevent charge carriers generated in the wear layer from undesirably flowing to the substrate.

[0035] A method for producing an electronic component can comprise providing a substrate with one or more walls. The one or more walls can protrude from a surface of the substrate, in particular protrude vertically. Part of the surface of the substrate is then covered by the wall. Otherwise, the surface of the substrate can be completely or partially exposed. The method can comprise depositing a first substance on the exposed surface of the substrate. If, in addition to the wall, one or more layers are present on the surface, the method can comprise depositing a first substance on the exposed surface of such a layer. Such a layer on the surface of the substrate can be applied directly or indirectly to the surface. The method can comprise depositing the first substance in a direction oblique to the wall.This allows the substance to be deposited on the exposed surface at a distance from the wall. The wall then shields an area of ​​the exposed surface in such a way that the first substance cannot be deposited on this area. The first substance can then only be deposited on a portion of the exposed surface.

[0036] The wall acts like a mask when a substance is deposited at an angle to the wall, as described above. Once a substance has been deposited, the wall does not need to be removed to deposit further layers as desired.

[0037] The wall may have one side that is straight and flat like a plane. Preferably, the wall has two opposite sides that are straight and flat like a plane. The two opposite long sides of a wall may be parallel to each other. One side of the wall that is straight and flat like a plane may form a right angle with the surface of the substrate. Each side of a wall may form a right angle with the surface of the substrate. The length of the wall may be greater than the thickness and / or the height of the wall. The wall may be impermeable to substances. The wall may be made of only one material or more than one material. The wall may be made of a different material or materials than the substrate. The wall may be attached to the substrate using an adhesion promoter.To create a wall, an adhesion promoter layer, such as titanium, can first be applied to a substrate. An AIO is preferred. X to avoid disadvantages during production. A layer consisting of the wall material can be applied to the optionally present adhesion promoter layer or directly to the substrate. The material can be a dielectric, preferably an electrically insulating dielectric. A mask made of platinum, for example, can then be applied to the layer. The mask covers the area of ​​the wall to be produced. The layer can be removed, for example, by ion etching, provided it is not shielded by the mask. This creates at least one wall on a substrate.

[0038] The first substance can consist of molecules, atoms, and / or ions. The first substance can consist of identical molecules, atoms, or ions. The first substance can consist of different molecules, atoms, or ions. The first substance can be gaseous during its deposition.

[0039] The substrate may be self-supporting. The substrate may comprise one surface that is straight and flat like a plane. The substrate may comprise two surfaces that are straight and flat like a plane. The two straight and flat surfaces may form the top and bottom of the substrate. The substrate may be round or square when viewed from a top view of a straight and flat top. The diameter of the substrate, or the length and width of the substrate, may be greater than the height of the substrate. The substrate may be monocrystalline or polycrystalline. The substrate may be made of a semiconductor such as gallium arsenide (GaAs) or silicon. The substrate may be a wafer.

[0040] The method may comprise depositing a second substance on the exposed surface of the substrate or an exposed surface of a layer applied to the surface of the substrate. The second substance may be deposited in a direction parallel to the wall. This allows the second substance to be deposited on the exposed surface without any distance from the wall. In this case, the wall does not act as a mask with respect to the exposed surface and therefore does not shield any area of ​​the exposed surface such that it cannot be reached by the second substance. There is then a wall that partially shields the exposed surface for the first substance, but not for the second substance. This does not preclude the possibility of a second wall on the substrate that acts as a mask for both substances or only for the second substance.

[0041] The second substance may be composed of different molecules, atoms, and / or ions than the first substance. The second substance may be composed of the same molecules, atoms, and / or ions as the first substance.

[0042] The first substance can consist, for example, of zinc chloride (ZnCl2) or nitrogen (N), for example to dope a II-VI semiconductor. The second substance can consist of zinc (Zn) and / or selenium (Se). The second substance can consist of cadmium and / or oxygen. The first substance can be carbon, magnesium, silicon, or tellurium, for example to dope a III-V semiconductor. The second substance can be gallium and / or arsenic. The second substance can be indium and / or antimony. The second substance can be aluminum and / or phosphorus.

[0043] The first and second substances can be deposited simultaneously. There may then be an area on the exposed surface where the second substance is deposited, but not the first substance. The first and second substances can then be deposited on another area. This makes it possible to coat different areas of an exposed surface differently in a single step.

[0044] The amount of the first substance can be much smaller than the amount of the second substance. This makes it possible to dope the second substance with the first substance. In particular, a layer can be produced that completely encompasses the second substance. This layer can have a region doped with the first substance. This layer can have a second region not doped with the first substance. Thus, a layer with a doped region and an undoped region can be created.

[0045] Doping refers to the introduction of foreign atoms into another substance. The introduced quantity of foreign atoms is very small compared to the other substance. The introduced quantity of foreign atoms cannot exceed 100 ppm. The quantity of foreign atoms can exceed 0.1 ppm. The foreign atoms can form defects in a semiconductor material, altering the electrical conductivity of the semiconductor material.

[0046] The method may include depositing a third substance on the exposed surface of the substrate or an exposed surface of a layer applied to the surface of the substrate simultaneously with the second substance. The third substance may be deposited in a direction parallel to the wall. This allows the third substance to be deposited on the exposed surface without any distance from the wall.

[0047] The second substance and the third substance can be such that a layer can only form on an exposed surface if the second substance and the third substance together reach an area of ​​the exposed surface. If an exposed surface is to be only partially coated with a layer comprising the second and the third substance, then it may be sufficient to shield only one area from deposition of only one of the two substances by the wall in order to achieve this. It may be sufficient to shield a first area from deposition of the second substance by the wall and another second area from deposition of the third substance in order to only partially coat the exposed surface with a layer formed from the second and the third substance. The first and the second area are then not coated with this layer.

[0048] A layer's surface can be straight and flat. The layer's surface can be curved or stepped. Such a layer's surface is exposed if the layer is not located between two layers or between the substrate and another layer.

[0049] The amount of the first substance can be much smaller than the amount of the third substance. This allows a layer to be produced that includes the third substance and is at least partially doped with the first substance.

[0050] In addition to the first wall, there may be another wall that forms an angle with the first wall. The other wall may have a long side that forms a right angle with a long side of the first wall. The other wall may be arranged so that separate layers can be formed by deposition. This may be the case if the distance between the two walls is smaller than the distance between the deposited layer and the first wall due to deposition at an angle to the wall.

[0051] In addition to the second wall, there may be another wall that forms an angle with the second wall. The other wall may have a long side that forms a right angle with a long side of the second wall. The other wall may be arranged so that separate layers can be formed by deposition. This may be the case if the distance between the two walls is smaller than the distance between the deposited layer and the second wall due to deposition at an angle to the wall.

[0052] It can be deposited using a device comprising a plurality of heads from which a substance can emerge. The device can be configured such that a first substance can emerge from a first head. The device can be configured such that a second substance can emerge from a second head. The device can be configured such that a third substance can emerge from a third head. Such a device can simplify and / or accelerate the manufacture of an electronic component.

[0053] The deposition device may include a holder for holding the substrate. The holder may be designed such that the substrate can be secured within the device. Such a device may further simplify and / or accelerate the manufacture of an electronic component.

[0054] The device used for deposition can be configured to change the position of the holder relative to the heads. This makes it possible to change the position of the wall on the substrate relative to the heads. This allows the shielding behavior of the wall relative to a head to be adjusted. Such a device can further simplify and / or accelerate the production of an electronic component.

[0055] The heads of the deposition device can be arranged around the substrate for the deposition of one or more substances. This makes it possible to coat the substrate or a layer on the substrate from different directions, thus optionally shielding or not shielding an area of ​​an exposed surface from deposition of a substance through the wall. The heads of the deposition device can be located above or below the substrate to achieve this. Typically, coating devices are designed so that substrates are installed upside down, and the heads are therefore arranged below the sample, pointing upwards.

[0056] The holder or the substrate can advantageously be rotated relative to the heads in order to be able to adjust the shielding behavior of the wall by simple rotating movements.

[0057] A substance can be deposited by vapor deposition, such as molecular beam epitaxy (MBE), to produce, for example, a thin, crystalline layer. A wall allows one or more regions to be selectively doped during the growth process. This can also be achieved in a technically simple manner, as only the direction of deposition requires appropriate adjustment.

[0058] A wall may have been manufactured separately from the substrate. The wall may have been attached to a surface of the previously manufactured substrate. The wall may have been attached to a surface of a previously applied coating of the substrate. The wall may have been formed by patterning. A part may have been attached to a surface of the substrate, which is subsequently patterned. A wall may have been manufactured by patterning a surface of the substrate. The substrate may be a planar Epiready semiconductor substrate. Patterning may be performed using lithography and / or etching. Patterning may comprise a combination of wet and dry chemical etching. A wall may be made of silicon dioxide or comprise silicon dioxide. A wall may be attached to the substrate using titanium as an adhesion promoter. A wall may comprise a final layer of platinum.Known deposition processes can be used to create the wall. The minimum achievable feature sizes may only be limited by the lithography method used. Shielded and open, unshielded areas can also be defined by the design of a wall, namely by its length and height. If more than one wall is present, shielded and open, unshielded areas can also be defined by the distances between applied walls. Since the width of the shielded areas on both sides of the walls is purely geometrical, it can be directly adjusted by the height of the walls. Walls just a few micrometers high typically result in shielding areas that are also a few micrometers wide.

[0059] Pre-structuring of the wall can be performed on a commercially available Epi-ready wafer. The substrate surface can then remain protected by the existing oxide during pre-processing. Before growth begins, i.e., the deposition of one or more substances, known and proven methods for preparing the substrate surface can be used. This can include thermal treatment under an ultra-high vacuum (UHV) atmosphere and / or a low-temperature treatment with atomic hydrogen. Analogous to growth on unstructured wafers, for example, an oxide and / or carbon compounds on the surface of the substrate can be removed to obtain ideal starting conditions for growth.

[0060] The invention particularly relates to material deposition on a substrate pre-structured by one or more walls. It can be exploited that, in the case of compound semiconductors, growth only takes place where the individual elements, for example the second and third materials mentioned, come together. Examples of such compound semiconductors are gallium arsenide (GaAs) or zinc selenide (ZnSe). Therefore, III-V or II-VI compound semiconductors, for example, can advantageously be deposited as a layer. For shielding, it may be sufficient to suitably align a substrate relative to a material flow. Since typical dopant concentrations are in the order of 1 E17 - 1 E19 cm³, 3and thus only approximately every 10,000 to 1,000,000 atoms of a compound semiconductor is replaced by a foreign atom, no change in layer thickness occurs in the undoped region in the case of in-situ doping. For example, if ZnSe is doped with CI, only every 10,000 to 1,000,000 Se atoms is replaced by a CI atom.

[0061] Shielding can be adjusted for each new substance being deposited independently of other substances by aligning it with its material flow or a head from which the new substance emerges. An effusion cell can serve as a head, for example, to create a layer on the substrate using MBE. By selectively switching the deposition of a dopant on and off, in-situ layer systems can also be created within a growth process without having to remove one or more walls. The process for the selective doping of compound semiconductors is not limited to such material systems. The process can also be combined with other in-situ growth steps.Other material systems such as metals or dielectrics, which can be produced using MBE or electron beam evaporation, for example, can also be shielded by the one or more applied walls and thus selectively deposited. The process can also be combined with uniform material deposition, for example, using chemical vapor deposition (CVD) or atomic layer deposition (ALD), for example, to passivate an entire layer.

[0062] A selectively doped layer can be processed, for example, using cleanroom processing. A selectively doped layer can be processed using lithography and other patterning techniques to isolate individual components.

[0063] It cannot be ruled out that one or more walls will eventually be removed again, for example by wet chemical means.

[0064] The component can, for example, comprise a II-VI semiconductor or a III-V semiconductor. For example, walls can be pre-structured on a III-V semiconductor substrate such as a GaAs substrate. However, the walls can also be applied to a coating of the semiconductor substrate. A first wall can enclose an angle with another wall. A second wall can enclose an angle with another wall. The first and second walls can lie opposite each other, partially overlapping. The two further walls can protrude outwards from the ends of the first and second walls, respectively, and be arranged offset from one another. Subsequently, a semiconducting layer, such as a GaAs layer, which is e.g. 100 nm thick, can be applied to the exposed surface of the substrate or the coating, in such a way that one or more walls do not shield, i.e. in a non-shielding configuration.However, a semiconducting layer, such as a GaAs layer, with a thickness of 50 to 200 nm, for example 100 nm, can also be applied subsequently to areas of the exposed surface of the substrate or coating in such a way that one or more walls provide shielding, i.e. in a shielding configuration. It is possible to produce a buffer layer and / or electronically insulating layer in this way that, starting from a front end, initially bends in a first direction and later bends in a second, opposite direction. The layer can be rotationally symmetrical. When viewed from above, there is then a central point. If the layer is rotated by 180°, the layer is imaged onto itself.

[0065] If a ternary compound semiconductor is to be suitably deposited, an additional metal can be deposited in a non-shielding configuration. The additional metal can be indium or aluminum, for example. Areas of interest can be coated with InGaAs or AlGaAs, for example, to deposit a buffer layer and / or electronically insulating layer directly or indirectly on the substrate.

[0066] Subsequently, a semiconductor layer which is, for example, 10 to 100 nm thick, for example 50 nm thick, can be applied in a shielding configuration and can be the useful layer. For example, a semiconductor layer which is, for example, 50 nm thick and doped in regions can be applied in a non-shielding configuration in a shielding configuration. Substances can then be deposited in such a way that a layer made of a compound semiconductor is formed on the previously deposited layer. This layer has an intrinsically conductive region which separates a p-doped region of the layer from an n-doped region of the layer. To produce the layer or useful layer, a first substance of the compound semiconductor can be deposited on the buffer layer parallel to the first and second walls, but at an angle to the other walls. To produce the layer or useful layer, a second substance of the compound semiconductor can be deposited on the buffer layer parallel to the first and second walls, but at an angle to the other walls.A useful layer can be deposited on the previously deposited layer parallel to the first and second walls, but from the opposite direction and at an angle to the other walls. To produce the layer, a first dopant can be deposited on the previously deposited layer at an angle to the first and second walls. To produce the layer or useful layer, a second dopant can be deposited on the previously deposited layer at an angle to the first and second walls, but from the opposite direction to the deposition of the first dopant. The first dopant is then selected such that a region that borders the intrinsically conductive region on one side is p-doped. The second dopant is then selected such that another region that borders the intrinsically conductive region on another, opposite side is n-doped. In this way, a useful layer can be produced in a single work step.Additionally, this manufacturing process may have resulted in areas that are both p-doped and n-doped. However, this is not necessarily the case. For example, it is not impossible that masks were applied to prevent the formation of areas in the wear layer that are both n-doped and p-doped. However, such additional masking, while harmless, does not necessarily make technical sense.

[0067] Subsequently, in a shielding configuration, a metal can be deposited such that a doped region, for example the n-doped region, is at least partially or completely coated with a metal. The metal is then not deposited on the intrinsically conductive region. The metal is then also at least not completely deposited on the other, for example p-doped region. Preferably, the other, for example p-doped region is then not coated with metal, i.e. not even partially. For example, aluminum and / or indium can have been deposited on the n-doped region, but not on the p-doped region. To deposit metal as described, the metal can be deposited obliquely to the first wall. The layer thickness of the deposited metal can be, for example, 50 nm to 200 nm. The layer thickness of the deposited metal can be, for example, 100 nm.

[0068] Subsequently, in a shielding configuration, a metal can be deposited such that the other doped region, for example the p-doped region, is at least partially coated with a metal. This metal is then also not deposited on the intrinsically conductive region. It is also possible that this metal is at least not completely deposited on the first deposited metal. For example, titanium and / or platinum can be deposited in this way on at least part of the p-doped region. For example, titanium and / or platinum can be deposited completely on the p-doped region. In order to deposit metal on at least part of the other doped region, the metal can be deposited obliquely to the second wall, but in the opposite direction compared to the previously described metal deposition.

[0069] A passivation layer, for example 10 to 100 nm, for example 30 nm thick, can then be applied in a shielding configuration or in a non-shielding configuration. The material of the passivation layer can be selected such that it cannot be deposited as a layer on top of the last applied metal. This can be achieved by applying a passivation layer to the intrinsically conductive region and yet deposited metal is at least not completely coated with a passivation layer. It can be achieved by not coating a metal region that electrically contacts one doped region with a passivation layer. It can be achieved by not coating another metal region that electrically contacts the other doped region with a passivation layer.Substances of the passivation layer, such as Zn and Se, can be deposited parallel to the first and second walls, for example. Substances of the passivation layer, such as Zn and Se, can be deposited at an angle to the other walls, for example. One substance of the passivation layer can be deposited at an angle from a first direction, and another substance of the passivation layer can be deposited at an angle from a second direction, for example, an opposite direction (as seen in plan view).

[0070] The invention enables a planar geometry of a component to be achieved through simultaneous selective p- and n-doping in one and the same epitaxial growth step. Two doping sources can be positioned opposite each other so that the material flows create complementary shadows on the walls. At the same time, both doping sources (as viewed from above onto the deposition) can also be arranged perpendicular to other material flows (e.g. arsenic and gallium for GaAs) of the layer materials. In addition, a further material source (e.g. indium) can be arranged vertically so that its material flows to the substrate surface without shadows or shielding by walls. In this way, for example, selective, simultaneous p- and n-doping of a ternary layer material such as InGaAs can be achieved. For reasons of feasibility, coatings are generally applied from bottom to top on the side of the substrate to be coated. However, this is not absolutely necessary.

[0071] The top side of the substrate refers to the side of the substrate to be coated, which is coated with the wear layer and optionally also with one or more intermediate layers.

[0072] Selective simultaneous doping enables the implementation of planar PIN diodes without the use of implantation techniques or annealing steps, making the component more stable and efficient. At the same time, the planar geometry enables the passivation of the light-sensitive layer, i.e. the intrinsic layer between the p- and n-doping, with other semiconductor materials. Shadowing of the light-sensitive layer by metal contacts is avoided. Both effects together drastically improve the performance of the component. The production of a PIN diode can be carried out entirely in-situ, i.e. the sample can remain in an ultra-high vacuum between the growth of the semiconductor layer and the metal deposition for the contacts. Consequently, any oxidation at the interfaces between the layers, which would degrade the component, can be avoided. Production using shadowing orShielding walls avoid subsequent fabrication steps such as lithography, etching, cleaning or further deposition steps, since the entire manufacturing process can be completed with epitaxy.

[0073] Epitaxy refers to the single-crystal growth of a thin layer on a single-crystal substrate or layer.

[0074] Production can comprise the following steps: a) A substrate with shading or shielding walls is provided before the deposition of a PIN diode. b) Growth by deposition of one or more binary (e.g. GaAs) or ternary (e.g. InGaAs) semiconductor layers without doping is optionally carried out. c) Simultaneous selective doping of one or more arbitrary semiconductor layers with p- and n- doping material is carried out, with the two doping sources being arranged opposite one another and, viewed from above, perpendicular to the material flows of semiconductor materials (here GaAs). Viewed from above, the substrate is arranged between the two doping sources. This creates a local n-doped region on one side and a local p-doped region on the other side.An area outside the shadows caused by the walls and the deposition directions can contain both dopings simultaneously. In particular, an undoped region of the deposited semiconductor material with intrinsic conductivity is created in the middle between the walls and between the p- and n-doped regions. This region can be the light-sensitive i-layer of a PIN diode. d) Metallization is carried out on the n-doped region of the layer, for example with aluminum. Metal is therefore deposited. e) Metallization of the p-contact on the p-doped layer, for example with titanium and platinum, is carried out.

[0075] Through steps d) and e), two ohmic metal contacts can be created on the selectively doped regions. At the same time, due to the shadows cast by both metals, the region with intrinsic conductivity can remain completely uncoated. f) Possible final passivation of the optically light-active layer with another layer material, such as ZnSe. In particular, ZnSe then grows only on the light-sensitive layer and not on the metal contacts. The metals of the metal contacts can be selected accordingly.

[0076] The invention is explained in more detail below with reference to figures.

[0077] They show:

[0078] Figure 1 : Substrate with wall;

[0079] Figure 2: Substrate with substances deposited parallel to the wall;

[0080] Figure 3: Substrate with substances deposited perpendicular to the substrate;

[0081] Figure 4: Substrate with substances deposited non-perpendicular to the substrate;

[0082] Figure 5: Substrate with substances deposited at an angle to the wall;

[0083] Figure 6: Substrate with dopant deposited obliquely to the wall;

[0084] Figure 7: Coating device;

[0085] Figure 8: Coating using a coating device;

[0086] Figure 9: Coating using a coating device for the production of a pin diode;

[0087] Figure 10: Substrate with applied walls;

[0088] Figure 11: Substrate from Figure 10 with deposited buffer layer;

[0089] Figure 12: Substrate according to Figure 10 with coating device;

[0090] Figure 13: Coating with selective doping; Figure 14: Component according to Figure 13 with coating device;

[0091] Figure 15: first electrical contact;

[0092] Figure 16: second electrical contact;

[0093] Figure 17: Passivation.

[0094] Figure 1 shows a substrate 1. The substrate 1 can be made of gallium arsenide or silicon, for example. One or more walls 2 can be created by structuring the substrate 1. The one or more walls 2 can protrude vertically upwards from the surface 3 of the substrate. To produce the substrate 1 with the one or more walls 2, a wafer, such as an epi-ready wafer, can be structured. A wafer can be structured, for example, using a laser.

[0095] If a substance is deposited on the substrate 1, a layer can form on the exposed substrate surface 3. A deposited layer can reach as far as the one or more walls 2, namely when the substance was deposited parallel to the one or more walls 2. If the deposition direction of the substance is such that the substance can strike a wall 2 at an angle and thus laterally, the wall 2 shields a region of the exposed substrate surface 3 behind it, adjacent to the wall 2. The substance cannot be deposited on this shielded region. The exposed surface 3 of the substrate 1 can then only be partially coated. Each wall 2 can therefore act like a mask, so that only a selected part of the exposed surface 3 is coated.

[0096] If a layer has already been deposited on the exposed surface 3 of the substrate 1, each wall 2 can act as a mask again to only partially coat the surface of the deposited layer. The one or more walls 2 can thus repeatedly act as a mask during the production of an electronic component without having to remove or add walls in between. The technical effort is minimal because each wall 2 only needs to be manufactured initially and can then serve as a mask multiple times as needed.

[0097] For example, a substance can be deposited by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). Figure 2 shows the case in which a substance is deposited in such a way that the deposition direction indicated by arrows runs parallel to the wall 2. A layer 4 is therefore deposited that extends completely to the wall 2. The exposed surface 3 of the substrate 1 is therefore completely covered. Figure 2 shows the deposition of Zn and Se on the substrate 1. The deposition directions of Zn and Se can run perpendicular to the surface 3 of the substrate 1. Figure 3 refers to this case in which the deposition direction of Zn and Se runs perpendicular to the surface 3 of the substrate 1. The view shown has been rotated by 90° compared to the view in Figure 2.

[0098] Although Figure 2 depicts the deposition process as if materials flow from top to bottom to be deposited on the substrate surface, in practice, the coating device used for deposition is located beneath the substrate 1. The wall 2 then protrudes downward from the substrate. The deposited materials then flow from bottom to top.

[0099] However, it is also possible that the deposition direction of Zn and Se forms an angle with the surface 3 of the substrate 1 that is less than 90°. Figure 4 refers to this case, where the deposition directions of Zn and Se form an angle with the surface 3 of the substrate 1 that is less than 90°. The view shown has been rotated by 90° compared to the view in Figure 2. Figure 4 illustrates that the deposition direction of Zn can differ from the deposition direction of Se. In the case of Figure 4, both Zn and Se are deposited obliquely, but from opposite directions.

[0100] Figure 5 shows the case where a wall 2 acts as a mask. As indicated by arrows, the deposition direction for Zn on the one hand and for Se on the other hand is such that Zn and Se can impinge on the wall 2 at an angle. The deposition directions of Zn and Se differ. The deposition direction of Zn is such that an area to the right of wall 2 is shielded. Zn cannot reach this area to the right of wall 2. The deposition direction of Se is such that an area to the left of wall 2 is shielded. Se cannot reach this area to the left of wall 2. Only areas that can be reached by both Zn and Se can be coated with layers 4. The surface 3 of the substrate 1 is therefore only partially coated. Layers 4 consisting of ZnSe then form on the substrate 1, which are at a distance from the wall 2.The distance is greater the smaller the angle formed by the deposition directions indicated by arrows with the surface of substrate 1. The distance also depends on the height of wall 2. The higher the wall 2, the greater the distance.

[0101] Figure 6 illustrates the deposition of Zn and Se as well as a small amount of ZnCl2 on substrate 1 to produce a partially doped layer 4, 4a. As indicated by arrows, the deposition direction of ZnCl2 forms an angle of less than 90° with the surface of substrate 1. The ZnCl2 material can also impinge on wall 2 at an angle. This shades or shields an area to the left of wall 2 for ZnCl2. An undoped area or section 4 of layer 4, 4a remains. Layer 4, 4a can thus be partially doped with Cl. An area 4 of layer 4, 4a that borders the left side of wall 2 remains undoped.

[0102] Figure 7 shows a top view of a coating device with heads 5 arranged in a ring. The heads 5 can be effusion cells. Viewed in top view, the heads 5 can be arranged around the substrate 1. The substrate 1 can be mounted so as to be rotatable relative to the heads 5. The heads 5 can be arranged in a plane below or above the substrate 1 in order to coat the substrate 1 from below or above.

[0103] Figure 8 shows that selenium (Se) emerges from head 5a toward the exposed surfaces 3 of substrate 1. Zinc (Zn) emerges from head 5b toward the exposed surfaces 3 of substrate 1. ZnCl2 emerges from head 5c toward the exposed surfaces 3 of substrate 1. Heads 5a and 5b are opposite each other and are arranged relative to wall 2 of the substrate such that the deposition directions of Se and Zn run parallel to wall 2. The exposed surfaces 3 are therefore completely coated with ZnSe. Head 5c is arranged such that ZnCl2 can impinge on wall 2 at an angle such that wall 2 shields an area to the left of wall 2 from impingement of ZnCl2. In this way, a layer formed from ZnSe that is partially doped with Cl can be produced in a single step. A region of the ZnSe layer adjacent to the left side of wall 2 is not doped.

[0104] The process thus enables in-situ doping, i.e., doping of a semiconductor layer or a region of a semiconductor layer during its growth. However, a layer or a region of a layer can also be doped subsequently.

[0105] By rotating substrate 1 relative to heads 5a, 5b, 5c, the alignment between wall 2 and heads 5a, 5b, 5c can be changed. Thus, with minimal technical effort, it is possible to adjust whether wall 2 acts as a shield or not.

[0106] Figure 9 shows a coating device for producing a PIN diode. It illustrates how heads of this device can be used for coating. Further details on the production of the PIN diode with this coating device can be found in the unpublished patent application with the official file number PCT / EP2023 / 083116. This unpublished application describes an advantageous production of a vertical arrangement in which, as shown in Figure 9, doping is generally carried out with only one material. Examples of possible doping materials are indicated in Figure 9. We hereby incorporate the disclosure content of this application as being part of the present invention. However, a horizontal arrangement is preferable.

[0107] Figure 10 shows a plan view of a substrate 1 with a first wall 2a applied above the substrate, a second wall 2b applied above the substrate, and two further walls 2c. One further wall 2c protrudes at an angle from the first wall 2a. The other further wall 2c protrudes at an angle from the second wall 2b. The first and second walls 2a, 2b can run parallel to one another, as shown in Figure 1. The first and second walls 2a, 2b can only partially lie directly opposite one another, as shown in Figure 1, and in this sense can be arranged so as to only partially overlap. There is a distance between the first and second walls 2a, 2b.

[0108] One further wall 2c can protrude at an angle from a front end of the first wall 2a. The other further wall 2c can protrude at an angle from a front end of the second wall 2b. This is advantageous for the production of a pin component, but not absolutely necessary. For example, it may also be sufficient for another wall to be at a distance from a front end of the first or second wall. The angle between two walls 2a and 2c or 2b and 2c can be 90°, as shown in Figure 10. This is advantageous for the production of a pin component, but not absolutely necessary.

[0109] A first and / or a second wall 2a, 2b can form an L-shape with another wall, as shown in Figure 10. The long legs of the L-shape can form the first and second walls, respectively. While this is advantageous for the production of a pin component, it is not absolutely necessary.

[0110] The first or second wall 2a or 2b can be connected to the other wall, as shown in Figure 10. While this is advantageous for the manufacture of a pin component, it is not absolutely necessary.

[0111] Figure 11 shows the substrate 1 with the walls 2a, 2b, 2c applied above the substrate 1. In addition, a layer 6 made of a compound semiconductor has been applied, which can be a buffer layer and / or electronically insulating layer. Starting from a front end, the layer 6 can initially run approximately parallel to another wall 2c. There can then be a distance to the immediately opposite other wall 2c, as shown in the top left and bottom right of Figure 11. The layer 6 can then bend and, after the bend, run, for example, parallel to the first wall 2a and parallel to the second wall 2b. Subsequently, the layer 6 can bend again, as shown in Figure 11, but then in the opposite direction.Following the renewed bend, layer 6 can again run parallel to another wall and be spaced from this directly opposite wall, as shown in Figure 11. Layer 6 can be mapped onto itself if layer 6 is rotated by 180°. In this sense, layer 6 can be rotationally symmetrical.

[0112] As a side effect of the deposition, one or more further layers 7 may be deposited, which are separated from layer 6, as shown in Figure 11. A further layer 7 may be adjacent to the first or second wall 2a, 2b, as shown in Figure 11. A further layer 7 may be spaced from the directly opposite further wall 2c, as shown in Figure 11.

[0113] This coating above the substrate 1 can be produced by depositing a first compound semiconductor material parallel to the first and second walls 2a, 2b, but at an angle to the other walls 2c, so that the other walls 2c shield an area behind the other walls 2c. At the same time, a second compound semiconductor material is deposited parallel to the first and second walls 2a, 2b and at an angle to the other walls 2c. The other walls 2c shield an area behind the other walls 2c. However, the second material is deposited on the substrate from an opposite direction (compared to the first material). Opposite directions refer to the directions visible in a top view of the deposit, as shown by way of example in Figure 11 for the materials gallium and arsenic. One of the materials can therefore be gallium.The other substance could therefore be arsenic. On the surface areas where the two substances come into contact, a layer consisting of the compound semiconductor forms.

[0114] The compound semiconductor can also be a ternary compound semiconductor. In this case, indium or aluminum, for example, can also be deposited in a non-shielding configuration. A layer of a ternary compound semiconductor is then formed at least on the area of ​​interest above substrate 1. Areas above the substrate that are not adequately shielded by a wall and which can therefore be exposed to the non-metallic substance, such as arsenic, of the compound semiconductor, can then be coated with a binary compound semiconductor. This, however, is fundamentally harmless to the properties of the component being manufactured.

[0115] Figure 12 shows a substrate 1 which corresponds to the substrate 1 in Figure 10. Heads of a coating device can be arranged around the substrate. Ga can emerge from a head 5a in the direction of the substrate 1 in such a way that gallium strikes the further walls 2c at an angle and also parallel to the first and second walls 2a and 2b. Arsenic can emerge from a head 5b arranged on the opposite side in the direction of the substrate 1 in such a way that arsenic strikes the further walls 2c at an angle and also parallel to the first and second walls 2a and 2b. In this way, a coating can be produced as shown in Figure 11.

[0116] If necessary, a second metal can emerge from an additional head, such that the second metal impinges perpendicularly or at least substantially perpendicularly on the substrate 1. Such an additional head can be arranged, for example, in a region to the bottom left of the substrate 1.

[0117] For example, a p-doped region, an n-doped region, and an intrinsically conductive region separating the p-doped region from the n-doped region can be deposited in one work step on the coated substrate 1 shown in Figure 11. Materials of a compound semiconductor can be deposited as in the case of Figure 11. Thus, a first material of a compound semiconductor can be deposited parallel to the first and second walls 2a, 2b, but obliquely impinging on the further walls 2c, so that the further walls 2c shield an area behind the further walls 2c. At the same time, a second material of the compound semiconductor can be deposited parallel to the first and second walls 2a, 2b and obliquely impinging on the further walls 2c. The further walls 2c shield an area behind the further walls 2c.The second substance is deposited on the substrate from an opposite direction (compared to the first substance). One substance can again be gallium. The other substance can again be arsenic. On the surface areas where the two substances come into contact, a layer of a compound semiconductor such as gallium arsenide forms. In contrast to the case in Figure 11, however, dopants are also deposited at the same time. One dopant can be an n-type dopant such as silicon (Si). The other dopant can be a p-type dopant such as carbon (C). Both dopants can be deposited obliquely to the first and second walls 2a, 2b and parallel to the other walls 2c, but from opposite directions, as indicated in Figure 13. This can result in the following coating.

[0118] The first and second walls shield a central region 8 from the dopants. The coating of the central region then consists of an undoped compound semiconductor.

[0119] A region 9, which adjoins the central region 8 on one side and borders the second wall 2b, is shielded from the p-type dopant by the second wall 2b. Therefore, an n-doped semiconductor is created here.

[0120] A region 10, which adjoins the central region 8 on the other side and borders the first wall 2a, is shielded from the n-type dopant by the first wall 2a. A p-doped semiconductor is therefore created here. An intrinsically conductive region 8 made of a compound semiconductor has thus been produced, separating a p-doped region 10 of the compound semiconductor from an n-doped region 9 of the compound semiconductor.

[0121] A wear layer can be produced in a single step. The wear layer can be produced on an intermediate layer as described.

[0122] As a side effect, further areas may have emerged, namely the following areas.

[0123] A region 11 that borders the n-doped region 9 and is separated from the second wall 2b by the n-doped region 9 and is spaced from an adjacent further wall 2c is not shielded by any wall. This region 11 is then formed from the compound semiconductor, which is then both p-doped and n-doped. This can apply equally to a further region 11 that borders the p-doped region 10 and does not directly border a wall 2a, 2b, 2c and is therefore not shielded by a wall. A region 13 that borders the first wall 2a and is formed from the compound semiconductor and is separated from the p-doped region 10 by the first wall 2a can be n-doped. This can then be followed by a region 12 formed from the compound semiconductor, which has a distance to each wall and is therefore both p-doped and n-doped.A region 14 formed from the compound semiconductor, adjacent to the second wall 2b and separated from the n-doped region 9 by the second wall 2b, can be p-doped. This region can then be followed by a region 12 formed from the compound semiconductor, which is spaced apart from each wall and is therefore both p-doped and n-doped. Coated regions that arise as a side effect can be prevented or removed by additional measures. However, it is technically more sensible to accept the regions created by side effects.

[0124] Figure 14 shows the component according to Figure 13 with a coating device with indicated deposition of the substances or materials.

[0125] Figure 15 illustrates a first electrical contact with a first metal, such as aluminum, to electrically contact the n-doped region 9. This is done by depositing the metal on the n-doped region, in that the metal is deposited from the same direction as the previous n-dopant. The metal then strikes the first wall 2a at an angle such that the intrinsically conductive region 8 and the p-doped region 10 are shielded by the first wall 2a. This creates a layered, electrically conductive contact 15. As a side effect, additional regions 16 can also be coated with the metal, as shown in Figure 15.

[0126] Figure 16 illustrates a second electrical contact with metal, such as titanium and platinum, to electrically contact the p-doped region. This is achieved by depositing metal on the p-doped region from the same direction as the previous p-dopant. This creates a layered electrical contact 17 made of metal on the p-doped region. Additional regions 18 can also be coated with metal as a secondary effect, as shown in Figure 16.

[0127] In particular, following electrical contacting, the region with intrinsic conductivity can be passivated, for example by depositing zinc and selenium to form a layer 19 of zinc selenide. This can take advantage of the fact that no zinc selenide is deposited on surfaces containing platinum and / or aluminum. Zinc and selenium can be deposited from opposite directions when viewed from above, namely parallel to the first wall 2a and the second wall 2b, as outlined in Figure 17. It is therefore possible to deposit a second metal layer, which may consist of platinum or aluminum, for example, on a first metal layer that directly contacts a doped region, in order to avoid deposition of a passivating layer on electrical contacts.

[0128] The second metal layer can therefore be selected so that a passivating layer material is not deposited on the second metal layer. This results in a component with a passivating layer that does not cover the electrical contacts.

Claims

Claims 1. Electronic component with a useful layer consisting of a compound semiconductor, which is spread out over a substrate (1) of the component, and, viewed in plan view onto the layer, an n-doped region (9) and a p-doped region (10).

2. Electronic component according to the preceding claim, characterized by an intrinsically conductive region (8) which separates the p-doped region (10) from the n-doped region (9).

3. Electronic component according to one of the preceding claims, with a first electrical contact (15) made of metal on the top side of the wear layer, which directly contacts the n-doped region (9), and a second electrical contact made of metal on the top side of the wear layer, which directly contacts the p-doped region (10).

4. Electronic component according to the preceding claim, characterized in that the first electrical contact (15) consists of a different metal than the second electrical contact (17).

5. Electronic component according to the preceding claim, characterized in that the useful layer is formed from a III-V compound semiconductor.

6. Electronic component according to the preceding claim, characterized in that the III-V compound semiconductor comprises gallium (Ga) and arsenide (As).

7. Electronic component according to one of the two preceding claims, characterized in that the III-V compound semiconductor comprises indium (In) or aluminum (Al).

8. Electronic component according to one of the preceding claims, characterized in that the electronic component is a light-sensitive component, in particular a photodetector.

9. Electronic component according to one of the preceding claims, characterized in that the p-doped region (10) of the useful layer is coated with a metal comprising platinum (Pt).

10. Electronic component according to the preceding claim, characterized in that the metal with which the p-doped region (10) of the useful layer is coated comprises titanium (Ti).

11. Electronic component according to one of the preceding claims, characterized in that the metal with which the p-doped region (10) of the useful layer is coated is not coated with zinc selenide.

12. Electronic component according to one of the preceding claims, characterized in that the intrinsically conductive region (8) of the wear layer is coated with zinc selenide.

13. Electronic component according to one of the preceding claims, characterized in that the n-doped region (9) of the useful layer is coated with aluminum and / or indium.

14. Electronic component according to one of the preceding claims, characterized in that a first wall (2a) or a first trench laterally adjoins the p-doped region (10) and the intrinsically conductive region (8), and a second wall (2b) or a second trench laterally adjoins the n-doped region (9) and the intrinsically conductive region, wherein the intrinsically conductive region (8) is located between the first and the second wall (2a, 2b) or the first and the second trench, and the two walls (2a, 2b) or the two trenches are directly opposite one another only in the intrinsically conductive region (8).

15. Electronic component according to the preceding claim, characterized in that at one end of the first wall (2a) in the n-doped region (9) a further wall (2c) protrudes at an angle and that at one end of the second wall (2b) in the p-doped region (10) a further wall (2c) protrudes at an angle or that at one end of the first trench in the n-doped region (9) a further trench protrudes at an angle and that at one end of the second trench in the p-doped region (10) a further trench protrudes at an angle.

16. Electronic component according to the preceding claim, characterized in that the first wall (2a) and the adjoining further wall (2c) are L-shaped and / or that the second wall (2b) and the adjoining further wall (2c) are L-shaped or that the first trench and the adjoining further trench are L-shaped and / or that the second trench and the adjoining further trench are L-shaped.

17. Electronic component according to one of the preceding claims, characterized in that the useful layer can be produced in one step by depositing semiconductor material and dopants.

18. Electronic component according to one of the preceding claims, characterized in that the wear layer, starting from a front end of the wear layer, initially bends in a first direction and thus opens into the n-doped region (9) and bends in an opposite second direction behind an intrinsically conductive region (8).

19. Electronic component according to one of the preceding claims, characterized in that the wear layer is rotationally symmetrical.

20. A method for producing an electronic component according to one of the preceding claims, characterized in that a layer system with two walls (2a, 2b) is provided on the layer system, wherein the two walls (2a, 2b) are arranged partially opposite one another and are spaced apart from one another, and semiconductor material is deposited on the layer system parallel to the two walls (2a, 2b) and at the same time a first dopant (Si) is deposited from one side obliquely to the first wall (2a) and at the same time a second dopant (C) is deposited from the other side obliquely to the second wall, in such a way that by the deposition in one work step an n-doped region (9), a p-doped region (10) and an intrinsically conductive region (8) are produced which separates the p-doped region (10) from the n-doped region (9).

21. Method according to the preceding claim, characterized in that a further wall (2c) protrudes at an angle from the walls (2a, 2b).

Images