Stacked device

Abstract

This stacked device 1 comprises: a first signal path connecting a pair of first terminals; a second signal path connecting a pair of second terminals; a first ground connection path connecting the first signal path and a first ground terminal; and a second ground connection path 2 connecting the second signal path and a second ground terminal. The first signal path and the second signal path have a common mode choke coil. The first ground connection path has a first counter electrode and a second counter electrode that face each other, and a first conductor line that electrically connects the second counter electrode and the first ground terminal. The second ground connection path has a third counter electrode and a fourth counter electrode that face each other, and a second conductor line that electrically connects the fourth counter electrode and the second ground terminal.

Description

stacked devices

[0001] The present disclosure relates to stacked devices.

[0002] 2. Description of the Related Art Conventionally, filters that remove common-mode noise contained in differential signals have been known. Patent Document 1 discloses an electronic component that removes common-mode noise.

[0003] Patent No. 5516160

[0004] The electronic component described in Patent Document 1 can block the passage of common mode signals of specific frequencies, but has the problem that the frequency band that can be blocked is narrow.

[0005] A laminated device according to one aspect of the present disclosure includes an insulator formed by stacking a plurality of insulating layers, one first terminal and the other first terminal provided on an outer surface of the insulator, one second terminal and the other second terminal provided on the outer surface of the insulator, a first ground terminal and a second ground terminal provided on the outer surface of the insulator, and a plurality of paths provided inside the insulator, the plurality of paths including a first signal path connecting the one first terminal and the other first terminal, a second signal path connecting the one second terminal and the other second terminal, a first ground connection path connecting the first signal path and the first ground terminal, and a second signal path connecting the second signal path and the front and a second ground connection path connecting the second ground terminal, wherein the first signal path has a first coil, the second signal path has a second coil that, together with the first coil, forms a common mode choke coil, the first ground connection path has a first opposing electrode connected to the first signal path, a second opposing electrode opposing the first opposing electrode, and a first conductor line that electrically connects the second opposing electrode and the first ground terminal, and the second ground connection path has a third opposing electrode connected to the second signal path, a fourth opposing electrode opposing the third opposing electrode, and a second conductor line that electrically connects the fourth opposing electrode and the second ground terminal.

[0006] According to a stacked device according to an aspect of the present disclosure, it is possible to widen a stop band that blocks the passage of common mode signals.

[0007] FIG. 1 is a diagram illustrating an equivalent circuit of the multilayer device according to the first embodiment. FIG. 2 is an external view of the multilayer device according to the first embodiment. FIG. 3 is a diagram illustrating internal conductors of the multilayer device according to the first embodiment. FIG. 4 is a cross-sectional view of the multilayer device according to the first embodiment. FIG. 5 is a diagram illustrating a first signal path and a second signal path of the multilayer device according to the first embodiment. FIG. 6 is a diagram illustrating a first ground connection path and a second ground connection path of the multilayer device according to the first embodiment. FIG. 7 is a diagram illustrating an equivalent circuit of a multilayer device according to a comparative example. FIG. 8 is a diagram illustrating a first signal path and a second signal path of the multilayer device according to the comparative example. FIG. 9 is a diagram illustrating the pass characteristics of a common mode signal of the multilayer device according to the comparative example. FIG. 10 is a diagram illustrating the pass characteristics of a common mode signal of the multilayer device according to the first embodiment. FIG. 11 is a diagram illustrating an equivalent circuit of a multilayer device according to a modification of the first embodiment. FIG. 12 is a diagram illustrating internal conductors of the multilayer device according to the modification of the first embodiment. FIG. 13 is a diagram illustrating the pass characteristics of a common mode signal of the multilayer device according to the modification of the first embodiment. FIG. 14 is a diagram illustrating internal conductors of the multilayer device according to the second embodiment. FIG. 15 is a diagram illustrating the first ground connection path and the second ground connection path of the multilayer device according to the second embodiment. Fig. 16 is a diagram showing the common mode signal passing characteristics of the multilayer device according to embodiment 2. Fig. 17 is a diagram showing internal conductors of the multilayer device according to embodiment 3. Fig. 18 is a diagram showing the common mode signal passing characteristics of the multilayer device according to embodiment 3.

[0008] Hereinafter, embodiments will be described with reference to the drawings. Each of the embodiments described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement positions, connection forms, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components.

[0009] Furthermore, in this specification, terms indicating the relationship between elements, such as parallelism, terms indicating the shape of elements, such as rectangular parallelepiped, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0010] In addition, each drawing is a schematic diagram in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present disclosure, and is not necessarily an exact illustration, and may differ from the actual shape, positional relationship, and proportion. In each drawing, substantially the same configuration is assigned the same reference numeral, and duplicated explanations may be omitted or simplified.

[0011] Furthermore, in this specification, the terms "top surface" and "bottom surface" in the configuration of a stacked device do not refer to the top surface (the surface on the vertically upper side) and bottom surface (the surface on the vertically lower side) in absolute spatial recognition, but are used as terms defined by the relative positional relationship of the components of the stacked device.

[0012] First Embodiment [Equivalent Circuit of Multilayer Device] An equivalent circuit of a multilayer device 1 according to a first embodiment will be described with reference to FIG.

[0013] FIG. 1 is a diagram showing an equivalent circuit of a stacked device 1 according to the first embodiment.

[0014] As shown in FIG. 1, the laminated device 1 includes a pair of first terminals, that is, one first terminal P1a and the other first terminal P1b, a pair of second terminals, that is, one second terminal P2a and the other second terminal P2b, and a first ground terminal G1 and a second ground terminal G2.

[0015] The stacked device 1 also includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, and a second signal path R2 connecting one second terminal P2a and the other second terminal P2b.

[0016] When the laminated device 1 is mounted on a substrate of an electronic device, the first ground terminal G1 and the second ground terminal G2 are set to ground potential. Differential signals are input to and output from the pair of first terminals P1a, P1b and the pair of second terminals P2a, P2b, and differential signals are transmitted through the first signal path R1 and the second signal path R2.

[0017] The first signal path R1 and the second signal path R2 are provided with a common mode choke coil 50. The common mode choke coil 50 is composed of a first coil 51 provided on the first signal path R1 and a second coil 52 provided on the second signal path R2. The first coil 51 is composed of two coils 51a and 51b connected in series, and the second coil 52 is composed of two coils 52a and 52b connected in series.

[0018] The first coil 51 and the second coil 52 are arranged so as to be electromagnetically coupled when a differential signal is transmitted to the first signal path R1 and the second signal path R2. In the multilayer device 1, the electromagnetic coupling between the first coil 51 and the second coil 52 makes it possible to remove common mode noise of a specific frequency contained in the differential signal.

[0019] Furthermore, the multilayer device 1 includes a first ground connection path Rg1 that connects the first signal path R1 and the first ground terminal G1, and a second ground connection path Rg2 that connects the second signal path R2 and the second ground terminal G2.

[0020] One end of the first ground connection path Rg1 is connected to a first node N1 located on the path between the first coil 51 and the other first terminal P1b in the first signal path R1. The other end of the first ground connection path Rg1 is connected to the first ground terminal G1. Note that the one end of the first ground connection path Rg1 may be connected to the path between the first coil 51 and one of the first terminals P1a instead of the first node N1.

[0021] One end of the second ground connection path Rg2 is connected to a second node N2 located on the path between the second coil 52 and the other second terminal P2b in the second signal path R2. The other end of the second ground connection path Rg2 is connected to the second ground terminal G2. Note that the one end of the second ground connection path Rg2 may be connected to the path between the second coil 52 and one of the second terminals P2a instead of the second node N2.

[0022] A first LC resonant circuit LC1 configured with a first capacitor C1 and a first inductor L1 connected in series is provided on the first ground connection path Rg1. A second LC resonant circuit LC2 configured with a second capacitor C2 and a second inductor L2 connected in series is provided on the second ground connection path Rg2. The resonant frequencies of the first LC resonant circuit LC1 and the second LC resonant circuit LC2 are set to predetermined frequencies different from the specific frequency removed by the common mode choke coil 50.

[0023] In the multilayer device 1 of this embodiment, when a differential signal is transmitted to the first signal path R1 and the second signal path R2, the first LC resonant circuit LC1 and the second LC resonant circuit LC2 each resonate at a predetermined frequency. By each of the first LC resonant circuit LC1 and the second LC resonant circuit LC2 resonating at a predetermined frequency, common mode noise of the predetermined frequency can be released to ground. This allows the multilayer device 1 to remove common mode noise of a predetermined frequency different from the specific frequency, in addition to the specific frequency removed by the common mode choke coil 50.

[0024] [Structure of the Multilayer Device] The structure of the multilayer device 1 according to the first embodiment will be described with reference to FIGS. 2 to 6. FIG.

[0025] Fig. 2 is an external view of the multilayer device 1. Fig. 3 is a diagram showing internal conductors of the multilayer device 1. Fig. 4 is a cross-sectional view of the multilayer device 1. In Fig. 3, the insulators 10 and external terminals of the multilayer device 1 are indicated by dashed lines, and the internal conductors of the insulators 10 are indicated by solid lines. Fig. 4(a) is a diagram showing a cross section taken along line IVa-IVa in Fig. 3, and Fig. 4(b) is a diagram showing a cross section taken along line IVb-IVb in Fig. 3.

[0026] The laminated device 1 is a surface-mount common mode noise filter and has dimensions of, for example, 2.0 mm in length, 1.25 mm in width, and 0.5 mm in height, or 1.25 mm in length, 1.0 mm in width, and 0.5 mm in height.

[0027] The stacked device 1 shown in Figures 2 to 4 includes an insulator 10 formed from an insulating material, one first terminal P1a and the other first terminal P1b provided on the outer surface of the insulator 10, one second terminal P2a and the other second terminal P2b provided on the outer surface of the insulator 10, a first ground terminal G1 and a second ground terminal G2 provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10.

[0028] The insulator 10 is formed, for example, by stacking multiple insulating layers 15 in a stacking direction (direction D3) with multiple interfaces 95 interposed therebetween (see FIG. 4 ). That is, each insulating layer 15 has two interfaces 95 among the multiple interfaces 95 that face each other in the stacking direction. The insulating layers 15 are formed of a magnetic material or a non-magnetic material such as glass. The insulator 10 may be formed by stacking multiple magnetic insulating layers 15 and multiple non-magnetic insulating layers 15. The non-magnetic insulating layers 15 may be dielectric layers. The thickness of the insulating layers 15 is appropriately selected, for example, from a range of 10 μm to 100 μm. Note that FIG. 4 omits the illustration of some of the multiple insulating layers 15. Also, although the insulating layers 15 are indicated by dashed lines in FIG. 4 , in reality, the multiple insulating layers 15 are bonded and integrated by firing or the like to form the insulator 10, and the interfaces 95 of the insulating layers 15 are invisible.

[0029] The insulator 10 has a rectangular parallelepiped shape and includes a bottom surface 18, a top surface 19 facing away from the bottom surface 18, and a plurality of side surfaces connecting the bottom surface 18 and the top surface 19. The side surfaces include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other. The bottom surface 18 and the top surface 19 are parallel to each other, the first side surface 11 and the second side surface 12 are parallel to each other, and the third side surface 13 and the fourth side surface 14 are parallel to each other. The first side surface 11 and the second side surface 12 are perpendicular to the third side surface 13 and the fourth side surface 14, respectively. The bottom surface 18 and the top surface 19 are perpendicular to the first side surface 11, the second side surface 12, the third side surface 13, and the fourth side surface 14, respectively. Corners (ridges) where the surfaces of the insulator 10 intersect may be rounded.

[0030] Here, the direction in which the first side surface 11 and the second side surface 12 face each other is called the first direction D1, the direction in which the third side surface 13 and the fourth side surface 14 face each other is called the second direction D2, and the direction in which the bottom surface 18 and the top surface 19 face each other is called the third direction D3. In this example, the stacking direction in which the multiple insulating layers 15 are stacked is the same as the third direction D3. The stacking direction is the same as the direction in which the coil axis of the common mode choke coil 50 extends. In the following, the negative side of the first direction D1 may be referred to as "one side," and the positive side opposite the negative side may be referred to as "the other side."

[0031] 2 and 3 , one first terminal P1a and one second terminal P2a are each provided on a part of a first side surface 11, which is the outer surface of the insulator 10. The other first terminal P1b and the other second terminal P2b are each provided on a part of a second side surface 12, which is the outer surface of the insulator 10. The first ground terminal G1 is provided on a part of a third side surface 13, which is the outer surface of the insulator 10. The second ground terminal G2 is provided on a part of a fourth side surface 14, which is the outer surface of the insulator 10. These external terminals may also be provided on parts of a bottom surface 18 and a top surface 19, respectively.

[0032] As shown in FIG. 3, the multiple paths inside the insulator 10 include a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2.

[0033] One end of the first signal path R1 is connected to one first terminal P1a, and the other end of the first signal path R1 is connected to the other first terminal P1b. The first signal path R1 has a first coil 51, which is composed of two spiral coils 51a and 51b.

[0034] One end of the second signal path R2 is connected to one second terminal P2a, and the other end of the second signal path R2 is connected to the other second terminal P2b. The second signal path R2 has a first coil 51 and a second coil 52 that constitutes a common mode choke coil 50. The second coil 52 is composed of two spiral coils 52a and 52b.

[0035] The common mode choke coil 50 located on the first signal path R1 and the second signal path R2 is composed of a plurality of common mode choke coils 50a, 50b. Of the plurality of common mode choke coils 50, the common mode choke coil 50a is formed by coils 51a and 52a, and the common mode choke coil 50b is formed by coils 51b and 52b. The plurality of common mode choke coils 50a, 50b are arranged side by side along the stacking direction (third direction D3) in which the plurality of insulating layers 15 are stacked.

[0036] Fig. 5 is a diagram showing the first signal path R1 and the second signal path R2 of the laminated device 1. Fig. 5 shows the first signal path R1 and the second signal path R2 shown in Fig. 3 turned upside down.

[0037] 3 and 5 have the same length. More specifically, the first signal path R1 and the second signal path R2 are formed of metal materials such as connection electrodes, wiring, land electrodes, via conductors, and coils, as shown below.

[0038] The first signal path R1 starts from a connection electrode a1 connected to one of the first terminals P1a, and is formed by connecting a land b1 to the connection electrode a1 by wiring, connecting a land c1 to the land b1 by a via conductor, connecting one end of a coil 51a to the land c1, connecting a land d1 to the other end of the coil 51a, connecting the land d1, the land e1, and the land f1 in this order by via conductors, connecting one end of a coil 51b to the land f1, connecting a land g1 to the other end of the coil 51b, connecting the land g1, the land h1, the land i1, and the land j1 in this order by via conductors, connecting a connection electrode k1 to the land j1 by wiring, and connecting the connection electrode k1 to the other first terminal P1b.

[0039] The second signal path R2 starts from a connection electrode a2 connected to one of the second terminals P2a, and is formed by connecting a land b2 to the connection electrode a2 by wiring, connecting one end of the coil 52a to the land b2, connecting a land c2 to the other end of the coil 52a, connecting the land c2, the land d2, and the land e2 in this order by via conductors, connecting one end of the coil 52b to the land e2, connecting a land f2 to the other end of the coil 52b, connecting the land f2, the land g2, the land h2, the land i2, and the land j2 in this order by via conductors, connecting the connection electrode k2 to the land j2 by wiring, and connecting the connection electrode k2 to the other second terminal P2b.

[0040] 3, the first ground connection path Rg1 and the second ground connection path Rg2 are provided outside the common mode choke coils 50a and 50b, rather than between the common mode choke coils 50a and 50b, in the stacking direction (third direction D3). In this example, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged closer to the bottom surface 18 than the common mode choke coil 50 (toward the negative side in the third direction D3).

[0041] Fig. 6 is a diagram showing the first ground connection path Rg1 and the second ground connection path Rg2 of the multilayer device 1. Fig. 6 shows the first ground connection path Rg1 and the second ground connection path Rg2 shown in Fig. 3 turned upside down.

[0042] As shown in FIGS. 3 and 6 , the first ground connection path Rg1 includes a first opposing electrode 21 , a second opposing electrode 22 , and a first conductor line 31 .

[0043] The first opposing electrode 21 and the second opposing electrode 22 are electrodes for forming capacitance in the first ground connection path Rg1.

[0044] The first opposing electrode 21 is connected to a first signal path R1 between the first coil 51 and the other first terminal P1b. Specifically, the first opposing electrode 21 is connected via a wire to a land i1 that corresponds to the first node N1 on the first signal path R1.

[0045] The second opposing electrode 22 is disposed to face the first opposing electrode 21 via the insulating layer 15. The second opposing electrode 22 is also disposed slightly away from the land j1 in the first direction D1 so as not to be connected to the land j1.

[0046] A first capacitor C1 is formed by the first opposing electrode 21 and the second opposing electrode 22 facing each other. The first opposing electrode 21 and the second opposing electrode 22 are L-shaped, and have rectangular holes formed therein to improve adhesion between the insulating layers 15 adjacent to each other in the stacking direction.

[0047] The first conductor line 31 is a line that forms an inductance in the first ground connection path Rg1. The first conductor line 31 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the second opposing electrode 22 and the first ground terminal G1. That is, the first conductor line 31 extends along a path from the second opposing electrode 22 to the first ground terminal G1. The first conductor line 31 has a predetermined length, cross-sectional area, and shape, and forms a first inductor L1. The length of the first conductor line 31 is the length along the path, and the cross-sectional area is the area of ​​a cross section perpendicular to the path.

[0048] The second ground connection path Rg2 includes a third opposing electrode 23 , a fourth opposing electrode 24 , and a second conductor line 32 .

[0049] The third opposing electrode 23 and the fourth opposing electrode 24 are electrodes for forming capacitance in the second ground connection path Rg2.

[0050] The third opposing electrode 23 is connected to a second signal path R2 between the second coil 52 and the other second terminal P2b. Specifically, the third opposing electrode 23 is connected via a wire to a land i2 that corresponds to the second node N2 on the second signal path R2.

[0051] The fourth opposing electrode 24 is disposed to face the third opposing electrode 23 via the insulating layer 15. The fourth opposing electrode 24 is also disposed slightly away from the land j2 in the first direction D1 so as not to be connected to the land j2.

[0052] The third opposing electrode 23 and the fourth opposing electrode 24 face each other to form a second capacitor C2. The third opposing electrode 23 and the fourth opposing electrode 24 are L-shaped, and have rectangular holes formed therein to improve adhesion between the insulating layers 15 adjacent to each other in the stacking direction.

[0053] The second conductor line 32 is a line that forms an inductance in the second ground connection path Rg2. The second conductor line 32 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the fourth opposing electrode 24 and the second ground terminal G2. That is, the second conductor line 32 extends along a path from the fourth opposing electrode 24 to the second ground terminal G2. The second conductor line 32 has a predetermined length, cross-sectional area, and shape, and forms a second inductor L2. The length of the second conductor line 32 is the length along that path, and the cross-sectional area is the area of ​​a cross section perpendicular to that path.

[0054] The first capacitor C1 and the second capacitor C2 have the same capacitance, and the first inductor L1 and the second inductor L2 have the same inductance.

[0055] In the stacked device 1, the first opposing electrode 21 and the third opposing electrode 23 are formed on a predetermined insulating layer 15a among the plurality of insulating layers 15. The second opposing electrode 22 and the fourth opposing electrode 24 are formed on another insulating layer 15b different from the predetermined insulating layer 15a. In this example, the insulating layer 15a on which the first opposing electrode 21 and the third opposing electrode 23 are formed is stacked on the insulating layer 15b on which the second opposing electrode 22 and the fourth opposing electrode 24 are formed. In detail, the insulating layers 15a and 15b among the plurality of insulating layers 15 are stacked on each other via an interface 95a, and the insulating layers 15b and 15c among the plurality of insulating layers 15 are stacked on each other via an interface 95b. The insulating layer 15a has an interface 95a. The insulating layer 15b has interfaces 95a and 95b facing each other. The insulating layers 15a and 15b share the interface 95a. The first opposing electrode 21 and the third opposing electrode 23 are formed on the interface 95a of the insulating layer 15a, and the second opposing electrode 22 and the fourth opposing electrode 24 are formed on the interface 95b of the insulating layer 15b.

[0056] The first conductor line 31 and the second conductor line 32 are formed on one or more identical insulating layers 15, including other identical insulating layers 15b. When the number of insulating layers 15 on which the first conductor line 31 and the second conductor line 32 are formed is two or more, the two or more insulating layers 15 may include an insulating layer 15a on which the first opposing electrode 21 and the third opposing electrode 23 are formed.

[0057] The first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf (see FIG. 4A), which is the central plane of the third side surface 13 and the fourth side surface 14 that face away from the second direction D2. That is, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf.

[0058] The first ground connection path Rg1 and the second ground connection path Rg2 have the same path length. For example, the line Rk1 of the first ground connection path Rg1 connecting the first node N1 on the first signal path R1 to the first opposing electrode 21 and the line Rk2 of the second ground connection path Rg2 connecting the second node N2 on the second signal path R2 to the third opposing electrode 23 have the same line length. Furthermore, the gap between the first opposing electrode 21 and the second opposing electrode 22 is the same as the gap between the third opposing electrode 23 and the fourth opposing electrode 24. Furthermore, the first conductor line 31 and the second conductor line 32 have the same line length.

[0059] More specifically, the first ground connection path Rg1 and the second ground connection path Rg2 are formed of metal materials such as counter electrodes, wiring, land electrodes, via conductors, and connection electrodes, which will be described below.

[0060] The first ground connection path Rg1 starts from a land i1 corresponding to the first node N1, and is formed by connecting a first opposing electrode 21 to the land i1 via a wiring, placing a second opposing electrode 22 opposite to the first opposing electrode 21 with an insulating layer 15 sandwiched therebetween, connecting a land l1 to the second opposing electrode 22 via a wiring, connecting a land m1 to the land l1 via a via conductor, connecting a land n1 to the land m1 via a wiring, connecting a land o1 to the land n1 via a via conductor, connecting a connection electrode p1 to the land o1 via a wiring, and connecting the connection electrode p1 to the first ground terminal G1. The first conductor line 31 is formed by wiring, land electrodes, via conductors, connection electrodes, etc. from the wiring connected to the second opposing electrode 22 to the connection electrode p1.

[0061] The second ground connection path Rg2 starts from a land i2 corresponding to the second node N2, and is formed by connecting the third opposing electrode 23 to the land i2 via a wiring, placing a fourth opposing electrode 24 opposite the third opposing electrode 23 with the insulating layer 15 interposed therebetween, connecting a land l2 to the fourth opposing electrode 24 via a wiring, connecting a land m2 to the land l2 via a via conductor, connecting a land n2 to the land m2 via a wiring, connecting a land o2 to the land n2 via a via conductor, connecting a connection electrode p2 to the land o2 via a wiring, and connecting the connection electrode p2 to the second ground terminal G2. The second conductor line 32 is formed by wiring, land electrodes, via conductors, connection electrodes, etc. from the wiring connected to the fourth opposing electrode 24 to the connection electrode p2.

[0062] As described above, the stacked device 1 of this embodiment has a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, a second signal path R2 connecting one second terminal P2a and the other second terminal P2b, a first ground connection path Rg1 connecting the first signal path R1 and the first ground terminal G1, and a second ground connection path Rg2 connecting the second signal path R2 and the second ground terminal G2.

[0063] The first signal path R1 has a first coil 51, and the second signal path R2 has a second coil 52 which constitutes a common mode choke coil 50 together with the first coil 51.

[0064] The first ground connection path Rg1 has a first opposing electrode 21 connected to the first signal path R1, a second opposing electrode 22 opposing the first opposing electrode 21, and a first conductor line 31 electrically connecting the second opposing electrode 22 and the first ground terminal G1.

[0065] The second ground connection path Rg2 has a third opposing electrode 23 connected to the second signal path R2, a fourth opposing electrode 24 opposing the third opposing electrode 23, and a second conductor line 32 electrically connecting the fourth opposing electrode 24 and the second ground terminal G2.

[0066] According to this configuration, an LC resonant circuit is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0067] [Effects, etc.] The effects of the multilayer device 1 having the above configuration will be described in comparison with the multilayer device 101 of the comparative example.

[0068] Fig. 7 is a diagram showing an equivalent circuit of the comparative example stacked device 101. Fig. 8 is a diagram showing the first signal path R1 and the second signal path R2 of the comparative example stacked device 101.

[0069] The stacked device 101 of the comparative example is the same as the stacked device 1 of embodiment 1 in that it includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, and a second signal path R2 connecting one second terminal P2a and the other second terminal P2b. On the other hand, the stacked device 101 of the comparative example differs from the stacked device 1 of embodiment 1 in that it does not include the first ground terminal G1 and the second ground terminal G2, and the first ground connection path Rg1 and the second ground connection path Rg2.

[0070] Fig. 9 is a diagram showing the common-mode signal passing characteristics of the laminated device 101 of the comparative example. Fig. 10 is a diagram showing the common-mode signal passing characteristics of the laminated device 1 according to the first embodiment. These diagrams show S-parameters (Scc21) that are characteristics when in-phase high-speed, high-frequency signals are input to one first terminal P1a and one second terminal P2a. The first ground terminal G1 and the second ground terminal G2 of the laminated device 1 according to the first embodiment are set to ground potential.

[0071] In this example, if the amount of attenuation is greater than 10 dB, it is determined that the common mode signal is sufficiently attenuated.

[0072] As shown in FIG. 9, the stacked device 101 of the comparative example can block the passage of common mode signals in a bandwidth of 7.7 GHz, which is in the frequency range of 1.34 GHz to 9.04 GHz.

[0073] 10 , in the multilayer device 1 of this embodiment, an attenuation pole is formed by the LC resonant circuit on the higher frequency side of the attenuation band formed by the common mode choke coil 50. Therefore, the multilayer device 1 can block the passage of common mode signals in a bandwidth of 12.9 GHz, which is the frequency range of 1.38 GHz to 14.26 GHz. In this way, the multilayer device 1 of this embodiment can widen the stop band that blocks the passage of common mode signals compared to the multilayer device 101 of the comparative example.

[0074] The frequency of the attenuation pole formed by the LC resonant circuit can be shifted to a higher or lower frequency by changing the resonant frequencies of the first LC resonant circuit LC1 and the second LC resonant circuit LC2, which makes it possible to change the stop band of the common mode signal according to the required specifications of the laminated device 1.

[0075] 11 to 13, a multilayer device 1A according to a modification of the first embodiment will be described. In this modification, an example will be described in which the multilayer device 1A is provided with a line for checking continuity between the ground terminal and the internal conductor.

[0076] FIG. 11 is a diagram showing an equivalent circuit of a stacked device 1A according to a modification of the first embodiment.

[0077] As shown in FIG. 11 , the modified stacked device 1A, like the stacked device 1 of embodiment 1, includes one first terminal P1a and the other first terminal P1b, one second terminal P2a and the other second terminal P2b, a first ground terminal G1 and a second ground terminal G2, a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2.

[0078] Furthermore, the multilayer device 1A of the modified example has a continuity check line 35 for checking the continuity between the first ground terminal G1 and the internal conductor or the continuity between the second ground terminal G2 and the internal conductor. The continuity check line 35 is provided to electrically connect the first ground terminal G1 and the second ground terminal G2.

[0079] Fig. 12 is a diagram showing the internal conductors of the multilayer device 1A. In Fig. 12, the insulators 10 and external terminals of the multilayer device 1A are indicated by dashed lines, and the internal conductors of the insulators 10 are indicated by solid lines.

[0080] Similar to the multilayer device 1 of the first embodiment, the multilayer device 1A of the modified example includes an insulator 10, one first terminal P1a and the other first terminal P1b, one second terminal P2a and the other second terminal P2b, a first ground terminal G1 and a second ground terminal G2, and a plurality of paths provided inside the insulator 10. The plurality of paths include a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2.

[0081] The multilayer device 1A of the modified example further includes a continuity check line 35 as one of the multiple paths. One end of the continuity check line 35 is connected to the land o1 of the first conductor line 31, and the other end of the continuity check line 35 is connected to the land o2 of the second conductor line 32. This configuration makes it possible to check the continuity between the first ground terminal G1 and the connection electrode p1 or the continuity between the second ground terminal G2 and the connection electrode p2.

[0082] For example, in the stacked device 1 of embodiment 1, the first capacitor C1 is provided in the first ground connection path Rg1, so it is difficult to confirm whether the first ground terminal G1 and the connection electrode p1 are electrically connected by checking the continuity between the external terminals.

[0083] In contrast, in the multilayer device 1A of the modified example, the first ground terminal G1 and the second ground terminal G2 are electrically connected, making it possible to check the continuity between the ground terminals and the connection electrodes. For example, the continuity check can be performed by contacting a measurement probe with each of the first ground terminal G1 and the second ground terminal G2. If the continuity check is successful, it can be determined that the first ground terminal G1 and the connection electrode p1 are electrically connected, and that the second ground terminal G2 and the connection electrode p2 are electrically connected. On the other hand, if the continuity check is unsuccessful, it can be inferred that the first ground terminal G1 and the connection electrode p1 are not electrically connected, and / or the second ground terminal G2 and the connection electrode p2 are not electrically connected.

[0084] Note that, in order to reduce the influence of the continuity check line 35 on the electromagnetic coupling of the common mode choke coil 50, it is desirable to place the continuity check line 35 in a position that does not overlap the common mode choke coil 50 when viewed from the stacking direction (third direction D3). In this example, the continuity check line 35 is provided outside the common mode choke coil 50 when viewed from the stacking direction (third direction D3).

[0085] FIG. 13 is a diagram showing the common mode signal passing characteristics of the multilayer device 1A.

[0086] 13, the multilayer device 1A of the modified example can block common mode signals in a bandwidth of 12.8 GHz, which is a frequency range of 1.40 GHz to 14.21 GHz. In this way, the multilayer device 1A of the modified example can widen the stop band that blocks common mode signals compared to the multilayer device 101 of the comparative example.

[0087] Second Embodiment A stacked device 1B according to a second embodiment will be described with reference to Figures 14 to 16. In the second embodiment, an example will be described in which two opposing electrodes and conductor lines are formed on the same insulating layer 15.

[0088] The equivalent circuit of the stacked device 1B is the same as that of the first embodiment, and therefore the description thereof will be omitted.

[0089] Fig. 14 is a diagram showing the internal conductors of the multilayer device 1B. In Fig. 14, the insulators 10 and external terminals of the multilayer device 1B are indicated by dashed lines, and the internal conductors of the insulators 10 are indicated by solid lines.

[0090] The stacked device 1B of embodiment 2 includes an insulator 10, one first terminal P1a and the other first terminal P1b, one second terminal P2a and the other second terminal P2b, a first ground terminal G1 and a second ground terminal G2, and a plurality of paths provided inside the insulator 10.

[0091] 14, the multiple paths include a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2. The configurations of the first signal path R1 and the second signal path R2 are the same as those in the first embodiment.

[0092] The multilayer device 1B of the second embodiment differs from the first embodiment in the configurations of the first ground connection path Rg1 and the second ground connection path Rg2.

[0093] FIG. 15 is a diagram showing the first ground connection path Rg1 and the second ground connection path Rg2 of the multilayer device 1B.

[0094] As shown in FIG. 15 , the first ground connection path Rg1 includes a first opposing electrode 21 , a second opposing electrode 22 , and a first conductor line 31 .

[0095] The first ground connection path Rg1 includes a rectangular plate-shaped first opposing electrode 21 and a frame-shaped second opposing electrode 22 arranged to surround the outside of the first opposing electrode 21. The first opposing electrode 21 and the second opposing electrode 22 are arranged at a predetermined interval in the first direction D1 and the second direction D2 to form a first capacitor C1. A meander-shaped first conductor line 31 is connected to the second opposing electrode 22. The meander-shaped first conductor line 31 forms a first inductor L1.

[0096] The second ground connection path Rg2 has a rectangular plate-shaped third opposing electrode 23 and a frame-shaped fourth opposing electrode 24 arranged to surround the outside of the third opposing electrode 23. The third opposing electrode 23 and the fourth opposing electrode 24 are arranged at a predetermined interval in the first direction D1 and the second direction D2 to form a second capacitor C2. A meander-shaped second conductor line 32 is connected to the fourth opposing electrode 24. The meander-shaped second conductor line 32 forms a second inductor L2.

[0097] The meander shape refers to a meandering shape. The first conductor line 31 and the second conductor line 32 shown in Figures 14 and 15 have a square wave meander shape. The meander shape is not limited to a square wave shape, and may be a triangular wave shape, a sinusoidal wave shape, or a circular arc wave shape. Furthermore, the meander shape may be a pulse wave shape that is convex or concave in the second direction D2.

[0098] The first opposing electrode 21, the second opposing electrode 22, the first conductor line 31, the third opposing electrode 23, the fourth opposing electrode 24, and the second conductor line 32 are formed on the same insulating layer 15. In detail, the first opposing electrode 21, the second opposing electrode 22, the first conductor line 31, the third opposing electrode 23, the fourth opposing electrode 24, and the second conductor line 32 are formed on the same interface of the same insulating layer 15.

[0099] FIG. 16 is a diagram showing the common mode signal passing characteristics of the multilayer device 1B.

[0100] 16, the multilayer device 1B can block common mode signals in a bandwidth of 16.96 GHz, which is the frequency range of 1.39 GHz to 18.35 GHz. In this way, the multilayer device 1B of the second embodiment can widen the stop band that blocks common mode signals compared to the multilayer device 101 of the comparative example.

[0101] Third Embodiment A stacked device 1C according to a third embodiment will be described with reference to Fig. 17 and Fig. 18. In the stacked device 1 according to the first embodiment, the plurality of insulating layers 15 are stacked vertically (vertically stacked), whereas in the stacked device 1C according to the third embodiment, an example will be described in which the plurality of insulating layers 15 are stacked horizontally (horizontally stacked).

[0102] The equivalent circuit of the stacked device 1C according to the third embodiment is the same as that of the modified example of the first embodiment, and therefore a description thereof will be omitted.

[0103] Fig. 17 is a diagram showing the internal conductors of the multilayer device 1C. In Fig. 17, the insulators 10 and external terminals of the multilayer device 1C are indicated by dashed lines, and the internal conductors of the insulators 10 are indicated by solid lines.

[0104] The stacked device 1C shown in Figure 17 includes an insulator 10 made of an insulating material, one first terminal P1a and the other first terminal P1b provided on the outer surface of the insulator 10, one second terminal P2a and the other second terminal P2b provided on the outer surface of the insulator 10, a first ground terminal G1 and a second ground terminal G2 provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10.

[0105] The insulator 10 is formed, for example, by stacking a plurality of insulating layers 15. The insulator 10 has a rectangular parallelepiped shape and has a bottom surface 18, a top surface 19 facing away from the bottom surface 18, and a plurality of side surfaces connecting the bottom surface 18 and the top surface 19. The plurality of side surfaces include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other.

[0106] Here, the direction in which the first side surface 11 and the second side surface 12 face each other is called the first direction D1, the direction in which the third side surface 13 and the fourth side surface 14 face each other is called the second direction D2, and the direction in which the bottom surface 18 and the top surface 19 face each other is called the third direction D3. In the third embodiment, the stacking direction in which the multiple insulating layers 15 are stacked is the same as the first direction D1. The stacking direction is the same as the direction in which the coil axis of the common mode choke coil 50 extends.

[0107] 17 , one first terminal P1a and one second terminal P2a are each provided on a part of a first side surface 11, which is the outer surface of the insulator 10. The other first terminal P1b and the other second terminal P2b are each provided on a part of a second side surface 12, which is the outer surface of the insulator 10. The first ground terminal G1 is provided on a part of a third side surface 13, which is the outer surface of the insulator 10. The second ground terminal G2 is provided on a part of a fourth side surface 14, which is the outer surface of the insulator 10. These external terminals are also provided on parts of a bottom surface 18 and a top surface 19, respectively.

[0108] The multiple paths inside the insulator 10 include a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2.

[0109] One end of the first signal path R1 is connected to one first terminal P1a, and the other end of the first signal path R1 is connected to the other first terminal P1b. The first signal path R1 has a first coil 51, which is composed of two spiral coils 51a and 51b.

[0110] One end of the second signal path R2 is connected to one second terminal P2a, and the other end of the second signal path R2 is connected to the other second terminal P2b. The second signal path R2 has a first coil 51 and a second coil 52 that constitutes a common mode choke coil 50. The second coil 52 is composed of two spiral coils 52a and 52b.

[0111] The common mode choke coil 50 located on the first signal path R1 and the second signal path R2 is composed of multiple common mode choke coils 50a, 50b. Of the multiple common mode choke coils 50, the common mode choke coil 50a is formed by coils 51a and 52a, and the common mode choke coil 50b is formed by coils 51b and 52b. The multiple common mode choke coils 50a, 50b are arranged side by side along the stacking direction (first direction D1) in which the multiple insulating layers 15 are stacked.

[0112] The first signal path R1 and the second signal path R2 have the same path length and are formed of metal materials such as connection electrodes, wiring, land electrodes, via conductors, and coils.

[0113] The first ground connection path Rg1 includes a first opposing electrode 21 , a second opposing electrode 22 , and a first conductor line 31 .

[0114] The first opposing electrode 21 and the second opposing electrode 22 are electrodes for forming capacitance in the first ground connection path Rg1. The first conductor line 31 is a line for forming inductance in the first ground connection path Rg1. The first opposing electrode 21 and the second opposing electrode 22 face each other to form a first capacitor C1, and the first conductor line 31, which has a predetermined length, cross-sectional area, and shape, forms a first inductor L1.

[0115] The first opposing electrode 21 is connected to a first signal path R1 between the first coil 51 and the other first terminal P1b. Specifically, the first opposing electrode 21 is connected to a first node N1 on the first signal path R1 via a wire.

[0116] The second opposing electrode 22 is disposed so as to face the first opposing electrode 21 via the insulating layer 15. The second opposing electrode 22 is also disposed slightly away from the first signal path R1 so as not to be connected to the first signal path R1.

[0117] The first conductor line 31 electrically connects the second opposing electrode 22 and the first ground terminal G1. The first conductor line 31 is formed by a plurality of wirings, land electrodes, via conductors, and the like.

[0118] The second ground connection path Rg2 includes a third opposing electrode 23 , a fourth opposing electrode 24 , and a second conductor line 32 .

[0119] The third opposing electrode 23 and the fourth opposing electrode 24 are electrodes for forming capacitance in the second ground connection path Rg2.

[0120] The third opposing electrode 23 is connected to a second signal path R2 between the second coil 52 and the other second terminal P2b. Specifically, the third opposing electrode 23 is connected to a second node N2 on the second signal path R2 via a wire.

[0121] The fourth opposing electrode 24 is disposed so as to face the third opposing electrode 23 via the insulating layer 15. The fourth opposing electrode 24 is also disposed slightly away from the second signal path R2 so as not to be connected to the second signal path R2.

[0122] The third opposing electrode 23 and the fourth opposing electrode 24 face each other to form a second capacitor C2.

[0123] The second conductor line 32 is a line for forming an inductance in the second ground connection path Rg2. The second conductor line 32 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the fourth opposing electrode 24 and the second ground terminal G2. The second conductor line 32 has a predetermined length, cross-sectional area, and shape and forms a second inductor L2.

[0124] In the laminated device 1C, the first opposing electrode 21 and the third opposing electrode 23 are formed on a predetermined same insulating layer 15 among the plurality of insulating layers 15. The second opposing electrode 22 and the fourth opposing electrode 24 are formed on another same insulating layer 15 that is different from the predetermined same insulating layer 15. The first conductor line 31 and the second conductor line 32 are formed on one or more same insulating layers 15, including other same insulating layers 15. When there are two or more insulating layers 15 on which the first conductor line 31 and the second conductor line 32 are formed, the two or more insulating layers 15 may include the insulating layer 15 on which the first opposing electrode 21 and the third opposing electrode 23 are formed.

[0125] The first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane (reference plane sf shown in FIG. 4 ) which is the central plane of the third side surface 13 and the fourth side surface 14 facing away from the second direction D2. That is, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to this reference plane.

[0126] The first ground connection path Rg1 and the second ground connection path Rg2 have the same path length. For example, the line connecting the first node N1 and the first opposing electrode 21 on the first signal path R1 and the line connecting the second node N2 and the third opposing electrode 23 on the second signal path R2 have the same line length. Furthermore, the gap between the first opposing electrode 21 and the second opposing electrode 22 is the same as the gap between the third opposing electrode 23 and the fourth opposing electrode 24. Furthermore, the first conductor line 31 and the second conductor line 32 have the same line length.

[0127] The multilayer device 1C further includes a continuity check line 35 as one of the multiple paths. One end of the continuity check line 35 is connected to the connection electrode p1 of the first conductor line 31, and the other end of the continuity check line 35 is connected to the connection electrode p2 of the second conductor line 32. This configuration makes it possible to check the continuity between the first ground terminal G1 and the connection electrode p1 or the continuity between the second ground terminal G2 and the connection electrode p2.

[0128] It is desirable that the continuity check line 35 be disposed in a position that does not overlap the common mode choke coil 50 when viewed from the stacking direction (first direction D1) in order to reduce the effect on the electromagnetic coupling of the common mode choke coil 50. In this example, the continuity check line 35 is provided outside the common mode choke coil 50 when viewed from the stacking direction (first direction D1).

[0129] FIG. 18 is a diagram showing the common mode signal passing characteristics of the multilayer device 1C.

[0130] 18, the multilayer device 1C can block common mode signals in a bandwidth of 14.24 GHz, which is in the frequency range of 1.42 GHz to 15.66 GHz. In this way, the multilayer device 1C of the second embodiment can widen the stop band that blocks common mode signals compared to the multilayer device 101 of the comparative example.

[0131] (Summary) Examples of laminated devices including laminated devices 1, 1A, 1B, and 1C of the present disclosure will be described.

[0132] The laminated device of Example 1 comprises an insulator 10 formed by stacking multiple insulating layers 15, one first terminal P1a and the other first terminal P1b provided on the outer surface of the insulator 10, one second terminal P2a and the other second terminal P2b provided on the outer surface of the insulator 10, a first ground terminal G1 and a second ground terminal G2 provided on the outer surface of the insulator 10, and multiple paths provided inside the insulator 10.

[0133] The multiple paths include a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, a second signal path R2 connecting one second terminal P2a and the other second terminal P2b, a first ground connection path Rg1 connecting the first signal path R1 and the first ground terminal G1, and a second ground connection path Rg2 connecting the second signal path R2 and the second ground terminal G2. The first signal path R1 includes a first coil 51, and the second signal path R2 includes a second coil 52 that configures a common mode choke coil 50 together with the first coil 51.

[0134] The first ground connection path Rg1 has a first opposing electrode 21 connected to the first signal path R1, a second opposing electrode 22 opposing the first opposing electrode 21, and a first conductor line 31 electrically connecting the second opposing electrode 22 and the first ground terminal G1.

[0135] The second ground connection path Rg2 has a third opposing electrode 23 connected to the second signal path R2, a fourth opposing electrode 24 opposing the third opposing electrode 23, and a second conductor line 32 electrically connecting the fourth opposing electrode 24 and the second ground terminal G2.

[0136] According to this configuration, an LC resonant circuit is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0137] The stacked device of Example 2 may be the stacked device described in Example 1, in which the first opposing electrode 21 and the second opposing electrode 22 are each an electrode for forming a capacitance in the first ground connection path Rg1, the first conductor line 31 is a line for forming an inductance in the first ground connection path Rg1, the third opposing electrode 23 and the fourth opposing electrode 24 are each an electrode for forming a capacitance in the second ground connection path Rg2, and the second conductor line 32 is a line for forming an inductance in the second ground connection path Rg2.

[0138] With this configuration, an LC resonant circuit having capacitance and inductance is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, common-mode noise of a predetermined frequency can be diverted to ground. This allows common-mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common-mode choke coil 50, thereby widening the stop band that prevents the passage of common-mode signals.

[0139] The laminated device of Example 3 is the laminated device described in Example 1 or 2, in which the common mode choke coil 50 is composed of a plurality of common mode choke coils 50a, 50b, the plurality of common mode choke coils 50a, 50b are arranged along the stacking direction in which the plurality of insulating layers 15 are stacked, and the first ground connection path Rg1 and the second ground connection path Rg2 may be provided outside the plurality of common mode choke coils 50a, 50b in the stacking direction, rather than between the plurality of common mode choke coils 50a, 50b.

[0140] With this configuration, the LC resonant circuit can be formed in a position that has minimal effect on the electromagnetic coupling of the common mode choke coil 50. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, common mode noise of a predetermined frequency can be diverted to ground. This makes it possible to further eliminate common mode noise of a predetermined frequency different from the specific frequency, in addition to the specific frequency removed by the common mode choke coil 50, and to widen the stop band that prevents the passage of common mode signals.

[0141] The stacked device of Example 4 is a stacked device described in any of Examples 1 to 3, in which the first opposing electrode 21 and the third opposing electrode 23 are provided on a predetermined same insulating layer 15a among the plurality of insulating layers 15, the second opposing electrode 22 and the fourth opposing electrode 24 are provided on another same insulating layer 15b different from the predetermined same insulating layer 15a among the plurality of insulating layers 15, and the first conductor line 31 and the second conductor line 32 may be provided on one or more same insulating layers 15 including another same insulating layer 15b among the plurality of insulating layers 15.

[0142] As a result, the counter electrodes of the first ground connection path Rg1 and the second ground connection path Rg2 are provided on the same insulating layer 15, and the conductor lines of the first ground connection path Rg1 and the second ground connection path Rg2 are provided on the same insulating layer 15. With this configuration, the number of insulating layers 15 required for the stacked device can be reduced compared to, for example, a case in which the counter electrodes of the first ground connection path and the second ground connection path are provided on different insulating layers and the conductor lines of the first ground connection path and the second ground connection path are provided on different insulating layers, thereby enabling the stacked device to be made smaller.

[0143] The stacked device of Example 5 is the stacked device according to any one of Examples 1 to 4, wherein the first ground connection path Rg1 and the second ground connection path Rg2 may have the same path length.

[0144] This allows the resonant frequencies of the LC resonant circuit of the first ground connection path Rg1 and the LC resonant circuit of the second ground connection path Rg2 to match, thereby forming an attenuation pole with a large amount of attenuation. Increasing the attenuation of the attenuation pole in this manner allows common-mode noise of a predetermined frequency to escape to ground. This allows common-mode noise of a predetermined frequency different from the specific frequency to be further removed in addition to the specific frequency removed by the common-mode choke coil 50, thereby widening the stop band that blocks the passage of common-mode signals.

[0145] The stacked device of Example 6 is the stacked device described in any one of Examples 1 to 5, wherein the line connecting the first signal path R1 and the first opposing electrode 21 in the first ground connection path and the line connecting the second signal path R2 and the third opposing electrode 23 in the second ground connection path have the same line length, the gap between the first opposing electrode 21 and the second opposing electrode 22 is the same as the gap between the third opposing electrode 23 and the fourth opposing electrode 24, and the first conductor line 31 and the second conductor line 32 may have the same line length.

[0146] This allows the capacitance of the first ground connection path Rg1 to be the same as the capacitance of the second ground connection path Rg2, and the inductance of the first ground connection path Rg1 to be the same as the inductance of the second ground connection path Rg2. This allows the resonant frequencies of the LC resonant circuits to be matched, forming an attenuation pole with a large amount of attenuation. Increasing the attenuation of the attenuation pole in this manner allows common mode noise of a predetermined frequency to escape to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further removed in addition to the specific frequency removed by the common mode choke coil 50, thereby widening the stop band that blocks common mode signals from passing through.

[0147] The stacked devices 1A and 1C of Example 7 are stacked devices described in any of Examples 1 to 6, and the multiple paths may further include a continuity check line 35 that electrically connects the first ground terminal G1 and the second ground terminal G2.

[0148] In this way, by providing the stacked devices 1A and 1C with the continuity check line 35, it is possible to easily check whether the first ground terminal G1 and the first ground connection path Rg1 are electrically connected, and whether the second ground terminal G2 and the second ground connection path Rg2 are electrically connected.

[0149] The stacked devices 1A and 1C of Example 8 are the stacked devices described in Example 7, and one end of the continuity check line 35 may be connected to the first conductor line 31, and the other end of the continuity check line 35 may be connected to the second conductor line 32.

[0150] This makes it easy to check whether the connection electrode that should be connected to the first ground terminal G1 is securely connected to the first ground terminal G1, and whether the connection electrode that should be connected to the second ground terminal G2 is securely connected to the second ground terminal G2.

[0151] The stacked devices 1, 1A, and 1B of Example 9 are the stacked devices according to any one of Examples 1 to 8, in which the insulator 10 is rectangular and has a bottom surface 18, a top surface 19, and four side surfaces. The four side surfaces include a first side surface 11 and a second side surface 12 that face each other, and a third side surface 13 and a fourth side surface 14 that face each other. The insulating layers 15 are stacked in a direction in which the bottom surface 18 faces each other and the top surface 19 faces each other. One first terminal P1a and one second terminal P2a may be formed on the first side surface 11, the other first terminal P1b and the other second terminal P2b may be formed on the second side surface 12, the first ground terminal G1 may be formed on the third side surface 13, and the second ground terminal G2 may be formed on the fourth side surface 14.

[0152] This makes it possible to provide the multilayer device 1, 1A, 1B in which a plurality of insulating layers 15 are stacked in a direction perpendicular to the substrate when the multilayer device 1, 1A, 1B is mounted on the substrate.

[0153] A stacked device 1C of Example 10 is the stacked device according to any one of Examples 1 to 8, in which the insulator 10 is rectangular parallelepiped and has a bottom surface 18, a top surface 19, and four side surfaces. The four side surfaces include a first side surface 11 and a second side surface 12 that face each other, and a third side surface 13 and a fourth side surface 14 that face each other. The insulating layers 15 are stacked in a direction in which the first side surface 11 and the second side surface 12 face each other. One first terminal P1a and one second terminal P2a may be formed on the first side surface 11, the other first terminal P1b and the other second terminal P2b may be formed on the second side surface 12, the first ground terminal G1 may be formed on the third side surface 13, and the second ground terminal G2 may be formed on the fourth side surface 14.

[0154] This makes it possible to provide a multilayer device 1C in which a plurality of insulating layers 15 are stacked in a direction perpendicular to the substrate when the multilayer device 1C is mounted on the substrate.

[0155] (Other Embodiments, etc.) While stacked devices and the like according to the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the embodiments and modifications, as well as other embodiments constructed by combining some of the components of the embodiments and modifications, are also included in the scope of the present disclosure.

[0156] The laminated device according to the present disclosure is useful as a common mode noise filter that suppresses the passage of common mode signals.

[0157] 1, 1A, 1B, 1C Multilayer device 10 Insulator 11 First side surface 12 Second side surface 13 Third side surface 14 Fourth side surface 15 Insulating layer 18 Bottom surface 19 Top surface 21 First opposing electrode 22 Second opposing electrode 23 Third opposing electrode 24 Fourth opposing electrode 31 First conductor line 32 Second conductor line 35 Continuity check line 50, 50a, 50b Common mode choke coil 51 First coil 51a, 51b Coil 52 Second coil 52a, 52b Coil P1a One first terminal P1b Other first terminal P2a One second terminal P2b Other second terminal G1 First ground terminal G2 Second ground terminal C1 First capacitor C2 Second capacitor Rg1 First ground connection path Rg2 Second ground connection path D1 First direction D2 Second direction D3 Third direction L1 First inductor L2 Second inductor LC1 First LC resonant circuit LC2 Second LC resonant circuit N1 First node N2 Second node R1 First signal path R2 Second signal path

Claims

1. An insulator formed by laminating a plurality of insulating layers; one first terminal and the other first terminal provided on the outer surface of the insulator; one second terminal and the other second terminal provided on the outer surface of the insulator; a first ground terminal and a second ground terminal provided on the outer surface of the insulator; and a plurality of paths provided inside the insulator, wherein the plurality of paths include a first signal path connecting the one first terminal and the other first terminal, a second signal path connecting the one second terminal and the other second terminal, a first ground connection path connecting the first signal path and the first ground terminal, and a second ground connection path connecting the second signal path and the second ground terminal, wherein the first signal path has a first coil, and the second signal path has a second coil that forms a common mode choke coil with the first coil, the first ground connection path includes a first opposing electrode connected to the first signal path, a second opposing electrode opposing the first opposing electrode, and a first conductor line electrically connecting the second opposing electrode and the first ground terminal; and the second ground connection path includes a third opposing electrode connected to the second signal path, a fourth opposing electrode opposing the third opposing electrode, and a second conductor line electrically connecting the fourth opposing electrode and the second ground terminal.

2. The stacked device according to claim 1, wherein each of the first opposing electrode and the second opposing electrode is an electrode for forming a capacitance in the first ground connection path, the first conductor line is a line for forming an inductance in the first ground connection path, each of the third opposing electrode and the fourth opposing electrode is an electrode for forming a capacitance in the second ground connection path, and the second conductor line is a line for forming an inductance in the second ground connection path.

3. The multilayer device according to claim 1, wherein the common mode choke coil is constituted by a plurality of common mode choke coils, the plurality of common mode choke coils are arranged along a stacking direction in which the plurality of insulating layers are stacked, and the first ground connection path and the second ground connection path are provided outside the plurality of common mode choke coils, rather than between the plurality of common mode choke coils, in the stacking direction.

4. The stacked device according to claim 1, wherein the first opposing electrode and the third opposing electrode are provided on a predetermined same insulating layer among the plurality of insulating layers, the second opposing electrode and the fourth opposing electrode are provided on another same insulating layer different from the predetermined same insulating layer among the plurality of insulating layers, and the first conductor line and the second conductor line are provided on one or more same insulating layers including the other same insulating layer among the plurality of insulating layers.

5. The stacked device according to any one of claims 1 to 4, wherein the first ground connection path and the second ground connection path have the same path length.

6. The stacked device according to any one of claims 1 to 4, wherein the line of the first ground connection path connecting the first signal path and the first opposing electrode, and the line of the second ground connection path connecting the second signal path and the third opposing electrode, have the same line length; the gap between the first opposing electrode and the second opposing electrode is the same as the gap between the third opposing electrode and the fourth opposing electrode; and the first conductor line and the second conductor line have the same line length.

7. The multilayer device according to any one of claims 1 to 4, wherein the plurality of paths further include a continuity check line that electrically connects the first ground terminal and the second ground terminal.

8. The stacked device according to claim 7, wherein one end of the continuity check line is connected to the first conductor line, and the other end of the continuity check line is connected to the second conductor line.

9. The stacked device according to any one of claims 1 to 4, wherein the insulator is a rectangular parallelepiped and has a bottom surface, a top surface, and four side surfaces, the four side surfaces including a first side surface and a second side surface facing back to back, and a third side surface and a fourth side surface facing back to back, the plurality of insulating layers are stacked in a direction in which the bottom surface and the top surface face back to back, the one first terminal and the one second terminal are formed on the first side surface, the other first terminal and the other second terminal are formed on the second side surface, the first ground terminal is formed on the third side surface, and the second ground terminal is formed on the fourth side surface.

10. The stacked device according to any one of claims 1 to 4, wherein the insulator is rectangular and has a bottom surface, a top surface, and four side surfaces, the four side surfaces including a first side surface and a second side surface facing back to back, and a third side surface and a fourth side surface facing back to back, the plurality of insulating layers are stacked in a direction in which the first side surface and the second side surface face back to back, the one first terminal and the one second terminal are formed on the first side surface, the other first terminal and the other second terminal are formed on the second side surface, the first ground terminal is formed on the third side surface, and the second ground terminal is formed on the fourth side surface.

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