Method performed by device, device and storage medium

Abstract

The present invention may comprise: encoding each of nL information blocks on the basis of a first matrix so as to determine nL local codewords; acquiring a first codeword of length n*nL on the basis of the nL local codewords; and encoding the first codeword on the basis of a second matrix so as to determine a second codeword having a length of nG, wherein nG = n*nL + mG, the second matrix corresponds to H Global = [ A P ], P is a matrix of mG-by-mG, A = [ A _1 A _2... A _nL], A _1 = A _2 =... = A _nL = A G, and A G is a matrix of mG-by-n.

Description

Methods performed by devices, devices and storage media

[0001] This specification relates to wireless communication systems.

[0002] Various devices and technologies, such as machine-to-machine (M2M) communication, machine-type communication (MTC), and smartphones and tablet PCs (personal computers) that require high data transmission rates, are emerging and becoming widespread. Consequently, the amount of data required to be processed on cellular networks is rapidly increasing. To meet this rapidly increasing data processing demand, technologies such as carrier aggregation and cognitive radio are being developed to efficiently utilize more frequency bands, while multi-antenna technology and multi-BS cooperation technology are being developed to increase the data capacity transmitted within a limited frequency range.

[0003] As more and more communication devices demand greater capacity, the need for enhanced mobile broadband (eMBB) communications is emerging, surpassing legacy radio access technology (RAT). Furthermore, massive machine type communication (mMTC), which connects multiple devices and objects to provide diverse services anytime, anywhere, is a key issue to be considered in next-generation communications.

[0004] Additionally, discussions are underway on communication systems designed to accommodate reliability- and latency-sensitive services and user equipment (UE). The introduction of next-generation wireless access technologies is being discussed, including enhanced mobile broadband (eMBB), mMTC, and ultra-reliable and low latency communication (URLLC).

[0005] Advances in communication technology are driving the need for increasingly larger transport blocks to be transmitted simultaneously. When errors occur during the transmission of large transport blocks, efficient methods and devices for recovering from transmission errors are required.

[0006] Additionally, to reduce the error rate of the transport block, it may be considered to use a globally coupled (GC) low density parity check (LDPC) code. In order to apply the GC LDPC code to communication, it is required to design a GC LDPC code suitable for the communication system.

[0007] Additionally, it is required to design a GC LDPC code that can reduce the error rate of a transport block or a group of code blocks.

[0008] The technical tasks that this specification aims to achieve are not limited to the technical tasks mentioned above, and other technical tasks that are not mentioned will be clearly understood by those skilled in the art related to this specification from the detailed description below.

[0009] In one aspect of the present disclosure, a method by a device is provided. In another aspect of the present disclosure, a device is provided, comprising: at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations. In another aspect of the present disclosure, a computer-readable, non-transitory storage medium is provided, storing at least one program code comprising instructions that, when executed, cause the at least one processor to perform operations. The method or the operations include: n L Determine the dog information blocks; the above n L Each of the dog information blocks is encoded based on the first matrix, and each of them has length n. L Obtain the local codewords of the dog; the n L length n*n based on local codewords L Obtain the first codeword; Encode the first codeword based on the second matrix to have length n G Obtain the second codeword, where n G = n*n L + m G ; determining coded bits to be transmitted based on the second codeword; and transmitting the coded bits. The second matrix has a size m. G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of , and A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G It is a matrix of -by-n.

[0010] In another aspect of the present disclosure, a method by a device is provided. In another aspect of the present disclosure, a device is provided, comprising: at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations. In another aspect of the present disclosure, a computer-readable non-transitory storage medium is provided, storing at least one program code that, when executed, includes instructions that cause the at least one processor to perform operations. The method or the operations include: receiving coded bits associated with a second codeword; and performing decoding on the coded bits based on a first matrix and a second matrix to generate n L Including determining dog information blocks, wherein the second codeword is obtained through encoding based on the second matrix for the first codeword, and the first codeword is n, each having a length n L Obtained based on the local codewords of the dog, and the above n L The local codewords are n L Each of the dog information blocks is obtained by encoding based on the first matrix, and the second matrix has a size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of , and A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G It is a matrix of -by-n.

[0011] In each aspect of this specification, P is of size m G -by-m Gcan be the identity matrix.

[0012] In each aspect of this specification, the method or the operations: replace each element of the second matrix with a Z-by-Z matrix H Global may further include obtaining, wherein said second matrix has a size M G -by-N G Matrix B Global = [BP B ], where m G = Z*M G , n G = Z*N G and, B= [B_1B_2 ...B_n L ] and B_1 =B_2 = ... =B_n L =B G And, B G is size size M G -by-N matrix, where n = Z*N, and P B is size M G -by-M G is a diagonal matrix.

[0013] In each aspect of this specification, P is P B It can be obtained by replacing each element in the diagonal of by a Z-by-Z identity matrix and replacing the remaining elements by a Z-by-Z zero matrix, where m G = Z*M G am.

[0014] In each aspect of this specification, B G Each of the N columns is floor(N / M) based on a predetermined column index sequence. G ) containing M columns G It can contain sets of ten, B G M of G Each of the dog rows is the M G Each column in a different set of columns among the sets of columns may contain integers representing a Z-by-Z matrix that is not a Z-by-Z zero matrix.

[0015] In each aspect of this specification, B G M of G Each of the dog rows is the M G Each of the remaining columns, excluding the corresponding column set among the sets of dog columns, may contain an integer representing a Z-by-Z zero matrix.

[0016] In each aspect of this specification, the predetermined column index sequence is B G It can be based on the number of decoding iterations required to determine the bit values ​​for each of the bits corresponding to the N columns above.

[0017] In each aspect of this specification, the predetermined column index sequence is ordered in ascending or descending order of the number of iterations, starting from the column index of the column with the fewest number of decoding iterations required to determine the corresponding bit value. G It may be identical to the sequence obtained by sorting the N column indices.

[0018] The above problem solving methods are only some of the examples of this specification, and various examples reflecting the technical features of this specification can be derived and understood by a person having ordinary knowledge in the relevant technical field based on the detailed description below.

[0019] According to some implementations of this specification, wireless communication signals can be transmitted and received efficiently. Consequently, the overall throughput of a wireless communication system can be increased.

[0020] Some implementations of this specification can reduce the probability of errors occurring during the transmission of transport blocks.

[0021] According to some implementations of this specification, even if an error occurs in a transport block or a portion of said transport block, the receiver can efficiently recover the portion in which the error occurred.

[0022] According to some implementations of this specification, the design complexity of GC LDPC codes for different transport block sizes or different numbers of code blocks can be reduced.

[0023] According to some implementations of this specification, a GC LDPC code with excellent error correction performance can be obtained.

[0024] The effects according to this specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art related to this specification from the detailed description below.

[0025] To aid in understanding implementations of this specification, the accompanying drawings, which are included as part of the detailed description, provide examples of implementations of this specification and, together with the detailed description, illustrate implementations of this specification:

[0026] Figure 1 illustrates an example of a communication system 1 to which implementations of the present specification are applied;

[0027] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification;

[0028] Figure 3 is the 3rd generation partnership project (3 rd It illustrates an example of a frame structure available in a wireless communication system based on the 3rd Generation Partnership Project (3GPP);

[0029] Figure 4 illustrates a processing process on the transmission side for a transport block (TB);

[0030] Figure 5 illustrates an example of a transport block encoding process according to several scenarios;

[0031] Figure 6 is a diagram illustrating the concept of the rate matching process;

[0032] Fig. 7 illustrates a parity check matrix H of an LDPC code and its corresponding Tanner graph;

[0033] Figures 6 and 7 are drawings illustrating a parity check matrix H of a low density parity check (LDPC) code using a bipartite graph;

[0034] Fig. 8 is an example of a systematic codeword structure generated by encoding;

[0035] Figures 9 and 10 are drawings illustrating the parity check matrix H of an LDPC code through a bipartite graph;

[0036] Figure 11 illustrates circulant permutation matrices (CPMs);

[0037] Fig. 12 illustrates a schematic structure of the basic graph of an LDPC code;

[0038] Figure 13 is a diagram illustrating the criteria for selecting an LDPC base graph;

[0039] Fig. 14 is an example of the structure of a globally coupled LDPC (GC LDPC) code;

[0040] Figures 15 and 16 illustrate the error correction performance of the GC LDPC code;

[0041] Fig. 17 illustrates the general structure of a parity check matrix of a GC LDPC code;

[0042] Fig. 18 is an example of a parity check matrix of a GC LDPC code;

[0043] Fig. 19 illustrates a Tanner graph corresponding to the GC LDPC code of Fig. 18;

[0044] FIG. 20 illustrates a schematic structure of a GC LDPC code according to some implementations of the present specification;

[0045] Figure 21 illustrates the structure of a codeword obtained by concatenating local codewords;

[0046] Fig. 22 illustrates the structure of a codeword obtained by adding global parity bits to the codeword of Fig. 21;

[0047] FIG. 23 illustrates the structure of a parity check matrix for a global code within the GC LDPC structure illustrated in FIG. 20;

[0048] FIG. 24 is an example of a parity check matrix of a GC LDPC code according to some implementations of the present specification;

[0049] Figures 25 and 26 illustrate the results of P-EXIT analysis for an example of a simple protograph LDPC code and the amount of mutual information for each variable node, respectively (respectively);

[0050] Figure 27 is an example of a base matrix for local codewords that may be used in some implementations of the present specification;

[0051] Figure 28 illustrates a 3-by-3 elementary matrix represented as an integer grid;

[0052] FIG. 29 is an example of a basic matrix of a global part according to some implementations of this specification;

[0053] Figure 30 illustrates the amount of mutual information (MI) per variable node obtained according to the P-EXIT chart analysis for the variable nodes of the basic matrix illustrated in Figure 27;

[0054] FIG. 31 is another example of a basic matrix of a global part according to some implementations of the present specification;

[0055] FIG. 32 is another example of a basic matrix of a global part according to some implementations of this specification;

[0056] Figure 33 is an example of a matrix obtained by expanding the basic matrix of the global family part;

[0057] Figures 34 to 36 illustrate parity check matrices obtained by extending the basic matrices of Figures 29, 31 and 32 for the global part, respectively;

[0058] Figure 37 illustrates the performance evaluation results of GC LDPC codes according to some implementations of the present specification;

[0059] FIG. 38 illustrates a channel encoding process according to some implementations of the present specification;

[0060] Figure 39 illustrates a channel decoding process according to some implementations of the present specification.

[0061] Hereinafter, implementations according to this specification will be described in detail with reference to the attached drawings. The detailed description provided below, together with the attached drawings, is intended to describe exemplary implementations of this specification and is not intended to represent the only possible implementations of this specification. The detailed description below includes specific details to provide a thorough understanding of this specification. However, one of ordinary skill in the art will appreciate that this specification may be practiced without these specific details.

[0062] In some cases, to avoid ambiguity in the concepts of this specification, known structures and devices may be omitted or illustrated in block diagram form focusing on the core functions of each structure and device. Furthermore, identical components are described using the same drawing reference numerals throughout this specification.

[0063] The techniques, devices, and systems described below can be applied to various wireless multiple access systems. Examples of multiple access systems include code division multiple access (CDMA) systems, frequency division multiple access (FDMA) systems, time division multiple access (TDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single carrier frequency division multiple access (SC-FDMA) systems, and multi-carrier frequency division multiple access (MC-FDMA) systems. CDMA can be implemented in wireless technologies such as Universal Terrestrial Radio Access (UTRA) or CDMA2000. TDMA can be implemented in wireless technologies such as Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), and Enhanced Data Rates for GSM Evolution (EDGE) (i.e., GERAN). OFDMA can be implemented in wireless technologies such as IEEE (Institute of Electrical and Electronics Engineers) 802.11 (WiFi), IEEE 802.16 (WiMAX), IEEE 802-20, and E-UTRA (evolved-UTRA). UTRA is part of UMTS (Universal Mobile Telecommunication System), and 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) is a part of E-UMTS that uses E-UTRA.3GPP LTE adopts OFDMA for the downlink (DL) and SC-FDMA for the uplink (UL). LTE-A (LTE-advanced) is an evolved form of 3GPP LTE.

[0064] For convenience of explanation, the following description assumes that this specification applies to 3GPP-based communication systems, such as LTE and NR. However, the technical features of this specification are not limited to this. For example, although the detailed description below is based on a mobile communication system corresponding to a 3GPP LTE / NR system, it can also be applied to any other mobile communication system, except for features specific to 3GPP LTE / NR.

[0065] For terms and technologies used in this specification that are not specifically explained, reference may be made to 3GPP-based standard documents, such as 3GPP TS 36.211, 3GPP TS 36.212, 3GPP TS 36.213, 3GPP TS 36.321, 3GPP TS 36.300 and 3GPP TS 36.331, 3GPP TS 37.213, 3GPP TS 38.211, 3GPP TS 38.212, 3GPP TS 38.213, 3GPP TS 38.214, 3GPP TS 38.300, 3GPP TS 38.331, etc.

[0066] In the examples of this specification described below, the expression "assumes" that a device "assumes" that the entity transmitting the channel transmits the channel in a manner consistent with the "assume." The entity receiving the channel may mean that, under the assumption that the channel was transmitted in a manner consistent with the "assume," the entity receiving the channel receives or decodes the channel in a manner consistent with the "assume."

[0067] In this specification, UE may be fixed or mobile, and includes various devices that communicate with a BS (base station) to transmit and / or receive user data and / or various control information. UE may be called (Terminal Equipment), MS (Mobile Station), MT (Mobile Terminal), UT (User Terminal), SS (Subscribe Station), wireless device, PDA (Personal Digital Assistant), wireless modem, handheld device, etc. In addition, in this specification, BS generally refers to a fixed station that communicates with UE and / or other BS, and exchanges various data and control information with UE and other BS. BS may be called by other terms such as ABS (Advanced Base Station), NB (Node-B), eNB (evolved-NodeB), BTS (Base Transceiver System), Access Point, PS (Processing Server), etc. In particular, the BS in UTRAN is called a Node-B, the BS in E-UTRAN is called an eNB, and the BS in a new radio access technology network is called a gNB. For convenience of explanation, BSs are collectively referred to as BSs below, regardless of the type or version of communication technology.

[0068] In this specification, a node refers to a fixed point that can transmit / receive radio signals by communicating with a UE. Various types of BSs can be used as nodes regardless of their names. For example, BSs, NBs, eNBs, pico-cell eNBs (PeNBs), home eNBs (HeNBs), relays, and repeaters can be nodes. Furthermore, a node may not be a BS. For example, it can be a radio remote head (RRH) or a radio remote unit (RRU). RRHs, RRUs, etc. generally have a lower power level than the BS. Since an RRH or RRU (hereinafter referred to as RRH / RRU) is generally connected to a BS via a dedicated line such as an optical cable, cooperative communication between an RRH / RRU and a BS can be performed more smoothly than cooperative communication between BSs that are generally connected via a wireless line. Each node is equipped with at least one antenna. The antenna may be a physical antenna, an antenna port, a virtual antenna, or an antenna group. A node is also called a point.

[0069] In this specification, a cell refers to a certain geographical area where one or more nodes provide communication services. Therefore, in this specification, communicating with a specific cell may mean communicating with a BS or node that provides communication services to the specific cell. In addition, the downlink / uplink signal of a specific cell refers to a downlink / uplink signal from / to a BS or node that provides communication services to the specific cell. A cell that provides uplink / downlink communication services to a UE is specifically referred to as a serving cell. In addition, the channel state / quality of a specific cell refers to the channel state / quality of a channel or communication link formed between a BS or node that provides communication services to the specific cell and the UE. In a 3GPP-based communication system, a UE can measure a downlink channel state from a specific node using CRS (Cell-specific Reference Signal) resources transmitted by antenna port(s) of the specific node on CRS resources allocated to the specific node and / or CSI-RS (Channel State Information Reference Signal) resources transmitted.

[0070] Meanwhile, 3GPP-based communication systems use the concept of cells to manage radio resources, and cells associated with radio resources are distinguished from cells in geographical areas.

[0071] A "cell" in a geographical area can be understood as the coverage over which a node can provide a service using a carrier, and a "cell" in a radio resource is associated with a bandwidth (BW), which is a frequency range configured by the carrier. Since downlink coverage, which is the range over which a node can transmit a valid signal, and uplink coverage, which is the range over which a node can receive a valid signal from a UE, depend on the carrier carrying the signal, the coverage of a node is also associated with the coverage of the "cell" of the radio resource used by the node. Therefore, the term "cell" can sometimes be used to mean the coverage of a service provided by a node, sometimes a radio resource, and sometimes the range over which a signal using the radio resource can reach with a valid intensity.

[0072] Meanwhile, the 3GPP communication standard uses the concept of a cell to manage radio resources. A "cell" associated with radio resources is defined as a combination of downlink resources (DL resources) and uplink resources (UL resources), i.e., a combination of a DL component carrier (CC) and an UL CC. A cell can be configured with DL resources alone or a combination of DL resources and UL resources. If carrier aggregation is supported, the linkage between the carrier frequency of the DL resources (or DL ​​CC) and the carrier frequency of the UL resources (or UL CC) can be indicated by system information. For example, the combination of DL resources and UL resources can be indicated by a System Information Block Type 2 (SIB2) linkage. Here, the carrier frequency can be the same as or different from the center frequency of each cell or CC. When carrier aggregation (CA) is established, the UE has only one radio resource control (RRC) connection with the network. One serving cell provides non-access stratum (NAS) mobility information during RRC connection establishment / re-establishment / handover, and one serving cell provides security input during RRC connection re-establishment / handover. Such a cell is called a primary cell (Pcell). A Pcell is a cell operating on the primary frequency where the UE performs initial connection establishment procedures or initiates connection re-establishment procedures.Depending on the UE capability, secondary cells (Scells) can be configured to form a set of serving cells together with Pcells. An Scell ​​can be configured after RRC (Radio Resource Control) connection establishment, and is a cell that provides additional radio resources in addition to the resources of a special cell (SpCell). The carrier corresponding to a Pcell in downlink is called a downlink primary CC (DL PCC), and the carrier corresponding to a Pcell in uplink is called an UL primary CC (DL PCC). The carrier corresponding to an Scell ​​in downlink is called a DL secondary CC (DL SCC), and the carrier corresponding to the Scell ​​in uplink is called an UL secondary CC (UL SCC).

[0073] For dual connectivity (DC) operation, the term SpCell refers to a Pcell of a master cell group (MCG) or a Pcell of a secondary cell group (SCG). A SpCell supports PUCCH transmission and contention-based random access and is always activated. An MCG is a group of serving cells associated with a master node (e.g., BS) and consists of a SpCell (Pcell) and optionally one or more Scells. For a UE configured for DC, an SCG is a subset of serving cells associated with a secondary node and consists of a PSCell and zero or more Scells. A PSCell is the primary Scell ​​of an SCG. For a UE in RRC_CONNECTED state that is not configured for CA or DC, there is only one serving cell consisting solely of Pcells. For a UE in RRC_CONNECTED state configured as CA or DC, the term serving cells refers to the set of cells consisting of SpCell(s) and all Scell(s). In DC, two medium access control (MAC) entities are configured in the UE: one for the MCG and one for the SCG.

[0074] For a UE where CA is set and DC is not set, a Pcell PUCCH group consisting of a Pcell and zero or more Scells and a Scell ​​PUCCH group consisting of only Scell(s) may be set. In the case of an Scell, an Scell ​​(hereinafter referred to as a PUCCH cell) on which a PUCCH associated with the cell is transmitted may be set. An Scell ​​indicated as a PUCCH Scell ​​belongs to an Scell ​​PUCCH group, and PUCCH transmission of the relevant UCI is performed on the PUCCH Scell, and an Scell ​​where a PUCCH Scell ​​is not indicated or is a Pcell indicated as a cell for PUCCH transmission, belongs to a Pcell PUCCH group, and PUCCH transmission of the relevant UCI is performed on the Pcell.

[0075] In a wireless communication system, a UE receives information from a base station (BS) via the downlink (DL), and the UE transmits information to the base station via the uplink (UL). The information transmitted and / or received by the BS and UE includes data and various control information, and various physical channels exist depending on the type and purpose of the information they transmit and / or receive.

[0076] 3GPP-based communication standards define downlink physical channels corresponding to resource elements that carry information originating from higher layers, and downlink physical signals corresponding to resource elements that are used by the physical layer but do not carry information originating from higher layers. For example, the physical downlink shared channel (PDSCH), physical broadcast channel (PBCH), and physical downlink control channel (PDCCH) are defined as downlink physical channels, and reference signals and synchronization signals are defined as downlink physical signals. A reference signal (RS), also referred to as a pilot, refers to a signal with a predefined special waveform that is known to the BS and UE. For example, the demodulation reference signal (DMRS) and the channel state information RS (CSI-RS) are defined as downlink reference signals. 3GPP-based communication standards define uplink physical channels corresponding to resource elements that carry information originating from higher layers, and uplink physical signals corresponding to resource elements that are used by the physical layer but do not carry information originating from higher layers.For example, a physical uplink shared channel (PUSCH), a physical uplink control channel (PUCCH), and a physical random access channel (PRACH) are defined as uplink physical channels, and a demodulation reference signal (DMRS) for uplink control / data signals and a sounding reference signal (SRS) used for uplink channel measurement are defined.

[0077] In this specification, the Physical Downlink Control CHannel (PDCCH) refers to a set of time-frequency resources (e.g., resource elements (REs)) that carry Downlink Control Information (DCI), and the Physical Downlink Shared CHannel (PDSCH) refers to a set of time-frequency resources that carry downlink data. In addition, the Physical Uplink Control CHannel (PUCCH), Physical Uplink Shared CHannel (PUSCH), and Physical Random Access CHannel (PRACH) refer to sets of time-frequency resources that carry Uplink Control Information (UCI), uplink data, and random access signals, respectively. Hereinafter, the expression that a user equipment transmits / receives a PUCCH / PUSCH / PRACH is used with the same meaning as transmitting / receiving uplink control information / uplink data / random access signal on or through the PUCCH / PUSCH / PUCCH / PRACH, respectively. In addition, the expression that a BS transmits / receives a PBCH / PDCCH / PDSCH is used with the same meaning as transmitting broadcast information / downlink control information / downlink data on or through the PBCH / PDCCH / PDSCH, respectively.

[0078] In this specification, radio resources (e.g., time-frequency resources) scheduled or configured by the BS to the UE for transmission or reception of PUCCH / PUSCH / PDSCH are also referred to as PUCCH / PUSCH / PDSCH resources.

[0079] Since the communication device receives SSB, DMRS, CSI-RS, PBCH, PDCCH, PDSCH, PUSCH, and / or PUCCH in the form of radio signals on a cell, it cannot selectively receive through an RF receiver only radio signals including only a specific physical channel or only a specific physical signal, or selectively receive through an RF receiver only radio signals excluding only a specific physical channel or only a physical signal. In actual operation, the communication device first receives radio signals on a cell through an RF receiver, converts the radio signals, which are RF band signals, into baseband signals, and decodes physical signals and / or physical channels within the baseband signals using one or more processors. Thus, in some implementations of the present specification, not receiving a physical signal and / or a physical channel may not actually mean that the communication device does not receive wireless signals containing the physical signal and / or physical channel at all, but rather that it does not attempt to recover the physical signal and / or physical channel from the wireless signals, e.g., does not attempt to decode the physical signal and / or the physical channel.

[0080] As more and more communication devices demand greater communication capacity, the need for improved mobile broadband communication over existing radio access technology (RAT) is emerging. Furthermore, massive MTC, which connects numerous devices and objects to provide diverse services anytime, anywhere, is also a key issue to be considered in next-generation communications. Furthermore, communication system design that considers reliability and latency-sensitive services / UEs is being discussed. The introduction of next-generation RATs that take advanced mobile broadband communication, massive MTC, and URLLC (Ultra-Reliable and Low Latency Communication) into account is currently under discussion. 3GPP is currently conducting studies on next-generation mobile communication systems beyond EPC. For convenience, this technology is referred to as new RAT (NR) or 5G RAT, and a system that uses or supports NR is referred to as an NR system.

[0081] FIG. 1 illustrates an example of a communication system 1 to which implementations of the present specification are applied. Referring to FIG. 1, the communication system (1) applied to the present specification includes a wireless device, a BS, and a network. Here, the wireless device refers to a device that performs communication using a wireless access technology (e.g., 5G NR (New RAT), LTE (e.g., E-UTRA)) and may be referred to as a communication / wireless / 5G device. Although not limited thereto, the wireless device may include a robot (100a), a vehicle (100b-1, 100b-2), an XR (eXtended Reality) device (100c), a hand-held device (100d), a home appliance (100e), an IoT (Internet of Things) device (100f), and an AI device / server (400). For example, the vehicle may include a vehicle equipped with a wireless communication function, an autonomous vehicle, a vehicle capable of performing vehicle-to-vehicle communication, etc. Here, the vehicle may include an Unmanned Aerial Vehicle (UAV) (e.g., a drone). XR devices include AR (Augmented Reality) / VR (Virtual Reality) / MR (Mixed Reality) devices, and may be implemented in the form of a Head-Mounted Device (HMD), a Head-Up Display (HUD) installed in a vehicle, a television, a smartphone, a computer, a wearable device, a home appliance, digital signage, a vehicle, a robot, etc. Mobile devices may include a smartphone, a smart pad, a wearable device (e.g., a smart watch, smart glasses), a computer (e.g., a laptop, etc.), etc. Home appliances may include a TV, a refrigerator, a washing machine, etc. IoT devices may include sensors, smart meters, etc. For example, a BS or network may also be implemented as a wireless device, and a specific wireless device may act as a BS / network node to other wireless devices.

[0082] Wireless devices (100a to 100f) can be connected to a network (300) via a BS (200). Artificial Intelligence (AI) technology can be applied to the wireless devices (100a to 100f), and the wireless devices (100a to 100f) can be connected to an AI server (400) via a network (300). The network (300) can be configured using a 3G network, a 4G (e.g., LTE) network, a 5G (e.g., NR) network, etc. The wireless devices (100a to 100f) can communicate with each other via the BS (200) / network (300), but can also communicate directly (e.g., sidelink communication) without going through the BS / network. For example, vehicles (100b-1, 100b-2) can communicate directly (e.g., V2V (Vehicle to Vehicle) / V2X (Vehicle to Everything) communication). In addition, IoT devices (e.g., sensors) can communicate directly with other IoT devices (e.g., sensors) or other wireless devices (100a to 100f).

[0083] Wireless communication / connection (150a, 150b) can be performed between wireless devices (100a~100f) / BS (200) - BS (200) / wireless devices (100a~100f). Here, the wireless communication / connection can be performed through various wireless access technologies (e.g., 5G NR) for uplink / downlink communication (150a) and sidelink communication (150b) (or D2D communication). Through the wireless communication / connection (150a, 150b), the wireless device and the BS / wireless device can transmit / receive wireless signals to / from each other. To this end, at least some of various configuration information setting processes for transmitting / receiving wireless signals, various signal processing processes (e.g., channel encoding / decoding, modulation / demodulation, resource mapping / demapping, etc.), and resource allocation processes can be performed based on various proposals of this specification.

[0084] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification. Referring to FIG. 2, a first wireless device (100) and a second wireless device (200) can transmit and / or receive wireless signals via various wireless access technologies (e.g., LTE, NR). Here, {the first wireless device (100), the second wireless device (200)} can correspond to {the wireless device (100x), the BS (200)} and / or {the wireless device (100x), the wireless device (100x)} of FIG. 1.

[0085] A first wireless device (100) includes one or more processors (102) and one or more memories (104), and may further include one or more transceivers (106) and / or one or more antennas (108). The processor (102) controls the memories (104) and / or the transceivers (106), and may be configured to implement functions, procedures, and / or methods described / suggested below. For example, the processor (102) may process information in the memory (104) to generate first information / signals, and then transmit a wireless signal including the first information / signals via the transceivers (106). In addition, the processor (102) may receive a wireless signal including second information / signals via the transceivers (106), and then store information obtained from signal processing of the second information / signals in the memory (104). The memory (104) may be connected to the processor (102) and may store various information related to the operation of the processor (102). For example, the memory (104) may perform some or all of the processes controlled by the processor (102), or may store software code including commands for performing the procedures and / or methods described / proposed below. Here, the processor (102) and the memory (104) may be part of a communication modem / circuit / chip designed to implement wireless communication technology (e.g., LTE, NR). The transceiver (106) may be connected to the processor (102) and may transmit and / or receive wireless signals via one or more antennas (108). The transceiver (106) may include a transmitter and / or a receiver. The transceiver (106) may be used interchangeably with an RF (Radio Frequency) unit. In this specification, a wireless device may also mean a communication modem / circuit / chip.

[0086] The second wireless device (200) includes one or more processors (202), one or more memories (204), and may further include one or more transceivers (206) and / or one or more antennas (208). The processor (202) controls the memories (204) and / or the transceivers (206), and may be configured to implement the functions, procedures, and / or methods described / suggested below. For example, the processor (202) may process information in the memory (204) to generate third information / signals, and then transmit a wireless signal including the third information / signals via the transceivers (206). In addition, the processor (202) may receive a wireless signal including fourth information / signals via the transceivers (206), and then store information obtained from signal processing of the fourth information / signals in the memory (204). The memory (204) may be connected to the processor (202) and may store various information related to the operation of the processor (202). For example, the memory (204) may perform some or all of the processes controlled by the processor (202), or may store software code including commands for performing the procedures and / or methods described / proposed below. Here, the processor (202) and the memory (204) may be part of a communication modem / circuit / chip designed to implement wireless communication technology (e.g., LTE, NR). The transceiver (206) may be connected to the processor (202) and may transmit and / or receive wireless signals via one or more antennas (208). The transceiver (206) may include a transmitter and / or a receiver. The transceiver (206) may be used interchangeably with an RF unit. In this specification, a wireless device may also mean a communication modem / circuit / chip.

[0087] The wireless communication technology implemented in the wireless device (100, 200) of the present specification may include not only LTE, NR, and 6G, but also Narrowband Internet of Things for low-power communication. At this time, for example, NB-IoT technology may be an example of LPWAN (Low Power Wide Area Network) technology, and may be implemented with standards such as LTE Cat NB1 and / or LTE Cat NB2, and is not limited to the above-described names. Additionally or alternatively, the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification may perform communication based on LTE-M technology. At this time, for example, LTE-M technology may be an example of LPWAN technology, and may be called by various names such as eMTC (enhanced Machine Type Communication). For example, LTE-M technology can be implemented by at least one of various standards such as 1) LTE CAT 0, 2) LTE Cat M1, 3) LTE Cat M2, 4) LTE non-BL (non-Bandwidth Limited), 5) LTE-MTC, 6) LTE Machine Type Communication, and / or 7) LTE M, and is not limited to the above-described names. Additionally or alternatively, the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification can include at least one of ZigBee, Bluetooth, and Low Power Wide Area Network (LPWAN) considering low-power communication, and is not limited to the above-described names. For example, ZigBee technology can create PAN (personal area networks) related to small / low-power digital communication based on various standards such as IEEE 802.15.4, and can be called by various names.

[0088] Hereinafter, hardware elements of the wireless device (100, 200) will be described in more detail. Although not limited thereto, one or more protocol layers may be implemented by one or more processors (102, 202). For example, one or more processors (102, 202) may implement one or more layers (e.g., functional layers such as a physical (PHY) layer, a medium access control (MAC) layer, a radio link control (RLC) layer, a packet data convergence protocol (PDCP) layer, a radio resource control (RRC) layer, and a service data adaptation protocol (SDAP) layer). One or more processors (102, 202) may generate one or more protocol data units (PDUs) and / or one or more service data units (SDUs) according to the functions, procedures, proposals, and / or methods disclosed in this specification. One or more processors (102, 202) may generate messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed in this specification. One or more processors (102, 202) may generate signals (e.g., baseband signals) including PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed in this specification, and provide the signals to one or more transceivers (106, 206). One or more processors (102, 202) may receive signals (e.g., baseband signals) from one or more transceivers (106, 206) and obtain PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed in this specification.

[0089] One or more processors (102, 202) may be referred to as a controller, a microcontroller, a microprocessor, or a microcomputer. One or more processors (102, 202) may be implemented by hardware, firmware, software, or a combination thereof. For example, one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), one or more Digital Signal Processing Devices (DSPDs), one or more Programmable Logic Devices (PLDs), or one or more Field Programmable Gate Arrays (FPGAs) may be included in one or more processors (102, 202). The functions, procedures, proposals, and / or methods disclosed in this specification may be implemented using firmware or software, and the firmware or software may be implemented to include modules, procedures, functions, etc. Firmware or software configured to perform the functions, procedures, suggestions and / or methods disclosed in this specification may be included in one or more processors (102, 202) or stored in one or more memories (104, 204) and executed by one or more processors (102, 202). The functions, procedures, suggestions and / or methods disclosed in this specification may be implemented using firmware or software in the form of codes, instructions and / or sets of instructions.

[0090] One or more memories (104, 204) may be coupled to one or more processors (102, 202) and may store various forms of data, signals, messages, information, programs, codes, instructions, and / or commands. The one or more memories (104, 204) may be configured as ROM, RAM, EPROM, flash memory, hard drives, registers, cache memory, computer-readable storage media, and / or combinations thereof. The one or more memories (104, 204) may be located internally and / or externally to the one or more processors (102, 202). Additionally, the one or more memories (104, 204) may be coupled to the one or more processors (102, 202) via various technologies, such as wired or wireless connections.

[0091] One or more transceivers (106, 206) may transmit user data, control information, wireless signals / channels, etc., as described in the methods and / or flowcharts of this specification, to one or more other devices. One or more transceivers (106, 206) may receive user data, control information, wireless signals / channels, etc., as described in the functions, procedures, proposals, methods and / or flowcharts of this specification, from one or more other devices. For example, one or more transceivers (106, 206) may be coupled to one or more processors (102, 202) and may transmit and / or receive wireless signals. For example, one or more processors (102, 202) may control one or more transceivers (106, 206) to transmit user data, control information, or wireless signals to one or more other devices. Additionally, one or more processors (102, 202) may control one or more transceivers (106, 206) to receive user data, control information, or wireless signals from one or more other devices. Additionally, one or more transceivers (106, 206) may be coupled to one or more antennas (108, 208), and one or more transceivers (106, 206) may be configured to transmit and / or receive user data, control information, wireless signals / channels, or the like, as referred to in the functions, procedures, proposals, methods, and / or operational flowcharts disclosed in this specification, via one or more antennas (108, 208). In this specification, one or more antennas may be multiple physical antennas or multiple logical antennas (e.g., antenna ports). One or more transceivers (106, 206) may convert received user data, control information, wireless signals / channels, etc. from RF band signals to baseband signals for processing using one or more processors (102, 202).One or more transceivers (106, 206) may convert user data, control information, wireless signals / channels, etc. processed by one or more processors (102, 202) from baseband signals to RF band signals. For this purpose, one or more transceivers (106, 206) may include an (analog) oscillator and / or filter.

[0092] In this specification, at least one memory (e.g., 104 or 204) can store instructions or programs that, when executed, cause at least one processor operably connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.

[0093] In this specification, a computer-readable (non-transitory) storage medium can store at least one instruction or computer program, which when executed by at least one processor causes the at least one processor to perform operations according to some embodiments or implementations of this specification.

[0094] In this specification, a processing device or apparatus may include at least one processor and at least one computer memory operatively connected to the at least one processor. The at least one computer memory may store instructions or programs, which, when executed, cause at least one processor operatively connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.

[0095] In this specification, a computer program may be stored in at least one computer-readable (non-transitory) storage medium and may include program code that, when executed, performs operations according to some implementations of the present specification or causes at least one processor to perform operations according to some implementations of the present specification. The computer program may be provided in the form of a computer program product. The computer program product may include at least one computer-readable (non-transitory) storage medium.

[0096] A communications device of the present specification comprises at least one processor; and at least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations according to the example(s) of the present specification described below.

[0097] Figure 3 illustrates an example of a frame structure available in a 3GPP-based wireless communication system.

[0098] The structure of the frame in Fig. 3 is only an example, and the number of subframes, the number of slots, and the number of symbols in the frame can be changed in various ways. In an NR system, OFDM numerology (e.g., subcarrier spacing (SCS)) may be set differently between multiple cells aggregated to a single UE. Accordingly, the (absolute time) duration of a time resource (e.g., a subframe, a slot, or a transmission time interval (TTI)) consisting of the same number of symbols may be set differently between the aggregated cells. Here, the symbol may include an OFDM symbol (or a cyclic prefix - orthogonal frequency division multiplexing (CP-OFDM) symbol), an SC-FDMA symbol (or a discrete Fourier transform-spread-OFDM (DFT-s-OFDM) symbol). In this specification, the terms symbol, OFDM-based symbol, OFDM symbol, CP-OFDM symbol, and DFT-s-OFDM symbols are interchangeable.

[0099] Referring to Figure 3, in the NR system, uplink and downlink transmissions are organized into frames. Each frame is T f = (△f max *N f / 100)*T c = 10 ms duration, divided into two half-frames of 5 ms each. Here, T is the basic time unit for NR. c = 1 / (△f max *N f ) and △f max = 480*10 3 Hz, and N f=4096. For reference, T is the basic time unit for LTE. s = 1 / (△f ref *N f,ref ) and △f ref = 15*10 3 Hz, and N f,ref =2048. T s Wow T c is a constant κ = T s / T c = 64 relationship. Each half-frame consists of 5 subframes, and the duration of a single subframe (SF) is T sf is 1ms. Subframes are further divided into slots, and the number of slots in a subframe depends on the subcarrier spacing. Each slot consists of 14 or 12 OFDM symbols based on the cyclic prefix. For a normal cyclic prefix (CP), each slot consists of 14 OFDM symbols, and for an extended CP, each slot consists of 12 OFDM symbols. The numerology is exponentially scalable with a subcarrier spacing △f = 2. u *Depends on 15 kHz. The following table shows the subcarrier spacing for regular CP △f = 2. u *Number of OFDM symbols per slot at 15 kHz (N) slot symb ), number of slots per frame (N frame,u slot ) and the number of slots per subframe (N subframe,u slot ) is shown.

[0100]

[0101] The following table shows the subcarrier spacing for extended CP △f = 2. u *Indicates the number of OFDM symbols per slot, the number of slots per frame, and the number of slots per subframe at 15 kHz.

[0102]

[0103] For a subcarrier spacing setting u, slots are n in increasing order within a subframe. u s ∈ {0, ..., nsubframe,u slot - 1} and n in increasing order within the frame u s,f ∈ {0, ..., n frame,u slot - Numbered as 1}.

[0104] A slot contains multiple (e.g., 14 or 12) symbols in the time domain. For each numeral (e.g., subcarrier spacing) and carrier, a common resource block (CRB) N is indicated by higher-layer signaling (e.g., radio resource control (RRC) signaling). start,u grid Starting from,N size,u grid,x *N RB sc Dog subcarriers and N subframe,u symb A resource grid of OFDM symbols is defined, where N size,u grid,x is the number of resource blocks (RBs) in the resource grid, and the subscript x is DL for downlink and UL for uplink. N RB sc is the number of subcarriers per RB, and in 3GPP-based wireless communication systems, N RB sc is typically 12. For a given antenna port p, subcarrier spacing configuration u, and transmission direction (DL or UL), there is one resource grid. The carrier bandwidth N for subcarrier spacing configuration u size,u gridis given to the UE by higher layer parameters (e.g., RRC parameters) from the network. Each element in the resource grid for antenna port p and subcarrier spacing configuration u is called a resource element (RE), and one complex symbol can be mapped to each RE. Each RE in the resource grid is uniquely identified by an index k in the frequency domain and an index l indicating the symbol position relative to a reference point in the time domain. In an NR system, an RB is defined by 12 consecutive subcarriers in the frequency domain. In an NR system, RBs can be classified into common resource blocks (CRBs) and physical resource blocks (PRBs). CRBs are numbered upwards from 0 in the frequency domain for the subcarrier spacing configuration u. The center of subcarrier 0 of CRB 0 for the subcarrier spacing configuration u coincides with 'Point A', which is a common reference point for the resource block grids. PRBs for subcarrier spacing u are defined within the bandwidth part (BWP) and range from 0 to N. size,u BWP,i -1, where i is the number of the bandwidth part. Common resource block n u CRB and bandwidth part i within physical resource block n PRB The relationship between the two is as follows: n u PRB = n u CRB +N start,u BWP,i , here N start,u BWP,i is a common resource block (BRB) whose bandwidth part starts relative to CRB 0. A BWP comprises multiple consecutive RBs in the frequency domain. For example, a BWP may be a given numeral u within a BWP i on a given carrier. iA subset of contiguous CRBs defined for a carrier. A carrier may include up to N (e.g., 5) BWPs. A UE may be configured to have one or more BWPs on a given component carrier. Data communication is performed through the activated BWPs, and only a predetermined number (e.g., 1) of BWPs configured for the UE may be activated on the carrier.

[0105] A UE configured with carrier aggregation may be configured to use one or more cells. If the UE is configured to have multiple serving cells, the UE may be configured to have one or more cell groups. The UE may be configured to have multiple cell groups associated with different BSs. Alternatively, the UE may be configured to have multiple cell groups associated with a single BS. Each cell group of the UE consists of one or more serving cells, and each cell group includes a single PUCCH cell configured with PUCCH resources. The PUCCH cell may be a Pcell or an Scell ​​configured as a PUCCH cell among the Scells of the corresponding cell group. Each serving cell of the UE belongs to one of the cell groups of the UE and does not belong to multiple cell groups.

[0106] NR frequency bands are defined by two types of frequency ranges, FR1 and FR2, with FR2 also referred to as millimeter wave (mmW). The following table lists the frequency ranges in which NR can operate.

[0107]

[0108] Figure 4 illustrates a processing process on the transmission side for a transport block (TB).

[0109] To enable the receiver to correct errors encountered in wireless signals over the wireless channel, the transmitter encodes the information it sends using a forward error correction code before transmitting it. The receiver demodulates the received signal and then decodes the error correction code to restore the transmitted information. This decoding process corrects errors in the received signal caused by the wireless channel.

[0110] Data arrives at the coding block in the form of up to two transport blocks per TTI per DL / UL cell. The following coding steps can be applied to each transport block in a DL / UL cell:

[0111] - Add cyclic redundancy check (CRC) code to the transport block;

[0112] - Code block segmentation and code block CRC attachment;

[0113] - Channel coding;

[0114] - Rate matching;

[0115] - Code block concatenation.

[0116] In actual communication systems, for ease of implementation, transport blocks larger than a certain size are divided into multiple smaller data blocks for encoding. These smaller data blocks are called code blocks.

[0117] Figure 5 illustrates an example of a transport block encoding process according to several scenarios. Referring to Figure 5, for example, a TB CRC may be attached to a TB. The TB CRC may be used to confirm the TB during the decoding process. If the TB CRC attached TB is not larger than a predetermined size, the TB CRC attached TB is encoded by a (channel) encoder. If the TB CRC attached TB is larger than the predetermined size, the TB CRC attached TB may be divided into multiple code blocks (CBs). If the TB CRC attached TB is divided into multiple CBs, in some scenarios, CB CRCs may be attached to each CB. This may result in multiple CB CRC attached CBs. The CB CRCs may be used to confirm the CBs during the decoding process by the receiver. Each of the above multiple CB CRC attached CBs can be encoded via a (channel) encoder. The CBs will generally have the same size, but due to the size limitation of the internal interleaver of the channel encoder, one of the multiple CBs may have a different size. The above multiple CB CRC attached CBs may be encoded in parallel via respective (channel) encoders, or may be encoded one by one via a single (channel) encoder. In some implementations, interleaving may be performed to reduce the impact of burst errors that occur when transmitting over a wireless channel after an error correction coding process is performed on a CB unit of a fixed interleaver size. Then, they are mapped to actual wireless resources and transmitted. Since the amount of wireless resources used in actual transmission is constant, rate matching must be performed on the encoded code blocks to match this. Rate matching is typically performed by puncturing or repetition.For example, if the amount of wireless resources, for example, the number of transmission bits that can be transmitted by the wireless resources, is M, and the number of coded bit sequences, i.e., the number of output bits of the encoder, is N, then if M and N are different, rate matching is performed to adjust the length of the coded bit sequence to match M. If M>N, all or part of the bits of the coded bit sequence are repeated so that the length of the rate-matched sequence becomes equal to M. M <N이면, 레이트 매칭된 시퀀스의 길이가 M과 같아지도록, 코딩된 비트 시퀀스의 비트들 중 일부가 펑처링되며, 펑처링된 비트는 전송에서 제외된다.

[0118] In a wireless communication system, a transmitter encodes data to be transmitted using channel coding having a specific code rate, and then adjusts the code rate of the data to be transmitted through a rate matching process consisting of puncturing and repetition.

[0119] The output bit sequence after rate matching and code block concatenation is modulated into modulation symbols through a modulator according to a modulation scheme. The modulation symbols are mapped to radio resources allocated by the base station and transmitted to the receiver through the radio resources. The decoding process of the channel code is the reverse process of the encoding process, and a decoder corresponding to each encoder of the transmitter is used in the decoding process performed at the receiver. The receiver performs decoding for each code block (CB), then forms a TB, and finally checks whether the TB CRC passes or fails. In the current 3GPP-based system, the CB CRC is used for fast decoding termination. For example, if the CB CRC fails, the receiver can generate a NACK without decoding other CBs.

[0120] Figure 6 is a diagram illustrating the concept of the rate matching process.

[0121] In some implementations, rate matching may be performed after channel coding. In 3GPP-based systems, rate matching for coded bits is defined per code block and may consist of sub-block interleaving, bit selection, and bit interleaving. For example, the input bit sequence to rate matching may be d0,d1,d2,d3,...,d N-1 After rate matching, the output bit sequence is f0,f1,f2,f3,...,f E-1 The bits input to the sub-block interleavers are coded bits d0,d1,d2,d3,...,d N-1 If we denote it, the coded bits d0,d1,d2,d3,...,d N-1 can be divided into multiple sub-blocks. Here, E can be a value determined based on the size of the radio resources scheduled for the corresponding transport block. It can be a predetermined or predefined length for the corresponding code block. The bits output from the sub-block interleavers are y0, y1, y2, y3,..., y N-1 If we denote it as , the bit sequence y0,y1,y2,y3,...,y after sub-block interleaving N-1 is written to a circular buffer of length N. If sub-block interleavers are not used, i.e., if sub-block interleaving is not applied, coded bits d0,d1,d2,d3,...,d N-1 This length is written to a circular buffer of size N.

[0122] Bits of the rate-matching output sequence length E are output as transmission bits from the circular buffer. For example, the redundancy version number for this transmission is rv id If sub-block interleaving is not applied, then the rate-matched output bit sequence f from the circular buffer for that code block k(where k=0,1,2,...,E-1) can be obtained as follows, where k0 is rv id The value of and the size of the circular buffer N cb , which may be a value determined based on the corresponding channel code.

[0123] > k = 0;

[0124] > j = 0;

[0125] > while k < E

[0126] >> if d(k0+j)mod Ncb≠ <null>

[0127] >>> f k = d(k0+j)mod Ncb;

[0128] >>> k = k+1;

[0129] >> end if

[0130] >> j = j+1

[0131] > end while.

[0132] In Fig. 4, the input bit sequences for the code block (CB) concatenation block are sequences f r0 , f r1 , f r2 , f r3 ,...,f r(Er-1) Here, r=0,...,C-1, C is the number of code blocks, and Er is the number of rate-matched bits for the r-th code block. Er may be a value determined based on the size of the radio resource. Through the code block concatenation, rate-matched outputs for different code blocks can be sequentially concatenated.

[0133] Hybrid automatic request (HARQ) is a technology that combines forward error correction (FEC) and automatic repeat request (ARQ). For example, a transmitter transmits all or part of the encoded coded bits using FEC, and a receiver detects whether there are errors in the received data and transmits a HARQ-ACK signal indicating an acknowledgment (ACK) or negative ACK (NACK) of the received data to the transmitter. If the receiver determines that the received data is error-free or below a certain threshold, the transmitter transmits new data. On the other hand, if the receiver determines that the received data contains errors or exceeds a certain threshold, the transmitter retransmits the corresponding data block. The receiver combines the retransmitted data block with previously transmitted data blocks and decodes it again to detect errors. This operation can be repeated until no errors are detected or until a predetermined number of errors are detected. The combining methods for decoding retransmitted data blocks can be divided into the following two types.

[0134] * Chase combining: For combining at the receiver, the transmitter retransmits coded bits identical to the initially transmitted coded bits. Chase combining can reduce the error probability through power gain during decoding of retransmitted data blocks.

[0135] * Incremental redundancy (IR): For combining at the receiver, the transmitter retransmits coded bits that are not identical to the coded bits that were initially transmitted. For example, the transmitter sends the redundancy that was not sent in the initial transmission to the receiver in the retransmission. Since the redundancy that was not sent in the previous transmission is sent in the retransmission, the redundancy of the previous transmission and the redundancy of the current transmission are combined to increase the redundancy, which has the effect of lowering the code rate. In other words, incremental redundancy can reduce the error probability through coding gain when decoding retransmitted data blocks. In general, since chase combining corresponds to the case where there is no incremental redundancy among incremental redundancies, chase combining can be interpreted as a special form of incremental redundancy.

[0136] In HARQ operation, the receiver generates an ACK or NACK for received or scheduled packets and provides them to the transmitter. A transmitter that receives a NACK for a transmission can retransmit the requested packet. The bits read from the circular buffer and sent in each retransmission may differ depending on the transmission start position determined by the redundancy version (RV). Referring to Figure 6, there are multiple (e.g., four) RVs that define the positions of the starting points from which bits are read from the circular buffer.

[0137] The circular buffer is a crucial component for rate matching and enables puncturing and / or repetition of coded bits. Referring to Figure 6, the coded bits or the output bits after sub-block interleaving of the coded bits are sequentially written to the circular buffer for the mother code. The number of coded bits is read sequentially from the starting point specified by the RV point within the circular buffer.

[0138] There are various types of error-correcting codes. Among them, the low-density parity check (LDPC) code is a linear block code with low density because most of the elements of the parity check matrix H are 0. It was proposed by Gallager in 1962. LDPC codes were so complex that they were impossible to implement with the technology available at the time of their proposal, and were thus forgotten. However, they were rediscovered in 1995, and their excellent performance has been proven, and research on them has been actively conducted since then (References: [1] Robert G. Gallager, "Low-Density Parity-Check Codes", The MIT Press, September 15, 1963. [2] DJCMackay, Good error-correcting codes based on very sparse matrices, IEEE Trans. Inform. Theory, IT-45, pp.399-431(1999)). Currently, LDPC codes are mainly used in 802.11n (see 'IEEE P802.11n=D10: 'Draft IEEE Standard for Local Metropolitan networks Specific requirements. Part 11: Wireless LAN Medium Access Control (MAC), and Physical Layer (PHY) specifications: Enhancements for Higher Throughput', March 2006.'), 802.11ac, and digital video broadcasting (DVB). Typically, in standards that apply LDPC (e.g., the DVB standard), encoding is performed using a parity-check matrix instead of a generator matrix.Since the parity check matrix of the LDPC code has a very small number of 1s, it can be decoded through iterative decoding even in very large block sizes. As the block size becomes very large, it shows performance approaching Shannon's channel capacity limit like a turbo code. In the parity check matrix, the number of 1s included in a row or column is called a weight. The LDPC code can be described by an (nk)*n parity check matrix H. The generator matrix G corresponding to the parity check matrix H can be obtained by the following mathematical formula.

[0139]

[0140]

[0141] Here, c is a codeword, and x are information bits. The receiver decoder must obtain information bits x from the codeword c, which is the encoding result by the transmitter, and finds x by using the property that Hc = 0. That is, when the received codeword is c', the value of Hc' is calculated, and if the result is 0, the k bits in front of c' are determined to be decoded information bits. If the value of Hc' is not 0, a sum-product algorithm through a graph, a belief propagation algorithm, etc. are used to find c' that satisfies the value of Hc' is 0, and x is recovered. The check expression Hc' = 0 is c'H according to the relationship between the corresponding information bit and the corresponding generator matrix G. T =0, and thus the above check formula can change depending on the relationship between the information bit and the generator matrix G.

[0142] Figure 7 illustrates the parity check matrix H of an LDPC code and its corresponding Tanner graph.

[0143] A parity check matrix is ​​a binary matrix that defines the parity check equations of an LDPC code. A parity check matrix defining an LDPC code can be represented by a Tanner graph. The column vector of a parity check matrix is ​​associated with a variable node, and the row vector of a parity check matrix is ​​associated with a check node. The presence of '1' in the i-th row and j-th column of a parity check matrix means that the i-th check node is connected to the j-th variable node. For example, suppose there is the following parity check matrix (PCM) H.

[0144]

[0145] Referring to the PCMH or FIG. 7(a), the first row of the PCMH, i.e., the first check node (CN), is connected to the first, second, third, and fourth variable nodes (VNs), the second CN is connected to the third, fourth, and sixth VNs, and the third CN is connected to the first, fourth, and fifth VNs. This can be expressed as a Tanner graph as in FIG. 7(b). The Tanner graph is composed of i) VNs representing coded bits, ii) CNs representing parity check equations that the coded bits must satisfy, and iii) edges connecting the VNs and CNs. In Tanner graphs, check nodes are conventionally expressed as rectangles, and variable nodes are expressed as circles. Properties of the PCMH, such as row and column weights, are converted into node degrees in the Tanner graph. Sparsely distributed non-zero entries in PCMH represent edges in the Tanner graph. The sparsity of these non-zero entries allows for efficient decoding of these codes using an iterative decoding algorithm known as the belief propagation (BP) algorithm.

[0146] Figure 8 is an example of a systematic codeword structure generated by encoding.

[0147] The PCM of an LDPC code specifies the set of all valid codewords. For LDPC codes, valid codewords are always xH T = 0 satisfies the parity check constraints defined by the . The process of mapping message bits to valid codewords is called encoding. A codeword is i) message bits u = [u1, u2, u3, ..., u K ] and ii) parity bits p=[p1, p2, p3, ..., p] mapped together by the constraints imposed by the PCM. N-K ] is composed of.

[0148] Since LDPC codes are linear block codes, the message u = [u1, u2, u3,..., u K ] as codeword x = [x0, x1x2, ..., x n-1 ] can be expressed as the product of u and G as: x = uG, where G is a K-by-N generator matrix.

[0149] For systematic LDPC codewords, matrix G is a K-by-K identity matrix I K And it consists of (NK)-by-K binary matrix A, G = [I K A] is a generator matrix of the form, and the first K codeword bits are message bits u1, u2, u3, ..., u K , which means that the i-th message bit is mapped to the i-th codeword bit, and the remaining NK codeword bits are parity bits p1, p2, p3, ..., p (which are linear sums of the message bits). N-K It consists of . The generated codeword x may have the form shown in Fig. 8.

[0150] Figures 9 and 10 illustrate the parity check matrix H of an LDPC code using a bipartite graph.

[0151] In the parity check matrix illustrated in Fig. 9(a), a '1' in a row represents an edge connected to a check node in the bipartite graph, and a '1' in a column represents an edge connected to a variable node. Fig. 9(b) illustrates a portion of a bipartite graph corresponding to the parity check matrix illustrated in Fig. 9(a). Referring to Fig. 9(b), the nodes on the left side of the reciprocal graph represent variable nodes, and the nodes on the right side represent check nodes.

[0152] Figure 10 illustrates another parity check matrix and the entire bipartite lines.

[0153] Referring to Fig. 10, since the product of the parity check matrix H and the codeword c' must be 0, the sum of the hard decision values ​​of the variable nodes connected to any one check node must be '0'. Mathematical formulas for the hard decision for each check node are exemplified in Fig. 10(b). Checking whether the sum of the variable node(s) connected to the check node is '0' in this way is called a syndrome check.

[0154] The LDPC code reflected in the NR standard can be classified as a quasi-cyclic LDPC (QC-LDPC) code. The QC-LDPC code has a low encoding / decoding complexity and a structure that is advantageous for parallelization. The parity check matrix of the QC-LDPC code is Z c -by-Z c It can be represented as an m-by-n array of circulant permutation matrices (CPMs). For example, a parity check matrix can be represented as Z for each element in the model matrix or base graph (BG) (also called the base matrix or base code). c -by-Z c CPM or Z c -by-Z c It can be obtained by replacing the zero matrix with a model matrix of size m-by-n or an LDPC BG of size m-by-n (mZ c )-by-(nZ c ) The process of obtaining a parity check matrix is ​​called lifting or expanding.

[0155] Figure 11 illustrates circulant permutation matrices (CPMs). In particular, Figure 11 illustrates a 4×4 CPM. Referring to Figure 11, CPMP a In , a is a circulant shift value, a non-negative integer, and has size Z. c× Z c It is obtained by cyclically shifting the identity matrix I to the right or left a number of times. In Fig. 11, the zero matrix is ​​P Δ It is expressed as , but it may be expressed differently depending on the definition in the system or standard. For example, depending on the system or standard, the cyclic transition value a = -1 may be used to represent the zero matrix.

[0156] In the model matrix for LDPC, each element represents a cyclic shift value or a zero matrix of CPM. Each element of the LDPC BG is either 0 or 1, and each element of value 0 in the LDPC BG has size Z. c× Z c is replaced by the zero matrix 0, and each element of value 1 in the LDPC BG is CPMI(P i,j ), where i and j are the row and column indices of the element, and I(P i,j ) is the size Z c -by-Z c The identity matrix I of P is moved to the right or left i,j It is obtained by cyclically transferring as many times as P. i,j The value of P i,j = mod(V i,j , Z c ) can be given by V i,j The value of may correspond to the cyclic shift value of the model matrix and may be predefined depending on the system in which LDPC is used. For example, in 3GPP TS 38.212 Release 15, V i,j The value of set index i LS and LDPC BG are given by Table 5.3.2-2 and Table 5.3.2-3 of 3GPP TS 38.212 Release 15 (see Section 5.3.2 of 3GPSS TS 38.212 Release 15).

[0157] For BG introduced in the NR standard, the first two columns of the base graph, corresponding to variable nodes with high degrees, are punctured. That is, the base graph and the lifting size Z c The first 2Z of the extended parity check matrix based on c The dog columns are punctured. Therefore, the first 2Z of the coded bits obtained after encoding using the parity check matrix c The bits are punctured. In addition, the BG introduced in the NR standard has the feature of a single parity extension to support low code rates. To support various data block sizes (e.g., transport block size or code block size) and to ensure good performance, two BGs are defined, each with eight CPM values ​​(i.e., respective (respective) cyclic shift values ​​for the eight CPMs). In this case, the parity check matrix can be expressed as follows: H = H BG + V i,j , here H BG is LDPC BG, and V i,j represents the cyclic transition value of CPM.

[0158] Fig. 12 illustrates a schematic structure of a basic graph of an LDPC code. In particular, Fig. 12(a) is a schematic structural diagram of LDPC basic graph 1 (BG1) according to the NR standard, and Fig. 12(b) is a schematic structural diagram of LDPC basic graph 2 (BG2) according to the NR standard.

[0159] According to 3GPP TS 38.212 Release 15, BG1 corresponds to K systematic information bits. b =22, supports a minimum code rate of 1 / 3, and is a 46-by-68 matrix. BG2 corresponds to K systematic information bits. b =10, supports a minimum code rate of 1 / 5, and is a 42-by-52 matrix. In general, BG1 is advantageous in terms of performance for large data block sizes, and BG2 is advantageous in terms of decoding latency for small data block sizes and low code rates.

[0160] Figure 13 is a diagram illustrating a criterion for selecting an LDPC base graph. For the (initial) transmission of a transport block having a coding rate R (i.e., code rate R) indicated by a modulation and coding scheme (MCS) index in a control information format that schedules a physical channel carrying a transport block, and for retransmission of the same transport block, each code block of the transport block can be encoded with LDPC BG1 or LDPC BG2. Referring to Figure 13, for example, if A ≤ 292, or if A ≤ 3824 and R ≤ 0.67, or if R ≤ 0.25, LDPC BG2 is used; otherwise, LDPC BG1 is used, where A is the payload size, for example, the transport block size (TBS).

[0161] Code block size K and BG's K b Using the value, the size Z of CPM can be calculated as follows: Z = K / K b .

[0162] Depending on the Z value determined by the above formula, CPM sizes (i.e. lifting sizes) can be selected using the following formula: i = {Z∈S j | j∈{1,...,8}}. The following table illustrates various sets of Z values ​​obtained using this formula.

[0163]

[0164] A parity check matrix can be obtained using the BG determined based on the TBS and coding rate R, and the CPM size (i.e., lifting size). For example, K in all sets of lifting sizes in the table above b *Z c Z is the minimum value of Z that makes ≥K' c is found, and for LDPC BG1, K = 22Z c A, for LDPC BG2, K = 10Z c can be set. Here, K' = B' / C, the number of bits in each code block K, B' = B + C*L, where B is the size of the TB to which the CRC is appended, B = A + L, A is the payload size (i.e., TBS), C is the number of code blocks, and L is the length of the CRC sequence attached to the TB, i.e., the number of CRC bits. The transport block (TB), which is the transmission data, is a MAC PDU, and the transmitter appends, for example, a 24-bit CRC sequence to the TB and performs LDPC encoding. However, if the size of the TB to which the CRC is appended is greater than a certain value, the TB to which the CRC is appended is segmented into multiple code blocks (CB). According to 3GPP TS 38.212 Release 15, for BG1, code block segmentation is performed when the size of the TB with CRC exceeds 8448 bits, and for BG2, code block segmentation is performed when the size of the TB with CRC exceeds 3840 bits. The number of code blocks C obtained based on one TB can be obtained using: C = CEIL{B / (K cb - L)}, where K cb is the maximum code block size and L is the length of the additional CRC sequence attached to each code block, i.e., the number of CRC bits. As mentioned earlier, B is the size of the TB to which the CRC is appended. According to 3GPP TS 38.212 Release 15, K cb For BG1, it is 8448, for BG2, it is 3840, and L is 24. If the number of CBs C > 1, a 24-bit CRC is added to each CB, and then LDPC encoding is performed.

[0165] The bit sequence input for a given code block is c0,c1,c2,c3,...,c K-1 and the bits after encoding are d0,d1,d2,d3,...,d N-1 , for each code block encoded by LDPC, for example, the following encoding process can be applied, where K is the number of bits to be encoded and N is the number of bits after encoding:

[0166] > 1) Z in Table 4 c Index i containing LS Find the inset.

[0167] > 2) for k = 2Z c to K-1

[0168] >> if c k ≠ <null>

[0169] >>> d k-2Zc = c k ;

[0170] >> else

[0171] >>> c k = 0;

[0172] >> end if

[0173] > end for

[0174] > 3) N+2Z to be c -K parity bits w=c=[w0,w1,w2,w3,...,c N+2Zc-K-1 ] T , where c = [c0,c1,c2,c3,...,c K-1 ] T ;0 is a column vector with all elements equal to 0. The encoding is performed in GF(2), where GF is the Galois field. In some scenarios, for LDPC BG1, H BG The matrix of can have 46 rows with row indices i=0,1,2,...,45 and 68 columns with column indices j=0,1,2,...,67. In some scenarios, for LDPC BG2, H BG The matrix H can have 42 rows with row indices i=0,1,2,...,41 and 52 columns with column indices j=0,1,2,...,51. The parity check matrix H is defined as follows: BG Each element of Z c -by-Z c It can be obtained by replacing it with a matrix:

[0175] -H BG Each element of my value 0 has size Z c *Z c is replaced by the zero matrix 0;

[0176] -H BG Each element of my value 1 has size Z c *Z c Circular permutation matrix I(P) i,j ) is replaced by I(P), where i and j are the row and column indices of the element, respectively. i,j ) is the size Z c -by-Z c The identity matrix I of P is moved to the right or left i,j It is obtained by cyclically transferring as many times as P. i,j The value of P i,j = mod(V i,j , Z c ) can be given by. For example, for 3GPP TS 38.212 Release 15, V i,j The value of the set index i LS and LDPC BG are given by Table 5.3.2-2 and Table 5.3.2-3 of 3GPP TS 38.212 Release 15 (see Section 5.3.2 of 3GPSS TS 38.212 Release 15).

[0177] > 4) for k = K to N+2Z c -1

[0178] >> d k-2Zc = w k-K ;

[0179] > end for.

[0180] To support communication systems requiring high data rates, more data bits must be transmitted per unit transmission time. Currently, in the 5G standard, transmission data bits are transmitted in the form of transport blocks (TBs). If a TB exceeds a certain size, it is divided into multiple code blocks (CBs), and the transmitter encodes and transmits each CB. In this case, to support higher data rates, the TBS increases, which increases the number of transmitted CBs. Typically, transmission parameters are set to satisfy a certain block error ratio (BLER) for TB transmission. As the number of CBs increases, the error requirements for each CB to satisfy the corresponding BLER also increase. Furthermore, because the entire TB must be retransmitted even if a specific CB fails, HARQ transmission efficiency decreases. To address this situation, the following transmission methods can be considered.

[0181] * Method 1: The transmitter can improve HARQ transmission efficiency by selectively retransmitting only CBs where errors occurred. In this case, the HARQ ACK feedback overhead and the number of control signaling bits increase.

[0182] * Method 2: CB BLER can be improved by having the transmitter perform inter-CB encoding and the receiver perform inter-CB decoding when a CB error occurs. This requires additional decoding, which increases complexity.

[0183] Method 1 has been adopted in the 5G standard. Considering signaling overhead, Method 1 can also be applied by defining multiple CBs as code block groups (CBGs), thereby reducing signaling overhead. However, in communication systems requiring higher data rates, as the TBS increases, the number of CBs within a CBG also increases, potentially reducing the efficiency of Method 1. Therefore, Method 2 is considered in some implementations of this specification described below.

[0184] In some implementations of this specification, globally coupled LDPC codes (GC LDPC) may be used for inter-CB encoding.

[0185] Fig. 14 is an example of the structure of a globally coupled LDPC (GC LDPC) code. For example, Fig. 14 may be the structure of a base matrix or a parity check matrix of a GC LDPC code. Fig. 14(a) illustrates the structure of a base matrix or a parity check matrix of a GC LDPC, and Fig. 14(b) illustrates GC LDPC from the perspective of a Tanner graph representation. The construction of GC LDPC codes typically goes through two steps. In the first step, a base matrix (i.e., a base graph) is designed, and then each element of the base matrix is ​​replaced with a CPM of size Z-by-Z or a zero matrix of size Z-by-Z.

[0186] Existing TB-based communication of 5G requires additional transmission for the entire TB or additional transmission for some TBs when errors occur in some CBs, which leads to high latency and resource consumption. GC LDPC codes are designed based on multiple constituent block LDPC codes (see the paper "Li, S. Lin, K. Abdel-Ghaffar, W. E. Ryan, and D. J. Costello, "Globally coupled LDPC codes," in Information Theory and Applications Workshop (ITA), Jan. 2016."). GC LDPC codes are a novel extension of traditional LDPC codes by introducing global coupling between variable nodes to enhance error correction capability. The base matrix or parity check matrix of a GC LDPC code includes disjoint copies of the block LDPC codes, called local codes, and a global part that concatenates the base matrices or parity check matrices of all local codes into a single large matrix. The above local codes, also called local LDPC codes, are connected only by global coupling check nodes, as illustrated in Fig. 14. These global check nodes provide diversity between codes during decoding, thereby improving the error correction performance of the constituent codes. In the global coupling portion at the bottom of the parity check matrix in Fig. 14, the check nodes connect all variable nodes, providing high connectivity for each coded bit, which provides faster convergence of iterative decoding and improves error correction performance. The structure of GC LDPC codes provides high throughput transmission because disjoint local codes can facilitate parallel encoding and decoding.

[0187] Hereinafter, a local codeword may mean a codeword generated by a local code, and a global codeword may mean a codeword obtained by applying a global code according to some implementations of the present specification to a codeword obtained from local codewords (e.g., a codeword obtained by concatenating the local codewords).

[0188] Figures 15 and 16 illustrate the error correction performance of GC LDPC codes. In particular, Figure 15 illustrates the performance as the number L of component codes (e.g., the number L of local codes) with a code rate of 0.5 varies, and Figure 16 compares the error rate performance of decoding for a single GC LDPC code and two-step decoding according to the code rate.

[0189] Referring to Fig. 15, it can be confirmed that, unlike the existing LDPC code whose TB error rate performance deteriorates as L increases under the appropriate code rate condition of 0.5, the GC LDPC code can obtain an error rate performance gain as the number L of coupled constituent codes increases.

[0190] For GC LDPC codes, the receiver first performs decoding on local codes, and if decoding of some local codes fails, decoding is performed on the entire code using global coupling check nodes. This allows the receiver to minimize decoding delay by minimizing the number of times global check nodes are utilized. In other words, for GC LDPC codes, the receiver can minimize delay and decoding complexity by decoding global codewords only when decoding of individual local codewords fails through two-stage decoding. Referring to Fig. 16, under the condition of code rate R = 0.5, when the receiver performs decoding more than a certain number of iterative times in the two-stage decoding process, it can be confirmed that the error rate performance can be improved through two-stage decoding compared to performing a single decoding on the local codes that constitute the GC LDPC code. This improves the TB error rate performance of LDPC codes consisting only of local codes.

[0191] Figure 17 illustrates the general structure of a parity check matrix of a GC LDPC code.

[0192] As explained earlier, a global-coupled (GC) LDPC code is a type of LDPC code that connects multiple local LDPC codes via global check node(s). In the case of GC LDPC codes, global check node(s) are added, and the addition of global check node(s) can be considered equivalent to adding new row(s) from the perspective of the parity check matrix. Therefore, n L A general parity check matrix H of a GC LDPC code using local LDPC codes GC may have a structure as illustrated in Fig. 17. Referring to Fig. 17, H GC My matrix H local,i (where 1≤i≤n L ) is a form that replicates the parity check matrix of the local LDPC code. The number of local LDPC codes that constitute one GC LDPC code is n L Since the parity check matrix of the local LDPC code is n in total, L It is replicated 1 time, and the above n L The dog replicas are n of the diagonal of the GC LDPC code. L It can be used as a parity check matrix. The parity check matrix H is illustrated in Fig. 17. GC Parts that are not defined in (e.g., parts marked as blank) can be considered as '0's or zero matrices.

[0193] Fig. 18 is an example of a parity check matrix of a GC LDPC code. Referring to Fig. 18, for example, assuming that the LDPC code of Equation 3 is used as a local code, and that one GC LDPC code includes two local codes in total and one global check node that determines the two local codes, H Global The corresponding parity check matrix consists of one row. It is assumed that each element of the row generated for adding the global check node is randomly assigned a value of '0' or '1'. In the example of Fig. 18, H local,1 and H local,2 Each has the same form as the matrix of Equation 3, and the matrix of Equation 3 is replicated twice, and the two replicates are used as two local LDPC codes in total. In the example of Fig. 18, the last row used as the global parity check matrix is ​​randomly generated.

[0194] Fig. 19 illustrates a Tanner graph corresponding to the GC LDPC code of Fig. 18. Referring to Fig. 19, in the first local code, the first, third, and fourth VNs are connected to a new CN (corresponding to the global parity check node of Fig. 19), and in the second local code, the second and third VNs are connected to the new VN. Referring to Figs. 17 to 19, in the case of the GC LDPC code, CN(s) are added through additional row(s) in addition to the rows of the local LDPC codes, and the connection(s) between CN(s) and VN(s) are not limited to the VN(s) of one local code, and connectivity with VNs of multiple local codes can be established.

[0195] GC LDPC codes depend on the global coupling check part that connects the local codes, and the performance of GC LDPC codes depends on the optimization of the global coupling check part. The design methods proposed so far for the global coupling check parts for GC LDPC codes have focused on optimizing the global coupling check part for a fixed TBS or a fixed number of local codes. However, since the number of CBs varies depending on the TBS, and thus the number of local codes also varies, if the global coupling check part is defined for a fixed TBS or a fixed number of local codes, the global coupling check part should be defined or optimized for each TBS or the number of local codes. For example, in the case of the existing GC LDPC code, to build the connectivity of the global parity check matrix, n L All connectivity for all VNs for local codewords is considered. Following the design method of the existing GC-LDPC code, the number of local codes n for one additional global check node L Since the number of VNs multiplied by the length n of the local code and the connection between the global CN must be considered, the total number of connection candidates to be searched for one global CN is 2^(n L Хn). Also, fixed n L Global parity check matrix H for Global Because the number of local codes (or the number of code blocks to be transmitted / received in a single transmission / reception period, or the number of code blocks within a code block group) is not suitable for use in flexible communication technologies, several implementations of the global coupling check part of the GC LDPC code are described below.

[0196] In some implementations of this specification described below, the global part of the global parity check matrix is ​​designed to match the size of each local code. Therefore, some implementations of this specification can design or determine GC LDPC codes to accommodate a dynamic or diverse number of local codes. This can reduce the search space for connecting additional global check node(s) to variable node(s) of local codes as a block-level design.

[0197] Fig. 20 illustrates a schematic structure of a GC LDPC code according to some implementations of the present specification. In Fig. 20, the part indicated as "Local Code" is the basic matrix or parity check matrix of the local codeword, and the part indicated as "Global part" is the basic matrix or parity check matrix of the global part corresponding to each local codeword. In addition, the part indicated as "Global parities" is a part that enables efficient encoding by the global parity check matrix as an additional parity variable node. In the following, for the convenience of explanation, the global basic matrix or global parity check matrix according to some implementations of the present specification will be described by taking as an example the case where the part corresponding to "Global parities" (hereinafter, "global parity part") is composed of an identity matrix. However, some implementations of this specification are not limited to the global parity matrix (e.g., the matrix in the part labeled "Global parities") being an identity matrix with each row or each column having weight 1, and some row(s) or column(s) may have weights greater than 1 (e.g., see the submatrix by the last 46 columns of Fig. 12(a) or the submatrix by the last 42 columns of Fig. 12(b)).

[0198] As illustrated in Fig. 20, according to some implementations of the present specification, global parities are generated by global parts that have a connection relationship with multiple local codes. In the case of LDPC encoding in the current NR standard, the number of code blocks varies according to the TBS, so it can be efficient to design the global parity part to be divided according to the length of the local code in terms of scalability of the number of code blocks. Referring to Fig. 20, for example, the length of the local code is N, and the length of the global parity is M. G When , the size of the matrix corresponding to the global part divided into units of the length of the local code is M G *N, the size of the global parity matrix is ​​M G *M G The global parts of the GC LDPC code according to some implementations of this specification form a connection between local codes, so that the local codes are reflected in the global parities. The number of CBs associated with one TB or the number of CBs in a CBG to be transmitted in one transmission period is n L Then, the number of local codes of the GC LDPC code used for channel encoding for each CB of the TB or CBG is n L It can be, n L The local codes are n L Respond to each of the dog CBs (respectively) or n L Each CRC additional CB can be corresponding to a different CRC additional CB. In this specification, an input sequence of length n input to a channel encoder or an information sequence corresponding to a local PCM of length n is also called an information block.

[0199] In order to maximize the performance of the GC LDPC code of the structure illustrated in Fig. 20, the design of the optimal global parity part(s) and the global part is required. When NR LDPC encoding is performed, the local code blocks have the same size and are LDPC encoded (respectively) using the same base graph (BG). Therefore, it may be efficient to utilize the repetition characteristic of the same structure in the design of the global part. For example, n L local codes of the dog (e.g., n L When LDPC encoding is performed on n code blocks, nGlobalPart global parts can be designed to have the same (parity) structure. In this case, since the number of global parts to be optimized is 1 / nGlobalPart, the global parity check matrix can be designed to be optimized efficiently. In some implementations of this specification, nGlobalPart = n L may be. In other words, in some implementations of this specification, all n L The global parts can be designed to have the same (parity) structure. This design approach can reduce optimization complexity. Furthermore, this design approach can be applied to cases where BG1 or BG2 according to the current NR standard, or the corresponding PCM, are used as local codes. In some implementations, the global part and the global parity part can be designed with a quasi-cyclic (QC) structure, and the following lifting method can be considered for the global part and the global parity part with the QC structure.

[0200] * Method 1: The design complexity can be reduced by using the same lifting method as the local code. For example, if the 5G LDPC code according to the current 5G standard is used as the local code, the lifting method according to the current 5G standard (e.g., lifting factor, number of cyclic shifts (e.g., cyclic shift value V of CPM) i,j ) etc.) can be applied to the global part and / or global parity part, the complexity for PCM design of the global part and / or global parity part can be reduced.

[0201] * Method 2: Performance can be improved by lifting methods that are not identical to the local code. For example, assuming that the PCM(s) of the local code are designed, if the PCM(s) of the global part and / or the global parity part are redesigned considering the PCM(s) of the local code, the performance of the GC LDPC code can be improved. Some implementations of the present specification described below (e.g., identity matrix-based global part, strong node to strong node-based global part, weak node to strong node-based global part, etc.) can improve the performance of the GC LDPC code by newly designing the basis matrix or PCM for the global code among the GC LDPC codes.

[0202] In some implementations, if the size of the base matrix / graph of the local code is M-by-N, an m-by-n PCM can be obtained from the base matrix / graph of size M-by-N by lifting with a lifting factor Z, where m=Z*M, n=Z*N. The size of the base matrix / graph of the global part is M. G -If by-N, size M through lifting using lifting factor Z G -From the above basic matrix / graph of -by-N, m G -by-n PCM can be obtained, where m G =Z*M G , n=Z*N. The size of the basic matrix / graph of the global parity part is M. G -by-M G In this case, size M is obtained by lifting using lifting factor Z. G -by-M G From the above basic matrix / graph of m G -by-m G The PCM of can be obtained, where m G =Z*M G am.

[0203] Encoding in communication standards for some scenarios can be performed in two stages. In the first stage, a transport block of the required length is segmented into one or more code blocks, and each code block is encoded to generate an individual local codeword. For example, in the 5G communication standard, the transmission rate can be calculated using the following equation:

[0204]

[0205] Here, the meaning of each variable can be as follows:

[0206] > J: Number of aggregated component carriers

[0207] > R max : Code rate

[0208] > v (j) Layers : Maximum number of supported layers

[0209] > Q (j) m : Maximum supported modulation order

[0210] >f (j) : Scaling factors (e.g., 1, 0.8, 0.75, and 0.4)

[0211] > T u s : average OFDM symbol duration in a subframe for numerology u

[0212] > N W(j),u PRB : maximum RB allocation in bandwidth BW(j) with numerology u

[0213] > OH (j) : overhead (e.g., 0.18 for frequency range 2 downlink)

[0214] The transmission unit of 5G communication is a transport block (TB0), and each TB can be divided into multiple code blocks (CBs) through a code block segmentation process. According to 5G standards, each TB requires a block error rate (BLER) of 10%, and the required BLER of a CB can be determined as follows.

[0215]

[0216] BLER here TB and BLER CB are the required BLER for TB and the required BLER for CB, respectively (respectively), and C is the number of CBs obtained from one TB.

[0217] The transport block size (TBS) is the number N of resource elements (REs) in a physical resource block (PRB). RE can be determined based on the number of REs allocated for PDSCH within PRB, N. ' RE can be calculated as follows:

[0218]

[0219] Here, the meaning of each variable can be as follows:

[0220] > N RB sc : The number of subcarriers in a physical resource block. For example, N RB sc = 12.

[0221] > N sh symb : Number of symbols of the PDSCH allocation within the slot

[0222] > N PRB DMRS : Number of REs for DM-RS per PRB in the scheduled duration

[0223] > N PRB oh : Overhead configured by higher layer parameter xOverhead in RRC configuration PDSCH-ServingCellConfig (e.g., 0, 6, 12, or 18)

[0224] Based on this, the intermediate variable N required for TBS calculation info and N ' info can be calculated as follows:

[0225]

[0226] Here, the meaning of each variable can be as follows:

[0227] > N RE = min(156, N ' RE )n PRB , where n PRB is the total number of allocated PRBs for the UE.

[0228] > R = code rate

[0229] > Q m : modulation order

[0230] > v : number of layers (vХv MIMO)

[0231] > n = floor{log2(N info - 24)} - 5

[0232] Based on this, the number C of TBS and code blocks can be calculated as follows.

[0233]

[0234] Therefore, according to the current 5G standard, a TB can be divided into C CB(s), and each of the multiple CRC-added CBs obtained by adding a CRC code to each CB can be encoded using an LDPC code according to the 5G standard. For example, a single local parity check matrix can be used repeatedly for multiple CBs.

[0235] Fig. 21 illustrates the structure of a codeword obtained by concatenating local codewords, and Fig. 22 illustrates the structure of a codeword obtained by adding global parity bits to the codeword of Fig. 21.

[0236] n in Fig. 21 L = C and means the number of local codewords, and in Fig. 21, it is assumed that each block has the same length as the length n of the (local) codeword (CW) after encoding.

[0237] Afterwards, in the second step, encoding is performed on the codeword obtained by concatenating local codewords to obtain global parity(s). After encoding for global parity(s), m G By adding a global parity bit(s) of the dog, a codeword having the form of, for example, Fig. 22 can be obtained.

[0238] In some implementations of this specification, the matrix corresponding to the global parity part may be constructed by an identity matrix, in which case a valid codeword by a GC LDPC code must satisfy the following: The added parity check bit sequence is p GC is expressed as

[0239]

[0240] Here, H Global is a parity check matrix, and can be expressed as [AI] by separating the matrix of global parts and the matrix of the global parity part, which is the identity matrix. x can be a codeword obtained by concatenating local codewords (or codewords obtained by applying rate-matching to local codewords).

[0241] Figure 23 illustrates the structure of a parity check matrix for a global code within the GC LDPC structure illustrated in Figure 20. In some implementations, I is m G -by-m G It can be an identity matrix.

[0242] If we interpret mathematical expression 9 as an XOR operation on a binary field, p GC =A·x must be satisfied. Therefore, the value of the i-th global parity check node after encoding can be given as follows.

[0243]

[0244] Referring to the mathematical formula above, the value of the i-th global parity check node after encoding is the sum of the information bits corresponding to the columns whose element values ​​of the parity check matrix are '1' in the i-th row of the matrix A. For example, it is assumed that the two local codewords c1 and c2 obtained after encoding for two CBs are as follows: c1 = (0, 1, 1, 1, 0), c2 = (1, 1, 0, 0, 1). And it is assumed that the added parity check row is as follows: h = (0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1), where the first sub-row vector h1 = [0, 0, 1, 1, 1] consisting of the first five elements and the second sub-row vector h2 = [0, 0, 1, 1, 1] consisting of the next five elements are the global parts for the local codewords c1 and c2, respectively, and the last element 1 is the global parity part. This means that the third, fourth, and fifth VNs in each local code are connected to the global parity check node, and since the length of the added parity check row is 1 longer than the length of the two local codes, it can mean that the length of the global parity check node is 1. The parity check equation is satisfied only when the result of the XOR calculation of the sum of the values ​​corresponding to the connected VNs is 0. Therefore, in this example, h·[c1c2] T = [0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1]·[0, 1, 1, 1, 0, 1, 1, 0, 0, 1, p] T The value p = 1 of the global parity node satisfying = (0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + p) mod 2 = 0 is transmitted as the global parity bit.

[0245] Fig. 24 is an example of a parity check matrix of a GC LDPC code according to some implementations of the present specification. Referring to Fig. 24, according to the first step described above, two codewords, each of which is a result of independently encoding by the local code illustrated in Fig. 24, are c1 = (c 11 , c 12 , c 13 , c 14 , c 15 , c 16 ) and c2= (c 21 , c 22 , c 23 , c 24 , c 25 , c 26 ), then the values ​​or column vector of VNs determined by the two codewords and the corresponding global parts according to the second step described above is a column vector with three bit values, and the three bit values ​​are respectively (respectively) p1 = (c 12 + c 13 + c 15 + c 16 + c 22 + c 23 + c 25 + c 26 ) mod 2, p2= (c 11 + c 13 + c 21 + c 23 ) mod 2, p3= (c 13 + c 16 + c 23 + c 26 ) mod 2. Therefore, the global parity bit sequence p calculated by the second step above GC = (p1, p2, p3), and p GC can be transmitted together with the codewords c1 and c2 obtained in the first step.

[0246] The question arises as to how to construct the matrix of the global part. In some implementations of this specification, the column(s) containing 1 for each row of the matrix of the global part can be determined using a P-EXIT chart. In other words, in some implementations of this specification, the elements containing 1 among the elements in the matrix of the global part can be determined using a P-EXIT chart.

[0247] Here's a brief description of the P-EXIT chart. The P-EXIT chart is a tool used to quantitatively evaluate the convergence of a decoding algorithm by visualizing the iterative message passing process of a decoder (also known as the iterative decoding process). In particular, the P-EXIT chart can be used to track how the mutual information (MI) exchanged at each node (e.g., VN or CN) changes during iterative decoding in a protograph-based LDPC code. While the conventional EXIT chart estimates the performance of an entire large ensemble of QC LDPC codes with specific column and row weights, the P-EXIT chart simulates the mutual information transfer characteristics of a type specified for each node in the base matrix. In the P-EXIT chart, the curve curve (VNP) on the variable node (VN) side and the curve curve (CNP) on the check node (CN) side are I A Wow I E Expressed in the form of a function (I A , I E ), check whether the decoding performance has converged. I in the P-EXIT chart A is the mutual information between the VN associated with the VNP and the VNP input (e.g., a priori information), and I E is the mutual information between the VN associated with the VNP and the VNP output (extrinsic information). For example, in the P-EXIT chart, I A can indicate how much the a priori information input to the VN is related to the actual coded bits, and I E can indicate the quality of the newly generated information by the VN (e.g., how much more accurate the information the VN provides after iterative decoding). At this point, we observe whether the two curves do not overlap and whether there is a tunnel that gradually connects them. The presence of this tunnel indicates that decoding can converge through iterative decoding. Thus, we can find the point where the tunnel first opens, or in other words, the signal-to-noise ratio (SNR) point where decoding begins to converge successfully. This value is called the threshold.

[0248] Meanwhile, a parity check matrix can be generated using a protograph LDPC code. A protograph LDPC code is a design technique that generates a large LDPC code, such as a parity check matrix, by expanding (also called lifting) a relatively small "base graph" multiple times based on it. The LDPC code currently used in 3GPP 5G NR also defines a "base graph (BG)" that matches the concept of a protograph, and lifts it to form a large matrix used in actual transmission. In the step of defining the protograph or base graph, a very small bipartite graph consisting of variable node(s) and check node(s) is first established. Next, the bipartite graph goes through a lifting or expansion process. In this step, the size of the graph is increased by replicating one edge existing in the protograph by a lifting factor. This ultimately forms a graph that is larger than the protograph by a factor of the expansion. However, since simple replication alone may shorten the girth (e.g., the shortest cycle in the Tanner graph of an LDPC code) or degrade performance, various techniques such as cyclic shifts are used to optimize the structure of the graph and improve performance. Each element of the protograph is replaced with a locally cyclically shifted form of the identity matrix through lifting. At this time, the matrix indicating the number of cyclic shifts of the identity matrix corresponding to each element can be defined as an exponent matrix. Finally, the final parity check matrix can be completed by organizing the connectivity of this expanded large-scale graph back into matrix form.As a result, if the size of the basic graph is MХN and the lifting factor is Z, the size of the parity check matrix obtained through lifting is (Z*M)Х(Z*N), and when the transmitter performs encoding using this, a codeword of length Z*N can be generated. For example, the basic matrix. , exponential matrix , and assuming that the lifting factor Z = 3, the parity check matrix obtained by expanding the basic matrix B can be as follows.

[0249]

[0250] The 1 in the first row and first column of the above basic matrix B is replaced with a 3-by-3 matrix obtained by cyclically shifting the 3-by-3 identity matrix by 0, which is the value of the first row and first column of the above exponential matrix E.

[0251] Figures 25 and 26 illustrate the results of P-EXIT analysis for an example of a simple protograph LDPC code and the amount of mutual information for each variable node, respectively (respectively). Basic matrix When the threshold is found through P-EXIT analysis, the value Eb / No = 0.7751, and the P-EXIT chart at this time is as shown in Fig. 25. Here, Eb means energy per bit, and No means noise power. The integer value in each element of the basic matrix represents the weight of each column or each row of the Z-by-Z matrix corresponding to the element (e.g., the number of 1s in each row or each row). For example, since the element value of the first row and the first column of the basic matrix B is 2, among the Z elements in each row or each column of the Z-by-Z matrix that replaces the first row and the first element, there are 2 elements with 1.

[0252] The amount of mutual information (MI) for each variable node according to the basic matrix B of the P-EXIT of FIG. 25 is illustrated in FIG. 26. The fact that the amount of mutual information for each variable node reaches 1 means that decoding convergence has been achieved. In some implementations of this specification, a variable node that quickly reaches decoding convergence is defined as a strong node, and a variable node that relatively slowly reaches decoding convergence is defined as a weak node, and the global part is designed using the concepts of strong and weak nodes. A strong node may mean a variable node for which the number of iterations required to determine the bit value corresponding to the variable node during the decoding process is smaller than the number of iterations required to determine the bit value corresponding to the weak node. Hereinafter, some implementations of this specification that design the global part using the concepts of strong and weak nodes are described, using a GC LDPC code for a Raptor-like LDPC code having the same structural characteristics as 5G as an example.

[0253] FIG. 27 is an example of a base matrix for a local codeword that may be used in some implementations of the present specification. For example, the base matrix of FIG. 27 may be used as a base matrix corresponding to one local code in the parity check matrix illustrated in FIG. 20. For convenience of explanation, some implementations of the present specification are described herein using a small-sized matrix as an example of the base matrix; however, LDPC base matrices or LDPC base graphs of different sizes and shapes may also be used for local codes.

[0254] In some implementations, the matrix corresponding to the global parity part, denoted as "Global parities" in the parity check matrix of FIG. 20, may be designed as an identity matrix. In the following, an integer grid is used to represent the position of 1 in the matrix. Among the intersection points in the integer grid, an intersection point with a round dot indicates the position of an element having '1' in the basic matrix, and an intersection point without a round dot indicates the position of an element having '0' in the basic matrix.

[0255] Figure 28 illustrates a 3-by-3 elementary matrix represented as an integer grid. In particular, Figure 28 is an example of a 3-by-3 identity matrix represented as an integer grid. In the integer grid, the horizontal axis is the column index axis, and the vertical axis is the row index axis.

[0256] In the structure of the GC LDPC code illustrated in Fig. 20, if the global parity part indicated as "Global parities" is configured by an identity matrix, the part to be designed in some implementations of the present specification may be one global part. For example, if the basic matrix of Fig. 27 is used as the basic matrix for one local codeword, the size of the basic matrix is ​​9X13.

[0257] FIG. 29 is an example of a base matrix of a global part according to some implementations of the present specification. In particular, FIG. 29 is an example of a base matrix of a global part that can be used when the base matrix of FIG. 27 is used as a base matrix for a local codeword.

[0258] The number of global inspection nodes is M G If we denote it as , the identity matrix-based fundamental matrix for the global part is of size M G -by-M G The identity matrix of can be obtained by cyclically concatenating the columns of the basic matrix until the number of columns of the basic matrix of the local codeword is equal to the number of columns of the basic matrix of the local codeword. M G =3, the identity matrix-based base matrix for the global part can be, for example, as shown in Fig. 29. The base matrix of Fig. 29 is a matrix of size 3X13, designed to have rows corresponding to three global check nodes and a row length matching the column length 13 of the base matrix for the local codeword (e.g., the base matrix illustrated in Fig. 27).

[0259] Fig. 30 illustrates the amount of mutual information per variable node according to the P-EXIT chart analysis for the variable nodes of the basic matrix illustrated in Fig. 27. In particular, Fig. 30 illustrates the extent to which the amount of mutual information per variable node of the basic matrix increases through the P-EXIT chart analysis of the variable nodes of the basic matrix for an example of the basic matrix illustrated in Fig. 27.

[0260] Through P-EXIT chart analysis, the characteristics of the variable nodes of the basic matrix of the local code illustrated in Fig. 27 can be obtained. By measuring the mutual information of each variable node at the half point of the maximum number of allocated iterations, the rank of the degree of decoding convergence for each variable node can be determined. If the variable nodes 1 to 13 of the basic matrix illustrated in Fig. 27 are sorted in descending order of the positive MI from the variable node with the highest MI in the special number of iterations, the following variable node sequence or column index sequence can be obtained: {5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7}. Referring to the above variable node sequence {5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7}, the basic matrix illustrated in FIG. 27 can determine the bit value of variable node 5 with fewer decoding iterations than the bit value of variable node 7.

[0261] In some implementations, the variable node sequence or row index sequence used to determine the order of the strong variable nodes can be obtained by sorting the variable node indices or row indices in positive descending or ascending order of MI. Alternatively, in some implementations, the variable node sequence or row index sequence used to determine the order of the strong variable nodes can be obtained by sorting the variable node indices or row indices in positive descending or ascending order of the number of decoding iterations required to determine the bit value corresponding to the corresponding variable node or row.

[0262] In some implementations of this specification, a GC LDPC structure that outperforms existing GC LDPC code structures that use a global parity check matrix composed of identity matrices can be obtained by connecting strong variable nodes to strong variable nodes to generate a base matrix or parity check matrix for the global part. Connecting strong variable nodes can perform better than connecting strong nodes to weak nodes. The reason for this performance improvement is as follows. Once a bit (e.g., a VN) is successfully decoded, information exchange through edges connected to the bit that have already been recovered in the Tanner graph is not actually performed during the decoding iteration. Therefore, the edge connected to the recovered bit can be considered to be effectively removed from the Tanner graph, and the node connected to the recovered bit can be advantageous for decoding because it is no longer connected during the remaining decoding process.

[0263] Some implementations of this specification that connect strong variable nodes to each other are described in terms of the basic matrix, for example, M for the global part. G For the basic matrix of -by-N, floor{N / M G} strongest variable nodes are connected to each other, and floor{N / M G } can be constructed in such a way that the next strongest variable nodes are connected to each other. Connecting the variable nodes can mean that the elements of the columns corresponding to the variable nodes in one row each have '1'. Since the parity check matrix is ​​obtained by lifting the basic matrix by the lifting factor, the variable nodes connected in the basic matrix are also connected in the parity check matrix. If N is M G If it is not an integer multiple of N - M G *floor{N / M G } > 0 and becomes 'N - M G *floor{N / M G The question is how to handle the weakest variable nodes N and M. G If it is not an integer multiple of N - M, or G *floor{N / M G } > 0, then in some implementations, 'N - M G *floor{N / M G }' weakest variable nodes can remain unconnected to other variable nodes. This M G If it is not an integer multiple of N - M, or G *floor{N / M G } > 0, then in some implementations, 'floor{N / M G } + N - M G *floor{N / M G }' can be connected to the weakest variable nodes.

[0264] Figure 31 is another example of a basic matrix of a global part according to some implementations of this specification.

[0265] Hereinafter, the global part according to some implementations of the present specification that connects strong variable nodes is described, taking as an example the basic matrix of a GC LDPC code including three global parity check nodes. In this example, it is assumed that the matrix of FIG. 27 is used as the basic matrix of a local code in the GC LDPC code. In this case, when connecting strong nodes to strong nodes according to some implementations of the present specification, based on the variable node sequence {5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7} described above, variable nodes {5, 3, 6, 1} can be connected to each other, variable nodes {2, 4, 11, 13} can be connected to each other, and variable nodes {9, 10, 12, 8} can be connected to each other. This could mean that in one of the three rows of the fundamental matrix for the global part, the 1st, 3rd, 5th, and 6th fundamental matrix values ​​(i.e., the elements in the 1st, 3rd, 5th, and 6th columns) are each '1', in one of the remaining two rows, the 2nd, 4th, 11th, and 13th values ​​are each '1', and in the remaining two rows, the 8th, 9th, 10th, and 12th values ​​are each '1'. In some implementations, the weakest variable node 7 could remain unconnected to any other variable node. Alternatively, in some implementations, the weakest variable node 7 could be interconnected with the weak variable nodes {9, 10, 12, 8}. Figure 31 illustrates a case in which the strongest variable nodes {5, 3, 6, 1} are connected in the first row of the fundamental matrix of the global part, the next strongest variable nodes {2, 4, 11, 13} are connected in the second row of the fundamental matrix of the global part, and the weakest variable nodes {9, 10, 12, 8} are connected in the last row of the fundamental matrix of the global part.

[0266] Fig. 32 is another example of a basic matrix of a global part according to some implementations of the present specification. In particular, Fig. 32 illustrates a basic matrix obtained by connecting weak variable nodes and strong variable nodes. In the case of weak node-strong node connection, for example, referring to Fig. 32, among the 13 variable nodes of the basic matrix, variable nodes {5, 3, 7, 8} may be connected to each other, variable nodes {6, 1, 12, 10} may be connected to each other, and variable nodes {2, 4, 9, 13} may be connected to each other. The basic matrix of Fig. 32 is M G = 3, and the result is that two strong nodes and two weak nodes are sequentially selected and connected to keep the number of '1's in each row to 4.

[0267] Thereafter, the basic matrix of the global code can be converted to PCM through lifting, and global parity bits can be generated through encoding using the PCM for codewords obtained from local codewords corresponding to local codes (e.g., codewords obtained by concatenating local codewords). Transmission bits can be determined (through rate matching) based on the codewords and the global parity bits, and the transmission bits can be transmitted to a receiver through a wireless channel.

[0268] Each element in the base matrix can be replaced by a Z-by-Z matrix through lifting. The Z-by-Z matrix that replaces each element through lifting can be a Z-by-Z zero matrix or a Z-by-Z circulant permutation matrix (CPM).

[0269] Simulated annealing (SA) can be used as a method for obtaining CPMs associated with cyclic shifts for the basic matrices designed according to some implementations of the present specification described above (the basic matrix of FIG. 29, the basic matrix of FIG. 31, and / or the basic matrix of FIG. 32). It is known that performance degradation occurs when the shortest cycle in the Tanner graph of an LDPC code is 4. In order to avoid performance degradation in all implementations, it may be desirable to design an LDPC code with a girth of 6. The parity check matrix generated by the CPM value(s) determined through the SA technique has a girth (e.g., the shortest cycle in the Tanner graph of the LDPC code) of 6. It is known that performance degradation occurs when the shortest cycle in the Tanner graph of the LDPC code is 4. In some implementations, it may be desirable to design an LDPC code with a circumference of 6 to avoid performance degradation. Using the SA technique, a PCM with a circumference of 6 can be obtained when the lifting factor is 33. When the lifting factor is 33, if the aforementioned 9-by-13 basic matrix for the local code is extended, the length of the local codeword becomes 13*33 = 429. Also, since the size of each global part is 3-by-13, the extended matrix is ​​a matrix of size (3*33)-by-(13*33) = 99-by-429. The number of global check nodes in the aforementioned basic matrix of the global part, M G = 3, so in the case of the parity check matrix, the number of global parity bits added due to the global parts of the GC LDPC code is 33*3 = 99, and a total of 99 global check nodes are used.

[0270] Figure 33 is an example of a matrix obtained by extending the basic matrix of the global parity part. When the basic matrix of the global parity part is extended by a lifting factor of 33, the parity check matrix of the global parity part becomes a 99-by-99 matrix.

[0271] FIGS. 34, 35, and 36 illustrate parity check matrices obtained by extending the basic matrices of FIGS. 29, 31, and 32 for the global part, respectively. By lifting the basic matrices of FIGS. 29, 31, and 32 by a lifting factor Z=33, the parity check matrices of FIGS. 34, 35, and 36 for the global part, respectively, can be obtained. In this case, a parity check matrix of size 99-by-429 corresponding to the global part of the GC LDPC code can be obtained. In particular, FIG. 34 illustrates an identity matrix-based parity check matrix for the global part, FIG. 35 illustrates a strong node-strong node connection-based parity check matrix for the global part according to some implementations of the present specification, and FIG. 36 illustrates a weak node-weak node connection-based parity check matrix for the global part according to some implementations of the present specification.

[0272] Figure 37 illustrates the performance evaluation results of GC LDPC codes according to some implementations of the present specification. In Figure 37, "Baseline" represents the performance by the identity matrix-based parity check matrix, "StoS" represents the performance by the strong node-strong node connection-based parity check matrix, and finally "WtoS" represents the performance by the weak node-strong node connection-based parity check matrix. In the performance evaluation of Figure 37, 10 codewords were used for one code block group, an additive white Gaussian noise (AWGN) channel, binary phase shift keying (BPSK) were assumed, and a two-stage decoder based on belief propagation (BP) decoder was used. Referring to Figure 37, it can be seen that “StoS” has a lower error rate of code block group (CBG) than “Baseline” and “StoS” for Eb / No values.

[0273] According to some implementations of this specification, a CG LDPC code can be designed efficiently. According to some implementations of this specification, a GC LDPC code having a scalable structure depending on the number of TBSs or CBs to be transmitted / received in one transmission occasion can be provided. According to some implementations of this specification, a GC LDPC code capable of reducing a TB or CBG error rate can be provided. According to some implementations of this specification, even if an error occurs in a TB, CB, or CBG, error correction can be enabled, reducing the number of retransmissions and thus improving system throughput.

[0274] Figure 38 illustrates a channel encoding process according to some implementations of this specification.

[0275] A communications device or encoder may perform operations according to some implementations of the present disclosure in connection with channel encoding. The communications device may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A processing device for the communications device or encoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer-readable (non-transitory) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer program or computer program product may be recorded on at least one computer-readable (non-transitory) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.

[0276] Referring to FIG. 38, in a method performed by the communication device, or in the communication device, the encoder, the processing device, the computer-readable (non-transitory) storage medium, and / or the computer program product, the operations are: n L Determine the dog information blocks; the above n L Each of the dog information blocks is encoded based on the first matrix, and each of them has length n. L Obtaining local codewords (S3801); the above n L length n*n based on local codewords L Obtain the first codeword; Encode the first codeword based on the second matrix to have length n G Obtain the second codeword (S3803), where n G = n*n L + m G ; determining coded bits to be transmitted based on the second codeword; and transmitting the coded bits. The second matrix may have a structure according to some implementations of the present specification. For example, the second matrix may have a size m. G -by-n G Parity check matrix H Global = [AP] can be related, where P is of size m G -by-m G is the matrix of , and A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G It is a matrix of -by-n.

[0277] Figure 39 illustrates a channel decoding process according to some implementations of the present specification.

[0278] A communications device or decoder may perform operations according to some implementations of the present disclosure in connection with channel decoding. The communications device may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A processing device for the communications device or decoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer-readable (non-transitory) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer program or computer program product may be recorded on at least one computer-readable (non-transitory) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.

[0279] Referring to FIG. 39, a method performed by the communication device, or in the communication device, the decoder, the processing device, the computer-readable (non-transitory) storage medium, and / or the computer program product, the operations include: receiving coded bits associated with a second codeword (S3901); and performing decoding on the coded bits based on a first matrix and a second matrix, thereby obtaining n L It may include determining the dog information blocks (S3903). The second codeword may be obtained through encoding based on the second matrix for the first codeword, and the first codeword may be n, each having a length n. L It can be obtained based on the local codewords of the above n L The local codewords are n L Each of the dog information blocks can be obtained by encoding based on the first matrix. The second matrix may have a structure according to some implementations of the present specification. For example, the second matrix may have a size m. G -by-n G Parity check matrix H Global = [AP] can be related, where P is of size m G -by-m G is the matrix of , and A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G It is a matrix of -by-n.

[0280] With respect to Fig. 38 or Fig. 39, P is of size m G -by-m G can be the identity matrix.

[0281] In connection with FIG. 38 or FIG. 39, the method or the operations: replace each element of the second matrix with a Z-by-Z matrix H Global may further include obtaining, wherein said second matrix has a size M G -by-N G Matrix B Global = [BP B ], where m G = Z*M G , n G = Z*N G and, B= [B_1B_2 ...B_n L ] and B_1 =B_2 = ... =B_n L =B G And, B G is size size M G -by-N matrix, where n = Z*N, and P B is size M G -by-M G is a diagonal matrix.

[0282] In relation to Fig. 38 or Fig. 39, P is P B It can be obtained by replacing each element in the diagonal of by a Z-by-Z identity matrix and replacing the remaining elements by a Z-by-Z zero matrix, where m G = Z*M G am.

[0283] In relation to Fig. 38 or Fig. 39, B G Each of the N columns is floor(N / M) based on a predetermined column index sequence. G ) containing M columns G It can contain sets of ten, B G M of G Each of the dog rows is the M G Each column in a different set of columns among the sets of columns may contain integers representing a Z-by-Z matrix that is not a Z-by-Z zero matrix.

[0284] In relation to Fig. 38 or Fig. 39, B G M of G Each of the dog rows is the M G Each of the remaining columns, excluding the corresponding column set among the sets of dog columns, may contain an integer representing a Z-by-Z zero matrix.

[0285] With respect to FIG. 38 or FIG. 39, the predetermined column index sequence is B G It can be based on the number of decoding iterations required to determine the bit values ​​for each of the bits corresponding to the N columns above.

[0286] With respect to FIG. 38 or FIG. 39, the predetermined column index sequence is B in ascending or descending order of the number of iterations, starting from the column index of the column with the fewest number of decoding iterations required to determine the corresponding bit value. G It may be identical to the sequence obtained by sorting the N column indices.

[0287] In relation to Fig. 38 or Fig. 39, the above n L The dog information blocks are obtained from the transport blocks. L It could be a bunch of dog code blocks.

[0288] In relation to Fig. 38 or Fig. 39, the above n L Dog information blocks are n L n obtained by adding a CRC code to each of the dog code blocks L These may be dog CRC additional code blocks.

[0289] In relation to Fig. 38 or Fig. 39, the above n L Each of the dog information blocks is encoded based on the first matrix, and each of them has length n. L Determining the local codewords of the dog comprises: obtaining the first PCM by lifting the first matrix by a lifting factor Z; and L It may include encoding each of the dog information blocks with the first PCM.

[0290] As described above, the examples disclosed herein are provided to enable those skilled in the art to implement and practice the present disclosure. While the examples have been described above with reference to the examples of the present disclosure, those skilled in the art will appreciate that various modifications and variations may be made to the examples of the present disclosure. Accordingly, the present disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0291] Implementations of this specification may be used in wireless communication systems, base stations, user equipment, or other equipment.< / null> < / null>

Claims

1. In a method performed by a device, n L Determine the dog information blocks; above n L Each of the dog information blocks is encoded based on the first matrix, and each of them has length n. L Obtain local codewords; above n L length n*n based on local codewords L Obtain the first codeword; Encode the above first codeword based on the second matrix to have length n G Obtain the second codeword, where n G = n*n L + m G ; Determine the coded bits to be transmitted based on the second codeword; and Including transmitting the above coded bits, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, method.

2. In paragraph 1, P is size m G -by-m G The identity matrix of , method.

3. In paragraph 1, Replace each element of the above second matrix with a Z-by-Z matrix H Global Including further obtaining, The above second matrix has size M G -by-N G Matrix B Global = [BP B ], where m G = Z*M G , n G = Z*N G And, B= [B_1B_2 ...B_n L ] and B_1 =B_2 = ... =B_n L =B G And, B G is size size M G -by-N matrix, where n = Z*N, P B is size M G -by-M G is a diagonal matrix of , method.

4. In paragraph 3, P is P B is obtained by replacing each element in the diagonal of with a Z-by-Z identity matrix and replacing the remaining elements with a Z-by-Z zero matrix, where m G = Z*M G person, method.

5. In paragraph 3, B G Each of the N columns is floor(N / M) based on a predetermined column index sequence. G ) containing M columns G Includes ten sets of dogs, B G M of G Each of the dog rows is the M G Among the sets of dog columns, each column in a different set of columns contains an integer representing a Z-by-Z matrix that is not a Z-by-Z zero matrix. method.

6. In paragraph 3, B G M of G Each of the dog rows is the M G In each of the remaining columns of the dog column sets, an integer representing a Z-by-Z zero matrix is included, method.

7. In paragraph 5, The above predetermined column index sequence is B G Based on the number of decoding iterations required to determine the bit values for each of the bits corresponding to the N columns above, method.

8. In paragraph 7, The above predetermined column index sequence is ordered in ascending or descending order of the number of decoding iterations, starting from the column index of the column with the fewest number of decoding iterations required to determine the corresponding bit value. G The sequence obtained by sorting the N column indices is identical to that of method.

9. At least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: n L Determine the dog information blocks; above n L Each of the dog information blocks is encoded based on the first matrix, and n of length n L Obtain local codewords; above n L Each of the length n*n is based on the local codewords L Obtain the first codeword; Encode the above first codeword based on the second matrix to have length n G Obtain the second codeword, where n G = n*n L + m G ; Determine the coded bits to be transmitted based on the second codeword; and Including transmitting the above coded bits, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, machinery and tools.

10. A computer-readable non-transitory storage medium storing at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, wherein the operations are: At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: n L Determine the dog information blocks; above n L Each of the dog information blocks is encoded based on the first matrix, and n of length n L Obtain local codewords; above n L Each of the length n*n is based on the local codewords L Obtain the first codeword; Encode the above first codeword based on the second matrix to have length n G Obtain the second codeword, where n G = n*n L + m G ; Determine the coded bits to be transmitted based on the second codeword; and Including transmitting the above coded bits, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, Storage media.

11. In a method performed by a device, Receive coded bits associated with the second codeword; and Decoding is performed based on the first and second matrices for the above coded bits, n L Including determining the dog information blocks, The second codeword is obtained through encoding based on the second matrix for the first codeword, The above first codewords are each n of length n L It is obtained based on the local codewords of the dog, above n L The local codewords are n L Each of the dog information blocks is obtained by encoding based on the first matrix, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, method.

12. At least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: Receive coded bits associated with the second codeword; and Decoding is performed based on the first and second matrices for the above coded bits, n L Including determining the dog information blocks, The second codeword is obtained through encoding based on the second matrix for the first codeword, The above first codewords are each n of length n L It is obtained based on the local codewords of the dog, above n L The local codewords are n L Each of the dog information blocks is obtained by encoding based on the first matrix, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, machinery and tools.

13. A computer-readable non-transitory storage medium storing at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, wherein the operations are: At least one computer memory operably connectable to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: Receive coded bits associated with the second codeword; and Decoding is performed based on the first and second matrices for the above coded bits, n L Including determining the dog information blocks, The second codeword is obtained through encoding based on the second matrix for the first codeword, The above first codewords are each n of length n L It is obtained based on the local codewords of the dog, above n L The local codewords are n L Each of the dog information blocks is obtained by encoding based on the first matrix, The above second matrix has size m G -by-n G Parity check matrix H Global = [AP] is related, where P is of size m G -by-m G is the matrix of, A= [A_1A_2 ...A_n L ] and A_1 =A_2 = ... =A_n L =A G And, A G is size m G -by-n matrix, Storage media.

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