Light emitting device with continuous regrowth layer and method for manufacture

Abstract

The invention concerns a light emitting device, in particular µLED array, comprising a semiconductor layer stack of at least a first layer of a first conductivity type, a second layer of a second conductivity type, and an active region comprising at least one quantum well arranged between the first and the second layer and being configured to emit light of a first wavelength. The semiconductor layer stack further comprises a top surface, a bottom surface opposite the top surface and at least one first side surface extending from the top surface into the direction of the bottom surface and laterally confining at least one light emitting portion of the semiconductor layer stack. In addition, the light emitting device comprises at least one continuous regrowth layer, in particular comprising at least one sub layer of the second conductivity type, with the regrowth layer covering the at least one first side surface and at least a portion of the top surface. The at least one first side surface is characterized that it comprises the second layer, the active region and at least 70% and in particular at least 90% of the thickness of the first layer.

Description

[0001] LIGHT EMITTING DEVICE WITH CONTINUOUS REGROWTH LAYER AND METHOD FOR

[0002] MANUFACTURE

[0003] The present application claims priority from German patent application DE 10 2024 104 027 . 0 filed on February 14 , 2024 , the disclosure of which is incorporated by way for reference in its entirety .

[0004] The present invention concerns a light emitting device , in particular pLED array, comprising a continuous regrowth layer extending along side surfaces of the light emitting device . In addition, the invention concerns a method for manufacturing such a light emitting device .

[0005] BACKGROUND pLEDs are light emitting devices that comprise a lateral dimension in the range from a few pm to about 40 pm. Such devices provide a variety of different applications , including but not limited to displays . pLED arrays on the other hand can for example be an array of a plurality of light emitting structures / portions each forming a pLED that comprise a lateral dimension in the range of a few pm that are arranged on a common semiconductor substrate , in particular connected by a common semiconductor layer of a semiconductor layer stack out of which they are pixelized .

[0006] In order to increase the external quantum efficiency ( EQE ) of for example pLEDs , or more general light emitting nanostructures , one can engineer the geometry, shape and surroundings (passivation, reflective mirror, ...) of the pLEDs in a way that the light extraction efficiency (LEE ) in a specific solid angle is maximized . Apart from the LEE the internal quantum efficiency ( IQE ) is as important , where a main loss factor originates from non-radiative recombination (NRR) of charge carriers within the pLED .

[0007] In particular pLEDs based on an InGaAlP material system suffer from decreasing performance with smaller size . A reason for this efficiency drop can be NRR of inj ected charge carriers at etched surfaces . For example , etching is a common and standard process for pixel etching ( etching through the active region and physical separation of individual pixels ) , that introduces damage to the surface and underlying layers dependent on the specific process and parameters used . Damage in this case means the creation of defect centres in the crystal lattice of the etched structure . Defects created on the surface and below of the active region - which is exposed during and after pixel etching - act as non-radiative recombination channels which in combination with NRR occurring anyhow for some material systems at the outer surfaces of the pLED dramatically reduce the IQE of the pLED leading to a bad overall performance . This effect is particularly pronounced for the InGaAlP material system due to its long charge carrier diffusion length and surface recombination velocities , as well as Fermi level pinning at the semiconductor surface . Especially for small pixels such as for the case of pLEDs with a high surface-to- volume ratio , in particular a high ratio of the exposed active region surface on the pixel ' s sidewall vs . the total active region volume , this is a maj or challenge .

[0008] To reduce non-radiative recombination at the edges of a pLED, a possible approach is a passivation of the pLED surface by, e . g . , dielectrics . However , by this the performance cannot be improved significantly and in a desired way . A further approach to reduce non-radiative recombination at the side surfaces of a pLED is to keep the charge carriers away from the side surfaces which comprise the non-radiative recombination centres . This can for example be done by quantum well intermixing the active regions in areas along the side surfaces of the pLED by means of which a respective dopant is diffused into the vicinity of the active region causing the bandgap of the active region along the side surfaces to enlarge due to intermixing processes . By this , charge carriers can be kept away from the side surfaces which comprise the non-radiative recombination centres . However, such an approach is limited for pLED sizes larger than several micrometres , as the intermixing resolution is insufficient for pLEDs in the micrometre size .

[0009] Another approach is a so-called epitaxial regrowth . After a first epitaxially growth step, including the active region, the epitaxially grown layers including the active region are structured and locally etched away where the later pLED side surfaces will be formed . This etching is realized ex-situ by dry or wet etching , or in-situ by Cl- containing vapor within the epi reactor . Using this approach, structured active regions in the micrometre range are possible . Then, a second epitaxially growth step with higher bandgap material is conducted over the whole structure , leading to an overgrowth of the non-etched islands as well as the etched regions . By this , some of the defects at the etched surface are passivated due to the similarity of the materials comprised in the active region and the regrown layers . Furthermore , like in the intermixing approach, charge carriers are blocked by high energy barriers to prevent diffusion to the pixel side surfaces .

[0010] However , because of a later definition of the later pLED, a further etching step is need for the separation of individual light emitting structures . This second etching step in particular also through the epitaxially regrown layer leads to an increased leakage at the etched sidewalls , in particular in an area of the epitaxially regrown layer and significantly decreases the pLEDs ' efficiency . Although it is possible to passivate this area by damage etching and / or application of a dielectric material , the efforts made are not sufficient to counteract a reduction in efficiency to a sufficient extent or are increasing the cost for manufacture to such an extend such that they are commercially not of interest .

[0011] The aim of the present application is therefore to provide a light emitting device which overcomes at least some of the aforementioned aspects , as well as to provide a method for manufacturing such a light emitting device .

[0012] SUMMARY OF THE INVENTION

[0013] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims . The inventors found that by growing an epitaxial passivation layer / regrowth layer along the entire side surfaces of a light-emitting portion of a light-emitting device after exposing the side surfaces of an active area of the portion and after structuring the light-emitting portion itself , leakage within the light-emitting device can be drastically reduced and the cost of manufacturing can be lowered . By this in addition a position of etching through the regrowth layer for for example final separation of the device can be shifted away from the active region as far as possible to a region where it does not significantly influence the efficiency of the device .

[0014] Advantages that may result from the proposed concept are a more effective passivation of the etched sidewalls , as an epitaxial passivation is more effective than a dielectric passivation . In addition due to a single epitaxial passivation step cost can be significantly reduced compared to several separate passivation steps .

[0015] According to a first aspect , a light emitting device , in particular pLED array, comprising a semiconductor layer stack is provided . The semiconductor layer stack comprises at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region comprising at least one quantum well arranged between the first and the second layer . The active region is thereby configured to emit light of a first wavelength . In particular the active region of the semiconductor layer stack comprises at least one quantum well , however the active region can also comprise a multi quantum well structure comprising several quantum wells .

[0016] The semiconductor layer stack comprises a top surface , a bottom surface opposite the top surface and at least one first side surface extending from the top surface into the direction of the bottom surface . The at least one first side surface thereby in particular laterally confines at least one light emitting portion of the semiconductor layer stack, which in the later light emitting device is configured to emit light of the first wavelength . The at least one first side surfaces extends from the top surface through the semiconductor layer stack such that it comprises at least the second layer, the active region and at least 70% and in particular at least 90% of the thickness of the first layer . For example , the at least one side surface can result from a step of structuring the semiconductor layer stack thereby removing a portion of the semiconductor layer stack and remaining another portion of the semiconductor layer stack, in particular the at least one light emitting portion . The at least one side surface can be a therefrom resulting side surface of the remained portion . In particular the at least one side surface can result from an etching step for structuring the semiconductor layer stack resulting in an etched side surface extending at least through the second layer , the active region and at least 70% and in particular at least 90% of the thickness of the first layer .

[0017] The light emitting device further comprises at least one continuous regrowth layer , in particular comprising at least one sub layer of the second conductivity type , arranged on the at least one side surface and covering at least a portion of the top surface . By means of the regrowth, layer defects created at the side surface can be passivated due to the similarity of the materials comprised in the active region and the regrown layers . In addition, by means of the regrowth layer charge carriers can be blocked by high energy barriers to prevent diffusion to the side surfaces .

[0018] The idea is that the regrowth layer extends continuously along the at least one first side surface and thus along the whole thickness of the second layer and the active region as well as along at least 70% and in particular at least 90% of the thickness of the first layer . This is to be understood independent of the at least one first side surface comprising a continuous portion or several laterally displaced portions . By means of continuously or continuous it is to be understood that the regrowth layer extends along the at least one first side surface in one piece in the direction extending along the at least one side surface and in particular results of s single regrowth step ( at least for each sublayer of the regrowth layer ) . In contrast a pieced together regrowth layer resulting from several regrowth steps is to be understood as not continuous . According to some aspects , the semiconductor layer stack is of an InGaAlP or InGaAlAs material system . For example the semiconductor layer stack can be of an Al and / or In containing semiconductor material system. For example , the semiconductor layer stack can be of a material system comprising Indium ( In) and Aluminium (Al ) and Gallium ( Ga ) and Arsenide (As ) and / or Phosphide ( P ) . The semiconductor layer stack can however also be of any other semiconductor material system.

[0019] According to some aspects , the active region comprises a multi quantum well structure . The quantum wells can thereby be substantially equal in size and / or composition, can however also vary between each other . The at least two quantum wells can for example comprise a substantially equal effective bandgap and can in particular be configured to emit light of a substantially equal wavelength .

[0020] According to some aspects , the regrowth layer and in particular a sublayer of the regrowth layer is of the second conductivity type . By means of the regrowth layer some of the defects created at the at least one first side surface are passivated due to the similarity of the materials comprised in the active region and the regrown layers . In addition, by means of the regrowth layer charge carriers can be blocked by high energy barriers to prevent diffusion to the side surfaces . Therefore , the regrowth layer is in particular of the second conductivity type electrically coupled to a potential applied to the second layer . By this NRR can be reduced within the active region .

[0021] According to some aspects , the first conductivity type is a n-type and the second conductivity type is a p-type . The first layer can thus be a n-type semiconductor layer and the second layer can be a p-type semiconductor layer .

[0022] According to some aspects , the at least one first side surface comprises at least a first and a second side surface portion being laterally displaced to each other, wherein the first side surface portion is directly adj acent to the top surface . The first side surface portion thereby comprises at least the second layer and the active region whereas the second side surface portion comprises a portion of "only" the first layer . The first and second side surface portion can together in particular comprise at least 70% and in particular at least 90% of the thickness of the first layer . The first and the second side surface portion can in particular be connected by a substantial horizontal intermediate side surface portion . For example the first side surface portion can result from a first etching step whereas the second side surface portion can result from a second etching step laterally displaced from the first etching step .

[0023] According to some aspects , the semiconductor layer stack comprises at least one second side surface being arranged directly adj acent to the at least one first side surface and being laterally displaced to the at least one first side surface . The at least one second side surface can in particular result from a further etching step laterally displaced to an etching step ( s ) resulting in the at least one first side surface . The at least one first side surface and the at least one second side surface can in particular be connected by a substantial horizontal intermediate side surface portion . The at least one second side surface extends from the at least one first side surface through the first layer until the bottom surface or close to the bottom surface . By means of the at least one second side surface the at least one light emitting portion of the semiconductor layer stack can further be confined separating the at least one light emitting portion from remaining portions of the semiconductor layer stack . The at least one side surface comprises a portion of the first layer and in particular extends from the first side surface to the bottom surface . However , the at least one second side surface is in particular free of the at least one continuous regrowth layer . This can in particular result as the further etching step resulting in the at least one second side surface can be conducted after a regrowth of the regrowth layer on the at least on the first side surface . The further etching step can thus be conducted etching through the regrowth layer as well as exposing the at least one second side surface of the semiconductor layer sack .

[0024] According to some aspects , a first contact layer is arranged on the bottom surface electrically contacting the first layer of the at least one light emitting portion of the semiconductor layer stack . According to some aspects , a second contact layer is arranged on the at least one continuous regrowth layer opposite the top surface electrically contacting the second layer of the at least one light emitting portion of the semiconductor layer stack . In particular the first contact layer can be electrically conductive n-type contact layer, whereas the second contact layer can be electrically conductive p-type contact layer . The first and second contact layer can thereby of the same material system as the semiconductor layer stack but can also be contact layers comprising a metal and / or a transparent conductive oxide (TCO ) such as for example indium tin oxide ( ITO ) . By means of the first and second contact layer a first and a second potential can be applied to the light emitting device to operate the light emitting device in a desired manner . For example the first contact layer can be of a TOO whereas the second contact layer can be metallic .

[0025] According to some aspects , the light emitting device further comprises a dielectric layer arranged on at least one of the following : on the at least one continuous regrowth layer opposite the at least one first side surface ; on the at least one continuous regrowth layer opposite the top surface , in particular exposing a contact portion for the second contact layer ; between the at least one continuous regrowth layer opposite the top surface and a second contact layer electrically contacting the second layer of the at least one light emitting portion of the semiconductor layer stack; and on the at least one second side surface .

[0026] The dielectric layer can in particular cover any side surfaces of the semiconductor layer stack not covered by the regrowth layer . In addition the dielectric layer can in some embodiments provide an electric isolation between the first and second contact layer .

[0027] According to some aspects , the light emitting device comprises a reflective contact layer arranged on the dielectric layer electrically contacting the second contact layer . The reflective contact layer together with the second contact layer can form a mirror , for example parabolic-like or parabolic mirror , for light generated in the semiconductor layer stack . By means of the combined mirror, light generated within the semiconductor layer stack can be outcoupled of the light emitting device through the bottom surface in an enhanced way, as well as a focusing of the light into a smaller solid angle is possible .

[0028] According to some aspects , the reflective contact layer comprises a through contact through the dielectric layer electrically contacting the second contact layer . The through contact can in particular be substantially centred with respect to the at least one light emitting portion or can for example due to manufacturing inaccuracies be off centred with respect to the at least one light emitting portion .

[0029] According to some aspects , the light emitting device comprises a top contact element electrically coupled to the first layer and the first contact layer respectively, wherein optionally the top contact element is of a reflective material and surrounds the at least one light emitting portion of the semiconductor layer stack in a circumferential direction . The top contact element can for example be a metallic grid surrounding the at least one light emitting portion in the circumferential direction . The top contact element can in particular be in form of a metallic grid comprising an element surrounding the semiconductor layer stack in the circumferential direction . Due to its conductivity, the metallic grid can together with the first contact layer and the reflective contact layer and second contact layer respectively in particular be used to electrically connect the at least one light emitting portion to a current source .

[0030] According to some aspects , the at least one continuous regrowth layer comprises a thinner thickness in an area of covering the at least one first side surface , in particular in an area of covering the second side surface portion, than in an area of covering the top surface and in particular than in an area of covering the top surface and the first side surface portion . By for example changing the slope of the at least on first side surface or the first and second side surface portion respectively the thickness of the regrowth layer can be varied along its main extension direction . In addition, by means of varying a distance between opposing first side surfaces or the first and second side surface portion respectively the thickness of the regrowth layer can be varied along its main extension direction as well . In particular by means of changing the thickness of the regrowth layer the resistance of the regrowth layer can be varied to prevent creating a short within the light emitting device by means of the regrowth layer .

[0031] According to some aspects , the light emitting device is a pLED array with the semiconductor layer stack comprising a plurality of first side surfaces laterally confining a plurality of light emitting portions of the semiconductor layer stack being arranged adj acent to each other . The light emitting portions can be arranged on a common carrier substrate , in particular semiconductor substrate . In some aspects , the common carrier substrate can be formed by a continuous residue of the first layer .

[0032] According to some aspects , the light emitting portions are separated by a plurality of gaps extending through the semiconductor layer stack . The gaps are thereby forming the first side surfaces and in particular the second side surface portions separating the plurality of light emitting portions in lateral direction . The gaps can in particular extend through the semiconductor layer stack from the top surface through the second layer, the active region and at least 70% and in particular at least 90% of the thickness of the first layer .

[0033] According to some aspects , between two adj acent light emitting portions of the semiconductor layer stack, a spacer portion of the semiconductor layer stack is arranged . The spacer portion thereby comprises at least a portion of the first layer . By means of the spacer portion a lateral distance between adj acent light emitting portions can be increased to reduce cross talk between adj acent light emitting portions . In particular, the light emitting portions can be formed by an individual gap surrounding a single light emitting portion not sharing the gap with an adj acent light emitting portion . Hence portions of the semiconductor layer stack between two adj acent light emitting portions remain forming the spacer portion . According to some aspects , the spacer portion is configured to not emit light when operating the light emitting device . This can in particular be achieved by removing the active region withing the spacer portion, for example by etching away at least the second layer and the active region of the spacer portion . The spacer portion not emitting light can however also be achieved by not connecting the spacer portion to a current source or disconnecting the spacer portion from at least one potential .

[0034] According to some aspects , wherein the spacer portion comprises a thickness of more than 30% of the thickness of the first layer . In particular the spacer potion can comprise a thickness that is greater than the depth of the at least one side surface . In particular , a distance from the bottom surface to a top surface of the spacer portion can be larger than a distance from the bottom surface to an adj acent edge of the at least one first side surface .

[0035] According to a further aspect , a method for manufacturing a light emitting device is provided . The method can in particular be a method for manufacturing a light emitting device according to at least some of aforementioned aspects . Hence all aspects already described for the light emitting device can in the same way be applied to the method for manufacturing the same .

[0036] The method comprises at least the following step :

[0037] Providing a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type , and an active region comprising at least one quantum well arranged between the first and the second layer and being configured to emit light of a first wavelength;

[0038] Structuring the semiconductor layer stack thereby remaining at least one first portion of the semiconductor layer stack and removing a second portion of the semiconductor layer stack adj acent to the at least one first portion, resulting in at least one first side surface of the at least one first portion comprising the second layer , the active region and at least 70% and in particular at least 90% of the thickness of the first layer; and Regrowing at least one regrowth layer , in particular comprising at least one sub layer of the second conductivity type , on the at least one first side surface and at least a portion of the top surface . According to some aspects the step of structuring the semiconductor layer stack comprises : a first step of mesa etching the semiconductor layer stack, in particular a wet etching step, resulting in a first surface portion of the at least one side surface adj acent to the top surface and comprising at least the second layer and the active region; and a second step of mesa etching the semiconductor layer stack, in particular a dry etching step , resulting in a second surface portion of the at least one side surface comprising a portion of the first layer .

[0039] The first and the second mesa etching step are thereby conducted in such that the first and the second side surface portion are laterally displaced to each other, and in particular the first and the second mesa etching step are conducted at laterally displaced positions .

[0040] According to some aspects the step of structuring the semiconductor layer stack comprises a third step of mesa etching the semiconductor layer stack, in particular a wet etching step , resulting in at least one second side surface adj acent to the at least one first side surface . The third mesa etching is thereby conducted such that the at least one first side surface and the at least one second side surface are laterally displaced to each other and in particular the third mesa etching step is conducted at a laterally displaced position compared to the structuring resulting in the at least one first side surface . The resulting at least one second side surface comprises a portion of the first layer and in particular extends from the first side surface to the bottom surface or through the first layer until close to the bottom surface . By means of the third etching step in particular a further confinement of a light emitting portion of the semiconductor layer stack can be achieved further separating the light emitting portion from other portions of the semiconductor layer stack .

[0041] According to some aspects the step of regrowing the regrowth layer is conducted before the third step of mesa etching the semiconductor layer stack . Hence the third etching step can in particular be conducted after the step of regrowing the regrowth layer on the at least one side wall . By this the third etching step can in particular be conducted to etch through the regrowth layer before etching into the first layer exposing the at least one second side surface .

[0042] According to some aspects the method further comprises a step of providing a dielectric layer on at least one of the following : on the at least one regrowth layer opposite the at least one first side surface ; on the at least one regrowth layer opposite the top surface , in particular exposing a contact portion for a second contact layer , the second contact layer being electrically coupled to the second layer of the at least one light emitting portion of the semiconductor layer stack; between the at least one continuous regrowth layer opposite the top surface and a second contact layer electrically contacting the second layer of the at least one light emitting portion of the semiconductor layer stack; and on the at least one second side surface .

[0043] The dielectric layer can in particular cover any side surfaces of the semiconductor layer stack not covered by the regrowth layer . In addition, the dielectric layer can in some embodiments provide an electric isolation between a first contact layer provided on the bottom surface electrically contacting the first layer and a second contact layer provided on the regrowth layer electrically contacting the second layer .

[0044] SHORT DESCRIPTION OF THE DRAWINGS

[0045] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which Figures 1A to IE show steps of a method for manufacturing a light emitting device in accordance with some aspects of the proposed principle ;

[0046] Figure 2 shows an embodiment of a light emitting device in accordance with some aspects of the proposed principle ;

[0047] Figure 3 shows another embodiment of a light emitting device some in accordance with some aspects of the proposed principle ;

[0048] Figure 4 shows a further embodiment of a light emitting device some in accordance with some aspects of the proposed principle ;

[0049] Figures 5A and 5B show further embodiments of a light emitting device some in accordance with some aspects of the proposed principle ; and

[0050] Figure 6 shows further embodiments of a light emitting device some in accordance with some aspects of the proposed principle .

[0051] DETAILED DESCRIPTION

[0052] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea . In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0053] Figures 1A to IE show steps of a method for manufacturing a light emitting device 1 in accordance with some aspects of the proposed principle . In a first step , shown in Figure 1A, a semiconductor layer stack 2 is provided . The semiconductor layer stack 2 comprises a first layer 3 of a first conductivity type , an active region 5 comprising one or more quantum wells and a second layer 4 of a second conductivity type . On a bottom surface 11b of the semiconductor layer stack 2 a first contact layer 8 , of for example a TOO , is provided .

[0054] The first conductivity type is thereby in particular an n-type and the second conductivity type is a p-type . The first layer 3 can thus be a n-type semiconductor layer and the second layer 4 can be a p-type semiconductor layer . The active region 5 and in particular the quantum well ( s ) included therein can in particular be configured to emit light of a first wavelength when provided with a respective supply current .

[0055] The semiconductor layer stack 2 is then structured starting from a top surface I la opposite the bottom surface 11b thereby remaining a first portion 17a of the semiconductor layer stack 2 and removing a second portion 17b of the semiconductor layer stack 2 adj acent to the first portion 17a . This structuring results in exposed side surface portions of the first layer 3 , the active region 5 and the second layer 4 resulting in first side surface portions 12a .

[0056] In a further step , as shown in Figure IB, a second structuring is conducted deeper into the first layer 3 thereby remaining the first portion 17a of the semiconductor layer stack 2 and removing the second portion 17b of the semiconductor layer stack 2 adj acent to the first portion 17a . This structuring results in exposed side surface portions of the first layer 3 resulting in second side surface portions 12b .

[0057] The structuring of Fig . 1A and IB in particular comprises two steps of mesa etching the semiconductor layer stack 2 , in particular a wet etching and a subsequent dry etching of the semiconductor layer stack 2 , resulting in first side surfaces 11c comprising a first and a second side surface portion 12a , 12b laterally displaced to each other . The first etching step is thereby provided to structure a core portion of a light emitting portion 6 of the semiconductor layer stack confining the active region 5 of the light emitting portion 6 . The second etching step on the other hand is provided to pixel a light emitting portion 6 of the semiconductor layer stack 2 e . g . spatially separate the light emitting portion 6 from other light emitting portions 6 or other portions of the semiconductor layer stack 2 .

[0058] The first etching step is thereby conducted until a depth so that at least the second layer 4 and the active region 5 are confined by the first side surface portions 12a . The second etching step is on the other hand conducted until a depth, such that at most 30% and in particular at most 10% of the thickness of the first layer 3 remain unetched / continuous .

[0059] In a further step , as shown in Figure 1C, a regrowth layer 16 is grown on the resulting structure and in particular at least on the first side surfaces 11c and the top surface Ila . By means of the regrowth layer 16 defects at the etched side surfaces can be passivated and charge carriers can be blocked by high energy barriers to prevent diffusion from the core of the active region of a light emitting portion 6 to the first side surfaces 11c . Therefore , the regrowth layer 16 is in particular of the second conductivity type or at least comprise a sub layer of the second conductivity type electrically connected to a potential applied to the second layer 4 . By this NRR can be reduced within the active region .

[0060] The core here is to provide the regrowth layer 16 as a continuous layer throughout the whole structure and in particular throughout the whole first side surfaces 11c at the same time . By this all etched side surfaces / side surface portions are equally passivated and no or at least hardly any leakage paths can occur .

[0061] In a further step , as shown in Figure ID, a dielectric layer 15 is provided throughout the whole structure and in particular covering the whole regrowth layer 16 . The dielectric layer 15 thereby serves to passivate the regrowth layer 16 as well as to prevent shorts within the later light emitting device . Then, a second contact layer 9 is provided on the underlying structure , in particular a second contact layer 9 of a semiconductor material of the second conductivity type or a metal . The second contact layer 9 comprises a through contact through the dielectric layer 15 electrically contacting the regrowth layer 16 in an area opposite the top surface I la . The second contact layer 9 can in particular act as a current spreading layer for a potential applied to the second contact layer 9 .

[0062] The structure is then, as shown in Figure ID, embedded in a reflective contact layer 10 to provide a bottom side reflector for the light emitting device 1 with desired optical properties . Said reflective contact layer 10 is arranged on the dielectric layer 15 following the underlying structure 16 and electrically contacting the second contact layer 9 . The reflective contact layer 10 can be a metallic layer following the underlying structure and forming a bottom side reflector for the light emitting device 1 to guide the light generated within the semiconductor layer stack 2 into a desired direction and with a desired beam profile .

[0063] The reflective contact layer 10 in particular forms a substantially even surface on a surface opposite the semiconductor layer stack 2 on which a carrier substrate 18 is arranged . The carrier substrate 18 can for example be or comprise an integrated circuit for controlling the light emitting device 1 and can thus for example be electrically connected ( not shown) to the reflective contact layer 10 by means of electric contact ( s ) . On the first contact layer 8 , a top contact element 14 is arranged being electrically coupled to the first contact layer 8 and the first layer 3 respectively, wherein the top contact element 14 is of a reflective material forming in addition a reflective structure and surrounding the semiconductor layer stack 2 and in particular a light emitting portion 6 of the semiconductor layer stack 2 in a circumferential direction U .

[0064] The top contact element 14 exposes a portion of the first contact layer 8 opposite the top surface Ila to form a light emitting window for the light emitting portion 6 . In the embodiments shown, the top contact element 14 is arranged on the first contact element 8 but it can also be arranged on the top surface Ila or can be embedded in the first layer 3 but only until a depth to not be in contact with the regrowth layer 16 or the reflective contact layer 10 to avoid a short within the light emitting device 1 . The top contact element 14 provides a reflector surrounding the light emitting portion 6 of the semiconductor layer stack 2 in the circumferential direction U, to reflect light generated within the semiconductor layer stack 2 into a desired direction . The top contact element 14 in addition can be used to electrically contact the first contact layer 8 and the first layer 3 respectively, on / in which the top contact element 14 is arranged .

[0065] The top contact element 14 together with the reflective contact layer 10 forms a mirror , in particular parabolic-like or parabolic mirror , for light generated in the semiconductor layer stack 2 . By means of the combined mirror , light generated within the semiconductor layer stack 2 can be outcoupled of the light emitting device 1 in an enhanced way, as well as a focusing of the light into a smaller solid angle is possible .

[0066] The top contact element 14 can be a metallic grid surrounding the light emitting portion 6 of the semiconductor layer stack 2 in the circumferential direction U . The top contact element 14 can in particular be in form of a metallic grid comprising an element surrounding the light emitting portion 6 of the semiconductor layer stack 2 in the circumferential direction U and comprising bars or residues of bars connecting elements surrounding the light emitting portion 6 of the semiconductor layer stack 2 in the circumferential direction U . Due to its conductivity, the metallic grid can together with the second contact element 9 and the reflective contact layer 10 be used to electrically connect the light emitting portion 6 of the semiconductor layer stack 2 to a current source .

[0067] Figure 2 shows a further embodiment of a light emitting device 1 in accordance with some aspects of the proposed principle . The embodiment shown in Fig . 2 is not embedded in a reflective contact layer 10 or provided with a top contact element 14 but can be in the same way as shown in Fig . IE . The embodiment shown in Fig . 2 differs to that one shown in Fig . ID in that the second portion 17b being removed when structuring the semiconductor layer stack 2 is smaller resulting in narrower gaps 13 separating the light emitting portion 6 from the remaining portions of the semiconductor layer stack 2 . By means of this , the thickness of the regrowth layer 16 on the first side surfaces 11c can be varied, as when growing the regrowth layer 16 less material accumulates in the narrower gaps and thus the growing speed on the first side surfaces 11c and areas between opposing side surfaces 11 is reduced . By this an addressability of the light emitting portion 6 can be improved as current leakage paths between neighbouring light emitting portions 6 can be suppressed by thinning possible current leakage paths .

[0068] Figure 3 shows a further embodiment of a light emitting device 1 in accordance with some aspects of the proposed principle . In Figure 3 the light emitting device 1 shown comprises several light emitting portions 6 being formed of the semiconductor layer stack 2 . The number of two light emitting portions 6 is however to be understood as exemplary and the light emitting device 1 can in particular comprise several light emitting portions 6 arranged in an array like pattern for example . In addition, between the light emitting portions 6 , the semiconductor layer stack 2 comprises a spacer portion 7 . The spacer portion 7 thereby comprise a portion of the first layer 3 and is configured to not emit light by removing the second layer 4 and the active region 5 . By means of the spacer portion 7 a lateral distance between adj acent light emitting portions 6 can be increased to reduce cross talk between adj acent light emitting portions 6 . In particular, the light emitting portions 6 can be formed by an individual gap 13 surrounding a single light emitting portion 6 not sharing the gap 13 with an adj acent light emitting portion 6 . Hence portions of the semiconductor layer stack 2 between two adj acent light emitting portions 6 remain forming the spacer portion 7 . In addition, by means of the spacer portion 7 , possible current leakage paths between adj acent light emitting portions 6 are reduced due to an increased distance between adj acent light emitting portions 6 in combination with for example thinning the regrowth layer 16 between adj acent light emitting portions 6 . Hence an addressability of the light emitting portion 6 can be improved .

[0069] In the embodiment shown, the spacer portion 7 comprises a height relating to the height resulting from a first etching step to expose the first side surface portions 12a, whereas the second etching step to expose the second side surface portions 12b results in the gaps 13 exposing the light emitting portions 6 and the spacer portion 7 . The structure shown is however to be understood as exemplary and the height of the spacer portion as well as the distance between adj acent light emitting portions 6 can vary in a desired way .

[0070] Figures 4 to 5B show further embodiments of a light emitting device 1 according to some aspects of the proposed principle . In the embodiments shown, a further etching step, for example wet etching step , has been conducted etching through the regrowth layer 16 and into or through the remained continuous portion of the first layer 3 . The further etching steps results in second side surfaces lid further separating light emitting portions 6 from other portions of the semiconductor layer stack 2 . In case of several light emitting portions 6 being arranged adj acent to each other , such a measure can prevent / reduce cross talk between adj acent light emitting portions 6 . In addition, due to the first side surface 11c extending through at least 70% and in particular at least 90% of the thickness t of the first layer 3 , an etching through the regrowth layer 16 and thus possible defects in this area can be shifted away from the active region 5 as far as possible to reduce any possible leakage caused in this area .

[0071] Figure 6 shows a further embodiment of a light emitting device 1 according to some aspects of the proposed principle . In the embodiment shown in Figure 6 , the first side surface 11c results from a single etching step exposing the side surface portions of the active region 5 as well as separating the light emitting portion 6 from other portions of the semiconductor layer stack 2 . The core here is that the etching extends from the top surface Ila through the second layer 4 , the active region 5 and at least 70% and in particular at least 90% of the thickness of the first layer 3 at a time resulting in a continuous first side surface 11c . The continuous first side surface 11c is then overgrown with the regrowth layer resulting in a continuous regrowth layer 16 covering the top surface I la and the fist side surfaces 11c .

[0072] However , the structure shown in Figure 6 can also be generated by means of two separate etching steps conducted at the same position, again resulting in a substantially continuous first side surface 11c that is then overgrown with the regrowth layer resulting in a continuous regrowth layer 16 covering the top surface Ila and the fist side surfaces 11c .

[0073] LIST OF REFERENCES

[0074] 1 light emitting device

[0075] 2 semiconductor layer stack

[0076] 3 first layer

[0077] 4 second layer

[0078] 5 active region

[0079] 6 light emitting portion

[0080] 7 spacer portion

[0081] 8 first contact layer

[0082] 9 second contact layer

[0083] 10 reflective contact layer

[0084] Ila top surface

[0085] 11b bottom surface

[0086] 11c first side surface lid second side surface

[0087] 12a , 12b side surface portion

[0088] 13 gap

[0089] 14 top contact element

[0090] 15 dielectric layer

[0091] 16 regrowth layer

[0092] 17a , 17b portion

[0093] 18 carrier substrate

[0094] U circumferential direction t thickness

Claims

CLAIMS1. Light emitting device (1) , in particular pLED array, comprising: a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type; a second layer (4) of a second conductivity type; and an active region (5) comprising at least one quantum well arranged between the first and the second layer (3, 4) and being configured to emit light of a first wavelength; a top surface (Ila) ; a bottom surface (11b) opposite the top surface (Ila) ; and at least one first side surface (11c) extending from the top surface (Ila) into the direction of the bottom surface (11b) and laterally confining at least one light emitting portion (6) of the semiconductor layer stack (2) ; and at least one continuous regrowth layer (16) , in particular comprising at least one sub layer of the second conductivity type, covering the at least one first side surface (11c) and at least a portion of the top surface (Ila) ; wherein the at least one first side surface (11c) comprises the second layer (4) , the active region (5) and at least 70% and in particular at least 90% of the thickness of the first layer (3) .

2. Light emitting device (1) according to claim 1, wherein the at least one first side surface (11c) comprises at least a first and a second side surface portion (12a, 12b) being laterally displaced to each other, wherein the first side surface portion (12a) is adjacent to the top surface (Ila) , and wherein the first side surface portion (12a) comprises at least the second layer (4) and the active region (5) .

3. Light emitting device (1) according to claim 1 or 2 ,wherein the semiconductor layer stack (2) comprises at least one second side surface (lid) adjacent to the at least one first side surface (11c) being laterally displaced to each other, wherein the at least one second side surface (lid) comprises a portion of the first layer (2) and in particular extends from the first side surface (11c) to the bottom surface (11b) , and wherein the at least one second side surface (lid) is in particular free of the at least one continuous regrowth layer (16) .

4. Light emitting device (1) according to any one of the preceding claims , wherein a first contact layer (8) is arranged on the bottom surface (11b) electrically contacting the first layer (3) of the at least one light emitting portion (6) of the semiconductor layer stack (2) .

5. Light emitting device (1) according to any one of the preceding claims , wherein a second contact layer (9) is arranged on the at least one continuous regrowth layer (16) opposite the top surface (Ila) electrically contacting the second layer (4) of the at least one light emitting portion (6) of the semiconductor layer stack (2) .

6. Light emitting device (1) according to any one of the preceding claims , further comprising a dielectric layer (15) that is arranged on at least one of the following: on the at least one continuous regrowth layer (16) opposite the at least one first side surface (lie) ; on the at least one continuous regrowth layer (16) opposite the top surface (Ila) , in particular exposing a contact portion for the second contact layer (9) ; and on the at least one second side surface (lid) .

7. Light emitting device (1) according to claim 6,further comprising a reflective contact layer (10) arranged on the dielectric layer (15) electrically contacting the second contact layer ( 9 ) .

8. Light emitting device (1) according to any one of the preceding claims , further comprising a top contact element (14) electrically coupled to the first layer (3) , wherein optionally the top contact element (14) is of a reflective material and surrounds the at least one light emitting portion (6) of the semiconductor layer stack (2) in a circumferential direction (U) .

9. Light emitting device (1) according to any one of the preceding claims , wherein the at least one continuous regrowth layer (16) comprises a thinner thickness in an area of covering the at least one first side surface (11c) , in particular in an area of covering the second side surface portion (12b) , than in an area of covering the top surface (Ila) and in particular than in an area of covering the top surface (Ila) and the first side surface portion (12a) .

10. Light emitting device (1) according to any one of the preceding claims , wherein the active region (5) comprises a multi quantum well structure .

11. Light emitting device (1) according to any one of the preceding claims , wherein the semiconductor layer stack (2) comprises a plurality of first side surfaces (11c) laterally confining a plurality of light emitting portions (6) of the semiconductor layer stack (2) .

12. Light emitting device (1) according to claim 11, wherein the light emitting portions (6) are separated by a plurality of gaps (13) extending through the semiconductor layer stack (2) , the gaps (13) forming the first side surfaces (11c) and in particular the second side surface portions (12b) .

13. Light emitting device (1) according to claim 11 or 12, wherein between two adjacent light emitting portions (6) of the semiconductor layer stack (2) , a spacer portion (7) of the semiconductor layer stack (2) is arranged, the spacer portion (7) comprising at least a portion of the first layer (3) .

14. Light emitting device (1) according to claim 13, wherein the spacer portion (7) is configured to not emit light when operating the light emitting device (1) .

15. Light emitting device (1) according to claim 13 or 14, wherein the spacer portion (7) comprises a thickness of more than 30% of the thickness of the first layer (3) .

16. Method for manufacturing a light emitting device (1) comprising the steps :Providing a semiconductor layer stack (2) of at least: a first layer (3) of a first conductivity type, a second layer (4) of a second conductivity type, and an active region (5) comprising at least one quantum well arranged between the first and the second layer (3, 4) and being configured to emit light of a first wavelength;Structuring the semiconductor layer stack (2) thereby remaining at least one first portion (17a) of the semiconductor layer stack (2) and removing a second portion (17b) of the semiconductor layer stack (2) adjacent to the at least one first portion (17a) , resulting in at least one first side surface (11c) of the at least one first portion (17a) comprising the second layer (4) , the active region (5) and at least 70% and in particular at least 90% of the thickness of the first layer (3) ; andRegrowing at least one regrowth layer (16) , in particular comprising at least one sub layer of the second conductivity type, on the at least one first side surface (11c) and at least a portion of the top surface (Ila) .

17. Method according to claim 16,wherein the step of structuring the semiconductor layer stack (2) comprises : a first step of mesa etching the semiconductor layer stack (2) , in particular wet etching step, resulting in a first surface portion (12a) of the at least one side surface (11c) adjacent to the top surface (Ila) and comprising at least the second layer (4) and the active region (5) ; and a second step of mesa etching the semiconductor layer stack (2) , in particular dry etching step, resulting in a second surface portion (12b) of the at least one side surface (11c) comprising a portion of the first layer (3) ; wherein the first and the second side surface portion (12a, 12b) are laterally displaced to each other.

18. Method according to claim 17, wherein the step of structuring the semiconductor layer stack (2) comprises a third step of mesa etching the semiconductor layer stack (2) , in particular wet etching step, resulting in at least one second side surface (lid) adjacent to the at least one first side surface (lie) ; wherein the at least one first side surface (11c) and the at least one second side surface (lid) are laterally displaced to each other; and wherein the at least one second side surface (lid) comprises a portion of the first layer (2) and in particular extends from the first side surface (11c) to the bottom surface (11b) .

19. Method according to claim 17, wherein the step of regrowing is conducted before the third step of mesa etching the semiconductor layer stack (2) .

20. Method according to any one of claims 16 to 19, further comprising a step of providing a dielectric layer (15) on at least one of the following: on the at least one regrowth layer (16) opposite the at least one first side surface (lie) ;on the at least one regrowth layer (16) opposite the top surface (Ila) , in particular exposing a contact portion for a second contact layer (9) ; and on the at least one second side surface (lid) .

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