Modulated frequency multiplier inverter

Abstract

Described is a frequency multiplier inverter and related systems and techniques.

Description

[0001]MODULATED FREQUENCY MULTIPLIER INVERTER RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. §119(e) of U.S. provisional application 63 / 554,435 filed on February 16, 2024 which application is hereby incorporated herein by reference in its entirety. GOVERNMENT RIGHTS Not applicable. BACKGROUND High-frequency inverters – also known as switched-mode radio-frequency power amplifiers – are used in a wide range of industrial, commercial and medical applications, including plasma generation, plasma heating, wireless power transfer, dc-dc converters, communications, battery chargers, induction heating, RF welding, and RF power transmission among other applications. In addition to providing high output frequencies, such radio-frequency (rf) inverters must often provide high control bandwidth (i.e., fast response speed) to changes in load characteristics (e.g., highly-variable load impedances) and / or desired power levels. For example, rf power amplifiers (PAs) for industrial applications, such as plasma generation for semiconductor processing equipment, operate at high output frequencies (e.g., tens of MHz) into variable load impedances at high power levels (e.g. peak power in kWs), high peak-to-average power ratios, with very fast dynamic response to output commands (e.g. ^s scale). It is also desired to have high peak and average efficiency to reduce cooling requirements and electricity costs. Unfortunately, to date, it has not been possible to satisfactorily meet the aforementioned performance metrics and efficiency is often sacrificed to meet the other performance metrics. This results in high-frequency inverters having a relatively large size, high power ratings and poor peak and average power efficiency. SUMMARY OF DISCLOSED EMBODIMENTS In accordance with one aspect of the concepts, systems, structures and techniques described herein are improved radio frequency (rf) power conversion techniques to address the aforementioned drawbacks / challenges existing in prior art high-frequency inverters. In addition to providing high output frequencies, radio-frequency inverters provided in accordance with the concepts, systems, structures and techniques described herein provide high control bandwidth (i.e., fast response speed) to changes in load and / or desired power level, while operating into highly-variable load impedances. For example, radio-frequency (rf) power amplifiers (PAs) for industrial applications, such as plasma generation for semiconductor processing equipment, operate at high output frequencies (e.g., tens of MHz) into variable load impedances at high power levels (e.g. peak power in kWs), high peak-to-average power ratios, with very fast dynamic response to output commands (e.g. ^s scale). In one aspect, an inverter provided in accordance with the concepts, systems, structures and techniques described herein includes: (a) a switch network including a first switch or set of switches that generate one or more first intermediate waveforms having a fundamental frequency; (b) a subset of these switches and / or additional switches that further modulate the first intermediate waveform(s) to synthesize a second intermediate waveform having a specified harmonic (e.g., second harmonic) of the fundamental frequency, with the amplitude of the specified harmonic component determined by the timing of the modulating switches and (c) an output filter network that filters the second intermediate waveform to deliver a signal at the specified harmonic frequency to the load. In another aspect, an inverter provided in accordance with the concepts, systems, structures and techniques described herein includes: (a) a switch network including a set of switches that operate at a fundamental frequency to generate one or more modulated intermediate waveforms having a fundamental frequency and a specified harmonic (e.g., second harmonic) of the fundamental frequency, with the amplitude of the specified harmonic component dynamically controlled by the timing of the switches; (b) an output filter network that filters the one or more modulated intermediate waveforms to deliver a signal at the specified harmonic frequency to the load; and (c) a reactive network connected to the switch network and driven by the modulated intermediate waveform to draw current including fundamental frequency current to provide zero-voltage switching of the switches. In some implementations, multiple modulated first intermediate waveforms are combined to generate a second intermediate waveform having no fundamental frequency component. In other implementations, the output filter network is designed to significantly suppress any fundamental frequency component in the second intermediate waveform from appearing in the output waveform. The output filter network may also be designed to suppress any dc component in the second intermediate waveform from appearing in the output. The inverter schemes described herein enable rapid power control and management of wide load impedance magnitude variations by using the timing of the modulating switches to control the amplitude of the second (or other) harmonic component that is delivered to the load. Moreover, the design may use narrow-band frequency modulation in conjunction with sharp tuning (frequency dependency) of the output filter network to enable further power control and to compensate for reactive variations in load impedance. To achieve high efficiency the inverter structure and switching can enable zero- voltage switching of the switches. Moreover, many or all of the switches may be switched at the fundamental switching frequency, rather than the higher output frequency. The concepts, systems, structures and techniques described herein find use in a wide-range of industrial, commercial and medical applications, including but not limited to plasma generation, plasma heating, wireless power transfer, dc-dc converters, communications, battery chargers, induction heating, RF welding, and RF power transmission among other applications. DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The manner and process of making and using the disclosed embodiments may be appreciated by reference to the figures of the accompanying drawings. It should be appreciated that the components and structures illustrated in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principals of the concepts described herein. Like reference numerals designate corresponding parts throughout the different views. Furthermore, embodiments are illustrated by way of example and not limitation in the figures, in which: Fig. 1 is a block diagram of a system comprising a modulated frequency multiplier inverter; Fig. 2A a block diagram of an example embodiment of a modulated frequency multiplier inverter appropriate for use in the system of Fig.1 and comprising first and second switch networks; Fig. 2B is a block diagram of an example embodiment of a modulated frequency multiplier inverter appropriate for use in the system of Fig.1 and comprising first and second switch networks where the second switch network is partially common to the first switch network (i.e., some switches are part of (or common to) both the first and second switch networks); Fig. 2C is a block diagram of an example embodiment of a modulated frequency multiplier inverter appropriate for use in the system of Fig.1 and comprising a single switch network which generates both a primary and a harmonic signal component; (i.e., there is only one switch network that switches at a fundamental frequency and generates both the primary and a harmonic component.) Fig. 3 is schematic diagram of an exemplary embodiment of a modulated frequency multiplier inverter; Fig. 4 is schematic diagram of an exemplary embodiment of a switch suitable for use in the modulated frequency multiplier inverter of Fig. 3 Fig. 5A is an example switching pattern for the frequency multiplier inverter of Fig. 3; Fig. 5B is a plot of a first intermediate waveform voltage (i.e. the voltage of the left-hand half bridge, and which represents a first intermediate waveform VL. where "L" designates “left”) VL vs. radians; Fig. 5C is a plot of first intermediate waveform voltage VR vs. radians; Fig. 5D is a plot of inductor voltage VLR and zero voltage switching (ZVS) current izvsvs. radians; Fig. 5E is a plot of synthesized second intermediate waveform voltage VXvs. radians overlaid with curves for current iX and ZVS current izvs; Fig. 6 is schematic diagram of an exemplary embodiment of a modulated frequency multiplier inverter suitable for use, for example, in the systems of Figs.1, 2A; Fig. 7A illustrates an example switching pattern which may be used in a frequency multiplier inverter such as the frequency multiplier inverter of Fig.6; Fig. 7B is a plot of synthesized voltage VL vs. radians in the frequency multiplier inverter of Fig. 6 using the switching pattern of Fig.7A; Fig. 7C is a plot of synthesized voltage VRvs. radians in the frequency multiplier inverter of Fig. 6 using the switching pattern of Fig.7A; Fig. 7D is a plot of inductor voltage VLR and ZVS current iLR vs. radians in the frequency multiplier inverter of Fig.6 using the switching pattern of Fig.7A; Fig. 7E is a plot of synthesized voltage VX vs. radians in the frequency multiplier inverter of Fig. 6 using the switching pattern of Fig.7A; Fig. 8 is a schematic diagram of an example embodiment of a modulated frequency multiplier; Fig. 9A is a series of curves corresponding to switching waveforms for switches q1-q7(annotated as FETD1- FETD7 in Fig. 8) for the modulated frequency multiplier of Fig. 8 with constant deadtimes included in the switching waveforms; Fig. 9B is a plot of Load / Vx Voltage and Current Waveforms; Fig. 9C is a plot of voltage and current waveforms of the ZVS inductor LZVS; Fig. 9D is a plot of power vs. beta, parameterized in resistance for a four times (4x) resistive load range; Fig. 10A is a schematic diagram of a “single-ended” modulated frequency multiplier requiring only unidirectional-blocking switches (with example operating waveforms being illustrated in Fig. 6); Fig. 10B is a schematic diagram of an example embodiment of a modulated frequency multiplier inverter in which a subset of switches used to general a signal at a fundamental frequency are used to generate a signal at a harmonic of the fundamental frequency; Figs. 11A-11C are a series of example operating waveforms and a switching pattern for the single-ended frequency multiplier inverter of Fig.10A; Fig. 12 is a schematic diagram of an example embodiment of a modulated frequency multiplier inverter incorporating an interphase transformer; Figs. 13A-13D are a series of example operating waveforms and a switching pattern for the for the modulated frequency multiplier inverter of Fig.12; Fig. 14 is a schematic diagram of an example embodiment of a modulated frequency multiplier inverter incorporating an interphase transformer and having multiple possible operating modes (with Figs.13A-13D and 15A-15D illustrating examples of waveforms of two different possible operating modes); Fig. 15A illustrates an example switching pattern for the frequency multiplier inverter of Fig. 14; Figs. 15B-15D illustrate a series of example operating waveforms for the switching pattern of Fig.15A and the frequency multiplier inverter of Fig.14 in which only one half- circuit operates; Fig. 16 is a schematic diagram of an example embodiment of a single-ended inverter or single-ended frequency multiplier derived from a class-E inverter; Figs. 17A-17C illustrate example switching waveforms for the single-ended inverter or single-ended frequency multiplier of Fig. 16; Fig. 18 is a schematic diagram of an example embodiment of a single-ended inverter or a single-ended frequency multiplier that provides inversion and modulation using only ground-referenced controlled switches; Fig. 19 is a schematic diagram of an example embodiment of a single-ended inverter or a single-ended frequency multiplier that provides inversion and modulation using only ground-referenced controlled switches; Fig. 20 is a schematic diagram of an example embodiment of a double-ended inverter or double-ended frequency multiplier that provides inversion and modulation using only ground-referenced controlled switches; Figs. 21A-21F illustrate example embodiments of output network structures; Fig. 22A is a schematic diagram of an example embodiment of an inverter which may be the same as or similar to the inverter of Fig. 5, comprising an auxiliary circuit for soft switching; Fig. 22B is a schematic diagram of an example embodiment of an auxiliary circuit to provide soft switching; Fig. 23 is a schematic diagram of an example embodiment of a full-bridge frequency multiplier with auxiliary circuit to provide soft switching; Fig. 24 is a schematic diagram of a “single-ended” direct synthesis modulated frequency multiplier. Fig. 25 are plots of operating waveforms for the modulated frequency multiplier of Fig. 24; Fig. 26A is a plot of magnitude of the second harmonic voltage vL,2 for the modulated frequency multiplier of Fig.17 plotted vs. control angle β for the operating waveforms in Fig. 2518; Fig. 26B is a plot of phase of the second harmonic voltage vL,2 for the modulated frequency multiplier of Fig.24 plotted vs. control angle β for the operating waveforms in Fig. 25; Figs. 27A-27D are a series of plots illustrating second harmonic voltage vL,2for the modulated frequency multiplier of Fig.24 at different control angles β from ^ to 3^ / 2 for the operating waveforms in Fig.25; Fig. 28 is a schematic diagram from a simulation of a single-ended direct synthesis modulated frequency multiplier. Illustrative simulation results are shown in Fig.22; Figs. 29A-29G are a series of plots which illustrate results of the simulation of the single-ended direct synthesis modulated frequency multiplier shown in Fig.28; Fig. 30 is a schematic diagram of a double-ended, or “two-way” direct synthesis modulated frequency multiplier; Fig. 31 is a schematic diagram of a double-ended, or “two-way” direct synthesis modulated frequency multiplier with a single ZVS inductor; and Fig. 32 is a schematic diagram of a four-way direct synthesis modulated frequency multiplier. DETAILED DESCRIPTION Referring now to Fig. 1, a system 10 includes a modulated frequency multiplier inverter 12 having an output 12a coupled to an input 14a of a system 14. While operating system 14 may have changing (i.e., variable) load impedances at input 14a and may also have a need to receive different and / or changing power levels at input 14a. System 14 may, for example, be any of: a plasma generation system, plasma heating system, a wireless power transfer system, a dc-dc converter, a communication system, a battery charger, an induction heating system, an RF welding system or an RF power transmission system. System 14 presents to changes in load and / or desired power level, while operating into highly-variable load impedances. Thus, the load impedance presented by system 14 to the output 12a of modulated frequency multiplier inverter 12 may change during operation. Furthermore, the power levels required to be provided by modulated frequency multiplier inverter 12 to the at input 14a of system 14 may also change. Accordingly, modulated frequency multiplier inverter 12 is capable of providing to the input of system 14 signals having different and / or changing power levels, while also adapting the impedance characteristic at port 12a (i.e., the output impedance of modulated frequency multiplier inverter 12) according to the impedances presented to the modulated frequency multiplier inverter output 12a at system input 14a. In embodiments, and as will be described in detail below in conjunction with Figs.2A16, modulated frequency multiplier inverter 12 includes (a) a switch network includinga first switch or set of switches that generate one or more first intermediate waveforms having a fundamental frequency; (b) a subset of these switches and / or additional switches that further modulate the first intermediate waveform(s) to synthesize a second intermediate waveform having a specified harmonic (e.g., second harmonic) of the fundamental frequency, with the amplitude of the specified harmonic component determined by the timing of the modulating switches; and (c) an output filter network that filters the second intermediate waveform to deliver a signal at the specified harmonic frequency to the load. In embodiments, a sensor (e.g. a current and / or voltage sensor) is coupled to the output of modulated frequency multiplier inverter 12. Sensor 16 is here shown in phantom since it may or may not be provided as part of modulated frequency multiplier inverter 12. That is, in some embodiments it may be preferable (or even required) that some or even all circuitry of sensor 16 be provided as one or more components separate from modulated frequency multiplier inverter 12. Conversely, in some embodiments it may be preferable (or even required) that some or even all circuitry of sensor 16 be provided as part of modulated frequency multiplier inverter 12. Sensor 16 senses (e.g. couples or otherwise measures) characteristic of an output signal provided at output 12a of modulated frequency multiplier inverter 12 and utilizes such sensed information (i.e., the coupled or otherwise measured characteristic of the output signal from modulated frequency multiplier inverter 12 ) to adjust (i.e., change or otherwise modify) impedance at port 12a and / or power level characteristics at signals provide by the modulated frequency multiplier inverter 12 at port 12a. For example, in embodiments, sensor 16 may comprise a coupler disposed to couple a portion of an output signal provided at output port 12a of modulated frequency multiplier inverter 12 and feed the coupled signal portion back to the modulated frequency multiplier inverter 12. In response to such coupled signal portions, modulated frequency multiplier inverter 12 may adjust the impedance at port 12a and / or adjust the power level characteristics of signals provide by the modulated frequency multiplier inverter 12 at port 12a. In addition to providing high output frequencies, modulated frequency multiplier inverters 12 provided in accordance with the concepts, systems, structures and techniques described herein provide high control bandwidth (i.e., fast response speed) to changes in load and / or desired power level, while operating into highly-variable load impedances. For example, radio-frequency (rf) power amplifiers (PAs) for industrial applications, such as plasma generation for semiconductor processing equipment, operate at high output frequencies (e.g., tens of MHz) into variable load impedances at high power levels (e.g. peak power in kWs), high peak-to-average power ratios, with very fast dynamic response to output commands (e.g. ^s scale).Referring now to Fig. 2A, a modulated frequency multiplier inverter 18 includes afirst switch network 19 including a set of switches (where a set may include one or more switches) operable to generate one or more first intermediate waveforms having a fundamental frequency. Thus, first switch network is sometimes referred to herein as a fundamental switch network (referring to a circuit which generates a waveform having a fundamental frequency). Coupled to the first switch network is a second switch network including a set of switches (where a set may include one or more switches) that further modulate the one or more first intermediate waveform(s) to synthesize one or more second intermediate waveforms having a specified harmonic (e.g., second harmonic) of the fundamental frequency, with the amplitude of the specified harmonic component determined by the timing of switches in the second switch network. Thus, the second switch network is sometimes referred to herein as a modulation switch network (referring to a circuit which generates (or synthesizes) a waveform which includes a harmonic component of the fundamental frequency). The first and second intermediate waveforms may sometimes be referred to as synthesized waveforms. An output filter network 22 is coupled to receive signals provided by the first and / or second switch network. Output filter network is provided having a filter characteristic selected to at least filter the second intermediate waveform to deliver a signal at the specified harmonic frequency at output 18a which is coupled to input 23a of a load 23 (load 23 is shown in phantom since load 23 is not properly a part of modulated frequency multiplier inverter 18). Filter characteristics of the output filter network may or may not disturb or in any way change characteristic of signals propagating at the fundamental frequency. The particular manner in which to implement the output filter network will depend upon a variety of factors including but not limited to the particular desired filter characteristic (e.g., a low pass filter characteristic, a high pass filter characteristic, a band pass filter characteristic, a notch filter characteristic and so on and so forth). In many practical embodiments, the filter network is provided having a bandpass filter characteristic. It should, however, be noted that in some instances a filter network having a low-pass filter characteristic may be used (e.g., if the synthesized waveform has no dc or fundamental component). After reading the disclosure provided herein, one of ordinary skill in the art will appreciate how to select a filter characteristic for use in a particular application. In embodiments, a sensor (e.g. a current and / or voltage sensor) is coupled to the output of modulated frequency multiplier inverter 18. Again, as above, sensor 16 is here shown in phantom since it may or may not be provided as part of modulated frequency multiplier inverter 18. Sensor 16 senses (e.g. couples or otherwise measures) characteristic of an output signal provided at output 18a of modulated frequency multiplier inverter 18 and utilizes such sensed information (i.e., the coupled or otherwise measured characteristic of the output signal from modulated frequency multiplier inverter 18) to adjust impedance at port 18a and / or power level characteristics at signals provide by the modulated frequency multiplier inverter 18 at port 18a. For example, in embodiments, sensor 16 may comprise a coupler disposed to couple a portion of an output signal provided at output port 18a of modulated frequency multiplier inverter 18 and feed the coupled signal portion back to the controller 24 for the modulated frequency multiplier inverter 18. In response to such coupled signal portions, modulated frequency multiplier inverter 18 may adjust the impedance at port 18a and / or adjust the control signals and power level characteristics of signals provide by the modulated frequency multiplier inverter 18 at port 18a, through techniques which may include feedback, adaptive feedforward, and digital predistortion. In embodiments, a controller 24 provides control signals 26, 28 to the first and second switch networks to control the timing of when switches in the first and second switch networks are biased into their high and low impedance states (with a switch biased in its high impedance state corresponding to the switch being in an “OFF” state and a switch biased in its low impedance state corresponding to the switch being in an “ON” state). The controller may be implemented with a field programmable gate array (FPGA), microprocessor, digital signal processing controller, Novena system, etc. In embodimentsa Xilinx FPGA system or equivalent, for example, may be used. Controller 16 is hereshown in phantom since it may or may not be provided as part of modulated frequency multiplier inverter 18. That is, in some embodiments it may be preferable (or even required) that some or even all circuitry of controller 24 be provided as one or more components separate from modulated frequency multiplier inverter 18. Conversely, in some embodiments it may be preferable (or even required) that some or even all circuitry of controller 24 be provided as part of modulated frequency multiplier inverter 18. In embodiments, controller may receive one or more signals form sensor 16 and in response thereto adjust switching patterns of one or more switches in either or both of the first and second switching networks to control (e.g., set and / or change) impedances at port 18a and / or power level characteristics of signals provided by the modulated frequency multiplier inverter 18 at output port 18a. For example, in embodiments, sensor 16 may provide to controller one or more of current and / or voltage signals or information derived from one or more of current and / or voltage signals (e.g. impedance values, power values, peak or average power values or other any other information which may be derived from current or voltage signals) which controller 24 may use to adjust (i.e., change or otherwise modify) the impedance at port 18a or at the input of the output filter network 22 or seen at the output of the second switch network 20 and / or adjust the power level characteristics of signals provided by the modulated frequency multiplier inverter 18 at port 18a. In embodiments, output filter network 22 may also receive a control signal 30 from controller 24 to adjust one or more characteristics of output filter network 22. In embodiments, controller may receive one or more signals form sensor 16 and in response thereto adjust one or more characteristics of output filter network 22 (e.g. to control (e.g., set and / or change) impedances and / or filter characteristics of output filter network 22. This may be accomplished, for example, by using tunable components in the filter, by adjusting the operating frequency of the system, or through other means. Referring now to Fig. 2B, an example embodiment of a frequency multiplier inverter may comprise a subset of switches (here illustrated as common switch network 27) used or operated with a selected switching pattern to generate one or more first intermediate waveforms and also used to generate a second intermediate waveform. That is, the example embodiment of Fig.2B comprises first and second switch networks where the second switch network is partially common to the first switch network (i.e., some switches are part of (or common to) both the first and second switch networks and are operated in coordination with other switches (i.e., switches not common to both the first and second switch networks) from either or both of the first and second switch networks to generated desired waveforms). This is contrast to the embodiment of Fig.2A in which a first set of switches (e.g. in first switch network 19) are operated or controlled (i.e., turned ON and OFF at specified times and for specified durations of time) with a first switching pattern to generate the one or more first intermediate waveforms and a second, different, set of switches (e.g. second switch network) are operated or controlled (i.e., turned ON and OFF at specified times and for specified durations of time) with a second, different switching pattern which is independent of the first switching pattern to generate the second intermediate waveform. Thus, the example embodiment of Fig.2B illustrates that a subset of the switches from either or both of the first and second switch networks, may be used (or operated with a selected switching pattern) to generate (or synthesize) the one or more first intermediate waveforms may also be used to generate the second intermediate waveform. Referring now to Fig. 2C, an example embodiment of a frequency multiplier inverter may comprise a single switch network 21. As will be described in further detail herein below (e.g. in conjunction with Figs.24-32), in such an embodiment, switches in switch network 21 may be operated such that the first and second intermediate waveforms become a single intermediate waveform having both fundamental and harmonic components. Fig. 3 shows an example possible implementation of a modulated frequency multiplier with exemplary operating waveforms and switching patterns for this implementation shown in Figs.5A-5E. Referring now to Fig. 3, a modulated frequency multiplier inverter includes switches q1and q2operated (i.e., are switched between their respective ON and OFF states with a particular timing and duration) to synthesize a voltage VL, and switches q3 and q4 operated to synthesize a voltage VRwith switches q1-q4each switching at a fundamental frequency (i.e., switching between ON and OFF states once per fundamental frequency cycle), and voltages VLand VRhaving a fundamental frequency component (e.g., which might be approximated as square waves at the fundamental frequency). Switches are operated q5, q6, and q7act to modulate and combine portions of VLand VRto synthesize a voltage Vx having a component at the second harmonic of the fundamental frequency. An inductor LZVS is coupled to provide a modulated frequency multiplier inverter with zero-voltage soft switching (ZVS) characteristic. Inductor current iZVS assists with soft switching of switches q1-q4. Soft switching of switches q5-q7 may be aided by tuning the output tank circuit (comprising inductor LZVS and capacitor C1) slightly inductively at the second harmonic frequency. With the timing indicated in Figs.5A-5E, waveform Vxhas no component at the fundamental frequency, and has a second-harmonic component whose value is determined by the timing of q5,q6, and q7, which is characterized by a switching angle β. An output filter (e.g. an output tank filter) filters signal Vx to deliver a current ix to a load that is dominated by the second harmonic of the fundamental frequency. Fig. 5A is an example switching pattern for a frequency multiplier inverter which may be the same as or similar to the frequency multiplier inverter of Fig.3 while Figs.5B- 5E are a series of operating waveforms of a frequency multiplier inverter which may be the same as or similar to the frequency multiplier inverter of Fig. 3 resultant from the switching pattern of Fig.5A. As noted the circuit of Fig.3 can be realized with zero-voltage soft switching (ZVS). Inductor current iZVSassists with soft switching of q1-q4. Soft switching of q5-q7 is aided by tuning the output tank slightly inductively at the second harmonic frequency. It will be appreciated that while a series-resonant tank structure is shown, additional resonant tank components and / or different tank structures (e.g., LLC, series-parallel, etc.) can be used, and / or additional inductive soft-switching branches (not shown) can be used (e.g. connected to the Vx node) to provide inductive current for soft switching). It will be recognized that providing for soft switching may require deadtimes and other timing adjustments for switching that are not illustrated in Figs.5A=5E. Adjustments for load reactance variation and further power control and adjustments for load resistance variation can be undertaken using frequency modulation in conjunction with an output tank providing significant variation in reactance with frequency. An advantage of this circuit is that all active switches q1-q6 operate at the fundamental frequency. (q7can be realized as a diode and / or with an active switch.) A limitation with the control signals shown in Fig. 5A is that switches q5 and q6 must have bidirectional blocking and carrying capabilities. This can be implemented with back-to-back switches, using switches that are natively bidirectional, or through other means, but usually represents an undesirable design aspect. Referring now Fig.6, shown is a modulated frequency multiplier inverter requiring only unidirectional-blocking switches while Figs.7A-7E illustrate example switching patterns and operating waveforms for a modulated frequency multiplier inverter which may be the same as or similar to the frequency multiplier inverter of Fig.6. Referring now to Fig. 6, this exemplary implementation illustrates that, combined with the switching patterns illustrated in Fig. 7A, embodiments of modulated frequency multiplier inverters exist which employ only unidirectional-blocking switches to be employed. It should be noted that one could use a separate zero voltage switching (ZVS) inductor and blocking capacitor(s) for each half-circuit, and one could also use a separate q7or d7 for each half-circuit (e.g., q7a and q7b each activated once per electrical cycle 2^), which can benefit layout and reduce the switching rate of the individual elements operating as q7. As noted above Fig.7A is an example switching pattern for a frequency multiplier inverter which may be the same as or similar to the frequency multiplier inverter of Fig.6 while Figs.7B-7E are a series of operating waveforms of the frequency multiplier inverter resultant from the switching pattern of Fig.7A. Note the switching pattern shown in Fig. 7A provides flexibility on when switch q7is active. As above, the switching patterns illustrated do not include dead times and other details utilized in realizing zero-voltage switching. Other tank structures and auxiliary circuits utilized to enable ZVS switching of the devices (not shown) can likewise be utilized. After reading the disclosure provided herein, those of ordinary skill in the art will appreciate how to implement tank structures and auxiliary circuits utilized to enable ZVS switching of the devices. In Fig. 8, a frequency multiplier inverter of Fig. 6 has been implemented in simulation to better illustrate the concept and show inclusion of switching deadtimes. Referring now to Fig. 8 shown is a complete inverter topology, the switching waveforms with constant deadtimes incorporated to enable ZVS soft switching (Fig.9A), the output voltage and current (Fig.9B), and waveforms associated with the zero-voltage switching inductor LZVS (Fig.9C). In Fig.8, switches q1 - q7 are implemented as field effect transistors (FET) and labelled as FETD1 – FET D7. The simulated inverter has a four times (4x) load range (5-20 ohms) at a four and one-half (4.5x) power range (150W – 700W). This requires a beta varying from pi / 30 to pi / 2, a net reactance of 8.8ohms, and a deadtime that is about 12% of the total period. These parameters were selected in simulation to maximize the output power ratio while simultaneously allowing for ZVS of switches q5-q7. It is worth noting that this range can be expanded by varying the deadtime based on what the value of Beta is, as opposed to keeping the deadtime constant. Fig.9D shows the relationship between the conduction angle beta, the total average output power, and the load resistance, and Table 1 summarizes the values for the output voltage, current, and power. With an additional load- independent current source placed in parallel with the LC tank and load network to facilitate ZVS for switches q5-q7 (as elaborated upon below), the operating range can be expanded. Table 1 Table 1 shows simulation results illustrating power range for different load resistances. An example “single-ended” modulated frequency multiplier is illustrated in Fig. 10A, with switching patterns shown in Fig. 11A and waveforms shown in Figs. 11B-11C. Again, switch timing details (e.g., deadtimes) and possible additional or alternative structures for ZVS are not shown. There is flexibility in the timing of switches q5 and q7 as illustrated in Figs.11B, 11C. If switches q5 and q7 are held on during the period where the on-state for switch q2 is indicated, then switch q2 may be optionally removed from the circuit. Alternatively, one can optionally select on-time durations for switches q5and q7(within the shown ranges), so that all switches have near 50% on-times; this can be valuable for some gate driving schemes. The flexibility in timing of switches q5and q7and the fact that load voltage VL is further modulated to synthesize intermediate voltages Vx provides flexibility in timing and commutation that can be valuable at high frequencies. Referring now to Fig. 10A, a frequency multiplier inverter 50 has a voltage source 52 coupled to an input thereof. Voltage source 52 is here shown in phantom since it is not properly a part of frequency multiplier inverter 50. The frequency multiplier inverter 50 includes a first set of switches q1, q2 operable with a first switching pattern selected to generate one or more first intermediate waveforms having a fundamental frequency. Coupled to the first set of switches are a set of modulation switches q5, q7. The set of modulation switches operate with a second, different switching pattern selected to further modulate the one or more first intermediate waveforms to synthesize a second intermediate waveform having a specified harmonic of the fundamental frequency. The amplitude of the specified harmonic component of the fundamental frequency is determined by the timing and switching pattern of the set of modulating switches. In the example embodiment of Fig. 10A, switches q1, q2may be operated independently from modulation switches q5, q7. That is, switching patterns and switching times of switches q1, q2 may be selected to generate a square wave as a fundamental component (see, for example, signal waveform VLin Fig. 11B) while switches q5, q7 may be independently operated with switching patterns and switching times selected to chop the square wave further to generate a signal waveform Vx(see, for example, signal waveform Vx in Fig. 11C where signal waveform Vx may be considered a narrowed version of signal waveform VL). An output filter network 58 coupled to the set of modulation switches is provided having a filter characteristic selected to filter harmonics of either or both of the first intermediate waveform and / or second intermediate waveform. In one example embodiment, output filter network 58 is provided having a filter characteristic selected to filter dc, the fundamental, and 3rdand higher harmonics of the second intermediate waveform such that an output signal having a frequency corresponding to a frequency of the second harmonic component is provided at the output of the frequency multiplier inverter 50. Although output filter network is here shown as comprising series coupled capacitor C1and inductor L1, it should be appreciated that other filter configurations may be used comprising one or any combination of inductors and / or capacitors and / or resistors. The particular manner in which to implement the output filter network (e.g., having a low pass filter characteristic, a high pass filter characteristic, a band pass filter characteristic, a notch filter characteristic and so on and so forth) will depend upon a variety of factors including but limited to the particular desired harmonic signal desired to be provided at the output. Often, however, a bandpass filter passing only the harmonic of interest is the desired filter structure. Thus, the frequency multiplier characteristic of the circuit shown in Fig. 10A, is achieved by having each of switches q1, q2, q5, q7 operate at a selected frequency and the frequency of the current waveform ix and voltage waveform Vx are at the harmonic of the selected frequency. Further, in this example embodiment, the first switch pair (q1, q2) and the modulation switch pair (e.g., q5, q7) may be entirely distinct switches. Also, it is noted that current ixpasses through a load having an impedance Z1 (where Z1 + R1 + jX1 and voltage Vx is the voltage applied to the output filter network. Referring now to Fig. 10B, an example embodiment of a frequency multiplier inverter 90 has a voltage source 92 coupled to an input thereof. Voltage source 92 is here shown in phantom since it is not properly a part of frequency multiplier inverter 90. The frequency multiplier inverter 90 includes a first set of switches q1, q5, q7 operable with a switching pattern selected to generate one or more first intermediate waveforms having a fundamental frequency (e.g. a square wave pattern in VL which may be the same as or similar to the square wave pattern in VL achieved by operation of switches q1, q2 in Fig. 10A) and also a second intermediate waveform having a specified harmonic of the fundamental frequency (e.g. a waveform such as waveform VX achieved by operation of switches q5, q7 in Fig.10A). Thus, in this embodiment while the first set of switches q1, q5,q7operate to generate one or more first intermediate waveforms having a fundamental frequency, a subset of the first set of switches (e.g. switches q5, q7) may also operate to synthesize the second intermediate waveform. The subset of switches q5, q7 may be operable with a switching pattern selected to both generate the first intermediate waveforms and also to further modulate the first intermediate waveforms to synthesize the second intermediate waveform. The amplitude of the specified harmonic component of the fundamental frequency may be determined by the timing and switching pattern of the subset of switches (e.g., switches q5, q7 which may be referred to as modulating switches). The example embodiment of Fig.10B thus illustrates that a subset of the switches used (or operated with a selected switching pattern) to generate the one or more first intermediate waveforms may also be used to generate the second intermediate waveform. This is contrast to the embodiment of Fig.10A in which a first set of switches (q1, q2) are operated or controlled (i.e., turned ON and OFF at specified times and for specified durations of time) with a first switching pattern to generate the one or more first intermediate waveforms and a second, different, set of switches (q5, q7) are operated or controlled (i.e., turned ON and OFF at specified times and for specified durations of time) with a second, different switching pattern which is independent of the first switching pattern to generate the second intermediate waveform. In the embodiment of Fig.10B, coupled to switches q1, q5, q7, is an output filter network 59. Output filter network 59 is provided having a filter characteristic selected to filter the second intermediate waveform to provide an output signal having a frequency corresponding to a frequency of the specified harmonic component. In the example embodiment of Fig.10B, waveform Vx will have a component at the fundamental frequency and thus output filter network 59 may be provided having a filter characteristic selected to filter out (or attenuate or ideally entirely remove) the component of Vx at the fundamental frequency. Although output filter network is here shown as comprising series coupled components (e.g. series coupled capacitor C1, inductor L1), it should be appreciated that other filter configurations may be used comprising one or any combination of inductors and / or capacitors and / or resistors. The particular manner in which to implement the output filter network will depend upon a variety of factors including but not limited to the particular desired filter characteristic (e.g., a low pass filter characteristic, a high pass filter characteristic, a band pass filter characteristic, a notch filter characteristic and so on and so forth). As elaborated upon later in the disclosure, it is also possible for the subset of the switches used to be the full first set of switches. For example, switch q5 may be held on continuously or replaced by a short circuit such that Vx=VL whereby the first and second intermediate waveforms become a single intermediate waveform having both fundamental and harmonic components. Referring now to Fig. 12, a modulated frequency multiplier inverter utilizes an interphase transformer to combine waveforms from inverter legs a and b. An example switching pattern is shown in Fig. 13A for use with the modulated frequency multiplier inverter of Fig. 12. Figs. 13B-13D illustrate example waveforms provided by the modulated frequency multiplier inverter in response to the switching patterns of Fig. 13A. Figs. 13A-13D do not include dead-times and other adjustments necessary for zero-voltage switching. In this example circuit, output voltage can be further reduced by having each half of the circuit operate with control angle (β) values that alternate among different values for the two half circuits. For example, by making β for the left hand circuit change between 0 and a desired value in alternate cycles, and vary between the desired value and 0 in alternate cycles, one only gets a single output voltage pulse over a full cycle (ωt=2^) rather than two, such that the second harmonic component of Vx is reduced by a factor of two. One can likewise operate the circuit with further sub-harmonic drive components, further reducing output voltage amplitude. Some circuit variants can achieve the same effect by shutting a half-circuit down, saving on switching and resonating losses for low output voltages and power levels. For example, Figure 14 shows an example circuit that can use the same switching pattern as illustrated in Fig.13A, while Fig.15A shows a second switching pattern in which the right half “B” circuit of Fig.14 is shut down (i.e., switches q2, q4off and switch q6held on) such that the output voltage is reduced. With appropriate adjustments (e.g., incorporating blocking capacitors, splitting ZVS switching circuits), similar operation-mode changes can be achieved with other circuits comprising two half circuits. Additional circuit implementations can use passive (e.g., resonant) networks in place of one or more switches, just as “class-E” inverters and frequency multipliers use a passive network instead of the second switch of a class-D design. Fig.16, for example, shows one possible circuit implementation in which a resonant network (comprising inductor Lrand capacitor Cr) is used instead of a switch in comparison to the systems of Figs. 10A, 10B. As with load-modulated class E inverters, the Lr-Cr network can be designed to result in VL to take on an approximate sinusoidal section over a portion of the cycle, and be zero the remaining portion of the cycle, with phase angle ^rset by the switching frequency and operating condition of the design. For a design operating with an output tank tuned near the second harmonic, it may be desirable to have ^rnear ^ / 2, ^, or 3^ / 2, though other values may be used and the value may vary with operating condition. Other harmonic designs may be used (and it is possible to have a version of the design with the output tank tuned near the fundamental frequency). Switches q2 and q3 serve to modulate the waveform VLproviding a desired frequency component (fundamental or harmonic component of the fundamental frequency) to the output tank. Other versions of this approach that can be used either for fundamental frequency operation or for frequency multiplier operation are shown in Figs.18 and 19. An advantage of the circuit designs in Figs. 18 and 19 are that they only require switches having ground- referenced control ports. Such an approach makes control significantly less difficult at high frequencies. Referring now to Fig.18, a circuit in which all active switches are ground referenced switches. For example, while switch D3 (illustrated as diode switch in this example embodiment) is not ground referenced, active switches q1, q2 are ground referenced switches. Such an approach allows the active switches to be easily driven. Such an approach may be useful in the case where it is desired to implement a very high frequency inverter (e.g. an inverter operating with frequencies in the MHz frequency range such as in the range of about 10 MHz to about 100 MHz and possibly in the 60 MHz range, for example). In this circuit, switch q1 is switched at the fundamental frequency, and acts – in conjunction with Lr and Cr to generate a first intermediate waveform VL, much as switch q1 in Fig.16. Switch q2 and diode D3 act as modulating switches, with the load and resonant tank L1 / C1 receiving voltage VLwhen q2 is on, and short circuiting the load and resonant tank L1 / C1 when D3 is on. Referring now to Fig. 19, shown is another exemplary embodiment of a circuit in which all active switches are ground referenced switches but which includes a transformer or balun T1, T2 coupled to a load R. This permits a ground-referenced load (here R) to be driven. Again, by using an architecture in which all active switches (e.g. switches q1, q2 in Fig. 19) are ground referenced switches, the active switches to be easily driven which may be useful in the case where it is desired to implement a very high frequency inverter (e.g. an inverter operating with frequencies in the MHz frequency range such as in the range of 60 MHz, for example). It is noteworthy that there are also “double ended” versions of the circuits of Figs. 16, 18 and 19 in analogy with the designs described above. One such design is illustrated in the example embodiment of Fig.20. When operated as a fundamental-frequency-output inverter, Lr, Cr might be tuned near the fundamental switching frequency (e.g., near 1-1.3 times a nominal fundamental switching frequency as in the load-modulation class E inverter) while the output networks might be tuned near the fundamental switching frequency, with the left and right-half circuits operated in phase (synchronized). When operated as a frequency doubler (frequency multiplier) circuit Lr, Cr might be tuned near the fundamental switching frequency (e.g., near 1-1.3 times the fundamental switching frequency as in the load-modulation class E inverter) while the output networks might be tuned near the second harmonic of the switching frequency, with the left and right-half circuits operated 180 degrees out of phase, such that fundamental components are out of phase and second harmonic components are in phase. It will be appreciated that more circuits might be introduced to supply the load current in similar fashion, with relative phases among the units selected to provide maximize delivery of a desired frequency (fundamental or harmonic) and cancel (or partially cancel) undesired components. The above examples show the use of a series output tank structure. Such a bandpass structure is useful because it can allow a desired frequency through while suppressing lower and higher frequencies. If tuned somewhat off of resonance, it can further provide reactive current for soft-switching of the devices, and with a high-Q output tank can be further used with frequency modulation (or “dynamic frequency tuning”) to compensate for reactive components of the load. It will be recognized that other output tank structures can be advantageously used in this application, including parallel, series-parallel, LLC, various matching network structures, etc. (e.g., [2,29,30]). One may also add additional ZVS inductors at one or more points in the output network to provide soft-switching currents. Some example output network structures are illustrated in Figs. 21A-21F. These circuit structures can provide current for soft switching over a wider range of load resistances and / or power levels than might be achieved with a series-resonant tank only. It is also worth noting that transformers may be used to provide isolation and voltage gain, and transformer parasitic components may also be included as part of the output filter network. Additionally or alternatively, further auxiliary circuits may be employed to facilitate soft switching over a wide load impedance range and / or wide output power range. One example active auxiliary circuit is illustrated in Fig. 22B. Active or passive auxiliary circuits to facilitate zero-voltage soft switching may likewise be used. For example, Fig.22A illustrates an example boost converter capable of drawing a dc current from a port of an inverter or frequency multiplier such as that of Fig. 10A, and deliver the power drawn from that port back to the input. The boost converter may be controlled to provide a constant desired current iZVS2 at its input (i.e., through its input inductor Laux), such that the current iZVS2can act like a constant dc current source to help provide soft switching for the inverter independent of the operating point. The boost converter can operate at low switching frequency (relative to the switching frequency of the inverter / frequency multiplier) to provide high efficiency. By using a relatively large inductive circuit element (such as inductor Laux), the converter can draw an approximately constant current despite the ac component of voltage Vx at its input. After reading the disclosure provided herein, those of ordinary skill in the art will appreciate that various other kinds of power electronic converters can be configured to draw soft-switching currents at desired nodes, and can be used to facilitate soft switching in various kinds of wide-range inverters and frequency multipliers. The benefits of adding an auxiliary circuit have been explored in simulation for the full-bridge inverter. As seen in Table 2 below, for a four times (4x) resistive range, the power ratio increases dramatically (compared to the previous results) when a constant current source of 4A is placed in parallel. This allows decreasing of the deadtime required to discharge C7 (7% of period in this example) and also decreasing of the net reactance needed, which allows the output voltage to increase. Table 2 There is a substantially linear relationship between the deadtime required to discharge C7 and the amount of current needed in parallel with the load. For instance, for a deadtime of 9%, 2.25A are needed, while a deadtime of 5% would require roughly 6.75A. The designs shown and described herein can be advantageously combined with further design and control techniques. One such approach is variable frequency multiplication (e.g., building upon the techniques described in Appendix A to expand the achievable output voltage, power or load resistance range. Referring now to Fig. 23, shown is an example embodiment of a full-bridge frequency multiplier with auxiliary circuit (schematically represented as constant current source Isourcein Fig.23) for soft switching. It should be appreciated that designs shown and described herein might be operated as a fundamental-frequency inverter (i.e., with inverter devices switching at the output frequency) for some operating range, and in frequency multiplier mode (e.g., with inverter devices switching at a frequency corresponding to one-half the output frequency, for “frequency doubling” and / or some other fraction of the output frequency) for some other portion(s) of the operating range. Likewise, one can combine power from multiple inverter or frequency multipliers herein, and – over some portion of the operating range – turn certain constituent inverters / frequency multipliers off (e.g., holding their outputs at a fixed potential) to provide multi-inverter discrete backoff (MIDB) operation. Additionally or alternatively, discrete or continuous supply modulation can be applied as a power control strategy. Moreover, multiple frequency multiplier units as described herein may be employed in an outphasing structure to provide additional means to control power to a load network. One may further include an output network incorporating phase-switched impedance modulation as a further means of power control or for tunable matching or load impedance adjustment. After reading the disclosure provided herein, one ordinary skill in the art will recognize that other techniques known to those of ordinary skill in the art may likewise be adopted to enhance the operating range and / or performance of designs introduced here. Direct Synthesis Implementations It should be appreciated that implementations of the concepts described herein proposed approach are possible in which a set of switches (e.g. a single switch network as shown, for example, in Fig. 2B) directly synthesize an intermediate voltage waveform having both a fundamental component and modulated harmonic component. This is used along with an output filter network that filters the intermediate waveform (or a further waveform derived from one or more intermediate waveforms) to deliver a signal at the specified harmonic frequency to the load ZL, and may also include auxiliary circuits that support zero-voltage soft switching of the switches. In such a direct synthesis implementation, the amplitude of the of the specified harmonic voltage is modulated by the timing of the set of switches, enabling output power to be modulated. Direct synthesis implementations can be advantageous because such implementations achieve operational goals with relatively few switches (e.g., fewer switches than may be required using a prior art approach to achieve the same or similar performance). In these designs, the intermediate waveform may be used to drive auxiliary circuit(s) to provide current for zero-voltage soft-switching (ZVS) of the switches (often including fundamental-frequency current for ZVS), while the harmonic component of the intermediate waveform is used to synthesize the output signal at the harmonic frequency. The output current may also optionally be used to support zero-voltage switching of the switches. Fig. 24, illustrates an example single-ended direct synthesis modulated frequency multiplier with illustrative operating waveforms shown in Fig.25. (Note that deadtimes and rise / fall times associated with zero-voltage switching have been ignored.) In the single-ended direct synthesis modulated frequency multiplier circuit of Fig. 24, switches q1and q2operate to synthesize an intermediate voltage VLhaving a fundamental-frequency component and a second harmonic component. The amplitude of the second harmonic component is modulated by controlling the switching angle β. The output network is tuned near the second harmonic, such that the output current ixis at the second harmonic, providing power to the load impedance ZL. The voltage applied by VL across inductor LZVSdrives a current iZVS(having a fundamental component the fundamental frequency) that supports zero-voltage switching of q1 and q2. (That is, iZVS is negative at the low-to-high transition in vL, and positive at the high-to-low transition.) As shown below, with appropriate control angles and loading the current iX may also support zero voltage switching. For purposes of modulating the output voltage (across ZL) and load current iX, the relationship of the second-harmonic component of vL to the switching angle β is of interest (switching angle β is sometime referred to herein as control angle β). For the waveform timing in Fig. 25 with vLidealized as a square wave, it may be shown that the second harmonic component of vL, denoted vL,2, may be expressed as: ^^^ ^^^(^)^^^(2^^ +^ –^) =^^^ ^^^(^)^^^(2^^(1) ^^,^= ^ 2 ^– ^)The amplitude of the second harmonic voltage is proportional to sin(β) and may thus be controlled by switching angle β. Similarly the fundamental component of vL, denoted vL,1, may be calculated as: (2) It can be seen that the fundamental component amplitude also varies with switching angle β, but with a different characteristic than that of the second harmonic (or other harmonics). The magnitude and phase ψ2 of vL,2 from equation 1 are plotted vs. switching angle (β) in Figs.26A, 26B, respectively. To modulate vL,2between zero and a maximum value of Vdc / ^, different ranges of control angle β may be used, including 0 ≤ ^ ≤ ^^ 2 ,^^ 2 ≤^ ≤ ^ , ^ ≤ ^ ≤ 3^2 , and3^^ 2 ≤ ^ ≤ 2^. Any of these may in modulation of preferable to others. The first and last ranges lead to small values of the fundamental component and to small-valued amplitudes of iZVS, which is undesirable as iZVSneeds to be sufficiently large to support zero-voltage switching. The middle two ranges can provide useful values of iZVS, and one may choose to use one or both of these. In many cases, however, the latter control range, ^ ≤ ^ ≤ 3^^ 2, is preferred. This is because the phase of the second harmonic voltage a resistively and / or inductively tuned load network (at the second harmonic) leads to currents iXthat aid (or at least only little oppose) zero voltage switching for q1and q2. That is, with a resistive / inductive load impedance, we may obtain zero or positive iX at the high-to-low transition of vL, and / or zero or negative iXat the low-to-high transition of vL. This may be seen in the plots of Fig. 27A-27D, which show the second harmonicvoltage vL,2 and the switching angle β for different control angles in the range ^ ≤ ^ ≤3^^ 2. The second harmonic voltage vL,2 is zero or positive and rising at ωt=0, and zero orpositive and falling at ωt=β. With ix lagging vL,2 sufficiently, the second harmonic current may be zero or negative at ωt=0 and zero or positive at ωt=β, as desired for generating currents iX that support zero-voltage switching with a resistive / inductive load (for which iXwill be in phase with or lag vL,2). The control range ^ ≤ ^ ≤ 3^^ 2 tends to yield currentsthat are more beneficial to the high-to-low voltage transition at ωt=β at the expense of thelow-to-high voltage transition at ωt=0. The control range ^^ 2 ≤ ^ ≤ ^ has complementarybenefits, with the current ix providing more benefit for voltage transition at the expense of the high-to-low voltage transition. also illustrates that the amplitude of vL,2 may be modulated over its range for switching angles between ωt=^ and ωt=3^ / 2 and also for switching angles between ωt=^ / 2 and ωt=^. To further illustrate the operation of this system, consider the simulation of Fig.28 (which, in this example, is a PLECS simulation although other simulation platforms may also be used). The design consists of a “half-bridge” topology with two switches, an inductor LZVSconnected to two blocking capacitors for soft switching, an LC tank, and the load which is represented as an inductor in series with a resistor. For the results here, the load is resistive (Lload= 0). Figs. 29A-29G show gate drive waveforms for switches 1 and 2, the voltage at the switch node, the voltage across the ZVS inductor and the current through it, and the voltage across and current through the load. While the design embodied in Figs. 24 and 28 employs a “half-bridge” switch structure, it is possible to achieve similar performance with a full-bridge switch structure in which the (differential) output waveform between the two half bridges is similarly modulated with a control angle β. With a full-bridge switch structure, a transformer or balun (and possibly a blocking capacitor) may be used to convert the differential output of the full bridge to a single-ended output to connect to the output tank and load. For operation with the second harmonic as the output frequency, the frequency multiplier of Fig.24 may be referred to as a “frequency doubler”, as the output frequency is twice that of the fundamental operating frequency. It should be appreciated that the frequency multiplier circuit of Fig. 24 can be designed and operated using other harmonic components of vL to synthesize the output. This may be accomplished by tuning the output network appropriately and selecting an appropriate range of angles β in keeping with the principles described. One could thus operate the circuit as a frequency tripler (with the third harmonic of the fundamental as the output) as a quadrupler (with the fourth harmonic as the output), and so on and so forth by selecting a desired harmonic. Moreover, it is possible to realize a modulated variable frequency multiplier in which the fundamental operating frequency is changed dynamically such that the fundamental and / or different harmonics are used to synthesize the output under different operating conditions (e.g., to realize a wide range of output power or amplitude levels, with higher-order harmonics used for lower output amplitudes). It is appreciated that while a single-ended version of the direct synthesis modulated frequency multiplier has been described, it is also appreciated that double-ended, or two- way versions may be synthesized using the concepts and techniques described herein. One variant of a double-ended direct synthesis frequency multiplier is shown in Fig. 30. In this circuit there are two switching networks, one synthesizing vL and the other synthesizing vR. For a second-harmonic output, the two networks are operated identically (e.g. with the same control angle β), but with switching waveforms shifted by half of a fundamental cycle. This means that the fundamentals of vL and vR are out of phase, but their second-harmonic components are in phase. The common-mode combiner (or “interphase transformer”) creates a voltage vx=(vL+vR) / 2, such that vx has no fundamental- frequency component and has an identical second harmonic voltage component to vL and vR. This second-harmonic component of vx(denoted vx,2) is filtered to provide an (approximately) sinusoidal output current ixat the second harmonic frequency. For frequency multipliers synthesizing harmonics besides the second, it is preferred to operate the multiple circuit sections such that the harmonic of interest from each of the individual sections are in phase. It will also be recognized, however, that one could instead choose to operate the left-hand subcircuit in Fig. 30 (i.e., subcircuit 1) with a switching angle β in the range of^ ≤ ^ ≤ 3^^ 2 to generate vL and the right subcircuit (i.e., subcircuit 2) with its start timeshifted by one half of a fundamental cycle but with the different switching angle β selected between ωt=^ / 2 and ωt=^ that generates a voltage vR having the same second harmonic magnitude as the left-hand subcircuit voltage vL. In this case, the second harmonic components of vL and vR will have the same magnitudes but different phases, thus yielding both β modulation and outphasing of the second harmonic components of vLand vRto modulate the second harmonic component in vx. For frequency multipliers synthesizing harmonics besides the second, one may choose to operate the multiple circuit sections such that the harmonic of interest from each of the individual sections have the same amplitudes but differences in phase to provide outphasing control of the output in addition to β modulation. To expand upon this selection of controls, one could choose to operate the left-hand subcircuit with a switching angle βL=π+γ and the right hand subcircuit with a switching angle βR=π-γ for some single control parameter γ in the range of [0,^ / 2], with γ used to modulate the second harmonic magnitude. Another version of a two-way modulated frequency multiplier is shown in Fig. 31. An advantage of this design is that it only requires a single ZVS inductor, which may optionally be integrated as the magnetizing inductance of the common-mode combiner.Moreover, this circuit can be advantageous if the control range ^ ≤ ^ ≤ 3^^ 2 is used andthe load is tuned such that ix is used to contribute current for ZVS. This is because as control angle β varies, iZVSis reduced at angles where vx,2and ixare of large amplitude, and iZVSbecomes larger at angles where vx,2 and ix are of small amplitude. It should also be appreciated that higher-way (i.e.3-way, 4-way, n-way, wherein n is an integer greater than 1) direct synthesis frequency multipliers can also be realized. For example, the two-way circuit of Fig.30 can be expanded to a 3-way circuit using 3 subcircuits and a 3-way power combiner (or interphase transformer). One might realize a 3-way power combiner as three transformers or baluns in which the primaries of the three transformers are connected to the three switching circuits via blocking capacitors, and the secondaries of the three transformers are connected in series to the filter and load network. A 3-way circuit would be particularly amenable to realizing a frequency tripler, with each subcircuit operated at the same control angle β, but 1 / 3 of a fundamental frequency cycle out of phase with each of the others. Fig. 32 shows an example of a 4-way frequency multiplier constructed in this manner, using a “corporate array” combiner or “wiffle-tree” interphase transformer structure. Such frequency multiplier circuits could also be realized with full-bridge inverter configurations, with transformer coupling from the differential outputs of the full bridges used to provide power combining (e.g., by placing the transformer secondary windings in series for connection to the output tank and load). In the 4-way design of Fig. 32, subcircuits q11 / q21 and q12 / q22 are operated with the same control angle β, but half a fundamental-frequency cycle out of phase, while subcircuits q13 / q23 and q14 / q24 are also operated with the same control angle β but shifted by half of a fundamental-frequency cycle. This configuration ensures cancellation of the fundamental frequency at the output of each combiner. For frequency doubler operation, subcircuits q11 / q21 and q13 / q23 are operated in phase such that second-harmonic components are reinforced in the synthesized voltage vx. For frequency quadrupler operation, subcircuits q11 / q21 and q13 / q23 are operated a quarter of a fundamental- frequency cycle out of phase such that the second-harmonic component is canceled in synthesized voltage vx but the fourth-harmonic components reinforce. It will be appreciated that with the inclusion of additional dc blocking capacitors at the inputs of one or more of the combiners, this circuit would also be suitable for use with multi-inverter discrete backoff (MIDB) operation. The 4-way design of Fig. 32 could also be operated with sets of complementary control angles to provide both outphasing beta modulation and a controlled degree of phase cancellation as described in conjunction with Fig.30 above. In the circuit of Fig. 32, switches q11 / q21 (which form a first half bridge) could be operated with a switching angle βL=π+γ and switches q12 / q22 (which form a second half bridge) operated with a switching angle βR=π-γ for some single control parameter γ in the range of [0,^ / 2], with γ used to modulate the second harmonic magnitude. These two half bridges may be operated with a half-cycle time shift to partially cancel the fundamental component in their combined output, but as they utilize different switching angles some fundamental component may remain. To address this, switches q13 / q23 are also operated with a switching angle βL=π+γ but shifted by one-half of a fundamental cycle from q12 / q22, and q14 / q24 are operated with a switching angle βR=π-γ but shifted by one-half of a fundamental cycle from q12 / q22. As a result, any fundamental component is cancelled in vx, while the second harmonic is controlled via both β modulation and outphasing through the angle γ. After reading the disclosure and broad concepts described herein, it will be appreciated that one of ordinary skill in the art will now be able to find other complementary control angle selections which provide similar effects in the net output waveform and such other complementary control angle selections are within the scope of this disclosure. Various embodiments of the concepts, systems, devices, structures and techniques sought to be protected are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the concepts, systems, devices, structures and techniques described herein. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and / or positional relationships, unless specified otherwise, can be direct or indirect, and the described concepts, systems, devices, structures and techniques are not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layer "C") is between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising, "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus. Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "one or more" and "one or more" are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include an indirect "connection" and a direct "connection". References in the specification to "one embodiment, "an embodiment," "an example embodiment," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. For purposes of the description hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal, "top," "bottom," and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms "overlying," "atop," "on top, "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements such as an interface structure can be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted that the term "selective to, "such as, for example, "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop. Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements. The terms “approximately” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value. The term “substantially equal” may be used to refer to values that are within ±20% of one another in some embodiments, within ±10% of one another in some embodiments, within ±5% of one another in some embodiments, and yet within ±2% of one another in some embodiments. The term “substantially” may be used to refer to values that are within ±20% of a comparative measure in some embodiments, within ±10% in some embodiments, within ±5% in some embodiments, and yet within ±2% in some embodiments. For example, a first direction that is “substantially” perpendicular to a second direction may refer to a first direction that is within ±20% of making a 90° angle with the second direction in some embodiments, within ±10% of making a 90° angle with the second direction in some embodiments, within ±5% of making a 90° angle with the second direction in some embodiments, and yet within ±2% of making a 90° angle with the second direction in some embodiments. It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. Therefore, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter. Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter.

Claims

What is claimed is:

1. A frequency multiplier inverter comprising: a first set of switches operable with a first switching pattern selected to generate one or more first intermediate waveforms having a fundamental frequency; a set of modulation switches, coupled to the first set of switches, the set of modulation switches operable with a second different switching pattern selected to further modulate the one or more first intermediate waveforms to synthesize a second intermediate waveform having a specified harmonic of the fundamental frequency with the amplitude of the specified harmonic component of the fundamental frequency determined by the timing and switching pattern of the modulating switches; and an output filter network coupled to the set of modulation switches, the output filter network having a filter characteristic selected to filter the second intermediate waveform to provide an output waveform signal having a frequency corresponding to a frequency of the specified harmonic component.

2. The frequency multiplier inverter comprising of claim 1 wherein the first set of switches and set of modulation switches operate to modulate and combine the one or more first intermediate waveforms to generate a second intermediate waveform having no fundamental frequency component.

3. The frequency multiplier inverter of claim 1 further comprising an output filter network having a filter characteristic selected to attenuate waveform components at the fundamental frequency in the second intermediate waveform from appearing in the output waveform signal.

4. The frequency multiplier inverter of claim 3 wherein the output filter network is configured to suppress any dc component in the second intermediate waveform from appearing at an output of the frequency multiplier inverter.

5. The frequency multiplier inverter of claim 3 wherein the timing of the set of modulating switches to control the amplitude of the second harmonic component that isdelivered to a load is selected to enable rapid power control and management of wide load impedance magnitude variations.

6. The frequency multiplier inverter of claim 1 wherein the set of modulation switches is configured to use narrow-band frequency modulation in conjunction with a narrow band filter characteristic of the output filter network to control power and to compensate for reactive variations in a load impedance.

7. The frequency multiplier inverter of claim 1 further comprising zero-voltage switching (ZVS) circuitry coupled to enable zero-voltage switching of one or more of the first set of switches and the set of modulation switches so as provide the frequency multiplier inverter having a high efficiency.

8. The frequency multiplier inverter of claim 1 further comprising an auxiliary circuit to provide soft switching.

9. The frequency multiplier inverter of claim 8 wherein the auxiliary circuit comprises one of: an active auxiliary circuit or a passive auxiliary circuit.

10. The frequency multiplier inverter of claim 8 wherein the auxiliary circuit comprises and inductor coupled to at least one of the first set of switches and / or the set of modulation switches.

11. The frequency multiplier inverter of claim 1 further comprising an auxiliary circuit comprising a boost converter coupled to draw a dc current from a port of the frequency multiplier inverter and deliver the power drawn from that port back to the input of the frequency multiplier inverter.

12. The frequency multiplier inverter of claim 11 wherein the boost converter is controlled to provide a constant desired current iZVS2 at its input such that the current iZVS2 can act like a constant dc current source to help provide soft switching for the inverter independent of the operating point.

13. The frequency multiplier inverter of claim 11 wherein the boost converter is configured to operate at low switching frequency (relative to the inverter / frequency multiplier) to provide high efficiency.

14. The frequency multiplier inverter of claim 11 wherein the boost converter comprises an inductor through which is provided a constant desired current iZVS2 such that the current iZVS2can act like a constant dc current source to help provide soft switching for the inverter independent of the operating point and wherein the inductor Laux, is provided having an inductance characteristic such that the converter can draw an approximately constant current despite the ac component of a voltage Vx at its input.

15. The frequency multiplier inverter of claim 1 wherein one or more of the switches in the first set of switches and one or more of the switches in the set of modulation switches may be switched at a switching frequency corresponding to the fundamental frequency, rather than a frequency corresponding to the frequency of the specified harmonic component.

16. A frequency multiplier inverter comprising: a plurality of switches coupled together and operable with a switching pattern selected to generate one or more first intermediate waveforms having a fundamental frequency with a subset of the first set of switches operable to synthesize a second intermediate waveform having a specified harmonic of the fundamental frequency with the amplitude of the specified harmonic component of the fundamental frequency determined by the timing and switching pattern of the subset of switches; and an output filter network coupled to the set of modulation switches, the output filter network having a filter characteristic selected to filter the second intermediate waveform to provide an output signal having a frequency corresponding to a frequency of the specified harmonic component.

17. A plasma generation system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

18. An induction heating system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

19. A wireless power transfer system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

20. A dc-dc converter comprising a frequency multiplier inverter as recited in any of claims 1 -16.

21. A communication system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

22. A battery charger comprising a frequency multiplier inverter as recited in any of claims 1 -16.

23. An induction heating system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

24. An RF welding system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

25. An RF power transmission system comprising a frequency multiplier inverter as recited in any of claims 1 -16.

26. A frequency multiplier inverter comprising: a plurality of switches operable with a switching pattern to generate one or more first intermediate waveforms having a fundamental frequency and one or more second intermediate waveforms having a specified harmonic component of the fundamental frequency with the amplitude of the specified harmonic component of the fundamental frequency determined by the timing and switching pattern of the plurality of switches; and an output filter network coupled to the set of switches, the output filter network having a filter characteristic selected to filter the second intermediate waveform to providean output signal having a frequency corresponding to a frequency of the specified harmonic component; and an auxiliary circuit driven by one or more of the intermediate waveforms that provides current for zero-voltage soft switching of at least some of the plurality of switches.

27. The frequency multiplier inverter of claim 26 wherein the auxiliary circuit current for zero-voltage soft switching has a fundamental-frequency component.

28. The frequency multiplier inverter of claim 27 wherein the first and second intermediate waveforms are the same waveform.

29. The frequency multiplier inverter of claim 27 wherein: a first set of switches operable with a first switching pattern generate the one or more first intermediate waveforms having a fundamental frequency; and a set of modulation switches, coupled to the first set of switches, the set of modulation switches operable with a second different switching pattern selected to further modulate the one or more first intermediate waveforms to synthesize a second intermediate waveform.

30. The frequency multiplier inverter of claim 27 wherein the first and second intermediate waveforms are different waveforms.

31. A plasma generation system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

32. An induction heating system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

33. A wireless power transfer system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

34. A dc-dc converter comprising a frequency multiplier inverter as recited in any of claims 26 -30.

35. A communication system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

36. A battery charger comprising a frequency multiplier inverter as recited in any of claims 26 -30.

37. An induction heating system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

38. An RF welding system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

39. An RF power transmission system comprising a frequency multiplier inverter as recited in any of claims 26 -30.

40. A frequency multiplier inverter having an output, the frequency multiplier inverter comprising: a plurality of switches operable with a switching pattern to generate one or more first intermediate waveforms having a fundamental frequency and one or more second intermediate waveforms having a specified harmonic component of the fundamental frequency with the amplitude of the specified harmonic component of the fundamental frequency determined by the timing and switching pattern of the plurality of switches wherein the fundamental frequency component of the waveform is used to facilitate zero- voltage soft switching in at least some of the plurality of switches and the specified harmonic component of the fundamental frequency is used to generate a signal at the output of the frequency multiplier inverter.

41. The frequency multiplier inverter of claim 40 further comprising an output filter network coupled to at least some of the plurality of switches, the output filter network having a filter characteristic selected to filter the second intermediate waveform to provide the output signal having a frequency corresponding to a frequency of the specified harmonic component.

42. The frequency multiplier inverter of claim 40 wherein the first and second intermediate waveforms are the same waveform.

43. The frequency multiplier inverter of claim 40 further comprising an auxiliary circuit, coupled to at least some of the plurality of switches, the auxiliary circuit driven by one or more of the intermediate waveforms that provides current for zero-voltage soft switching of at least some of the plurality of switches.

44. The frequency multiplier inverter of claim 43 wherein the current for zero-voltage soft switching has a fundamental-frequency component.

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