Liquid crystal display panel and display device

Abstract

A liquid crystal display panel. The liquid crystal display panel comprises a first sub-display area and a second sub-display area adjacent to each other. The display panel comprises an array substrate and a counter substrate arranged opposite each other. The array substrate comprises a plurality of pixel units, wherein the plurality of pixel units comprise a first pixel unit located in the first sub-display area and a second pixel unit located in the second sub-display area. A first signal line comprises a first line segment and a second line segment, wherein the first line segment is electrically connected to the first pixel unit, and the second line segment is electrically connected to the second pixel unit. A common electrode layer comprises a first common electrode located in the first sub-display area and a second common electrode located in the second sub-display area, and a first slit extending in a second direction is provided between the first common electrode and the second common electrode. The counter substrate comprises a light-shielding layer, wherein the light-shielding layer comprises a first light-shielding portion, and the orthographic projection of the first light-shielding portion on a first base at least partially overlaps the orthographic projection of the first slit on the first base.

Description

Liquid Crystal Display Panel and Display Device Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a liquid crystal display panel and a display device. Background Art

[0002] Currently, liquid crystal display devices (English full name: Liquid Crystal Display, English abbreviation: LCD) have been widely used in electronic products such as mobile phones and computers.

[0003] Summary of the Invention

[0004] On the one hand, a liquid crystal display panel is provided. The liquid crystal display panel has a display area, and along a first direction, the display area includes adjacent first and second sub-display areas. The display panel includes: an array substrate, a counter substrate, and a liquid crystal layer disposed between the array substrate and the counter substrate. The array substrate includes: a first substrate, and a plurality of pixel units located on the first substrate, a plurality of first signal lines extending along the first direction, and a common electrode layer. The pixel unit includes at least one sub-pixel area, and the plurality of pixel units include a first pixel unit located in the first sub-display area and a second pixel unit located in the second sub-display area. The first signal line includes a first segment and a second segment, the first segment is electrically connected to the first pixel unit, and the second segment is electrically connected to the second pixel unit. The common electrode layer includes a first common electrode and a second common electrode, the first common electrode is located in the first sub-display area, the second common electrode is located in the second sub-display area, and there is a first gap extending along a second direction between the first common electrode and the second common electrode. The first direction and the second direction intersect. The counter substrate includes a light-shielding layer, and the light-shielding layer includes a first light-shielding portion, and a positive projection of the first light-shielding portion on the first substrate at least partially overlaps a positive projection of the first gap on the first substrate.

[0005] In some embodiments, a positive projection of the first light-shielding portion on the first substrate covers a positive projection of the first gap on the first substrate.

[0006] In some embodiments, the array substrate further includes a plurality of second signal lines, the plurality of second signal lines extend along the second direction and are arranged along the first direction. One of the second signal lines is located on a side of a column of the sub-pixel areas electrically connected thereto away from a first reference line. Wherein, the first reference line is a boundary line between the first sub-display area and the second sub-display area.

[0007] In some embodiments, the sub-pixel region includes: a driving transistor and a pixel electrode. The control electrode of the driving transistor is electrically connected to the first signal line, the first pole of the driving transistor is electrically connected to the pixel electrode, and the second pole of the driving transistor is electrically connected to the second signal line. The sub-pixel region in the first pixel unit is the first sub-pixel region, and the sub-pixel region in the second pixel unit is the second sub-pixel region. In the first sub-pixel region and the second sub-pixel region arranged along the first direction: the driving transistors in the first sub-pixel region and the driving transistors in the second sub-pixel region are mirror-symmetrical with respect to the second reference line. Wherein, the second reference line is the center line of the connection line between the first sub-pixel region and the second sub-pixel region.

[0008] In some embodiments, the pixel electrode is a dual-domain pixel electrode. The dual-domain pixel electrode includes a first domain portion and a second domain portion, and the extending directions of the first domain portion and the second domain portion intersect. The corner formed by the intersection of the first domain portion and the second domain portion of the pixel electrode in any one of the first sub-pixel regions is the first corner, and the corner formed by the intersection of the first domain portion and the second domain portion of the pixel electrode in any one of the second sub-pixel regions is the second corner. Wherein, the first corner and the second corner protrude in one direction.

[0009] In some embodiments, the array substrate further includes a gate metal layer, an active layer, a source-drain metal layer, and the pixel electrode layer stacked on the first substrate. The pixel electrode layer includes a plurality of pixel electrodes. The common electrode layer is located between the source-drain metal layer and the pixel electrode layer. The common electrode layer includes a plurality of vias, and the positive projection of the pixel electrode on the common electrode layer covers the vias. The gate metal layer includes the first signal line. Along the first direction, the first signal line includes a first portion and a second portion. The first portion is multiplexed as the control electrode of the driving transistor, and the positive projection of the via on the first substrate is located between the positive projections of the first portion and the second portion on the first substrate. The source-drain metal layer includes the second signal line. The first sub-part of the second signal line is multiplexed as the second pole of the driving transistor. The source-drain metal layer further includes a first conductive portion. The first conductive portion includes a third portion and a fourth portion. The third portion is multiplexed as the first pole of the driving transistor, and the positive projection of the via on the first substrate is located between the positive projections of the third portion and the fourth portion on the first substrate. The positive projection of the second portion of the first signal line on the first substrate at least partially overlaps with the positive projection of the fourth portion of the first conductive portion on the first substrate.

[0010] In some embodiments, an orthographic projection of the fourth portion of the first conductive portion on the first substrate is located within a boundary of an orthographic projection of the second portion of the first signal line on the first substrate.

[0011] In some embodiments, along the first direction, a length of the fourth portion of the first conductive portion is greater than or equal to 2 μm.

[0012] In some embodiments, the light shielding layer further includes a plurality of second light shielding portions, and the orthographic projections of the second signal line on the first substrate are located within the boundaries of the orthographic projections of the second light shielding portions on the first substrate. Along the first direction, the width of the first light shielding portion is W1, and the width of the second light shielding portion is W2, where W1 ≤ 1.5W2.

[0013] In some embodiments, the liquid crystal display panel further includes a plurality of supporting portions, and the plurality of supporting portions are located between the array substrate and the alignment substrate. The plurality of supporting portions include a first supporting portion and a second supporting portion, the sub-pixel region includes a driving transistor, and the orthographic projection of the first supporting portion on the first substrate at least partially overlaps with the orthographic projection of the driving transistor on the first substrate. The orthographic projection of the second supporting portion on the first substrate is located within the orthographic projection of the first gap on the first substrate, and the second supporting portion and the plurality of first supporting portions are arranged along the first direction. Along the first direction, the spacing between two adjacent first supporting portions is d1, and the spacing between adjacent first supporting portions and second supporting portions is d2, and |d2-d1|≤0.1d1.

[0014] In some embodiments, the pixel unit includes a plurality of sub-pixel regions; the array substrate further includes a gate metal layer, an active layer, a source / drain metal layer, and a first metal layer stacked on the first substrate. The first metal layer is located between the source / drain metal layer and the common electrode layer, and the first metal layer includes a plurality of first traces, wherein an orthographic projection of one of the first traces on the first substrate is located between orthographic projections of any two adjacent sub-pixel regions in the pixel unit on the first substrate.

[0015] In some embodiments, the sub-pixel region includes a driving transistor, and an orthographic projection of the first wiring on the first substrate does not overlap with an orthographic projection of the driving transistor on the first substrate.

[0016] In some embodiments, the array substrate further includes a plurality of second signal lines extending along the second direction and arranged along the first direction, wherein an orthographic projection of the first line on the first substrate at least partially overlaps an orthographic projection of the second signal line on the first substrate.

[0017] In some embodiments, the light-shielding layer further includes a plurality of second light-shielding portions, and the orthographic projection of the first trace on the first substrate is located within the boundary of the orthographic projection of the second light-shielding portion on the first substrate.

[0018] In some embodiments, the array substrate further comprises an organic layer, and the organic layer is located between the source / drain metal layer and the first metal layer. The thickness of the organic layer ranges from

[0019] In some embodiments, the liquid crystal display panel is an irregular liquid crystal display panel, and the multiple first lines include at least two first lines of unequal lengths along the second direction. Among the two first lines of unequal lengths, the length of the first first line is greater than the length of the second first line, and the line width of the first first line is greater than the line width of the second first line.

[0020] In some embodiments, within the first sub-display area or the second sub-display area, among the multiple first routing lines arranged along a direction close to a first reference line: the lengths of the multiple first routing lines gradually increase, and the widths of the multiple first routing lines gradually increase; wherein, the first reference line is the boundary line between the first sub-display area and the second sub-display area.

[0021] In some embodiments, the array substrate further includes an auxiliary electrode layer, the auxiliary electrode layer is located on a side of the common electrode layer facing away from the first substrate, and the auxiliary electrode layer is in contact with the common electrode layer.

[0022] In some embodiments, the light-shielding layer further includes a plurality of second light-shielding portions, the auxiliary electrode layer includes a plurality of auxiliary electrodes, and the orthographic projections of the auxiliary electrodes on the first substrate are located within the boundaries of the orthographic projections of the second light-shielding portions on the first substrate.

[0023] In another aspect, a display device is provided, comprising: a cover plate and a liquid crystal display panel according to any of the above embodiments, wherein the cover plate is located on the light-emitting side of the liquid crystal display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a schematic diagram of a display device according to some embodiments;

[0026] FIG2 is a plan view of a display panel according to some embodiments;

[0027] FIG3 is a cross-sectional view of a display panel according to some embodiments;

[0028] FIG4 is a structural diagram of a display panel according to some embodiments;

[0029] FIG5 is a layout diagram of the display panel of FIG4;

[0030] FIG6 is a structural diagram of a display panel according to some other embodiments;

[0031] FIG7 is a layout structure diagram of the display panel of FIG6;

[0032] FIG8 is a cross-sectional view taken along the line M1-M1′ in FIG7 ;

[0033] FIG9 is a diagram showing the stacked structure of the gate metal layer, the active layer, and the source / drain metal layer in FIG7 ;

[0034] FIG10 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, and common electrode layer in FIG7 ;

[0035] FIG11 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, common electrode layer, and pixel electrode layer in FIG7 ;

[0036] FIG12 is a structural diagram of the light shielding layer in FIG7;

[0037] FIG13 is another layout structure diagram of the display panel of FIG6;

[0038] FIG14 is a cross-sectional view taken along the line M2-M2' in FIG13;

[0039] FIG15 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, common electrode layer, and pixel electrode layer in FIG13 ;

[0040] FIG16 is a structural diagram of the light shielding layer in FIG13;

[0041] FIG17 is another layout structure diagram of the display panel of FIG6;

[0042] FIG18 is a cross-sectional view taken along the line M3-M3' in FIG17;

[0043] FIG19 is a diagram showing the stacked structure of the gate metal layer and the active layer in FIG17 ;

[0044] FIG20 is a diagram showing the stacked structure of the gate metal layer, active layer, and source / drain metal layer in FIG17 ;

[0045] FIG21 is a structural diagram of the common electrode layer in FIG17 ;

[0046] FIG22 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, and common electrode layer in FIG17 ;

[0047] FIG23 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, common electrode layer, and pixel electrode layer in FIG17 ;

[0048] FIG24 is a structural diagram of the light shielding layer in FIG17;

[0049] FIG25 is a partial enlarged view of I in FIG23;

[0050] FIG26 is a cross-sectional view taken along the line N1-N1′ in FIG25 ;

[0051] FIG27 is a cross-sectional view taken along the line N2-N2' in FIG25;

[0052] FIG28 is another layout structure diagram of the display panel of FIG6 ;

[0053] FIG29 is a structural diagram of the support layer in FIG28;

[0054] FIG30 is a diagram showing the stacked structure of the gate metal layer, active layer, source / drain metal layer, and support layer in FIG28 ;

[0055] FIG31 is another layout structure diagram of the display panel of FIG6 ;

[0056] FIG32 is a cross-sectional view taken along the line H1-H1′ in FIG31;

[0057] FIG33 is a cross-sectional view taken along the line H2-H2' in FIG31;

[0058] FIG34 is a cross-sectional view taken along the line H3-H3' in FIG31;

[0059] FIG35 is a cross-sectional view taken along the line H4-H4' in FIG31;

[0060] FIG36 is a plan view of a display panel according to some other embodiments. DETAILED DESCRIPTION

[0061] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0062] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", or "some examples" and the like are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0063] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0064] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0065] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0066] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0067] As used herein, the term "if" is optionally interpreted to mean "when" or "at the time of" depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining that" depending on the context.

[0068] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0069] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0070] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0071] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0072] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0073] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0074] FIG1 is a schematic diagram of a display device according to some embodiments. As shown in FIG1 , some embodiments of the present disclosure provide a display device 200 , which includes a liquid crystal display panel 100 .

[0075] Exemplarily, the display device 200 further includes a frame, a display driver integrated circuit (English full name: Integrated Circuit, English abbreviation: IC) and other electronic components.

[0076] Exemplarily, the display device 200 may be a liquid crystal display (LCD). In this case, the display device 200 includes a cover plate, a liquid crystal display panel 100, and a backlight assembly. The liquid crystal display panel 100 is positioned between the cover plate and the backlight assembly. The cover plate protects the liquid crystal display panel 100, and the backlight assembly provides light for the liquid crystal display panel 100.

[0077] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0078] 2 is a plan view of a display panel according to some embodiments, FIG. 3 is a cross-sectional view of a display panel according to some embodiments, FIG. 4 is a structural diagram of a display panel according to some embodiments, and FIG. 5 is a layout diagram of the display panel of FIG. 4 .

[0079] 2 to 5 , the liquid crystal display panel 100 has a display area (full name: Active Area, AA area for short; also called effective display area) AA.

[0080] The liquid crystal display panel 100 includes an array substrate 10 , a cell substrate 20 , and a liquid crystal layer 30 disposed between the array substrate 10 and the cell substrate 20 .

[0081] The array substrate 10 includes a first substrate 11 , and a gate metal layer G, an active layer Act, a source / drain metal layer SD, a common electrode layer 12 , and a pixel electrode layer 13 stacked on the first substrate 11 .

[0082] In some examples, the first substrate 11 may be a flexible substrate. For example, the material of the first substrate 11 may be an organic material. For example, the material of the first substrate 11 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0083] In other examples, the first substrate 11 may be a rigid substrate. For example, the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0084] The common electrode layer 12 includes a common electrode 121 , which may be a surface electrode.

[0085] In some examples, the common electrode 121 is a transparent electrode. For example, the common electrode 21 may be made of at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin dioxide (FTD).

[0086] The pixel electrode layer 13 includes a plurality of pixel electrodes 131 . The pixel electrodes 131 may be a comb-tooth structure of a plurality of strip-shaped sub-electrodes.

[0087] In some examples, the pixel electrode 131 is a transparent electrode. For example, the material of the pixel electrode 61 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin dioxide (FTD).

[0088] The orthographic projection of the common electrode 121 on the first substrate 11 at least partially overlaps with the orthographic projection of the pixel electrode 131 on the first substrate 11. The electric field formed between the common electrode 121 and the pixel electrode 131 is used to deflect the liquid crystals in the liquid crystal layer 30 of the display panel 100 to achieve image display.

[0089] The array substrate 10 also includes a plurality of pixel units P, and the plurality of pixel units P are located in the display area AA. For ease of explanation, the present disclosure uses an example of an array arrangement of the plurality of pixel units P. In this case, the pixel units P arranged in a row along the first direction X are referred to as a row of pixel units, and the pixel units P arranged in a row along the second direction Y are referred to as a column of pixel units. Specifically, the plurality of first pixel units P1 are arranged in an array within the first sub-display area AA1, and the plurality of second pixel units P2 are arranged in an array within the second sub-display area AA2, so that the plurality of pixel units P are arranged in an array within the display area AA.

[0090] The first direction X intersects the second direction Y. The first direction X may be substantially parallel to the row direction, and the second direction Y may be substantially parallel to the column direction.

[0091] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and in this case, the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0092] The pixel unit P includes at least one sub-pixel region P0. One sub-pixel region P0 corresponds to the smallest unit for the liquid crystal display panel 100 to display an image.

[0093] In some examples, a pixel unit P may include multiple sub-pixel regions P0. In this case, the display area AA of the liquid crystal display panel 100 includes multiple sub-pixel regions P0. FIG2 illustrates an example in which a pixel unit P includes three sub-pixel regions P0.

[0094] For ease of explanation, the above-mentioned multiple sub-pixel regions P0 are described in this disclosure as being arranged in a matrix. In this case, the sub-pixel regions P0 arranged in a row along the first direction X are referred to as a row of sub-pixel regions, and the sub-pixel regions P0 arranged in a row along the second direction Y are referred to as a column of sub-pixel regions.

[0095] Among them, the multiple sub-pixel areas P0 may include a first color sub-pixel area, a second color sub-pixel area, and a third color sub-pixel area. The first color sub-pixel area, the second color sub-pixel area, and the third color sub-pixel area respectively emit three primary colors of light. For example, the first color sub-pixel area can emit red light, the second color sub-pixel area can emit green light, and the third color sub-pixel area can emit blue light. Based on this, by adjusting the brightness (grayscale) of the color sub-pixel areas of different colors, a variety of colors can be displayed through color combination and superposition, thereby realizing full-color display of the liquid crystal display panel 100.

[0096] In some other examples, one pixel unit P may include one sub-pixel region P0. In this case, the pixel unit P and the sub-pixel region P0 correspond one to one, and the display area AA of the liquid crystal display panel 100 includes multiple sub-pixel regions P0.

[0097] In addition, the array substrate 10 further includes a plurality of signal lines L, which may include a plurality of first signal lines L1 , extending along the first direction X and arranged in the second direction Y. In this example, the first signal lines L1 may be gate lines.

[0098] The plurality of signal lines L may further include a plurality of second signal lines L2 , which extend along the second direction Y and are arranged in the first direction X. Exemplarily, the second signal lines L2 may be data lines.

[0099] In some examples, a row of sub-pixel regions P0 may be connected to a first signal line L1 (gate line), and a column of sub-pixel regions P0 may be connected to a second signal line L2 (data line).

[0100] However, the present disclosure is not limited thereto. In other examples, the first direction X may be substantially parallel to the column direction, and the second direction Y may be substantially parallel to the row direction. Then, the first signal line L1 may be a data line, and the second signal line may be a gate line.

[0101] A pixel circuit W for controlling the sub-pixel region P0 to display is provided in the sub-pixel region P0 . The pixel circuit W is provided on the first substrate 11 .

[0102] Exemplarily, the pixel circuit W includes a drive transistor TD and a liquid crystal capacitor C. The two plates of the liquid crystal capacitor C are respectively formed by a pixel electrode 131 and a common electrode 121. The control electrode of the drive transistor TD is connected to the gate line GL, the first electrode of the drive transistor TD is connected to the liquid crystal capacitor C, and the second electrode of the drive transistor TD is connected to the second signal line L2 (data line) for transmitting the data signal on the second signal line L2 (data line) to the liquid crystal capacitor C. In other words, the electric field formed between the common electrode 121 and the pixel electrode 131 can be used to deflect the liquid crystal in the liquid crystal layer 30 of the display panel 100 to achieve image display.

[0103] However, the inventors have discovered that, because a row of sub-pixel regions P0 can be connected to a single first signal line L1 (gate line), and the common electrode 121 in the common electrode layer 12 is a surface electrode designed as a whole layer, the sub-pixel regions P0 in a row of the liquid crystal display panel 100 are driven simultaneously. Furthermore, the sub-pixel regions P0 in the entire display area AA of the liquid crystal display panel 100 are driven simultaneously. Therefore, the liquid crystal display panel 100 cannot divide the display area AA into at least two areas for independent control, which limits the application scenarios of the liquid crystal display panel 100.

[0104] For example, when the display area AA is divided into two adjacent display sub-areas, neither of the two display sub-areas can be independently controlled. In other words, the LCD panel 100 cannot achieve half-screen driving, which reduces the applicability of the LCD panel 100.

[0105] Figure 6 is a structural diagram of a display panel according to some other embodiments, Figure 7 is a layout structure diagram of the display panel of Figure 6, Figure 8 is a cross-sectional diagram taken along the M1-M1' direction in Figure 7, Figure 9 is a stacked structure diagram of the gate metal layer, active layer and source-drain metal layer in Figure 7, Figure 10 is a stacked structure diagram of the gate metal layer, active layer, source-drain metal layer and common electrode layer in Figure 7, Figure 11 is a stacked structure diagram of the gate metal layer, active layer, source-drain metal layer, common electrode layer and pixel electrode layer in Figure 7, and Figure 12 is a structural diagram of the light-shielding layer in Figure 7.

[0106] Based on this, in conjunction with Figures 6 to 12 , in the liquid crystal display panel 100 provided by some embodiments of the present disclosure, the display area AA may include a first sub-display area AA1 and a second sub-display area AA2 adjacent to each other along the first direction X. The edge of the first sub-display area AA1 adjacent to the second sub-display area AA2 overlaps with the edge of the second sub-display area AA2 adjacent to the first sub-display area AA1.

[0107] The plurality of pixel units P include a plurality of first pixel units P1 located in the first sub-display area AA1 and a plurality of second pixel units P2 located in the second sub-display area AA2. The sub-pixel region P0 in the first pixel unit P is a first sub-pixel region P01, and the sub-pixel region P0 in the second pixel unit P is a second sub-pixel region P02.

[0108] The first signal line L1 includes a first line segment L11 and a second line segment L12, which are disconnected from each other. The first line segment L11 is located in the first sub-display area AA1, and the second line segment L12 is located in the second sub-display area AA2. The first line segment L11 is electrically connected to the first pixel unit P1, so that the first pixel unit P1 located in the first sub-display area AA1 is driven by the first line segment L11 located in the first sub-display area AA1. The second line segment L12 is electrically connected to the second pixel unit P2, so that the second line segment L12 located in the second sub-display area AA2 is driven by the second pixel unit P2 located in the second sub-display area AA2.

[0109] That is, the plurality of first signal lines L1 can be disconnected at the first reference line O. The portion of the first signal line L1 located in the first sub-display area AA1 is a first line segment L11, and the portion of the first signal line L1 located in the second sub-display area AA2 is a second line segment L12. The first reference line O can be the boundary between the first sub-display area AA1 and the second sub-display area AA2.

[0110] Exemplarily, the first reference line O may be the center line of the liquid crystal display panel 100 , so that the number of sub-pixel regions in the first sub-display area AA1 is substantially equal to the number of sub-pixel regions in the second sub-display area AA2 .

[0111] Based on this, the first line segment L11 of the first signal line L1 can be used to connect with multiple first sub-pixel areas P01 located in the first sub-display area AA1 in a row of sub-pixel areas corresponding to the first signal line L1, and the second line segment L12 of the first signal line L1 can be used to connect with multiple second sub-pixel areas P02 located in the second sub-display area AA2 in a row of sub-pixel areas corresponding to the first signal line L1.

[0112] Thus, different segments of the first signal line can be used to drive the sub-pixel regions P0 in different display areas, thereby preventing one first signal line L1 from simultaneously driving all sub-pixel regions P0 in a row of sub-pixel regions in the display area AA.

[0113] The common electrode layer 12 includes a first common electrode C1 located in the first sub-display area AA1 and a second common electrode C2 located in the second sub-display area AA2 .

[0114] That is, the common electrode 121 in the common electrode layer 12 is disconnected at the position of the first reference line O. The portion of the common electrode 121 located in the first sub-display area AA1 is the first common electrode C1 , and the portion of the common electrode 121 located in the second sub-display area AA2 is the second common electrode C2 .

[0115] The orthographic projection of the first common electrode C1 on the first substrate 11 can cover the pixel electrodes 131 in all first sub-pixel regions P01 within the first sub-display area AA1. Therefore, when the first line segment L11 drives the pixel circuit W in the first sub-pixel region P01 to conduct, an electric field can be formed between the first common electrode C1 and the pixel electrodes 131 in the first sub-pixel region P01, thereby causing the liquid crystal in the liquid crystal layer 30 corresponding to the first sub-display area AA1 to deflect, thereby enabling the first sub-display area AA1 of the liquid crystal display panel 100 to display an image.

[0116] In addition, the orthographic projection of the second common electrode C2 on the first substrate 11 can cover the pixel electrodes 131 in all second sub-pixel regions P02 within the second sub-display area AA2. Based on this, when the second line segment L12 drives the pixel circuit W in the second sub-pixel region P02 to conduct, an electric field can be formed between the second common electrode C2 and the pixel electrode 131 in the second sub-pixel region P02, which can further cause the liquid crystal in the liquid crystal layer 30 corresponding to the second sub-display area AA2 to deflect, so that the second sub-display area AA2 of the liquid crystal display panel 100 can realize image display.

[0117] Thus, it is possible to independently drive a portion of the display area AA in the liquid crystal display panel 100 to realize picture realization, thereby achieving partition control of the liquid crystal display panel 100 and improving the applicability of the liquid crystal display panel 100 .

[0118] In some examples, a first gap Q is defined between the first common electrode C1 and the second common electrode C2 along the first direction X, and the first gap Q extends along the second direction Y. This increases the spacing between the first common electrode C1 in the first sub-display area AA1 and the second common electrode C2 in the second sub-display area AA2, thereby reducing mutual coupling between the first common electrode C1 and the second common electrode C2 when the first sub-pixel region P01 in the first sub-display area AA1 is driven alone, or when the second sub-pixel region P02 in the second sub-display area AA2 is driven alone. This prevents light leakage from occurring in undriven sub-display areas, thereby improving the accuracy of zoning control of the liquid crystal display panel 100.

[0119] In some examples, along the first direction X, the width of the first gap Q is greater than or equal to 8 μm.

[0120] When the width of the first slit Q in the first direction X is equal to or close to 8 μm, the width of the first slit Q is relatively large. That is, the distance between the first common electrode C1 located in the first sub-display area AA1 and the second common electrode C2 located in the second sub-display area AA2 is relatively large, which can prevent mutual coupling between the first common electrode C1 and the second common electrode C2, thereby preventing light leakage in the undriven sub-display area.

[0121] For example, the width of the first gap Q is about 8 μm, 8.2 μm, 8.5 μm, 8.8 μm, 9 μm, 9.5 μm, or 10 μm. However, the present disclosure is not limited thereto.

[0122] It should be noted that the example below uses a first gap Q width of approximately 8 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, and measurement errors), the first gap Q can be considered to be 8 μm when its width fluctuates within a range of ±10% × 8 μm.

[0123] In some examples, as shown in Figures 6 to 8 , the alignment substrate 20 further includes a second substrate 22 and a color filter layer (not shown) located on the second substrate 22. In this case, the alignment substrate 20 may also be referred to as a color filter substrate (CF). The color filter layer includes at least a red light-blocking unit, a green light-blocking unit, and a blue light-blocking unit. The red light-blocking unit, the green light-blocking unit, and the blue light-blocking unit are respectively aligned with the sub-pixel regions P0 on the array substrate 10.

[0124] The cell substrate 20 further includes a light shielding layer 21 disposed on the second substrate 22 . The light shielding layer 21 is used to separate the red photoresist unit, the green photoresist unit, and the blue photoresist unit.

[0125] In some examples, the material of the light shielding layer 21 may be a light shielding material. For example, the material of the light shielding layer 21 may be a black resin.

[0126] The light shielding layer 21 includes a first light shielding portion 211 , and an orthographic projection of the first light shielding portion 211 on the first substrate 11 at least partially overlaps with an orthographic projection of the first slit Q on the first substrate 11 .

[0127] In other words, by positioning the first light shielding portion 211 on the side of the first slit Q facing away from the first substrate 11, the first light shielding portion 211 can be used to shield light emitted from the location of the first slit Q, thereby preventing light leakage from occurring at the location of the first slit Q. This further reduces light leakage at the boundary O between the first sub-display area AA1 and the second sub-display area AA2 in the liquid crystal display panel 100, thereby improving the display quality of the liquid crystal display panel 100.

[0128] In summary, the liquid crystal display panel 100 provided in the embodiment of the present disclosure divides the display area AA into two areas: a first sub-display area AA1 and a second sub-display area AA2. The first signal line L1 and the common electrode 121 within the first sub-display area AA1 and the second sub-display area AA2 are truncated, so that the signal lines, electrodes, or other conductive structures within any sub-display area of ​​the display area AA of the liquid crystal display panel 100 are independent structures. This allows for independent driving of a portion of the display area AA of the liquid crystal display panel 100 to realize a display image, thereby achieving zoning control of the liquid crystal display panel 100 and improving the applicability of the liquid crystal display panel 100. In addition, a first light shielding portion 211 corresponding to the first gap Q can be provided on the cell substrate 20 of the liquid crystal display panel 100 to reduce light leakage at the boundary O between the first sub-display area AA1 and the second sub-display area AA2 of the liquid crystal display panel 100, thereby improving the display quality of the liquid crystal display panel 100.

[0129] In some embodiments, as shown in FIG6 to FIG8 , the orthographic projection of the first light shielding portion 211 on the first substrate 11 at least partially overlaps with the orthographic projection of the first slit Q on the first substrate 11 , which may include the following three situations:

[0130] The first type: the orthographic projection of the first light shielding portion 211 on the first substrate 11 overlaps with the orthographic projection of the first slit Q on the first substrate 11 .

[0131] The second type: the boundary of the orthographic projection of the first light shielding portion 211 on the first substrate 11 substantially overlaps with the boundary of the orthographic projection of the first slit Q on the first substrate 11 .

[0132] The third type: the orthographic projection of the first slit Q on the first substrate 11 is located within the boundary of the orthographic projection of the first light shielding portion 211 on the first substrate 11. That is, the orthographic projection of the first light shielding portion 211 on the first substrate 11 covers the orthographic projection of the first slit Q on the first substrate 11.

[0133] In any of the three aforementioned arrangements of the first light shielding portion 211 and the first slit Q, the first light shielding portion 211 can block light emitted from the first slit Q to a certain extent, thereby improving the problem of light leakage at the first slit Q. The larger the size of the first light shielding portion 211, the more light emitted from the first slit Q can be blocked. The third arrangement can block more light emitted from the first slit Q than the first and second arrangements.

[0134] In some examples, when the width of the first slit Q along the first direction X is greater than or equal to 8 μm, the width of the first light shielding portion 211 along the first direction X can be set to be greater than or equal to 8 μm, so as to better realize the second and third setting methods of the above-mentioned first light shielding portion 211 and the first slit Q, so as to block more light emitted from the position of the first slit Q, and improve the problem of light leakage at the boundary line O between the first sub-display area AA1 and the second sub-display area AA2 in the liquid crystal display panel 100.

[0135] In some embodiments, in combination with Figures 6 to 8 and Figure 12, the shading layer 21 further includes a plurality of second shading portions 212 extending along the second direction Y. The second shading portions 212 are used to isolate two adjacent color group units in the first direction X to prevent the colored lights emitted by the two adjacent color group units in the first direction X from interfering with each other, resulting in a color cross-talk problem between two adjacent sub-pixel areas P0.

[0136] It should be noted that the difference between the first light-shielding portion 211 and the second light-shielding portion 212 in the light-shielding layer 21 is that the first light-shielding portion 211 in the light-shielding layer 21 is used to isolate the color group unit located in the first sub-display area AA1 from the color group unit located in the adjacent second sub-display area AA2, thereby improving the problem of light leakage at the boundary O between the first sub-display area AA1 and the second sub-display area AA2. The second light-shielding portion 212 in the light-shielding layer 21 is used to isolate two adjacent color group units in the same sub-display area in the first direction X, thereby preventing the problem of cross-color between two adjacent sub-pixel areas P0 in the same sub-display area.

[0137] In some examples, the orthographic projection of the second signal line L2 on the first substrate 11 at least partially overlaps with the orthographic projection of the second light shielding portion 212 on the first substrate 11. The second light shielding portion 212 can be used to prevent the second signal line L2 from reflecting light and prevent light leakage at the position of the second signal line L2.

[0138] The orthographic projection of the second signal line L2 on the first substrate 11 at least partially overlaps with the orthographic projection of the second light shielding portion 212 on the first substrate 11 , which may include the following three configurations.

[0139] The first type: the orthographic projection of the second signal line L2 on the first substrate 11 partially overlaps with the orthographic projection of the second light shielding portion 212 on the first substrate 11 .

[0140] The second type: the boundary of the orthographic projection of the second signal line L2 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11 .

[0141] The third type: the orthographic projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11 .

[0142] In the three aforementioned arrangements of the second signal line L2 and the second light shielding portion 212, any of the arrangements can utilize the second light shielding portion 212 to reduce light leakage at the location of the second signal line L2 to a certain extent. In the third arrangement, compared to the first and second arrangements, the second light shielding portion 212 can completely cover the second signal line L2, thereby further reducing light leakage at the location of the second signal line L2.

[0143] In some embodiments, as shown in FIG6 , FIG7 , FIG8 and FIG12 , along the first direction X, the width of the first light shielding portion 211 is W1 , the width of the second light shielding portion 212 is W2 , and W1 ≤ 1.5W2 .

[0144] This arrangement ensures that the first light shielding portion 211 completely covers the first gap Q while preventing the first light shielding portion 211 from being too wide, which would result in a large difference between the width of the first light shielding portion 211 and the width of the second light shielding portion 212 and cause a black line to appear at the location of the first light shielding portion 211 in the liquid crystal display panel 100. Therefore, setting the width of the first light shielding portion 211 to be less than or equal to 1.5 times the width of the second light shielding portion 212 is beneficial for improving the quality of the image displayed by the liquid crystal display panel 100.

[0145] In some examples, W1≤1.3W2. Based on this, while ensuring that the first light shielding portion 211 completely covers the first gap Q, the difference between the width of the first light shielding portion 211 and the width of the second light shielding portion 212 can be further reduced to prevent the problem of black lines appearing at the position of the first light shielding portion 211 in the liquid crystal display panel 100.

[0146] For example, W1=1.2W2, W1=1.3W2, W1=1.4W2, or W1=1.5W2. However, the embodiments of the present disclosure are not limited thereto.

[0147] In some embodiments, the light shielding layer 21 further includes a plurality of third light shielding portions 213 extending along the first direction X. The third light shielding portions 213 are used to isolate two adjacent color group units in the second direction Y, thereby preventing the colored light emitted by the two adjacent color group units in the second direction Y from interfering with each other and causing cross-color issues between two adjacent sub-pixel regions P0. The plurality of first light shielding portions 211, the second light shielding portions 212, and the plurality of third light shielding portions 213 in the light shielding layer 21 can surround the light shielding layer 21 in a grid-like pattern.

[0148] In some examples, the orthographic projection of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the third shading portion 213 on the first substrate 11. The third shading portion 213 can be used to prevent the first signal line L1 from reflecting light and prevent light leakage at the position of the first signal line L1.

[0149] The orthographic projection of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 , which may include the following three configurations.

[0150] The first type: the orthographic projection of the first signal line L1 on the first substrate 11 partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0151] The second type: the boundary of the orthographic projection of the first signal line L1 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0152] The third type: the orthographic projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0153] In the three aforementioned arrangements of the first signal line L1 and the third light shielding portion 213, any of the arrangements can utilize the third light shielding portion 213 to reduce light leakage at the location of the first signal line L1 to a certain extent. In the third arrangement, compared to the first and second arrangements, the third light shielding portion 213 can completely cover the first signal line L1, thereby further reducing light leakage at the location of the first signal line L1.

[0154] In some examples, the orthographic projection of the driving transistor TD on the first substrate 11 at least partially overlaps with the orthographic projection of the third shading portion 213 on the first substrate 11. The third shading portion 213 can be used to prevent the driving transistor TD from reflecting light and prevent light leakage at the position of the driving transistor TD.

[0155] The orthographic projection of the driving transistor TD on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 , which may include the following three configurations.

[0156] The first type is that the orthographic projection of the driving transistor TD on the first substrate 11 partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0157] The second type: the boundary of the orthographic projection of the driving transistor TD on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0158] The third type: the orthographic projection of the driving transistor TD on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0159] In the three aforementioned arrangements of the driving transistor TD and the third light shielding portion 213, any of the arrangements can utilize the third light shielding portion 213 to reduce light leakage at the location of the driving transistor TD to a certain extent. In the third arrangement, compared to the first and second arrangements, the third light shielding portion 213 can completely cover the driving transistor TD, thereby further reducing light leakage at the location of the driving transistor TD.

[0160] Figure 13 is another layout structure diagram of the display panel in Figure 6, Figure 14 is a cross-sectional view taken along the M2-M2' direction in Figure 13, Figure 15 is a stacked structure diagram of the gate metal layer, active layer, source / drain metal layer, common electrode layer and pixel electrode layer in Figure 13, and Figure 16 is a structural diagram of the light-shielding layer in Figure 13. Figure 17 is another layout structure diagram of the display panel of Figure 6, Figure 18 is a cross-sectional diagram taken along the M3-M3' direction in Figure 17, Figure 19 is a stacked structure diagram of the gate metal layer and the active layer in Figure 17, Figure 20 is a stacked structure diagram of the gate metal layer, the active layer and the source-drain metal layer in Figure 17, Figure 21 is a structure diagram of the common electrode layer in Figure 17, Figure 22 is a stacked structure diagram of the gate metal layer, the active layer, the source-drain metal layer and the common electrode layer in Figure 17, Figure 23 is a stacked structure diagram of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in Figure 17, and Figure 24 is a structure diagram of the light-shielding layer in Figure 17.

[0161] The difference between the liquid crystal display panel shown in FIG13 and the liquid crystal display panel shown in FIG17 is that the sub-pixel regions are arranged differently, and the specific arrangement will be described in detail below.

[0162] The difference between the liquid crystal display panels shown in Figures 13 and 17 and the liquid crystal display panel 100 shown in Figures 7 and 8 is that in the liquid crystal display panel 100 shown in Figures 7 and 8 , the second signal line L2 in the first sub-display area AA1 and the second signal line L2 in the second sub-display area AA2 are both located on the same side of the column of sub-pixel regions P0 to which they are connected. For example, the second signal line L2 in the first sub-display area AA1 and the second signal line L2 in the second sub-display area AA2 are both located to the left of the column of sub-pixel regions P0 to which they are connected. As a result, the orthographic projection of the second signal line L2 in the second sub-display area AA2, which is closest to the first sub-display area AA1, on the first substrate 11 is located on the side of the orthographic projection of the second common electrode C2 on the first substrate 11 that is closer to the first sub-display area AA1. In other words, the orthographic projection of the second signal line L2 in the second sub-display area AA2, which is closest to the first sub-display area AA1, on the first substrate 11 does not overlap with the orthographic projection of the second common electrode C2 on the first substrate 11.

[0163] Because the orthographic projection of the second signal line L2 on the first substrate 11 does not overlap with the orthographic projection of the second common electrode C2 on the first substrate 11, there is no common electrode layer between the second signal line L2 and the liquid crystal layer. As a result, the electric field generated by the second signal line L2 when transmitting a data signal causes the liquid crystal at the corresponding position in the liquid crystal layer to deflect, resulting in light leakage.

[0164] 7 and 8 , in order to improve the light leakage problem of the LCD panel 100, the width of the first light shielding portion 211 is increased so that the first light shielding portion 211 covers the second signal line L2, thereby preventing light leakage at the location of the second signal line L2. However, increasing the width of the first light shielding portion 211 can easily cause black lines to appear on the LCD panel 100.

[0165] Based on this, in some embodiments, as shown in FIG. 13 to FIG. 20 , a second signal line L2 is disposed on a side of a column of sub-pixel regions P0 electrically connected thereto, away from the first reference line O.

[0166] Since the orthographic projection of the first common electrode C1 on the first substrate 11 can cover the pixel electrodes 131 in all the first sub-pixel areas P01 in the first sub-display area AA1, an electric field is formed between the first common electrode C1 and the pixel electrodes 131 in the first sub-pixel area P01, so as to deflect the liquid crystal in the first sub-display area AA1 in the liquid crystal display panel 100, thereby realizing half-screen display control of the liquid crystal display panel 100.

[0167] Based on this, any second signal line L2 is arranged to be located on the side of the column of sub-pixel regions P0 electrically connected thereto, away from the first reference line O. That is, the second signal line L2 located in the first sub-display area AA1 is located on the side of the column of first sub-pixel regions P01 electrically connected thereto, away from the second sub-display area AA2. This allows the orthographic projection of the second signal line L2 located in the first sub-display area AA1 on the first substrate 11 to be located on a side away from the orthographic projection of the pixel electrode 131 electrically connected thereto, on the first substrate 11.

[0168] Thus, the orthographic projections of the second signal lines L2 in the first sub-display area AA1 on the first substrate 11 can all be located within the boundaries of the orthographic projections of the first common electrodes C1 on the first substrate 11 .

[0169] With this arrangement, the first common electrode C1 can be used to shield the second signal line L2 and the liquid crystal layer to prevent the electric field generated by the second signal line L2 when transmitting the data signal from causing the liquid crystal at the corresponding position of the liquid crystal layer to deflect, thereby causing light leakage.

[0170] The second signal line L2 located in the second sub-display area AA2 is located on the side of a column of second sub-pixel areas P02 to which it is electrically connected, away from the second sub-display area AA2, so that the positive projection of the second signal line L2 located in the second sub-display area AA2 on the first substrate 11 is located on the side of the positive projection of the pixel electrode 131 to which it is electrically connected, away from the positive projection of the first gap Q on the first substrate 11.

[0171] Thus, the orthographic projections of the second signal lines L2 in the second sub-display area AA2 on the first substrate 11 can all be located within the boundaries of the orthographic projections of the second common electrodes C2 on the first substrate 11 .

[0172] With this arrangement, the second common electrode C2 can be used to shield the second signal line L2 and the liquid crystal layer to prevent the electric field generated by the second signal line L2 when transmitting the data signal from causing the liquid crystal at the corresponding position of the liquid crystal layer to deflect, thereby causing light leakage.

[0173] In addition, since the orthographic projections of the first common electrode C1 and the second common electrode C2 on the first substrate 11 can cover the orthographic projections of all second signal lines L2 on the first substrate 11, the common electrode layer 12 can act as a shield. Based on this, there is no need to widen the first light shielding portion 211 to improve the light leakage problem of the liquid crystal display panel 100. Furthermore, the width of the first light shielding portion 211 in the liquid crystal display panel 100 shown in Figures 13 and 17 can be reduced by the line width of one second signal line L2 relative to the width of the first light shielding portion 211 in the liquid crystal display panel 100 shown in Figures 7 and 8. This is conducive to improving the problem of black lines appearing on the liquid crystal display panel 100 and improving the aperture ratio of the liquid crystal display panel 100.

[0174] In some embodiments, as shown in Figures 13 to 24, the driving transistor TD in the sub-pixel region P0 needs to be electrically connected to the first signal line L1, the second signal line L2, and the pixel electrode 131. Specifically, the control electrode g of the driving transistor TD is electrically connected to the first signal line L1, the first electrode s of the driving transistor TD is electrically connected to the pixel electrode, and the second electrode d of the driving transistor TD is electrically connected to the second signal line L2.

[0175] Among them, the driving transistor TD in the first sub-pixel area P01 needs to be electrically connected to the first line segment L11, the second signal line L2 and the pixel electrode 131 respectively, and the positive projections of the pixel electrode 131 and the first common electrode C1 on the first substrate 11 at least partially overlap, so that an electric field is formed between the pixel electrode 131 and the first common electrode C1, so that the liquid crystal in the first sub-display area AA1 is deflected, so as to realize the first sub-display area AA1 in the liquid crystal display panel 100 to display the picture, and the second sub-display area AA2 can display the picture or not according to its internal control.

[0176] The driving transistor TD in the second sub-pixel area P02 needs to be electrically connected to the second line segment L12, the second signal line L2 and the pixel electrode 131 respectively, and the positive projections of the pixel electrode 131 and the second common electrode C2 on the first substrate 11 at least partially overlap, so that an electric field is formed between the pixel electrode 131 and the second common electrode C2, so that the liquid crystal in the second sub-display area AA2 is deflected, so as to realize the second sub-display area AA2 in the liquid crystal display panel 100 to display the picture, and the first sub-display area AA1 can display the picture or not according to its internal control.

[0177] Based on this, the driving transistor TD can be set to be projected on the first substrate 11 and located within the area enclosed by the projected directions of the first signal line L1, the second signal line L2 and the pixel unit P on the first substrate 11, so as to facilitate the electrical connection of the driving transistor TD with the first signal line L1, the second signal line L2 and the pixel electrode 131, thereby reducing the problem of winding of the various film layers in the array substrate and improving the regularity of the array substrate routing.

[0178] The similarities between the liquid crystal display panel shown in FIG13 and the liquid crystal display panel shown in FIG17 include the following: In the liquid crystal display panel 100 shown in FIG13 , in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the first sub-pixel region P01 and the second sub-pixel region P02 are mirror-symmetric about a second reference line. That is, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the drive transistor TD in the first sub-pixel region P01 and the drive transistor TD in the second sub-pixel region P02 are mirror-symmetric about the second reference line. In the liquid crystal display panel shown in FIG17 , in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the drive transistor TD in the first sub-pixel region P01 and the drive transistor TD in the second sub-pixel region P02 are also mirror-symmetric about the second reference line.

[0179] Among them, the second reference line is the center line of the line connecting the first sub-pixel area P01 and the second sub-pixel area P02. The center line can be a line perpendicular to the line connecting the first sub-pixel area P01 and the second sub-pixel area P02, and passing through the center of the line connecting the first sub-pixel area P01 and the second sub-pixel area P02.

[0180] In some embodiments, as shown in Figures 13 and 17, in a first sub-pixel region P01 and a second sub-pixel region P02 arranged along the first direction: the driving transistor TD in the first sub-pixel region P01 is mirror-symmetrical with the driving transistor TD in the second sub-pixel region P02 about the second reference line.

[0181] This arrangement allows the second electrode d of the driving transistor TD in the first sub-pixel region P01 to be closer to the second signal line L2 relative to the pixel electrode 131 in the same first sub-pixel region P01. This facilitates electrical connection between the second electrode d of the driving transistor TD and its corresponding second signal line L2, and also facilitates electrical connection between the first electrode s of the driving transistor TD and its corresponding pixel electrode 131, when any second signal line L2 is located on the side of the column of sub-pixel regions P0 to which it is electrically connected. This also facilitates electrical connection between the first electrode s of the driving transistor TD and its corresponding pixel electrode 131. This facilitates simplifying the wiring layout in the array substrate.

[0182] The difference between the liquid crystal display panel shown in FIG13 and the liquid crystal display panel shown in FIG17 is that in the liquid crystal display panel 100 shown in FIG13 , in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the first sub-pixel region P01 and the second sub-pixel region P02 are mirror-symmetric about the second reference line. That is, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the pixel electrode 131 in the first sub-pixel region P01 and the pixel electrode 131 in the second sub-pixel region P02 are also mirror-symmetric about the second reference line. However, in the liquid crystal display panel shown in FIG17 , in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction, the pixel electrode 131 in the first sub-pixel region P01 and the pixel electrode 131 in the second sub-pixel region P02 do not need to be mirror-symmetric about the second reference line.

[0183] In some embodiments, as shown in conjunction with Figures 17 to 22 , the pixel electrode 131 is a dual-domain pixel electrode, comprising a first domain portion 131A and a second domain portion 131B, wherein the first domain portion 131A and the second domain portion 131B extend in intersecting directions. The corner formed by the intersection of the first domain portion 131A and the second domain portion 131B of the pixel electrode within any first sub-pixel region is a first corner, and the corner formed by the intersection of the first domain portion 131A and the second domain portion 131B of the pixel electrode within any second sub-pixel region is a second corner. The first corner and the second corner protrude in the same direction.

[0184] In other words, the arrangement of all pixel electrodes 131 in the liquid crystal display panel 100 is the same. This arrangement allows the dual-domain pixel electrodes in the first sub-pixel region P01 in the first sub-display area AA1, which is closest to the second sub-display area AA2, to be arranged in the same manner as the dual-domain pixel electrodes in the second sub-pixel region P02 in the second sub-display area AA2, which is closest to the first sub-display area AA1.

[0185] Based on this, the edge of the first common electrode C1 near the second sub-display area AA2 can be arranged along the outline of the dual-domain pixel electrode in the first sub-pixel region P01 in the column closest to the second sub-display area AA2 within the first sub-display area AA1, which is located near the second sub-display area AA2, to form an electric field between the first common electrode C1 and the pixel electrode 131. Similarly, the edge of the second common electrode C2 near the first sub-display area AA1 can be arranged along the outline of the dual-domain pixel electrode in the second sub-pixel region P02 in the column closest to the first sub-display area AA1 within the second sub-display area AA2, which is located near the first sub-display area AA1, to form an electric field between the second common electrode C2 and the pixel electrode 131.

[0186] In the above structure, the first corner corresponding to the dual-domain pixel electrode in the first sub-pixel region P01 closest to the second sub-display region AA2 in the first sub-display region AA1 and the second corner corresponding to the dual-domain pixel electrode in the second sub-pixel region P02 closest to the first sub-display region AA1 in the second sub-display region AA2 protrude in the same direction, and the corresponding common electrodes are also arranged to correspond to the outer contours of the pixel electrodes. Compared to the liquid crystal display panel 100 shown in Figures 13 to 17 , the first corner corresponding to the dual-domain pixel electrode in the first sub-pixel region P01 closest to the second sub-display region AA2 in the first sub-display region AA1 and the second corner corresponding to the dual-domain pixel electrode in the second sub-pixel region P02 closest to the first sub-display region AA1 in the second sub-display region AA2 are arranged in opposite directions, and the corresponding common electrodes are also arranged to correspond to the outer contours of the pixel electrodes. This can help reduce the spacing between the pixel electrodes on the left and right sides of the first reference line O. Furthermore, this can indirectly reduce the first gap Q between the first common electrode C1 and the second common electrode C2. Therefore, the width of the first light shielding portion 211 may be correspondingly reduced to reduce the problem of black lines appearing on the liquid crystal display panel 100 , thereby improving the aperture ratio of the liquid crystal display panel 100 .

[0187] Furthermore, the orientation of the drive transistor TD in the first sub-pixel region P01 and the second sub-pixel region P02 is designed to be mirror-symmetrical, and all other parameters of the drive transistor TD are identical. For example, parameters such as the channel width, channel length, and via size of the drive transistor TD in the first sub-pixel region P01 and the second sub-pixel region P02 are identical.

[0188] In some examples, as shown in Figures 20 to 23, since the common electrode layer 12 is located between the pixel electrode layer 13 and the source and drain metal layer SD, the first electrode s of the driving transistor TD located on the source and drain metal layer SD needs to be electrically connected to the pixel electrode 131 located in the pixel electrode layer 13.

[0189] Based on this, the common electrode on the common electrode layer can be configured to include a plurality of vias K, and the orthographic projection of the pixel electrode 131 on the first substrate 11 can cover the orthographic projection of the hollow region K on the first substrate 11. Based on this, the first electrode s of the drive transistor TD located on the source / drain metal layer SD can be electrically connected to the pixel electrode 131 located in the pixel electrode layer 13 through the hollow region K, thereby preventing the first electrode s of the drive transistor TD from being short-circuited with the common electrode.

[0190] Illustratively, the via holes K on the first common electrode C1 correspond to the pixel electrodes 131 in the first sub-pixel region P01. Similarly, the via holes K on the second common electrode C2 correspond to the pixel electrodes 131 in the second sub-pixel region P02.

[0191] In some embodiments, as shown in combination with FIG. 17 and FIG. 19 , the gate metal layer G may include a first signal line L1 , the first signal line L1 includes a first portion 01 , and the first portion 01 is multiplexed as a control electrode g of the driving transistor TD.

[0192] The first line segment L11 of the first signal line L1 may include a first portion 01 , and the first portion 01 may be multiplexed as a control electrode g of a driving transistor TD electrically connected to the first line segment L11 .

[0193] This configuration eliminates the need to separately form the control electrode g of the driving transistor TD, thereby simplifying the manufacturing process of the liquid crystal display panel 100. Furthermore, there is no need to provide an additional conductive portion to electrically connect the control electrode g of the driving transistor TD to the first line segment L11, thereby simplifying the structure of the driving circuit.

[0194] Similarly, the second line segment L12 of the first signal line L1 may include a first portion 01 , and the first portion 01 may be multiplexed as a control electrode g of the driving transistor TD electrically connected to the second line segment L12 .

[0195] This configuration eliminates the need to separately form the control electrode g of the driving transistor TD, thereby simplifying the manufacturing process of the liquid crystal display panel 100. Furthermore, there is no need to provide an additional conductive portion to electrically connect the control electrode g of the driving transistor TD to the second line segment L12, thereby simplifying the structure of the driving circuit.

[0196] In some examples, as shown in combination with FIG. 17 and FIG. 20 , the source-drain metal layer SD includes a second signal line L2 , the second signal line L2 includes a first sub-portion L21 , and the first sub-portion L21 is multiplexed as the second electrode d of the driving transistor TD.

[0197] This configuration eliminates the need to separately form the second electrode d of the driving transistor TD, thereby simplifying the manufacturing process of the liquid crystal display panel 100. Furthermore, there is no need to provide an additional conductive portion to electrically connect the second electrode d of the driving transistor TD to the second signal line L2, thereby simplifying the structure of the driving circuit.

[0198] In addition, the source / drain metal layer SD may further include a first conductive portion E, which includes a third portion O3. The third portion O3 is multiplexed as the first electrode s of the drive transistor TD. The first conductive portion E, the second electrode d of the drive transistor TD, and the second signal line L2 are designed to be on the same layer, which can simplify the manufacturing process of the liquid crystal display panel 100.

[0199] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0200] FIG25 is a partial enlarged view of I in FIG23 , FIG26 is a cross-sectional view taken along N1-N1′ in FIG25 , and FIG27 is a cross-sectional view taken along N2-N2′ in FIG25 .

[0201] In some embodiments, as shown in Figures 19 to 23 and 25 to 27 , the first signal line L1 may further include a second portion 02 , and the first portion 01 and the second portion 02 on the first signal line L1 are arranged along the first direction X. The orthographic projection of the via K on the first substrate 11 is located between the orthographic projections of the first portion 01 and the second portion 02 of the first signal line L1 on the first substrate 11 .

[0202] In some examples, the first signal line L1 includes a first notch B, which divides the first signal line L1 into a first portion 01 and a second portion 02. The orthographic projection of the first notch B on the first substrate 11 at least partially overlaps with the orthographic projection of the via K on the first substrate 11, thereby preventing the formation of coupling capacitance between the first signal line L1 and the pixel electrode 131 thereover, thereby preventing the problem of increased load.

[0203] In some examples, as shown in Figures 19 to 23 and 25 to 27, the first signal line L1 may further include a first connecting portion 011, which is located within the first notch B. That is, the first connecting portion 011 is located between the first portion 01 and the second portion 02 of the first signal line L1, and is used to connect the first portion 01 and the second portion 02 of the first signal line L1. The orthographic projection of the first connecting portion on the first substrate 11 is located on one side of the orthographic projection of the pixel electrode 131 on the first substrate 11, so that the orthographic projection of the first connecting portion on the first substrate 11 does not overlap with the orthographic projection of the pixel electrode 131 on the first substrate 11, thereby preventing the formation of coupling capacitance between the two, which would increase the load on both.

[0204] The first conductive portion E on the source-drain metal layer SD may further include a fourth portion 04 , and the third portion 03 and the fourth portion 04 of the first conductive portion E are arranged along the first direction X. The first conductive portion E may further include a second connecting portion 012 , which is located between the third portion 03 and the fourth portion 04 of the first conductive portion E and is used to connect the third portion 03 and the fourth portion 04 of the first conductive portion E.

[0205] The orthographic projection of the via K on the first substrate 11 is located between the orthographic projections of the third portion 03 and the fourth portion 04 of the first conductive portion E on the first substrate 11. In other words, the via K can expose the second connecting portion 012 of the first conductive portion E on the source-drain metal layer SD, so that the pixel electrode 131 in the pixel electrode layer 13 can be electrically connected to the second connecting portion 012 of the first conductive portion E through the via K, and further electrically connected to the first electrode s of the driving transistor TD.

[0206] The orthographic projection of the first part 01 of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the third part 03 of the first conductive part E on the first substrate 11, and the orthographic projection of the second part 02 of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the fourth part 04 of the first conductive part E on the first substrate 11.

[0207] Based on the above structure, when an offset occurs between the gate metal layer G and the source-drain metal layer SD in the liquid crystal display panel 100, the coupling capacitance formed between the second portion 02 of the first signal line L1 and the fourth portion 04 of the first conductive part E can be used to compensate for the coupling capacitance formed between the first portion 01 of the first signal line L1 and the third portion 03 of the first conductive part W, so as to improve the problem that the capacitance value of the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 in the liquid crystal display panel 100 and the capacitance value of the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2 are too different.

[0208] Specifically, when the source / drain metal layer SD is offset to the left, the overlap area between the orthographic projection of the first portion O1 of the first signal line L (first line segment L11) located on the metal layer G and the orthographic projection of the third portion O3 (the first electrode s of the drive transistor TD) of the first conductive portion W on the source / drain metal layer SD on the first substrate 11 in the first sub-display area AA1 increases. However, the overlap area between the orthographic projection of the second portion O2 of the first signal line L (first line segment L11) located on the metal layer G and the orthographic projection of the fourth portion O4 of the first conductive portion W on the source / drain metal layer SD on the first substrate 11 decreases. Therefore, regardless of whether an offset occurs between the gate metal layer G and the source / drain metal layer SD in the liquid crystal display panel 100, the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the first sub-display area AA1 can be maintained at a dynamically stable value.

[0209] Similarly, when the source / drain metal layer SD is offset to the left, the overlap area between the orthographic projection of the first portion O1 of the first signal line L (second line segment L12) located on the metal layer G and the orthographic projection of the third portion O3 of the first conductive portion W on the source / drain metal layer SD (the first electrode s of the drive transistor TD) on the first substrate 11 in the second sub-display area AA2 will decrease. However, the overlap area between the orthographic projection of the second portion O2 of the first signal line L (second line segment L12) located on the metal layer G and the orthographic projection of the fourth portion O4 of the first conductive portion W on the source / drain metal layer SD on the first substrate 11 will increase. Therefore, regardless of whether there is an offset between the gate metal layer G and the source / drain metal layer SD in the liquid crystal display panel 100, the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the second sub-display area AA2 can be maintained at a dynamically stable value.

[0210] In summary, since the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 can be maintained at a dynamically stable value, and the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2 can be maintained at a dynamically stable value, the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the display area AA of the liquid crystal display panel 100 can be maintained at a dynamically stable value, thereby alleviating the problem of a large difference in capacitance between the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 and the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2 of the liquid crystal display panel 100.

[0211] In some embodiments, as shown in FIG. 25 and FIG. 26 , the orthographic projection of the fourth portion 04 of the first connecting portion E on the first substrate 11 is located within the boundary of the orthographic projection of the second portion 02 of the first signal line L1 on the first substrate 11 .

[0212] Because the second portion 02 of the first signal line L1 is located in the gate metal layer G, and the fourth portion 04 of the first connection portion E is located in the source / drain metal layer SD, the second portion 02 of the first signal line L1 is located between the fourth portion 04 of the first connection portion E and the first substrate 11. In other words, the second portion 02 of the first signal line L1 is located below the fourth portion 04 of the first connection portion E. Therefore, by arranging the orthographic projection of the fourth portion 04 of the first connection portion E onto the first substrate 11 within the boundary of the orthographic projection of the second portion 02 of the first signal line L1 onto the first substrate 11, this can prevent unevenness below the fourth portion 04 of the first connection portion E, which could occur due to the second portion 02 of the first signal line L1 being located between a portion of the fourth portion 04 of the first connection portion E and the first substrate 11, while not being located between another portion of the fourth portion 04 of the first connection portion E and the first substrate 11. This could lead to various problems caused by the slope of the fourth portion 04 of the first connection portion E, thereby improving the yield of the fourth portion 04 of the first connection portion E.

[0213] In some embodiments, along the first direction X, a length of the fourth portion 04 of the first connecting portion E is greater than or equal to 2 μm.

[0214] When the length of the fourth portion 04 of the first connection portion E along the first direction X is equal to or close to 2 μm, the length of the fourth portion of the first connection portion E can be made larger. This prevents the fourth portion 04 of the first connection portion E located in the first sub-display area AA1 from being close to the orthographic projection of the edge of the second sub-display area AA2 on the first substrate 11 and being located within the boundary of the orthographic projection of the gap B of the first signal line L (first line segment L11) on the first substrate 11, resulting in the orthographic projection of the fourth portion 04 of the first connection portion E on the first substrate 11 not overlapping with the orthographic projection of the second portion 02 of the first signal line L1 (first line segment L11) on the first substrate 11, thereby affecting the formation of coupling capacitance between the gate metal layer G and the source / drain metal layer SD in the first sub-display area AA1. Similarly, it can prevent the fourth portion 04 of the first connection portion E located in the second sub-display area AA2 from being close to the orthographic projection of the edge of the first sub-display area AA1 on the first substrate 11, and being located within the boundary of the orthographic projection of the gap B of the first signal line L (second line segment L12) on the first substrate 11, resulting in the orthographic projection of the fourth portion 04 of the first connection portion E on the first substrate 11 having no overlap with the orthographic projection of the second portion 02 of the first signal line L1 (second line segment L12) on the first substrate 11, thereby affecting the formation of a coupling capacitance between the gate metal layer G and the source / drain metal layer SD in the second sub-display area AA2.

[0215] Therefore, the length of the fourth portion 04 of the first connection portion E is set to be greater than or equal to 2 μm. This allows the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the display area AA of the liquid crystal display panel 100 to maintain a dynamically stable value, thereby improving the problem of a large difference in capacitance between the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the first sub-display area AA1 of the liquid crystal display panel 100 and the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the second sub-display area AA2.

[0216] In some examples, along the first direction X, the length of the fourth portion 04 of the first connection portion E is greater than or equal to 3 μm, and the length of the fourth portion of the first connection portion E can be further increased to ensure that the orthographic projection of the fourth portion of the first connection portion E on the first substrate 11 can overlap with the orthographic projection of the first signal line L1 on the first substrate 11, so that the coupling capacitance formed between the gate metal layer G and the source / drain metal layer SD in the display area AA of the liquid crystal display panel 100 is at a dynamically stable value.

[0217] For example, along the first direction X, the length of the fourth portion 04 of the first connection portion E is approximately 2 μm, 2.5 μm, 3 μm, or 3.5 μm. However, the embodiments of the present disclosure are not limited thereto.

[0218] It should be noted that, in the description, an example is given in which the length of the fourth portion 04 of the first connection portion E is approximately 2.5 μm along the first direction X. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the length of the fourth portion 04 of the first connection portion E can also be considered to be equal to 2.5 μm when the length fluctuates within the range of ±10%×2.5 μm.

[0219] FIG28 is another layout structure diagram of the display panel of FIG6 , FIG29 is a structural diagram of the support layer in FIG28 , and FIG30 is a stacked structure diagram of the gate metal layer, active layer, source / drain metal layer, and support layer in FIG28 . The difference between the liquid crystal display panel shown in FIG28 and the liquid crystal display panel shown in FIG17 is that the liquid crystal display panel 100 in FIG28 schematically illustrates the support layer 23 , while the structures of the other film layers in the liquid crystal display panel 100 can be consistent with those of the other film layers shown in the liquid crystal display panel shown in FIG17 . Therefore, the structures of the other film layers in the liquid crystal display panel shown in FIG28 , except for the support layer, can refer to the structures of the other film layers shown in the liquid crystal display panel shown in FIG17 .

[0220] In some embodiments, as shown in Figures 28 to 30, the liquid crystal display panel 100 also includes a supporting layer 23, and the supporting layer 23 includes a plurality of supporting portions 230. The plurality of supporting portions 230 are located between the array substrate 10 and the matching substrate 20 to support the array substrate 10 and the matching substrate 20.

[0221] Among them, the multiple support parts 230 include multiple first support parts 231 and multiple second support parts 232. The multiple first support parts 231 are located in the first sub-display area AA and the second sub-display area AA2, and the multiple second support parts 232 are located at the intersection (reference line O) of the first sub-display area AA and the second sub-display area AA2, that is, the positive projections of the multiple second support parts 232 on the first substrate 11 are located in the positive projections of the first gap Q on the first substrate 11.

[0222] With such a configuration, multiple first support portions 231 and multiple second support portions 232 can be distributed in various areas of the liquid crystal display panel 100, so as to improve the supporting force of the multiple support portions 230 and prevent the problem of uneven force caused by the lack of support portions 230 in a certain area of ​​the liquid crystal display panel 100, thereby affecting the quality of the liquid crystal display panel 100.

[0223] In some examples, as shown in combination with FIG. 23 and FIG. 28 to FIG. 30 , the orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps with the orthographic projection of the driving transistor TD on the first substrate 11 .

[0224] Such a configuration is equivalent to arranging the first support portion 231 and the driving transistor TD opposite to each other, so as to prevent the first support portion 231 from affecting the light emission of the liquid crystal display panel 100 and affecting the aperture ratio of the liquid crystal display panel 100 .

[0225] The orthographic projection of the first supporting portion 231 on the first substrate 11 at least partially overlaps with the orthographic projection of the driving transistor TD on the first substrate 11 , which may include the following three configurations.

[0226] The first type: the orthographic projection of the first supporting portion 231 on the first substrate 11 partially overlaps with the orthographic projection of the driving transistor TD on the first substrate 11 .

[0227] The second type: the boundary of the orthographic projection of the first supporting portion 231 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the driving transistor TD on the first substrate 11 .

[0228] The third type: the orthographic projection of the first supporting portion 231 on the first substrate 11 is located within the boundary of the orthographic projection of the driving transistor TD on the first substrate 11 .

[0229] In any of the three aforementioned arrangements for the first support portion 231 and the driving transistor TD, the first support portion 231 and the driving transistor TD can overlap in a direction perpendicular to the first substrate, thereby reducing the effect of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100. In the third arrangement, compared to the first and second arrangements, the orthographic projection of the driving transistor TD on the first substrate completely overlaps the orthographic projection of the first support portion 231 on the first substrate, thereby further reducing the effect of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100.

[0230] In some examples, as shown in FIG. 23 and FIG. 28 to FIG. 30 , the orthographic projection of the first supporting portion 231 on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0231] This arrangement is equivalent to arranging the first support portion 231 and the third light shielding portion 213 opposite to each other, so as to prevent the first support portion 231 from affecting the light emission of the liquid crystal display panel 100 and affecting the aperture ratio of the liquid crystal display panel 100 .

[0232] The orthographic projection of the first supporting portion 231 on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 , which may include the following three configurations.

[0233] The first type: the orthographic projection of the first supporting portion 231 on the first substrate 11 partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0234] The second type: the boundary of the orthographic projection of the first supporting portion 231 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0235] The third type: the orthographic projection of the first supporting portion 231 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0236] In any of the three aforementioned arrangements for the first support portion 231 and the third light shielding portion 213, the first support portion 231 and the third light shielding portion 213 can overlap in a direction perpendicular to the first substrate, thereby reducing the effect of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100. In the third arrangement, compared to the first and second arrangements, the orthographic projection of the third light shielding portion 213 on the first substrate completely covers the orthographic projection of the first support portion 231 on the first substrate, thereby further reducing the effect of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100.

[0237] In some examples, as shown in Figures 28 to 30 , the second support portion 232 and the plurality of first support portions 231 are arranged along the first direction X. Along the first direction X, the spacing between two adjacent first support portions 231 is d1, and the spacing between adjacent first support portions 231 and second support portions 232 is d2. Here, |d2-d1|≤0.1d1.

[0238] This arrangement ensures that the ratio of the spacing d2 between adjacent first support portions 231 and second support portions 232 to the spacing d1 between any two adjacent first support portions 231 is less than or equal to 0.1. Consequently, the spacing d2 between adjacent first support portions 231 and second support portions 232 can be minimized compared to the spacing d1 between any two adjacent first support portions 231, thereby reducing the spacing between adjacent support portions 230. Consequently, the distribution of the support portions (first support portions 231 and second support portions 232) in the support layer 23 can be relatively uniform, ensuring a relatively uniform support force across the support layer 23.

[0239] In some examples, as shown in Figures 28 to 30 , the second support portion 232 and the plurality of first support portions 231 are arranged along the first direction X. Along the first direction X, the spacing between two adjacent first support portions 231 is d1, and the spacing between adjacent first support portions 231 and second support portions 232 is d2, where 0 μm ≤ d2 - d1 ≤ 2 μm.

[0240] With such an arrangement, the distance d2 between adjacent first support portions 231 and second support portions 232 can be smaller than the distance d1 between any two adjacent first support portions 231, so as to achieve a smaller distance between two adjacent support portions 230, so that the supporting force of the supporting layer 23 is more uniform, thereby reducing the problem of insufficient supporting force at a certain position of the liquid crystal display panel 100.

[0241] It should be noted that the spacing between the multiple first sub-pixel regions P01 within the first sub-display area AA1 and the multiple second sub-pixel regions P02 within the second sub-display area AA2 can be adjusted to ensure that the orthographic projection of the second support portion 232 on the first substrate 11 is located within the boundary of the orthographic projection of the first gap Q on the first substrate 11, and that 0μm≤d2-d1≤2μm is satisfied. This ensures that the support force provided by the support layer 23 in the liquid crystal display panel 100 is relatively uniform, while also preventing the width of the first gap Q from being too large, which would otherwise cause the appearance of black lines on the liquid crystal display panel 100 due to the correspondingly large width of the first light shielding portion 211.

[0242] The inventors have found that the liquid crystal display panel 100 mainly uses nematic liquid crystals. However, when the operating temperature of the liquid crystal display exceeds the operating temperature range (Tsn-Tni) of the liquid crystal display, the liquid crystal display panel 100 may not operate normally.

[0243] Figure 31 is another layout structure diagram of the display panel in Figure 6, Figure 32 is a cross-sectional view taken along H1-H1' in Figure 31, Figure 33 is a cross-sectional view taken along H2-H2' in Figure 31, Figure 34 is a cross-sectional view taken along H3-H3' in Figure 31, and Figure 35 is a cross-sectional view taken along H4-H4' in Figure 31.

[0244] Based on this, in some embodiments, as shown in conjunction with Figures 31 to 35, the array substrate 10 of the liquid crystal display panel 100 may further include a first metal layer 14, which is located between the source / drain metal layer SD and the common electrode layer 12. In this case, the array substrate 10 includes a first substrate 11, and a gate metal layer G, an active layer Act, a source / drain metal layer SD, a first metal layer 14, a common electrode layer 12, and a pixel electrode layer 13, which are stacked on the first substrate 11. The first metal layer 14 is configured to provide heat to the liquid crystal layer.

[0245] With such a configuration, the first metal layer 14 can be used to provide heat to the liquid crystal layer 30 in the liquid crystal display panel 100 so that the liquid crystal layer 30 in the liquid crystal display panel 100 can be within the operating temperature range of the liquid crystal display, thereby improving the problem that the liquid crystal in the liquid crystal layer 30 of the liquid crystal display panel 100 cannot operate normally due to temperature problems.

[0246] In some examples, a driving current may be applied to the first metal layer 14 . When the driving current flows through the first metal layer 14 , the first metal layer 14 generates corresponding heat, thereby providing heat to the liquid crystal layer 30 .

[0247] It should be noted that the operating temperature range of the liquid crystal display of the liquid crystal layer 30 in the liquid crystal display panel 100 may be Tsn to Tni, where Tsn is the transition temperature between the smectic phase and the nematic phase of the liquid crystal, and Tni is the temperature at which the liquid crystal transitions from the nematic phase to the liquid phase.

[0248] In some examples, the operating temperature range of the liquid crystal layer 30 in the liquid crystal display panel 100 may be -20°C to 75°C. The first metal layer 14 is configured to provide heat to the liquid crystal layer so that the liquid crystal in the liquid crystal layer 30 in the liquid crystal display panel 100 is in an operating environment of -20°C to 75°C, thereby improving the problem of the liquid crystal display panel 100 not being able to operate normally due to temperature.

[0249] In addition, the first metal layer 14 is disposed between the source / drain metal layer SD and the common electrode layer 12 , and the orthographic projections of the first metal layer 14 , the common electrode layer 12 and the liquid crystal layer 30 on the first substrate 11 have overlapping areas.

[0250] Based on this, it is equivalent to setting the common electrode layer 12 between the first metal layer 14 and the liquid crystal layer 30, so as to utilize the common electrode layer 12 to isolate the first metal layer 14 and the liquid crystal layer 30, and prevent the electric field generated by the first metal layer 14 when the driving current flows through it from causing the liquid crystal in the liquid crystal layer 30 to deflect, thereby causing light leakage problems in the liquid crystal display panel 100.

[0251] In some examples, the orthographic projection of the first metal layer 14 on the first substrate 11 is located within the boundary of the orthographic projection of the common electrode layer 12 on the first substrate 11 .

[0252] Thus, the common electrode layer 12 can completely cover the first metal layer 14 to prevent the electric field generated by the first metal layer 14 from causing the liquid crystal in the liquid crystal layer 30 to deflect, thereby causing light leakage in the liquid crystal display panel 100 .

[0253] In some embodiments, as shown in FIG. 31 to FIG. 35 , the first metal layer 14 includes a plurality of first traces 141 . One first trace 141 is provided corresponding to one pixel unit P to provide heat to the liquid crystal at a position corresponding to the pixel unit P.

[0254] The first wiring 141 may be arranged corresponding to a pixel unit P in the following two ways.

[0255] First, the pixel unit P may include a plurality of sub-pixel regions P0. The orthographic projection of a first wiring 141 on the first substrate 11 is located between the orthographic projections of two adjacent pixel units P on the first substrate.

[0256] This arrangement is equivalent to disposing the first routing line 141 corresponding to a side of a sub-pixel region P0 at the outermost side of a pixel unit P, close to its adjacent pixel unit. In other words, the first routing line 141 is disposed along the edge of a sub-pixel region P0 at the outermost side of a pixel unit P. Based on this, the first routing line 141 can be used to provide heat to the liquid crystal at the corresponding position of the pixel unit P, while also reducing the impact of the first routing line 141 on the aperture ratio of the sub-pixel region P0 within the pixel unit P.

[0257] Second, the pixel unit P may include multiple sub-pixel regions P0. The orthographic projection of a first trace 141 on the first substrate 11 is located between any two adjacent sub-pixel regions P0 in a pixel unit P. This configuration prevents the orthographic projection of the first trace 141 on the first substrate 11 from overlapping with the orthographic projection of the opening area of ​​any sub-pixel region P0 in the pixel unit P on the first substrate 11, thereby reducing the aperture ratio of the sub-pixel region P0 in the pixel unit P.

[0258] For example, along the first direction X, the multiple sub-pixel regions P0 within a pixel unit P may be a first color sub-pixel region, a second color sub-pixel region, and a third color sub-pixel region, in sequence. For example, the first color sub-pixel region may emit red light, the second color sub-pixel region may emit green light, and the third color sub-pixel region may emit blue light.

[0259] The orthographic projection of the first wiring 141 on the first substrate 11 can be set to be located between the orthographic projections of the second color sub-pixel region and the third color sub-pixel region on the first substrate 11 in the pixel unit P. Alternatively, the orthographic projection of the first wiring 141 on the first substrate 11 can be set to be located between the orthographic projections of the first color sub-pixel region and the second color sub-pixel region on the first substrate 11 in the pixel unit P.

[0260] With this configuration, the first wiring 141 can be used to provide heat to the liquid crystal at the corresponding position of the pixel unit P, and the influence of the first wiring 141 on the aperture ratio of the sub-pixel region P0 in the pixel unit P can be reduced.

[0261] In some embodiments, as shown in FIG. 31 to FIG. 35 , the orthographic projection of the first trace 141 on the first substrate 11 does not overlap with the orthographic projection of the driving transistor TD of any sub-pixel region P0 on the first substrate 11 .

[0262] Since one first line 141 corresponds to one pixel unit P, rather than one first line 141 corresponding to one sub-pixel region P0, the orthographic projection of the first line 141 on the first substrate 11 is arranged so as not to overlap with the orthographic projection of the drive transistor TD of any sub-pixel region P0 on the first substrate 11. This prevents the first line 141 from passing through the drive transistor TD of a sub-pixel region P0 within a pixel unit P, causing the temperature of the drive transistor TD to be higher than that of other sub-pixel regions P0, resulting in different heating of the drive transistors TD in different sub-pixel regions P0 and causing display abnormalities.

[0263] In some embodiments, as shown in Figures 31 to 35 , the first trace 141 is disposed opposite the second signal line L2. That is, the first trace 141 is disposed along the extension direction of the second signal line L2, and the orthographic projection of the first trace 141 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11.

[0264] In this way, the first routing line 141 and the second signal line L2 are centrally arranged, and the orthographic projection of the second light shielding portion 212 on the first substrate 11 can be realized without increasing the width of the second light shielding portion 212, so as to cover the orthographic projection of the first routing line 141 and the second signal line L2 on the first substrate 11, thereby preventing light leakage at the positions of the first routing line 141 and the second signal line L2.

[0265] The orthographic projection of the first trace 141 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11 , which includes the following three configurations.

[0266] The first type: the orthographic projection of the first trace 141 on the first substrate 11 partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11 .

[0267] The second type: the boundary of the orthographic projection of the first trace 141 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the second signal line L2 on the first substrate 11 .

[0268] The third type: the orthographic projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthographic projection of the first trace 141 on the first substrate 11 .

[0269] In the above three configurations of the first trace 141 and the second signal line L2, the width of the first trace 141 gradually increases. However, the disclosed embodiment is not limited thereto, and the width of the first trace 141 can be adjusted according to actual needs.

[0270] In some embodiments, as shown in FIG. 31 to FIG. 35 , the orthographic projection of the first trace 141 on the first substrate 11 is located within the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11 .

[0271] With this arrangement, the orthographic projection of the second light shielding portion 212 on the first substrate 11 can be utilized to completely cover the orthographic projection of the first trace 141 on the first substrate 11, thereby utilizing the second light shielding portion 212 to block light and prevent light leakage at the location of the first trace 141. It is understood that the maximum width of the first trace 141 can be the width of the second light shielding portion 212 to prevent the orthographic projection of a portion of the first trace 141 on the first substrate 11 from overlapping with the orthographic projection of the second light shielding portion 212 on the first substrate 11, thereby preventing the second light shielding portion 212 from being unable to completely block the first trace 141 and causing light leakage.

[0272] In some embodiments, in combination with Figures 31 to 35, when the first routing line 141 is arranged along the extension direction of the second signal line L2, a first routing line 141 can be set on the side of a column of pixel units P away from the first reference line O, and the first reference line O is the boundary line between the first sub-display area AA1 and the second sub-display area AA2.

[0273] This arrangement eliminates the need for first traces 141 at locations corresponding to the first slits Q. This facilitates ensuring that the orthographic projections of all first traces 141 in the first metal layer 14 on the first substrate 11 are located within the boundaries of the orthographic projection of the common electrode layer 12 on the first substrate 11. This prevents the electric field generated by the first metal layer 14 from causing deflection of the liquid crystal in the liquid crystal layer 30, which could lead to light leakage in the liquid crystal display panel 100. Furthermore, there is no need to increase the width of the first light shielding portion 211 to prevent light leakage at the locations of the first slits Q, thereby reducing the problem of black lines in the liquid crystal display panel 100.

[0274] In other embodiments, the first trace 141 is disposed opposite to the first signal line L1. That is, the first trace 141 is disposed along the extension direction of the first signal line L1, and the orthographic projection of the first trace 141 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11.

[0275] In this way, the first routing line 141 and the first signal line L1 are centrally arranged, and the orthographic projection of the second shading portion 212 on the first substrate 11 can be realized without increasing the width of the second shading portion 212, so as to cover the orthographic projection of the first routing line 141 and the first signal line L1 on the first substrate 11, thereby preventing light leakage at the positions of the first routing line 141 and the first signal line L1.

[0276] The orthographic projection of the first trace 141 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11 , which includes the following three configurations.

[0277] The first type: the orthographic projection of the first trace 141 on the first substrate 11 partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11 .

[0278] The second type: the boundary of the orthographic projection of the first trace 141 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the first signal line L1 on the first substrate 11 .

[0279] The third type: the orthographic projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthographic projection of the first trace 141 on the first substrate 11 .

[0280] In the above three configurations of the first trace 141 and the first signal line L1, the width of the first trace 141 gradually increases. However, the disclosed embodiment is not limited thereto, and the width of the first trace 141 can be adjusted according to actual needs.

[0281] It should be noted that when the first trace 141 is arranged along the extension direction of the first signal line L1, the first trace 141 also needs to be disconnected at the reference line O. This ensures that the portion of the first trace 141 located within the first sub-display area AA1 corresponds to the first line segment L11, and the portion of the first trace 141 located within the second sub-display area AA2 corresponds to the second line segment L12. This prevents the portion of the first trace 141 corresponding to the first slit Q from being shielded by the common electrode layer 12, which could cause liquid crystal deflection at the location corresponding to the first slit Q and lead to light leakage.

[0282] In some embodiments, when the first trace 141 is arranged opposite to the first signal line L1 , the orthographic projection of the first trace 141 on the first substrate 11 may be arranged within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0283] With this arrangement, the orthographic projection of the third light shielding portion 213 on the first substrate 11 can be utilized to completely cover the orthographic projection of the first trace 141 on the first substrate 11, thereby utilizing the third light shielding portion 213 to block light and prevent light leakage at the location of the first trace 141. It is understood that the maximum width of the first trace 141 can be the width of the third light shielding portion 213 to prevent the orthographic projection of a portion of the first trace 141 on the first substrate 11 from overlapping with the orthographic projection of the third light shielding portion 213 on the first substrate 11, thereby preventing the third light shielding portion 213 from being unable to completely block the first trace 141 and causing light leakage.

[0284] In yet other embodiments, the plurality of first traces 141 in the first metal layer 14 may form a grid structure. That is, the plurality of first traces 141 may include two portions of first traces 141: one portion corresponding to the first signal line L1, and one portion corresponding to the second signal line L2. This arrangement allows the first traces 141 in the first metal layer 14 to be uniformly distributed, thereby achieving uniform heating of the liquid crystal in the liquid crystal layer 30. However, the disclosed embodiments are not limited thereto.

[0285] It should be noted that, with respect to the above-mentioned configuration in which the first wiring 141 corresponds only to the first signal line L1, or the configuration in which the first wiring 141 corresponds only to the second signal line L2, multiple first wirings 141 can be set up and connected in series with each other, which can facilitate the transmission of driving current to the first wiring 141. In addition, it can also be beneficial to the layout of wiring in the peripheral area of ​​the liquid crystal display panel 100. For example, four first wirings 141 can be set up and connected in series with each other. Based on this, the number of wirings in the peripheral area of ​​the liquid crystal display panel 100 can be reduced by 75%, thereby realizing the transmission of driving current to each first wiring 141. However, the embodiments of the present disclosure are not limited to this.

[0286] In some embodiments, as shown in Figures 31 to 35, the array substrate 10 may further include a first insulating layer 15, which is located between the gate metal layer G and the active layer Act, so as to utilize the first insulating layer 15 to electrically insulate the gate metal layer G and the active layer Act.

[0287] Exemplarily, the material of the first insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0288] The array substrate 10 may further include a second insulating layer, which may be an organic layer 16 . The organic layer 16 is located between the source / drain metal layer SD and the first metal layer 14 , so as to electrically insulate the source / drain metal layer SD from the first metal layer 14 .

[0289] For example, the organic layer 16 may include at least one of a photosensitive agent, an acrylic resin, and an organic solvent. However, the present disclosure is not limited thereto.

[0290] In addition, when the second insulating layer is set as an organic layer 16, compared with setting the second insulating layer as an insulating layer composed of any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide, the dielectric constant of the organic layer 16 of 3.2 can be significantly lower than the dielectric constant of 6.5 of the insulating layer (SiNx).

[0291] Furthermore, because the orthographic projection of the source / drain metal layer SD on the first substrate 11 overlaps with the orthographic projection of the first metal layer 14 on the first substrate 11, a coupling capacitance is formed between the source / drain metal layer SD and the first metal layer 14. According to the capacitance calculation formula C = εS / 4πkd, the smaller the dielectric constant ε of the second insulating layer, the smaller the coupling capacitance between the source / drain metal layer SD and the first metal layer 14, thereby alleviating the problem of increased load on both the source / drain metal layer SD and the first metal layer 14. In other words, configuring the second insulating layer as an organic layer 16 can effectively reduce the coupling capacitance between the source / drain metal layer SD and the first metal layer 14, and thus alleviate the problem of increased load on both, compared to configuring the second insulating layer as an insulating layer composed of any of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.

[0292] In some examples, k is a constant, d is the thickness of the second insulating layer (organic layer 16), and S is the overlapping area. The overlapping area may include the positive projection of the first electrode s and the second electrode d of the driving transistor TD located in the source-drain metal layer SD on the first substrate 11, and the overlapping area formed by the positive projection of the first trace 141 located in the first metal layer 14 on the first substrate 11.

[0293] Based on this, setting the second insulating layer as an organic layer 16 can effectively reduce the coupling capacitance formed between the driving transistor TD and the first wiring 141, reduce the load of the driving transistor TD, and improve the stability of the driving transistor TD, compared to setting the second insulating layer as an insulating layer composed of any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.

[0294] Furthermore, the overlapping area may also include the overlapping area formed by the orthographic projection of the second signal line L2 in the source / drain metal layer SD on the first substrate 11 and the orthographic projection of the first trace 141 in the first metal layer 14 on the first substrate 11 .

[0295] Based on this, setting the second insulating layer as an organic layer 16 can effectively reduce the coupling capacitance formed between the second signal line L2 and the first wiring 141, reduce the load of the second signal line L2, and reduce the problem of poor display of the liquid crystal display panel 100, compared with setting the second insulating layer as an insulating layer composed of any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.

[0296] In other examples, k is a constant, d is the thickness of the second insulating layer (organic layer 16), and S is the overlapping area. The overlapping area can be the overlapping area formed by the positive projection of the first electrode s and the second electrode d of the driving transistor TD in the source-drain metal layer SD on the first substrate 11, and the positive projection of the common electrode (the first common electrode C1 or the second common electrode C2) in the common electrode layer 12 on the first substrate 11.

[0297] Based on this, setting the second insulating layer as an organic layer 16 can effectively reduce the coupling capacitance formed between the driving transistor TD and the common electrode (the first common electrode C1 or the second common electrode C2), reduce the load of the driving transistor TD, and improve the stability of the driving transistor TD, compared to setting the second insulating layer as an insulating layer composed of any one of the inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.

[0298] In addition, the overlapping area may also include the overlapping area formed by the orthographic projection of the second signal line L2 located in the source / drain metal layer SD on the first substrate 11 and the orthographic projection of the common electrode (first common electrode C1 or second common electrode C2) located in the common electrode layer 12 on the first substrate 11.

[0299] Based on this, setting the second insulating layer as an organic layer 16 can effectively reduce the coupling capacitance formed between the second signal line L2 and the common electrode (the first common electrode C1 or the second common electrode C2), reduce the load of the second signal line L2, and reduce the problem of poor display of the liquid crystal display panel 100, compared to setting the second insulating layer as an insulating layer composed of any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.

[0300] In some examples, when the second insulating layer is an insulating layer composed of any one of the inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide, due to the limitation of the material, in order to prevent the second insulating layer from being separated, the thickness of the second insulating layer is in the range of approximately When the second insulating layer is an organic layer 16, the thickness of the second insulating layer (organic layer 16) ranges from

[0301] When the thickness of the organic layer 16 is When the thickness of the organic layer 16 is within the range of 0.0447° and 0.0800°, the thickness of the organic layer 16 can be made thicker, which can facilitate increasing the distance between the source / drain metal layer SD and the first metal layer 14 to prevent the formation of coupling capacitance between the source / drain metal layer SD and the first metal layer 14, which would increase the load and affect the display. Furthermore, the distance between the source / drain metal layer SD and the common electrode layer 12 can be increased to prevent the formation of coupling capacitance between the source / drain metal layer SD and the common electrode layer 12, which would increase the load and affect the display.

[0302] In some examples, the thickness of the organic layer 16 may range from

[0303] Such a setting can make the thickness of the organic layer 16 thicker, thereby increasing the spacing between the source and drain metal layer SD, the first metal layer 14 and the common electrode layer 12, and reducing the coupling capacitance formed between the source and drain metal layer SD, the first metal layer 14 and the common electrode layer 12; and can also meet the process requirements for manufacturing the organic layer 16.

[0304] For example, the thickness of the organic layer 16 is approximately However, the embodiments of the present disclosure are not limited thereto.

[0305] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness of the organic layer 16 is approximately As an example, the thickness of the organic layer 16 is When the thickness of the organic layer 16 fluctuates within the range of

[0306] In some embodiments, in combination with Figures 31 to 35, when the second insulating layer is an organic layer 16, the array substrate 10 can be set to also include a first protective layer (not shown in the figure) and a second protective layer (not shown in the figure), and the first protective layer and the second protective layer are respectively located on both sides of the organic layer 16.

[0307] In some examples, the material of the first protective layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first protective layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0308] In some examples, the material of the second protective layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second protective layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0309] The adhesion between the first and second protective layers and the metal layer is stronger than the adhesion between the organic layer 16 and the metal layer. Therefore, the first protective layer is positioned between the source / drain metal layer SD and the organic layer 16. The first protective layer can be used to improve the adhesion between the source / drain metal layer SD and the organic layer 16, thereby improving the stability between the source / drain metal layer SD and the organic layer 16.

[0310] Furthermore, a second protective layer may be provided between the organic layer 16 and the first metal layer 14 . The second protective layer may be used to improve the adhesion between the organic layer 16 and the first metal layer 14 , thereby improving the stability between the organic layer 16 and the first metal layer 14 .

[0311] In some examples, the thickness of the first protective layer can range from When the thickness of the first protective layer is When it is within the range, the thickness of the first protective layer is relatively moderate, which can not only meet the process accuracy requirements for manufacturing the first protective layer, but also achieve the fixation of the organic layer 16 and the source and drain metal layer SD, and will not cause the problem of excessive thickness of the first protective layer leading to waste of resources.

[0312] For example, the thickness of the first protective layer is approximately or However, the embodiments of the present disclosure are not limited thereto.

[0313] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness of the first protective layer is approximately As an example, the thickness of the first protective layer is When the thickness of the first protective layer fluctuates within the range, it can also be considered that the thickness of the first protective layer satisfies

[0314] In some examples, the thickness of the second protective layer can range from When the thickness of the second protective layer is When it is within the range, the thickness of the second protective layer is relatively moderate, which can not only meet the process accuracy requirements for manufacturing the second protective layer, but also fix the organic layer 16 and the first metal layer 14, and will not cause the problem of excessive thickness of the second protective layer leading to waste of resources.

[0315] For example, the thickness of the second protective layer is approximately or However, the embodiments of the present disclosure are not limited thereto.

[0316] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness of the second protective layer is approximately As an example, the thickness of the second protective layer is When the thickness of the second protective layer fluctuates within the range, it can also be considered that the thickness of the second protective layer satisfies

[0317] In some embodiments, the array substrate 10 may further include a third insulating layer 17 . The third insulating layer 17 is located between the first metal layer 14 and the common electrode layer 12 , so that the first metal layer 14 and the common electrode layer 12 are electrically insulated by the third insulating layer 17 .

[0318] For example, the material of the third insulating layer 17 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0319] In some embodiments, the array substrate 10 may further include a fourth insulating layer 18 located between the common electrode layer 12 and the pixel electrode layer 13 , so as to electrically insulate the common electrode layer 12 from the pixel electrode layer 13 using the third insulating layer 17 .

[0320] For example, the material of the fourth insulating layer 18 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0321] In some feasible embodiments, taking the common electrode layer 12 as an example, the material of indium tin oxide is higher than the resistivity of metal, which results in a larger resistance of the first common electrode C1 and the second common electrode C1 in the common electrode layer 12, thereby causing crosstalk and greenish phenomenon in the array substrate 10, affecting the picture quality of the liquid crystal display panel.

[0322] Based on this, in some embodiments, in combination with Figures 31 to 35, the array substrate 10 may further include an auxiliary electrode 19 layer, which is located on the side of the common electrode layer 12 away from the first substrate 11, and the auxiliary electrode layer 19 is in contact with the common electrode layer 12.

[0323] With this configuration, the auxiliary electrode layer 19 can be connected to the common electrode layer 12 to reduce the resistance of the common electrode layer 12. This can reduce the voltage fluctuation problem caused by the second signal line L2 on the first and second common electrodes C1 and C2 in the common electrode layer 12.

[0324] In addition, by directly forming the auxiliary electrode layer 19 on the side of the common electrode layer 12 facing away from the first substrate 11 , the auxiliary electrode layer 19 can be formed without increasing the number of masks used in manufacturing the array substrate 10 .

[0325] Specifically, the common electrodes (first common electrode C1 and second common electrode C2 ) of the common electrode layer 12 and the auxiliary electrode 191 of the auxiliary electrode layer 19 may be formed by a single photolithography process using a half-tone mask (HTM).

[0326] In some examples, since metal materials have low resistance, the auxiliary electrode layer 19 may be made of metal materials to further reduce the resistance of the common electrode layer 12 .

[0327] For example, the metal material may include copper or aluminum, etc. However, the embodiments of the present disclosure are not limited thereto.

[0328] In some embodiments, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 is located within the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11 .

[0329] With this arrangement, the orthographic projection of the second light shielding portion 212 on the first substrate 11 can be utilized to completely cover the orthographic projection of the auxiliary electrode 191 on the first substrate 11, so that the second light shielding portion 212 can block light and prevent light leakage at the location of the auxiliary electrode 191. It is understood that the maximum width of the auxiliary electrode 191 can be the width of the second light shielding portion 212 to prevent the orthographic projection of a portion of the auxiliary electrode 191 on the first substrate 11 from overlapping with the orthographic projection of the second light shielding portion 212 on the first substrate 11, which would result in the second light shielding portion 212 being unable to completely block the auxiliary electrode 191 and cause light leakage.

[0330] In some examples, the auxiliary electrode layer 19 includes a plurality of auxiliary electrodes 191 , and an orthographic projection of the auxiliary electrodes 191 on the first substrate 11 at least partially overlaps with an orthographic projection of the second signal line L2 on the first substrate 11 .

[0331] In this way, the auxiliary electrode 191 and the second signal line L2 are centrally arranged, and the orthographic projection of the second light-shielding portion 212 on the first substrate 11 can be realized without increasing the width of the second light-shielding portion 212, thereby covering the orthographic projection of the auxiliary electrode 191 and the second signal line L2 on the first substrate 11, so as to prevent light leakage at the positions of the auxiliary electrode 191 and the second signal line L2.

[0332] The orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11 , including the following three configurations.

[0333] The first type: the orthographic projection of the auxiliary electrode 191 on the first substrate 11 partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11 .

[0334] The second type: the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the second signal line L2 on the first substrate 11 .

[0335] The third type: the orthographic projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11 .

[0336] In the above three configurations of the auxiliary electrode 191 and the second signal line L2, the width of the auxiliary electrode 191 gradually increases. However, the embodiment of the present disclosure is not limited thereto, and the width of the auxiliary electrode 191 can be adjusted according to actual needs.

[0337] It should be noted that when the auxiliary electrode 191 is arranged along the extension direction of the second signal line L2, the auxiliary electrode 191 also needs to be disconnected at the reference line O. This ensures that the portion of the auxiliary electrode 191 located within the first sub-display area AA1 corresponds to the first line segment L11, and the portion of the auxiliary electrode 191 located within the second sub-display area AA2 corresponds to the second line segment L12. This prevents the portion of the auxiliary electrode 191 corresponding to the first slit Q from being shielded by the common electrode layer 12, which could cause liquid crystal deflection at the location corresponding to the first slit Q and lead to light leakage.

[0338] In some other embodiments, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11 .

[0339] With this arrangement, the orthographic projection of the third light-shielding portion 213 on the first substrate 11 can be used to completely cover the orthographic projection of the auxiliary electrode 191 on the first substrate 11, so that the third light-shielding portion 213 can block light and prevent light leakage at the location of the auxiliary electrode 191. It is understood that the maximum width of the auxiliary electrode 191 can be the width of the third light-shielding portion 213 to prevent the orthographic projection of a portion of the auxiliary electrode 191 on the first substrate 11 from overlapping with the orthographic projection of the third light-shielding portion 213 on the first substrate 11, which would result in the third light-shielding portion 213 being unable to completely block the auxiliary electrode 191 and cause light leakage.

[0340] In some examples, the auxiliary electrode 191 is disposed opposite to the first signal line L1. That is, the auxiliary electrode 191 is disposed along the extension direction of the first signal line L1, and the orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11.

[0341] In this way, the auxiliary electrode 191 and the first signal line L1 are centrally arranged, and the orthographic projection of the second light-shielding portion 212 on the first substrate 11 can be realized without increasing the width of the second light-shielding portion 212, thereby covering the orthographic projection of the auxiliary electrode 191 and the first signal line L1 on the first substrate 11, so as to prevent light leakage at the positions of the auxiliary electrode 191 and the first signal line L1.

[0342] The orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11 , including the following three configurations.

[0343] The first type: the orthographic projection of the auxiliary electrode 191 on the first substrate 11 partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11 .

[0344] The second type: the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the first signal line L1 on the first substrate 11 .

[0345] The third type: the orthographic projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11 .

[0346] In the above three configurations of the auxiliary electrode 191 and the first signal line L1, the width of the auxiliary electrode 191 gradually increases. However, the embodiment of the present disclosure is not limited thereto, and the width of the auxiliary electrode 191 can be adjusted according to actual needs.

[0347] It should be noted that when the auxiliary electrode 191 is arranged along the extension direction of the first signal line L1, the auxiliary electrode 191 also needs to be disconnected at the reference line O. This ensures that the portion of the auxiliary electrode 191 located within the first sub-display area AA1 corresponds to the first line segment L11, and the portion of the auxiliary electrode 191 located within the second sub-display area AA2 corresponds to the second line segment L12. This prevents the portion of the auxiliary electrode 191 corresponding to the first slit Q from being shielded by the common electrode layer 12, which could cause liquid crystal deflection at the location corresponding to the first slit Q and lead to light leakage.

[0348] In yet other embodiments, the plurality of auxiliary electrodes 191 in the auxiliary electrode layer 19 may form a grid structure. That is, the plurality of auxiliary electrodes 191 may include two portions of auxiliary electrodes 191: one portion corresponding to the first signal line L1, and the other portion corresponding to the second signal line L2. This arrangement allows the auxiliary electrodes 191 in the first metal layer 14 to be uniformly distributed, thereby achieving uniform heating of the liquid crystals in the liquid crystal layer 30. However, the disclosed embodiments are not limited thereto.

[0349] In some embodiments, as shown in Figures 2 and 31, when the liquid crystal display panel 100 is a conventional liquid crystal display panel, for example, when the shape of the liquid crystal display panel 100 is rectangular, the length of each first trace 141 can be set to be equal, and then the width of each first trace 141 can be set to be equal, so that the heat provided by each first trace 141 is roughly equal, so that the first metal layer 14 can uniformly provide heat to the liquid crystal at various positions in the liquid crystal layer of the liquid crystal display panel 100, thereby preventing poor display problems in the liquid crystal display panel 100 due to uneven heating.

[0350] FIG36 is a plan view of a display panel according to some other embodiments.

[0351] In other embodiments, as shown in Figures 31 and 36, the liquid crystal display panel 100 is an irregular liquid crystal display panel, and the multiple first lines 141 include at least two first lines 141 of unequal lengths along the second direction Y. Among the two first lines 141 of unequal lengths, the length of the first first line 141 is greater than the length of the second first line 141, and the line width of the first first line 141 is greater than the line width of the second first line 141.

[0352] Since the heating effect of the first trace 141 depends on the heating power P, and the heating power of the first trace 141 is related to the resistance R of the first trace 141. It can be seen from the calculation formula that the length of the first trace 141 is inversely proportional to the width of the first trace 141 , where W is the length of the first trace 141 , L is the width of the first trace 141 , and Rs is the square resistance of the first trace 141 .

[0353] Based on this, the longer length of the first trace 141 results in a higher heating power for the first trace 141. Therefore, the longer first trace 141 can be configured with a longer width, so that the heating power for the first trace 141 can be reduced by increasing the width of the first trace 141. In other words, the width of the first trace 141 along the first direction X can be adjusted accordingly based on the length of the first trace 141 along the second direction Y, so as to reduce the difference in resistance between any two first traces 141 and reduce the difference in heating power between any two first traces 141, thereby improving the heating uniformity of the liquid crystal display panel 100.

[0354] It should be noted that the special-shaped LCD panel can be an irregular-shaped LCD panel. For example, the display area AA in the special-shaped LCD panel 100 includes a special-shaped boundary S1, and the special-shaped boundary S1 extends non-linearly. For example, the special-shaped boundary S1 can be an arc.

[0355] In some embodiments, the first sub-display area AA1 of the liquid crystal display panel 100 includes a plurality of regions along a direction away from the first reference line O, and the number of first traces 141 in each region is substantially equal.

[0356] When the length of the first trace 141 in each region gradually increases along the direction approaching the first reference line O, the width of the first trace 141 in each region may be correspondingly set to gradually increase.

[0357] With such a configuration, the resistance of the first trace 141 in multiple areas within the first sub-display area AA1 can gradually change, and the heating power of the first trace 141 in multiple areas within the first sub-display area AA1 can gradually change, thereby improving the heating uniformity of the liquid crystal display panel 100.

[0358] In addition, the second sub-display area AA2 can be similarly configured with reference to the configuration of the first traces 141 in each area of ​​the first sub-display area AA1, which will not be described in detail here.

[0359] In some embodiments, in combination with Figures 31 and 36, among the multiple first lines 141 arranged along the direction close to the first reference line O in the first sub-display area AA1 of the liquid crystal display panel 100, the lengths of the multiple first lines 141 in the second direction Y gradually increase. The lengths of the multiple first lines 141 in the second direction Y gradually increase, so that the differences between the multiple first lines 141 can be gradually changed to prevent the problem of large differences between two adjacent first lines 141, which leads to large differences in the heating power of the two first lines 141.

[0360] In addition, among the multiple first lines 141 arranged along the direction close to the first reference line O in the first sub-display area AA1 of the liquid crystal display panel 100, the lengths of the multiple first lines 141 in the second direction Y gradually increase, and the widths of the multiple first lines 141 in the first direction X can be set to gradually increase accordingly.

[0361] That is, the width of the first line 141 along the first direction X can be adjusted accordingly according to the length of the first line 141 along the second direction Y, so as to reduce the resistance difference between two adjacent first lines 141 and reduce the resistance difference of multiple first lines 141, so that the heating power of the multiple first lines 141 is roughly equal, which is beneficial to improving the heating uniformity of the first sub-display area AA1 of the liquid crystal display panel 100.

[0362] Furthermore, the second sub-display area AA2 can be similarly configured with reference to the arrangement of the first traces 141 in each area within the first sub-display area AA1. Specifically, within the second sub-display area AA2, the plurality of first traces 141 arranged along a direction close to the first reference line O can have their lengths gradually increase in the second direction Y, and accordingly, the plurality of first traces 141 can have their widths gradually increase in the first direction X.

[0363] That is, the width of the first line 141 along the first direction X can be adjusted accordingly according to the length of the first line 141 along the second direction Y, so as to reduce the resistance difference between two adjacent first lines 141 and reduce the resistance difference of multiple first lines 141, so that the heating power of the multiple first lines 141 is roughly equal, which is beneficial to improving the heating uniformity of the second sub-display area AA2 of the liquid crystal display panel 100.

[0364] By disposing the first traces 141 in the first sub-display area AA1 and the second sub-display area AA2 as described above, the heating uniformity of the liquid crystal display panel 100 can be improved.

[0365] 31 and 36 , the lengths of the plurality of first traces 141 of the liquid crystal display panel 100 gradually decrease in a direction away from the first reference line O. An example in which n first traces 141 are included in the first sub-display area AA1 is used for description.

[0366] In the first sub-display area AA1 , the first routing line 141 farthest from the first reference line O is the first first routing line 141_1 , and the first routing line 141 closest to the first reference line O is the nth first routing line 141_n.

[0367] The shortest length of the first first trace 141_1 is Lmin, and the longest length of the nth first trace 141_n is Lmax. Based on this, the length difference between two adjacent first traces 141 can be obtained based on the difference between the length of the nth first trace 141_n and the length of the first first trace 141_1. Here, n is a positive integer.

[0368] For example, the difference between the length of the m-1th first trace and the length of the mth first trace is Here, m is a positive integer, and m≤n+1.

[0369] Based on this, it is possible to gradually increase the lengths of the multiple first lines 141 along the arrangement direction of the multiple first lines 141, so that the differences between the multiple first lines 141 can gradually change to prevent the problem of large differences between two adjacent first lines 141, which leads to large differences in the heating power of the two first lines 141.

[0370] It should be noted that the length Lmin of the shortest first trace 141_1 and the length Lmax of the longest n-th first trace 141_n can be defined according to the shape of the LCD panel 100. That is, the length of each first trace 141 can match the shape of the LCD panel 100.

[0371] Correspondingly, in the first sub-display area AA1 , the first routing line 141 farthest from the first reference line O is the first first routing line 141_1 , and the first routing line 141 closest to the first reference line O is the nth first routing line 141_n.

[0372] The shortest width of the first first trace 141_1 is Wmin, and the longest width of the nth first trace 141_n is Wmax. Based on this, the difference in width between two adjacent first traces 141 can be obtained based on the difference between the width of the nth first trace 141_n and the width of the first first trace 141_1, where n is a positive integer.

[0373] For example, the difference between the width of the m-1th first trace and the width of the mth first trace is Here, m is a positive integer, and m≤n+1.

[0374] Based on this, the width of the multiple first lines 141 can be gradually increased along the arrangement direction of the multiple first lines 141, so that the difference between the multiple first lines 141 can be gradually changed to prevent the problem of large difference between two adjacent first lines 141, which leads to large difference in heating power of the two first lines 141.

[0375] It should be noted that the width Wmax of the nth first trace 141_n, which has the largest width, can be substantially equal to the width of the second light shielding portion 212 to prevent the orthographic projection of the second light shielding portion 212 on the first substrate 11 from failing to completely cover the first trace 141, thereby causing light leakage from the liquid crystal display panel 100. The width Wmin of the first trace 141_1, which has the smallest width, can be set based on the length Lmin of the first trace 141_1 and must meet existing operating precision requirements.

[0376] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A liquid crystal display panel, comprising a display area, wherein along a first direction, the display area includes a first sub-display area and a second sub-display area adjacent to each other; The display panel comprises: an array substrate, a cell substrate and a liquid crystal layer arranged between the array substrate and the cell substrate; The array substrate includes: a first substrate; a plurality of pixel units located on the first substrate, the pixel unit including at least one sub-pixel region, the plurality of pixel units including a first pixel unit located in the first sub-display area and a second pixel unit located in the second sub-display area; a plurality of first signal lines extending along the first direction, the first signal lines including a first line segment and a second line segment, the first line segment being electrically connected to the first pixel unit, and the second line segment being electrically connected to the second pixel unit; a common electrode layer comprising a first common electrode and a second common electrode, wherein the first common electrode is located in the first sub-display area, the second common electrode is located in the second sub-display area, and a first gap extending along a second direction is defined between the first common electrode and the second common electrode; the first direction intersects the second direction; The box-matching substrate comprises: The light-shielding layer includes a first light-shielding portion, wherein an orthographic projection of the first light-shielding portion on the first substrate at least partially overlaps with an orthographic projection of the first slit on the first substrate.

2. The liquid crystal display panel according to claim 1, wherein: The orthographic projection of the first light shielding portion on the first substrate covers the orthographic projection of the first slit on the first substrate.

3. The liquid crystal display panel according to claim 1 or 2, wherein: The array substrate further includes: A plurality of second signal lines extending along the second direction and arranged along the first direction, one second signal line being located on the side of a column of sub-pixel areas to which it is electrically connected, away from the first reference line; wherein the first reference line is the boundary line between the first sub-display area and the second sub-display area.

4. The liquid crystal display panel according to claim 3, wherein: The sub-pixel region includes: a driving transistor and a pixel electrode, the control electrode of the driving transistor is electrically connected to the first signal line, the first electrode of the driving transistor is electrically connected to the pixel electrode, and the second electrode of the driving transistor is electrically connected to the second signal line; The sub-pixel region in the first pixel unit is a first sub-pixel region, and the sub-pixel region in the second pixel unit is a second sub-pixel region; In the first sub-pixel region and the second sub-pixel region arranged along the first direction: the driving transistor in the first sub-pixel region and the driving transistor in the second sub-pixel region are mirror-symmetrical relative to a second reference line; wherein the second reference line is the center line connecting the first sub-pixel region and the second sub-pixel region.

5. The liquid crystal display panel according to claim 4, wherein: The pixel electrode is a dual-domain pixel electrode, comprising a first domain portion and a second domain portion, wherein the first domain portion and the second domain portion extend in an intersecting direction; The corner formed by the intersection of the first domain portion and the second domain portion of the pixel electrode in any of the first sub-pixel areas is a first corner, and the corner formed by the intersection of the first domain portion and the second domain portion of the pixel electrode in any of the second sub-pixel areas is a second corner; wherein, the first corner and the second corner protrude in one direction.

6. The liquid crystal display panel according to claim 4 or 5, wherein: The array substrate further includes a gate metal layer, an active layer, a source / drain metal layer, and the pixel electrode layer stacked on the first substrate; the pixel electrode layer includes a plurality of pixel electrodes; the common electrode layer is located between the source / drain metal layer and the pixel electrode layer; the common electrode layer includes a plurality of via holes; the orthographic projections of the pixel electrodes on the common electrode layer cover the via holes; The gate metal layer includes the first signal line. Along the first direction, the first signal line includes a first portion and a second portion. The first portion is multiplexed as the control electrode of the driving transistor. The orthographic projection of the via on the first substrate is located between the orthographic projections of the first portion and the second portion on the first substrate. The source-drain metal layer includes the second signal line, the second signal line includes a first sub-portion, and the first sub-portion of the second signal line is multiplexed as the second electrode of the driving transistor; the source-drain metal layer also includes a first conductive portion, the first conductive portion includes a third portion and a fourth portion, the third portion is multiplexed as the first electrode of the driving transistor, and the orthographic projection of the via on the first substrate is located between the orthographic projections of the third portion and the fourth portion on the first substrate; An orthographic projection of the second portion of the first signal line on the first substrate at least partially overlaps with an orthographic projection of the fourth portion of the first conductive portion on the first substrate.

7. The liquid crystal display panel according to claim 6, wherein: An orthographic projection of the fourth portion of the first conductive portion on the first substrate is located within a boundary of an orthographic projection of the second portion of the first signal line on the first substrate.

8. The liquid crystal display panel according to claim 7, wherein: Along the first direction, a length of the fourth portion of the first conductive portion is greater than or equal to 2 μm.

9. The liquid crystal display panel according to any one of claims 3 to 8, wherein The light shielding layer further includes a plurality of second light shielding portions, and the orthographic projections of the second signal lines on the first substrate are located within the boundaries of the orthographic projections of the second light shielding portions on the first substrate; Along the first direction, the width of the first light shielding portion is W1, the width of the second light shielding portion is W2, and W1≤1.5W2.

10. The liquid crystal display panel according to claim 9, further comprising a plurality of supporting portions, wherein the plurality of supporting portions are located between the array substrate and the cell substrate; The plurality of support portions include a first support portion and a second support portion, The sub-pixel region includes a driving transistor, and the orthographic projection of the first supporting portion on the first substrate is The orthographic projections of the driving transistors on the first substrate at least partially overlap; The orthographic projection of the second supporting portion on the first substrate is located within the orthographic projection of the first gap on the first substrate, and the second supporting portion and the plurality of first supporting portions are arranged along the first direction; Along the first direction, a distance between two adjacent first supporting portions is d1, a distance between adjacent first supporting portions and second supporting portions is d2, and |d2-d1|≤0.1d1.

11. The liquid crystal display panel according to any one of claims 1 to 10, wherein The pixel unit includes a plurality of sub-pixel regions; the array substrate further includes a gate metal layer, an active layer, a source / drain metal layer and a first metal layer stacked on the first substrate; The first metal layer is located between the source / drain metal layer and the common electrode layer. The first metal layer includes a plurality of first routing lines. The orthographic projection of one of the first routing lines on the first substrate is located between the orthographic projections of any two adjacent sub-pixel areas in a pixel unit on the first substrate.

12. The liquid crystal display panel according to claim 11, wherein: The sub-pixel area includes a driving transistor, and an orthographic projection of the first wiring on the first substrate does not overlap with an orthographic projection of the driving transistor on the first substrate.

13. The liquid crystal display panel according to claim 11 or 12, wherein: The array substrate further includes a plurality of second signal lines extending along the second direction and arranged along the first direction; An orthographic projection of the first trace on the first substrate at least partially overlaps with an orthographic projection of the second signal line on the first substrate.

14. The liquid crystal display panel according to any one of claims 11 to 13, wherein The light-shielding layer further includes a plurality of second light-shielding portions, and the orthographic projection of the first trace on the first substrate is located within the boundary of the orthographic projection of the second light-shielding portion on the first substrate.

15. The liquid crystal display panel according to any one of claims 11 to 14, wherein The array substrate further includes an organic layer, wherein the organic layer is located between the source / drain metal layer and the first metal layer; The thickness of the organic layer ranges from 16. The liquid crystal display panel according to any one of claims 11 to 15, wherein The liquid crystal display panel is an irregular-shaped liquid crystal display panel, and the multiple first lines include at least two first lines of unequal lengths along the second direction. Among the two first lines of unequal lengths, the length of the first first line is greater than the length of the second first line, and the line width of the first first line is greater than the line width of the second first line.

17. The liquid crystal display panel according to claim 16, wherein: In the first sub-display area or the second sub-display area, among the multiple first routing lines arranged along a direction close to a first reference line: the lengths of the multiple first routing lines gradually increase, and the widths of the multiple first routing lines gradually increase; wherein, the first reference line is the boundary line between the first sub-display area and the second sub-display area.

18. The liquid crystal display panel according to any one of claims 1 to 17, wherein the array substrate further comprises: An auxiliary electrode layer is located on a side of the common electrode layer facing away from the first substrate, and the auxiliary electrode layer is in contact with the common electrode layer.

19. The liquid crystal display panel according to claim 18, wherein: The light shielding layer further includes a plurality of second light shielding portions, the auxiliary electrode layer includes a plurality of auxiliary electrodes, and the orthographic projections of the auxiliary electrodes on the first substrate are located within the boundaries of the orthographic projections of the second light shielding portions on the first substrate.

20. A display device comprising: The liquid crystal display panel according to any one of claims 1 to 19; and, The cover plate is located on the light-emitting side of the liquid crystal display panel.

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