Chip system, operation method, data processing board, and electronic device

Abstract

Embodiments of the present application provide a chip system, an operation method, a data processing board, and an electronic device, applied to the field of chip processing. The chip system comprises a control circuit, a memory, a storage gating circuit, and at least two first processors. The at least two first processors are coupled to the memory by means of the storage gating circuit. The control circuit is used for: in response to the startup of the at least two first processors, outputting a storage gating control signal to the storage gating circuit, wherein the storage gating control signal is used for instructing the storage gating circuit to select one first processor among the at least two first processors to establish a data interaction connection with the memory. The selected first processor is used for: when establishing the data interaction connection with the memory, reading first program firmware from the memory by means of the storage gating circuit, wherein the first program firmware is used for functional operation of one or more first processors among the at least two first processors. According to the embodiments of the present application, the device cost is reduced by means of the implementation above.

Description

Chip system, operation method, data processing board and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 22, 2024, with application number 202410199394.1 and application name “A chip system, operating method, data processing board and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip system data processing technology, and in particular to a chip system, an operation method, a data processing board and an electronic device. Background Art

[0003] An electronic device may include a chip system. A processor and a memory for implementing data processing may be provided in the chip system. With the development and progress of data information processing technology, in practical applications, the requirements for the data processing capabilities of the chip system are gradually increasing. In order to meet the demand for greater data processing capabilities, multiple processors (e.g., two or more processors) may be provided in the chip system, and multiple processors may communicate with each other by establishing communication connections. In this case, data processing may be implemented with the aid of the computing power of multiple processors, and interaction and integration of data processing operations may be implemented based on mutual communication, thereby meeting the demand for greater data processing capabilities.

[0004] Because each of the multiple processors needs to import program firmware to run certain corresponding functions when it is started and / or working. One existing method for importing program firmware is as follows: because the multiple processors are independent of each other, it is necessary to set up multiple memories in the chip system, each memory corresponding to a processor, and the multiple memories are used to store the program firmware required by the corresponding multiple processors. Each processor accesses and reads the program firmware in the corresponding processor to run the corresponding program function. This implementation method results in a high device cost for the chip system.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a chip system, an operating method, a data processing board, and an electronic device, which reduce the device cost of storing program firmware required to start and run multiple processors.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a chip system is provided, comprising a control circuit, a memory, a memory gating circuit, and at least two first processors. The at least two first processors are coupled to the memory via the memory gating circuit. The control circuit is configured to, in response to the at least two first processors being powered on, output a memory gating control signal to the memory gating circuit, the memory gating control signal being configured to instruct the memory gating circuit to select one of the at least two first processors to establish a data interaction connection with the memory. The selected first processor is configured to, when establishing a data interaction connection with the memory, read a first program firmware from the memory via the memory gating circuit, the first program firmware being configured to operate the functions of one or more of the at least two first processors.

[0009] In an embodiment of the present application, multiple first processors can share the same memory for storing program firmware. The gating of the data interaction link between different first processors and the memory is realized by a storage gating circuit. The storage gating control signal output by the control circuit is used to select a corresponding first processor to establish a data interaction connection with the memory, so that the selected first processor can access and read the relevant first program firmware from the memory. Through the design of the embodiment of the present application, the number of storage devices for storing program firmware and the number of related configuration devices of these storage devices can be reduced, thereby reducing the device cost on the basis of providing greater data processing computing power.

[0010] In one possible embodiment, the first program firmware includes communication program firmware, which is used to establish a communication connection between at least two first processors. The control circuit is specifically configured to, in response to the at least two first processors being powered on, sequentially output at least two first storage gating control signals to the storage gating circuit. The at least two first storage gating control signals correspond one-to-one to the at least two first processors, and each first storage gating control signal is configured to instruct the storage gating circuit to select the corresponding first processor as a selected first processor to establish a data interaction connection with the memory. The selected first processor is configured to, when establishing a data interaction connection with the memory based on the corresponding first storage gating control signal, read the communication program firmware from the memory through the storage gating circuit.

[0011] In the embodiments of the present application, for each first processor, the other processors are considered peripheral devices of that first processor. Different first processors cannot exchange data or information with each other during initial startup. Therefore, each time the chip system is powered on, a communication connection must be established between the different first processors. By establishing communication connections, multiple first processors are integrated to achieve greater data processing capabilities. A communication connection refers to establishing an inter-node communication path between different first processors, enabling data link and / or control link interaction between the different first processors based on this communication path, and enabling each first processor to directly access the memory space of another first processor based on the communication connection. For example, different technologies can be used to establish a communication connection depending on the application scenario and design. Although the design technologies and names used by different product manufacturers vary, they all serve the purpose of achieving the functional purpose explained above for the communication connection. In one approach, during the startup phase of each first processor, communication connections between multiple first processors can be established based on a bootloader within each first processor. However, this approach results in very complex bootloader code. And because the boot program cannot be changed after it is designed once, in actual applications, the design complexity and implementation difficulty of the boot program are greatly increased according to the different networking methods of the chip system. Establishing a communication connection by running the program firmware can make the design more flexible and simple. In the chip system startup phase, the embodiment of the present application outputs a first storage selection control signal corresponding to different first processors through the control circuit, so that each first processor accesses and reads the communication program firmware as a selected first processor in turn. After accessing and reading the communication program firmware, each first processor can perform the relevant configuration of establishing a communication connection between different first processors by running the communication program firmware.

[0012] In one example, the control circuit is specifically used to: output a first storage selection control signal to the storage selection circuit, output a feedback signal to a currently selected first processor, and the feedback signal is used to instruct the corresponding first processor to read the communication program firmware. Each selected first processor is used to: read the communication program firmware from the memory in response to the corresponding feedback signal. In an embodiment of the present application, during the power-on startup phase, the control circuit can output a feedback signal to the corresponding currently selected first processor after outputting the corresponding first storage selection control signal. The currently selected first processor can access and read the relevant program firmware in response to the feedback signal. By outputting the first storage selection control signal corresponding to each first processor in turn, all first processors can be used as the selected first processor to read the communication program firmware in turn.

[0013] In one example, the first processor includes a status interface. The first processor is coupled to the control circuit via the status interface. Each of the at least two first processors is specifically configured to: in response to power-on startup, set the status interface to a first level state, the first level state being used to instruct the control circuit to output a corresponding first storage gating control signal to the memory. In response to a corresponding feedback signal, the communication program firmware is read from the memory via the storage gating circuit, and the status interface is set to a second level state, the second level state being used to instruct the corresponding first processor to complete reading the communication program firmware. In an embodiment of the present application, the first processor can provide feedback to the control circuit indicating whether the first processor needs to access the read program firmware by configuring the level state of the status interface. For example, during the power-on startup phase, when the boot program inside each first processor is running, the status interface can be configured to a first level state to inform the control circuit that it needs to access the communication program firmware. The control circuit outputs a corresponding first storage gating control signal and a feedback signal based on the state of the status interface of each first processor. When the first processor receives the feedback signal, it can determine that it is set as the currently selected first processor based on the corresponding first storage selection control signal. As the currently selected first processor, it can access and read the communication program firmware. After the access and read are successful, the corresponding status interface can be set to the second level state to indicate that the access and read of the communication program firmware are completed. Then, after detecting that the status interface of the currently selected first processor is set to the second level state, the control circuit can continue to output new first storage selection control signals and feedback signals to other first processors to select other first processors as the selected first processors to access and read the communication program firmware.

[0014] In one example, the communication program firmware includes storage address information and network node address information. The storage address information and network node address information are used for communication interaction between at least two first processors. Each first processor is configured to configure the storage address information and network node address information to establish a communication connection between the at least two processors.

[0015] In one possible embodiment, the first program firmware further includes at least one shared program firmware, wherein the at least one shared program firmware is a first processor and program firmware required for at least one shared first processor, or is program firmware required for at least one shared first processor. The at least one shared first processor is one or more first processors other than the first processor. The control circuit is specifically configured to: during an operational phase between at least two first processors, output a second storage gating control signal to the storage gating circuit, the second storage gating control signal being configured to instruct the storage gating circuit to select a first processor to establish a data exchange connection with the memory. The selected first processor is configured to: upon establishing a data exchange connection with the memory based on the second storage gating control signal, read the at least one shared program firmware from the memory; and output the shared program firmware to the at least one shared first processor. In this embodiment of the present application, after different first processors establish communication connections and the chip system is in an operational state, the control circuit may select a first processor as a fixed selected first processor based on the second storage gating control signal, or dynamically select a different first processor as the selected first processor. When determining the selected first processor, the first program firmware may be accessed and read based on the selected first processor. The first program firmware can be required for the operation of the selected first processor itself, or it can be required for the operation of other first processors (i.e., at least one shared first processor). Because the selected first processor occupies the communication access connection with the memory, for at least one shared first processor for which a data interaction connection has not been established, when these shared first processors need to run a certain program firmware, in one way, the shared first processor can be switched to a newly selected first processor through a new second storage selection control signal, and then the newly selected first processor accesses and reads the required program firmware; in another way, the program firmware required to read the shared first processor (i.e., shared program firmware) can be accessed and read through the currently selected first processor, and transmitted to these shared first processors. By transmitting the shared program firmware, the switching action of a first processor can be reduced, etc., and the processing delay can be reduced. At the same time, the data transmission rate of the communication connection between multiple first processors is also faster, which can meet the low-latency processing requirements of multiple first processors.

[0016] In one possible implementation, the first processor includes a first interface circuit; at least two first processors transmit shared program firmware based on the first interface circuit. In embodiments of the present application, a first interface circuit for interactive communication is typically designed between different processors. The first interface circuit is used to establish a communication connection between different first processors. After the communication connection is established, the selected first processor and the shared first processor can implement the transmission of shared program firmware based on the first interface circuit.

[0017] In one possible implementation, each first processor further includes a verification circuit, and the first processor is used to: parse and verify the read first program firmware based on the verification circuit. If a circuit or device related to security metric verification is designed outside the first processor, then after each access and reading of the program firmware, the program firmware needs to be transported and transferred to an external verification device for security metric verification, and the data after the security metric verification is completed is transported to the inside of the processor. This external security metric verification method makes the security metric process more cumbersome and the data flow complicated. In an embodiment of the present application, a verification circuit can be designed inside the first processor. After the program firmware is accessed and read into a selected first processor, the relevant security metric verification is directly performed based on the internal verification circuit. Under this implementation, the cost of the peripheral security metric device can be reduced, and the processing rate after the program firmware is accessed and read can also be improved.

[0018] In one example, during the operating phase of the chip system, when shared program firmware is required by a currently selected first processor and at least one shared first processor, the currently selected first processor can perform a security metric check on the shared program firmware, and then transmit the program firmware data after the security metric check to the shared program firmware. In this embodiment, for program firmware shared by multiple first processors, the security metric check process can be performed only once, avoiding the problem of different first processors separately performing security metric checks on the commonly required program firmware.

[0019] In one example, during the working phase of the chip system, when the shared program firmware is required by at least one shared first processor, a selected first processor can perform a security metric check on the shared program firmware, and then transmit the program firmware data after the security metric check to at least one shared first processor. Alternatively, the selected first processor may not perform a security metric check on the shared program firmware, but directly output the shared program firmware to the shared first processor, and the shared first processor that receives the shared program firmware performs the relevant security metric check processing. In the embodiment of the present application, different methods can be selected to perform security metric check processing on the shared program firmware according to different actual designs, as well as different designs and requirements such as the computing power of the currently selected first processor.

[0020] Exemplarily, the verification circuit includes a verification processing circuit and a verification information buffer. The verification information buffer is used to store verification code element information required for parsing and verifying the first program firmware. The verification processing circuit is used to parse and verify the first program firmware based on the verification code element information. In an embodiment of the present application, a relevant verification information buffer can be provided within the verification circuit to store relevant verification code element information required for security metric verification. Taking the security metric verification based on a hash algorithm as an example, the verification code element information can include a public key hash value, a program firmware encryption root key, and the like.

[0021] In one possible implementation, each first processor further includes a second interface circuit; the first processor is coupled to the memory via a memory gating circuit based on the second interface circuit. In the embodiments of the present application, based on the memory type and access and reading methods, and in combination with the memory gating circuit, a second interface circuit using corresponding technology can be designed. For example, if the memory is a flash memory, a second interface circuit based on serial flash controller (SFC) technology can be designed.

[0022] In one possible embodiment, the chip system also includes at least one second processor. The at least one second processor is coupled to the memory through a storage gating circuit. Wherein: the control circuit is also used to: output a third storage gating control signal to the storage gating circuit, and the third storage gating control signal is used to instruct the storage gating circuit to select one of the at least one second processors to establish a data interaction connection with the memory. The selected second processor is used to: read the second program firmware from the memory through the storage gating circuit when establishing a data interaction connection with the memory, and the second program firmware is used for the functional operation of the selected second processor. In an embodiment of the present application, in addition to the first processor designed for data calculation and other processing, at least one second processor that performs other auxiliary functions can also be designed in the chip system. The second processor can also share the memory to store the relevant second program firmware.

[0023] In one possible implementation, the control circuit can be a software-based control chip. Alternatively, it can be a hardware digital logic circuit. Hardware digital logic circuits have low device cost, simple design, and are easy to implement control logic in different networking scenarios.

[0024] In a second aspect, an embodiment of the present application further provides an operating method, which is applied to a chip system, wherein the chip system includes a memory, a storage gating circuit, and at least two first processors. The at least two first processors are coupled to the memory through the storage gating circuit. The method includes: outputting a storage gating control signal to the storage gating circuit, the storage gating control signal being used to instruct the storage gating circuit to select one of the at least two first processors to establish a data interaction connection with the memory. When the selected first processor establishes a data interaction connection with the memory, the first program firmware is read from the memory through the storage gating circuit, and the first program firmware is used for the functional operation of one or more first processors of the at least two first processors.

[0025] In one possible embodiment, the first program firmware includes communication program firmware, and the communication program firmware is used to establish a communication connection between at least two first processors. Wherein: the above-mentioned output of the storage gating control signal to the storage gating circuit includes: in response to the at least two first processors being powered on, outputting at least two first storage gating control signals to the storage gating circuit in sequence, the at least two first storage gating control signals corresponding one-to-one to the at least two first processors, and each first storage gating control signal is used to instruct the storage gating circuit to select the corresponding first processor as the selected first processor to establish a data interaction connection with the memory. The above-mentioned reading of the first program firmware from the memory through the storage gating circuit includes: when the selected first processor establishes a data interaction connection with the memory based on the corresponding first storage gating control signal, the communication program firmware is read from the memory.

[0026] In one possible embodiment, the sequentially outputting at least two first storage gating control signals to the storage gating circuit includes: sequentially outputting a first storage gating control signal to the storage gating circuit, outputting a feedback signal to a currently selected first processor, the feedback signal being used to instruct the currently selected first processor to read the communication program firmware; and outputting a next first storage gating control signal to the storage gating circuit after the currently selected first processor completes reading the communication program firmware. Each of the first processors reading the communication program firmware from the memory via the storage gating circuit includes: the selected first processor reading the communication program firmware from the memory in response to the feedback signal.

[0027] In one possible embodiment, the first processor includes a status interface. Reading the communication program firmware from the memory includes: in response to the corresponding first processor being powered on, setting the status interface to a first level state, the first level state being used to instruct output of a corresponding first storage gating control signal to the memory. In response to a feedback signal, the communication program firmware is read from the memory via the storage gating circuit, and the status interface is set to a second level state, the second level state being used to instruct the corresponding first processor to complete reading the communication program firmware.

[0028] In one example, the communication program firmware includes storage address information and network node address information. The storage address information and network node address information are used for communication interaction between at least two first processors. The method further includes: configuring each first processor with the storage address information and the network node address information, and establishing a communication connection between the at least two processors.

[0029] In a possible embodiment, the first program firmware also includes at least one shared program firmware, and the at least one shared program firmware is a first processor and the program firmware required for at least one shared first processor, or is the program firmware required for at least one shared first processor. Wherein: the above-mentioned output of the storage gating control signal to the storage gating circuit includes: in the working operation stage between at least two first processors, outputting a second storage gating control signal to the storage gating circuit, the second storage gating control signal is used to instruct the storage gating circuit to select a first processor to establish a data interactive connection with the memory. The above-mentioned reading of the first program firmware from the memory through the storage gating circuit includes: when the selected first processor establishes a data interactive connection with the memory based on the second storage gating control signal, reading at least one shared program firmware from the memory through the storage gating circuit. The method also includes: the selected first processor transmits the shared program firmware to at least one shared first processor.

[0030] In a possible implementation, each of the first processors further includes a verification circuit, and the method further includes: the first processor parsing and verifying the read first program firmware based on the verification circuit.

[0031] In a possible implementation manner, the parsing and verifying the first program firmware read from the memory through the memory gating circuit includes: parsing and verifying the first program firmware based on check code element information.

[0032] In one possible embodiment, the chip system further includes at least one second processor. The at least one second processor is coupled to the memory via a memory gating circuit. The method further includes: outputting a third memory gating control signal to the memory gating circuit, the third memory gating control signal being used to instruct the memory gating circuit to select one of the at least one second processors to establish a data exchange connection with the memory. When the selected second processor establishes a data exchange connection with the memory, the memory gating circuit reads a second program firmware from the memory via the memory gating circuit, and the second program firmware is used to operate the functions of the selected second processor.

[0033] In a third aspect, an embodiment of the present application further provides a data processing board, which includes a lining board and a chip system as described in the first aspect above, and the chip system is processed on the lining board.

[0034] In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes a housing and a data processing board as described in the third aspect above, wherein the data processing board is partially or fully disposed in the housing.

[0035] Exemplarily, the electronic device may be a server device including a multi-way first processor.

[0036] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a server, the server executes the operating method described in the second aspect above.

[0037] Regarding the technical principles and beneficial effects of the second, third, fourth and fifth aspects mentioned above, please refer to the relevant description of the first aspect mentioned above, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic structural diagram of a chip system provided in an embodiment of the present application;

[0039] FIG2 is a schematic structural diagram of a first chip system provided in an embodiment of the present application;

[0040] FIG3 is a first structural diagram of a second chip system provided in an embodiment of the present application;

[0041] FIG4 is a second structural diagram of a second chip system provided in an embodiment of the present application;

[0042] FIG5 is a third structural diagram of a second chip system provided in an embodiment of the present application;

[0043] FIG6 is a fourth structural diagram of a second chip system provided in an embodiment of the present application;

[0044] FIG7 is a fifth structural diagram of a second chip system provided in an embodiment of the present application;

[0045] FIG8 is a sixth structural diagram of a second chip system provided in an embodiment of the present application;

[0046] FIG9 is a seventh structural diagram of a second chip system provided in an embodiment of the present application;

[0047] FIG10 is a structural diagram eight of a second chip system provided in an embodiment of the present application;

[0048] FIG11 is a schematic diagram of a flow chart of an operating method provided in an embodiment of the present application;

[0049] FIG12 is a schematic diagram of a process flow of a security metric verification provided by an embodiment of the present application;

[0050] FIG13 is a schematic diagram of a program firmware processing flow during the boot-up and operation phases provided by an embodiment of the present application;

[0051] FIG14 is a flow chart of another operating method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0053] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0054] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0055] An embodiment of the present application provides an electronic device, which includes a housing and a data processing board, wherein the data processing board is partially or completely arranged in the housing. Among them, the data processing board includes a lining board and a chip system, and the chip system is processed on the lining board. As shown in Figure 1, the chip system 1000 includes at least two processors 100. Each processor 100 in the at least two processors 100 can perform related data calculation processing respectively, and communication interaction between the processors 100 is achieved by establishing a communication connection between different processors 100 to integrate the calculation processing resources of at least two processors 100, so that the chip system 1000 can have a higher calculation processing capability. However, in the process of each processor 100 starting up and / or working, it is necessary to read some basic program firmware (basic input output system, BIOS) to realize the relevant functional operation. These program firmware are usually stored in related storage devices to meet the reading and operation requirements of the processor 100. Depending on the design of the chip system 1000, these program firmware can be stored in different ways.

[0056] In some possible implementations, the chip system 1000 shown in Figure 1 may be a first chip system based on multiple memories storing program firmware for different processors 100. As shown in Figure 2, the first chip system 1000A includes at least two processors 100, at least two bridge chips 200A, and at least two first memories 300A. At least two processors 100 correspond one to one with at least two bridge chips 200A and at least two first memories 300A. Each first memory 300A stores the program firmware required by the corresponding processor 100. Each processor 100 is coupled to a first memory 300A through a corresponding bridge chip 200A to obtain the program firmware from the corresponding first memory 300A.

[0057] Depending on the design, the multiple processors 100 in the first chip system 1000A may establish communication connections in different ways:

[0058] In some examples, a boot rom can be set in the processor 100. When the first chip system 1000A is powered on, the processors 100 are powered on separately, and each processor 100 realizes the establishment of a communication connection with other processors 100 based on the boot rom configured at the internal software level. In an embodiment of the present application, the establishment of a communication connection in the power-on phase of multiple processors 100 is realized based on software configuration. However, the boot rom is immutable, that is, after being set once, the boot rom cannot be changed. Therefore, in actual applications, as the complexity and variability of the networking configuration between multiple processors 100 develop, the flexible adaptability of the boot rom is low. In addition, when the networking configuration between multiple processors 100 is more complex, the code design of the boot rom will also be very complex.

[0059] In some possible implementations, in order to ensure the security of the program firmware read by the first chip system 1000A, it is also necessary to perform a security check on the program firmware read. At this point, as shown in Figure 2, the first chip system 1000A also includes a trusted security module (trusted platform module, TPM) chip 400A. The trusted security module chip 400A is coupled to the bridge chip 200A. The bridge chip 200A transfers the program firmware read by the processor 100 to the trusted security module chip 400A for security measurement verification. The program firmware after passing the security measurement verification is then transferred to the corresponding processor 100.

[0060] In some examples, the first chip system 1000A may further include a baseboard management controller (BMC) 500A, which is coupled to the first memory 300A via the bridge chip 200A. The first memory 300A may also store program firmware required by the BMC 500A. In this case, the trusted security module chip 400A may also perform security measurement verification on the program firmware of the BMC 500A.

[0061] In the embodiment of the present application as shown in FIG2 , a corresponding first memory 300A can be provided for each of the multiple processors 100, and a corresponding bridge chip 200A, a trusted security module chip 400A, and a baseboard management controller 500A can be provided. However, under this embodiment, the required device cost is relatively high. At the same time, when it is necessary to perform a security metric check on the program firmware read by the processor 100, each of the multiple processors 100 corresponds to multiple program firmwares. When each processor 100 needs to perform a security metric check on the program firmware, it is necessary to rely on the optional security module chip 400A of the peripheral or other peripheral security chip to perform the processing, which makes the security metric check process more complicated. In addition, if the communication connection between the multiple processors 100 is established after startup based on the boot program configuration inside the processor 100, the design is also relatively complicated.

[0062] In order to reduce the device cost of a chip system 1000 having multiple processors 100, in some possible implementations, the chip system 1000 shown in FIG1 may be a second chip system based on storage medium sharing. As shown in FIG3, the second chip system 1000B includes at least two first processors 100B, a storage gating circuit 200B, a second memory 300B, and a control circuit 400B. The at least two first processors 100B are coupled to the second memory 300B via the storage gating circuit 200B.

[0063] The control circuit 400B is configured to output a storage strobe control signal to the storage strobe circuit 200B. The storage strobe control signal is configured to instruct the storage strobe circuit 200B to select one of the at least two first processors 101B to establish a data exchange connection with the second memory 300B. The selected first processor 101B is configured to read the first program firmware from the second memory 300B via the storage strobe circuit 200B when establishing the data exchange connection with the second memory 300B. The first program firmware is configured to operate the functions of one or more of the at least two first processors 100B.

[0064] In one example, the first program firmware read by the selected first processor 101B may be the program firmware required for the selected first processor 101B to run. In another example, the first program firmware read by the selected first processor 101B may also be the program firmware required by other first processors 100B other than the selected first processor 101B.

[0065] In an embodiment of the present application, at least two first processors 100B are provided in the second chip system 1000B, and the data processing capability of the second chip system 1000B can be improved based on the at least two first processors 100B. At the same time, at least two first processors 100B are coupled to the same second memory 300B based on the storage gating circuit 200B. The second memory 300B stores the program firmware required for each first processor 100B in the at least two first processors 100B. The control circuit 400B outputs a storage gating control signal to the storage gating circuit 200B to select the corresponding first processor 100B as the selected first processor 101B and establish a data interaction connection with the second memory 300B. The selected first processor 101B can access and read the program firmware from the second memory 300B based on the established data interaction connection. Through the embodiment of the present application, it is possible to realize that multiple first processors 100B share the same storage medium for storing program firmware. In addition, each first processor 100B can obtain the required program firmware.

[0066] In one possible embodiment, as shown in FIG4 , the first processor 100B includes a status interface 110B. The first processor 100B is coupled to the control circuit 400B via the status interface 110B. Exemplarily, the status interface 110B may be a general-purpose input / output (GPIO) interface. In an embodiment of the present application, the first processor 100B may indicate that it needs to access the second memory 300B to read the relevant first program firmware by setting the status interface 110B to a first level state. The first processor 100B may indicate that it does not need to access the second memory 300B temporarily by setting the status interface 110B to a second level state.

[0067] In one possible implementation, as shown in FIG5 , the first processor 100B includes a first interface circuit 120B; at least two first processors 100B transmit and share program firmware based on the first interface circuit 120B. Exemplarily, a communication connection refers to establishing an inter-node communication path between different first processors 100B, enabling data link and / or control link interaction between different first processors 100B based on the communication path, and enabling one first processor 100B to directly access the storage space of another first processor 100B based on the communication connection. Although the design technologies and names of different product manufacturers vary, they are all intended to achieve the functional purpose explained in the above-mentioned communication connection.

[0068] In one possible implementation, as shown in Fig. 5 , the first processor 100B further includes a second interface circuit 130B. The first processor 100B is coupled to the second memory 300B via a memory strobe circuit 200B based on the second interface circuit 130B.

[0069] Exemplarily, the second memory 300B may be a non-volatile memory, such as a flash memory. Exemplarily, the second interface circuit 130B may be a serial flash controller (SFC). Exemplarily, the storage gating circuit 200B may be a serial flash controller switch (SFC switch) with a gating function, or the storage gating circuit 200B may be a multiplexer selection circuit with a gating function.

[0070] In one possible implementation, as shown in FIG5 , the first processor 100B further includes a verification circuit 140B, and the verification circuit 140B is configured to parse and verify the read first program firmware.

[0071] Exemplarily, relevant encryption information may be set in the file header of the program firmware stored in the second memory 300B, and the encryption information is used to assist the verification circuit 140B in implementing relevant parsing verification.

[0072] Exemplarily, the verification circuit 140B may be a hardware security module (HSM) built into the first processor 100B.

[0073] In some possible implementations, depending on the application scenario and design, verification circuit 140B can implement security metric verification of the first program firmware based on different algorithms. For example, as shown in FIG6 , verification circuit 140B includes a verification processing circuit 141B and a verification information buffer 142B. Verification information buffer 142B is configured to store verification code element information required for parsing and verifying the first program firmware. Verification processing circuit 141B is configured to parse and verify the first program firmware based on the verification code element information.

[0074] In one possible embodiment, as shown in Figure 7, each first processor 100B may include one or more processing cores 150B, and the multiple processing cores 150B are coupled to the first interface circuit 120B, the verification circuit 140B and the second interface circuit 130B via the system bus BUS. The operation of different processing cores 50B may require the same or different first program firmware. In one example, each first processor 100B can be used as a selected first processor to access and read the required first program firmware. In one example, other first processors 100B can also be used as a selected first processor to read the first program firmware required by the first processor 100B, and the first processor 100B obtains the required first program firmware from the selected first processor.

[0075] For example, corresponding cache devices SRAM can be set in each of the multiple processing cores 150B and the verification circuit 140B. As shown in FIG8 , the verification circuit 140B can store the first program firmware read by access in the corresponding cache device SRAM1. The verification processing circuit 141B performs security metric verification on the first program firmware stored in its cache device SRAM1 based on the verification code element information stored in the verification information buffer 142B. The first program firmware after the security metric verification can then be transferred to the cache device SRAM2 of the corresponding processing core 150B in the first processor 100B. Each processing core 150B can obtain the relevant first program firmware from the corresponding cache device SRAM2.

[0076] Exemplarily, the boot program of each first processor 100B may run in the verification circuit 140B.

[0077] In some possible implementations, the control circuit 400B may be a control device implementing control logic based on software, or a hardware digital logic circuit implementing control logic based on hardware, such as a complex programmable logic device (CPLD).

[0078] In some possible implementations, as shown in FIG9 , the second chip system 1000B may further include at least one second processor 500B. The at least one second processor 500B is coupled to a second memory 300B via a memory gating circuit 200B. In this case, the second memory 300B may also be used to store second program firmware required for the operation of the second processor 500B.

[0079] In one example, the at least two first processors 100B may be two first processors 100B. In one example, as shown in FIG10 , the at least two first processors 100B may be four first processors 100B. Alternatively, the at least two first processors 100B may be other larger numbers of first processors 100B.

[0080] In some examples, the first processor 100B and / or the second processor 500B may be a chip, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0081] In some possible implementations, the second chip system 1000B may be a chip system in a multi-processor server.

[0082] Based on the second chip system 1000B having the structures shown in FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , and FIG. 9 , the operating method including the operations of steps S100 to S300 shown in FIG. 11 below may be executed:

[0083] S100 , outputting a memory gating control signal to the memory gating circuit 200B to gating a selected first processor 101B.

[0084] In some possible implementations, as shown in Figures 3, 4, 5, 6, 7, 8, 9, and 10, a control circuit 400B may output a storage gating control signal, which may be used to control a storage gating circuit 200B to select a first processor 101B from at least two first processors 100B. The selected first processor 101B establishes a data exchange connection with the second memory 300B through the storage gating circuit 200B, thereby accessing the second memory 300B.

[0085] In some possible implementations, during the power-on and startup phase of the second chip system 1000B, different first processors 100B also power on and start up. When each first processor 100B establishes a communication connection based on the program firmware, the first program firmware includes a communication program firmware, and the communication program firmware is used to establish a communication connection between at least two first processors 100B. During the power-on and startup phase of the first processor 100B, each first processor 100B needs to access and read the communication program firmware, and establish a communication connection between different first processors 100B based on the communication program firmware. Therefore, in the power-on and startup phase of the at least two first processors 100B, step S100 may include: in response to the power-on and startup of the at least two first processors 100B, outputting at least two first storage gating control signals to the storage gating circuit 200B in sequence, the at least two first storage gating control signals corresponding to the at least two first processors 100B one-to-one, and each first storage gating control signal is used to instruct the storage gating circuit 200B to use the corresponding first processor 100B as the selected first processor 101B to establish a data interaction connection with the second memory 300B. In an embodiment of the present application, during the startup phase, a first storage strobe control signal can be outputted for each first processor 100B that is started. Based on multiple first storage strobe control signals, each first processor 100B can be selected as one first processor 101B at a time during the startup phase to access and read the communication program firmware. A communication connection is established between at least two first processors 100B via the communication program firmware.

[0086] Exemplarily, the communication program firmware includes storage address information and network node address information. The storage address information and network node address information are used for communication interaction between at least two first processors. The operation of establishing a communication connection includes: configuring each first processor with the storage address information and the network node address information, and establishing a communication connection between the at least two processors.

[0087] For example, as shown in Figures 4, 5, 6, 7 and 9, for each first processor 100B, in response to the corresponding first processor 100B being powered on, the status interface 110B is set to a first level state, and the first level state is used to indicate that the corresponding first storage selection control signal is output to the second memory 300B. In an embodiment of the present application, during the power-on process of each first processor 100B, its status interface 110B can be set, and the control circuit 400B can determine whether the corresponding first processor 100B has accessed and read the second memory 300B during the power-on phase based on the level state of the status interface 110B of each first processor 100B. For example, when the status interface 110B of a certain first processor 100B is set to a high level state, it means that it needs to perform access and read processing.

[0088] For example, as shown in Figures 4, 5, 6, and 7, the control circuit 400B can sequentially output corresponding first storage strobe control signals to the second memory 300B based on the level state of the status interface 110B. After each output of the first storage strobe control signal, a feedback signal is output to the corresponding first processor 100B, and the feedback signal is used to instruct the corresponding first processor 100B to read the communication program firmware.

[0089] In some possible implementations, during the operation phase of the second chip system 1000B, the control circuit 400B may output a second storage strobe control signal to select a first processor 100B among the at least two first processors 100B as the selected first processor 101B. For example, step S100 may further include: after establishing a communication connection between the at least two first processors 100B, outputting a second storage strobe control signal to the storage strobe circuit 200B, the second storage strobe control signal being used to instruct the storage strobe circuit 200B to establish a data exchange connection between the selected first processor 101B and the second memory 300B.

[0090] Illustratively, during the working phase of the second chip system 1000B, a first processor 100B can be selected as a fixed selected first processor 101B based on the second storage selection control signal, or a different first processor 100B can be changed as a new selected first processor 101B based on the second storage selection control signal.

[0091] S200 , a selected first processor 101B reads a first program firmware from the second memory 300B through the memory gating circuit 200B.

[0092] In one example, during the power-on startup phase, in step S100, based on multiple first storage selection control signals, each first processor 100B can be selected as a first processor 101B at a time during the power-on startup phase, so that each first processor 100B as a selected first processor 101B can access and read the communication program firmware.

[0093] For example, as shown in FIG3 , during the startup phase, after the control circuit 400B outputs a first storage selection control signal, a first processor 100B is selected as a first processor 101B. At the same time, the control circuit 400B outputs a corresponding feedback signal to the selected first processor 101B. During the startup phase, each first processor 100B selected as a first processor 101B can respond to the feedback signal and read the first program firmware as the communication program firmware from the second memory 300B via the storage selection circuit 200B.

[0094] For example, as shown in Figures 4, 5, 6, and 7, during the startup phase, each first processor 100B, as a selected first processor 101B, may set the status interface 110B to the second level state after accessing and reading the communication program file. For example, after reading the communication program file, the status interface 110B is set to a low level state. The second level state is used to indicate that the corresponding selected first processor 101B has completed reading the communication program firmware.

[0095] In one example, in the working stage after different first processors 100B establish a communication connection, a selected first processor 101B can read different first program firmware when the second chip system 1000B is in a working state. Exemplarily, the read first program firmware may include only the program firmware required for the operation of the selected first processor 101B. Exemplarily, the read first program firmware may also include at least one shared program firmware, at least one shared program firmware is the selected first processor 101B and at least one shared first processor 102B other than the selected first processor 101B. Alternatively, at least one shared program firmware is the program firmware required for at least one shared first processor 102B. When the selected first processor 101B establishes a data interaction connection with the second memory 300B based on the second storage selection control signal, the at least one shared program firmware is read from the second memory 300B through the storage selection circuit 200B.

[0096] S300: The selected first processor 101B runs the first program firmware and / or transmits the first program firmware.

[0097] In some possible implementations, when a selected first processor 101B accesses and reads a certain first program firmware from the second memory 300B, the selected first processor 101B can run the first program firmware. For example, in the power-on startup phase, before a communication connection is established between different first processors 100B, different first processors 100B cannot share the first program firmware obtained interactively. Therefore, for the communication program firmware accessed and read during the startup phase, the corresponding selected first processor 101B is only used for its own operation and will not be interactively transmitted with other first processors 100B. For example, in the working operation phase after the communication connection is established, for some first program firmware required for only the selected first processor 101B to run, the selected first processor 101B will not share the transmission to other first processors 101B after accessing and reading.

[0098] In some possible implementations, a selected first processor 101B may transmit shared program firmware to at least one shared first processor 102B based on a communication connection. In one example, when a selected first processor 101B accesses and reads a certain shared program firmware from the second memory 300B, if the shared program firmware is the program firmware required by at least one shared first processor 102B, the selected first processor 101B may not run the first program firmware and transmit the first program firmware to at least one shared first processor 102B. In one example, when a first processor 101B accesses and reads a certain shared program firmware from the second memory 300B, when the shared program firmware is the program firmware required by the selected first processor 101B and at least one shared first processor 102B, the selected first processor 101B may run the first program firmware and may also transmit the first program firmware to at least one shared first processor 102B.

[0099] In some possible implementations, before running the first program firmware or transmitting the first program firmware in step S300 , a security metric verification process may be performed on the first program firmware.

[0100] Exemplarily, a security metric check is performed on the first program firmware based on the check circuit 140B as shown in Figures 5, 6, 7 and 8. As shown in Figure 8, in one example, at the power-on startup stage, the control circuit 400B can obtain the first program firmware 0 from the second memory 300B based on each selected first processor 101B selected by the first storage selection control signal. The first program firmware 0 is a communication program firmware for establishing a communication connection between the first processors 100B. The selected first processor 101B can perform a security metric check on the first program firmware 0 based on the check circuit 140B. In one example, at the power-on startup stage, the control circuit 400B can obtain the first program firmware 1, the first program firmware 2 and the first program firmware 3, etc. based on the first program firmware 1 and the first program firmware 2, and perform security metric checks respectively. In one example, taking the first program firmware 1 and the first program firmware 2 as the program firmware required for the operation of a selected first processor 101B, after the security metric verification, the verification circuit 140B will transmit the first program firmware 1 and the first program firmware 2 to the cache device SRAM2 in the corresponding processing core 150B in the selected first processor 101B based on the data bus, so as to be required for the operation of the corresponding processing core 150B. In another example, taking the first program firmware 1 and the first program firmware 2 as the shared program firmware required for the operation of other shared first processors 102B, after the verification circuit 140B completes the security metric verification of the first program firmware 1 and the first program firmware 2, it will also transmit the first program firmware 1 and the first program firmware 2 to the shared first processor 102B based on the first interface circuit 120B. In an example, taking the first program firmware 3 as the program firmware that is not needed for the selected first processor 101B to run and is the shared program firmware required for the shared first processor 102B to run, the selected first processor 101B can perform a security measurement check on the first program firmware 3 after accessing and reading the first program firmware 3, and after passing the security measurement check, transmit the first program firmware 3 to the shared first processor 102B.

[0101] Exemplarily, relevant encryption information can be set in the file header of the first program firmware, and the encryption information is used to assist the verification circuit 140B in implementing relevant parsing verification. As shown in Figure 8, the verification circuit 140B caches the program firmware that has exclusive access to the cache device Sram1. Verification code element information is stored in the verification information buffer 142B, and the verification code element information is used to verify the encrypted information. The verification processing circuit 141B can call the verification code element information stored in the verification information buffer 142B and the encryption information of the program firmware file header in the cache device Sram1 to implement security measurement verification. In an example, taking the encryption information of the file header as the public key and encryption indication information, and the verification code element information as the public key hash value and the firmware encryption root key as an example, its security measurement verification process can be as shown in Figure 12. First, the verification circuit 140B imports the program firmware into the cache device Sram1. Secondly, the verification circuit 140B calculates a public key hash value based on the public key of the firmware file header, and compares the calculated public key hash value with the public key hash value stored in the verification information buffer 142B. If the comparison results are different, the security metric verification of the program firmware fails. If the comparison results are the same, the decryption key of the program firmware is calculated based on the encryption instruction information of the file header and the firmware encryption root key. The symmetric cryptographic algorithm is further called based on the decryption key to decrypt the program firmware. Then, an asymmetric algorithm is called to perform signature verification on the program firmware. If the signature verification fails, the security metric verification of the program firmware fails. If the signature verification passes, it means that the security metric verification of the program firmware is successful.

[0102] For example, taking the at least two first processors 100B including two first processors 100B as an example, a possible situation in which the second chip system 1000B accesses and reads the second memory 300B during the boot-up phase and the working phase, the two first processors 100B are processor 1 and processor 2 respectively, is described as follows:

[0103] As shown in Figure 13, during the startup phase: First, in step S100A, processor 1 of the two first processors 100B is powered on, the boot program in the verification circuit 140B is started, processor 1 is initialized, and the status interface 110B of processor 1 is set to a high level. The control circuit 400B outputs a corresponding first storage strobe control signal to the storage strobe circuit 200B to establish a data exchange connection between processor 1 and the second memory 300B through the storage strobe circuit 200B. Then, in step S200A, processor 1 accesses the second memory 300B to read the communication program firmware. The communication program firmware is used to establish a communication connection between processor 1 and processor 2. After reading the communication program firmware, processor 1 sets the status interface 110B to a low level. Then, in step S300A, processor 1 begins running the communication program firmware to configure the relevant parameters for establishing a communication connection with processor 2. Similarly, in steps S100B-S300B, processor 2 is also powered on and reads and executes the communication program firmware based on a corresponding first storage selection control signal output by control circuit 400B. For the description of steps S100B-S300B, reference can be made to the description of steps S100A-S300A, and will not be repeated here.

[0104] During the post-boot operation phase, after processors 1 and 2 establish a communication connection, the control circuit 400B can select one of the two as a fixed, selected first processor 101B and the other as a fixed, shared first processor 102B based on the second storage conduction control signal, or dynamically set the selected first processor 101B and the shared first processor 102B based on the second storage selection control signal. For a second storage selection control signal, steps S100C to S300C as shown in FIG13 can be executed: In step S100C, the control circuit 400B outputs the second storage selection control signal to determine processor 1 as the selected first processor 101B. In step S200C, processor 1, as the selected first processor 101B, can access and read different first program firmware from the second memory 300B. In step S300C, processor 1, as the selected first processor 101B, executes the first program firmware according to the difference in the first program firmware, or transmits the corresponding shared program firmware to processor 2, as the shared first processor 102B.

[0105] The embodiment shown in FIG13 illustrates the case where two first processors 100B share the same second memory 300B to read and execute the first program firmware. The technical principles and effects of a larger number of first processors 100B sharing the same second memory 300B to read and execute the first program firmware can be found in the relevant description of the embodiment shown in FIG13 and will not be repeated here.

[0106] In some possible implementations, when the second chip system 1000B is further provided with at least one second processor 500B, the operating method further includes the operations of steps S100' to S300' as shown in FIG14 below:

[0107] S100 ′, outputting a third storage selection control signal to the storage selection circuit 200B.

[0108] In some possible implementations, the third storage strobe control signal is used to instruct the storage strobe circuit 200B to establish a data exchange connection between a selected second processor 501B among the at least one second processor 500B and the second memory 300B.

[0109] S200 ′: the selected second processor 501B reads the second program firmware from the second memory 300B through the memory gating circuit 200B.

[0110] In some possible embodiments, when a selected second processor 501B is determined based on a third storage selection control signal, so that the selected second processor 501B establishes a data interaction connection with the second memory 300B, the selected second processor 501B reads the second program firmware from the second memory 300B through the storage selection circuit 200B, and the second program firmware is used for the functional operation of the selected second processor 501B.

[0111] S300 ′: the selected second processor 501B runs the second program firmware.

[0112] In an embodiment of the present application, the second program firmware is the program firmware required for the operation of a selected second processor 501B. The second memory 300B can also be shared between at least two first processors 100B and at least one second processor 500B for storing the program firmware. When a second processor 500B needs to access and read its corresponding second program firmware, the control circuit 400B can select it as a selected second processor 501B through the third storage selection control signal, and the selected second processor 501B establishes a data interaction connection with the second memory 300B through the storage selection circuit 200B, thereby achieving access to the required second program firmware. After reading the required second program firmware, the second program firmware can be run.

[0113] An embodiment of the present application also provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a server, the server executes the operating method described in the above embodiments (for example, the operating method described in the embodiments of Figures 11, 12, 13 and 14).

[0114] The memory and cache devices involved in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0115] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0116] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0119] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0120] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0121] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0122] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip system, characterized in that: The system comprises a control circuit, a memory, a storage gating circuit, and at least two first processors; the at least two first processors are coupled to the memory via the storage gating circuit; wherein: The control circuit is configured to: in response to the at least two first processors being powered on, output a storage gating control signal to the storage gating circuit, wherein the storage gating control signal is configured to instruct the storage gating circuit to select one of the at least two first processors to establish a data interaction connection with the memory; The selected first processor is used to: when establishing a data interaction connection with the memory, read the first program firmware from the memory through the storage selection circuit, and the first program firmware is used for the functional operation of one or more of the at least two first processors.

2. The chip system according to claim 1, characterized in that The first program firmware includes communication program firmware, and the communication program firmware is used to establish a communication connection between the at least two first processors; wherein: The control circuit is specifically configured to: in response to the at least two first processors being powered on, sequentially output at least two first storage strobe control signals to the storage strobe circuit, wherein the at least two first storage strobe control signals correspond one-to-one to the at least two first processors, and each first storage strobe control signal is configured to instruct the storage strobe circuit to select the corresponding first processor as the selected first processor to establish a data interaction connection with the memory; The selected one first processor is used for: reading the communication program firmware from the memory through the storage gating circuit when establishing a data interaction connection with the memory based on the corresponding first storage gating control signal.

3. The chip system according to claim 2, characterized in that: The control circuit is specifically configured to: output a first storage gating control signal to the storage gating circuit, and output a feedback signal to the currently selected first processor, wherein the feedback signal is used to instruct the currently selected first processor to read the communication program firmware; and output a next first storage gating control signal to the storage gating circuit after the currently selected first processor completes reading the communication program firmware. The selected one first processor is configured to read the communication program firmware from the memory in response to the corresponding feedback signal.

4. The chip system according to claim 3, characterized in that: The first processor includes a status interface; the first processor is coupled to the control circuit via the status interface; wherein: Each of the at least two first processors is specifically configured to: In response to power-on, setting the status interface to a first level state, wherein the first level state is used to instruct the control circuit to output the corresponding first storage selection control signal to the memory; In response to the corresponding feedback signal, the communication program firmware is read from the memory through the storage selection circuit, and the status interface is set to a second level state, which is used to indicate that the corresponding first processor completes the reading of the communication program firmware.

5. The chip system according to any one of claims 2 to 4, characterized in that: The communication program firmware includes storage address information and network node address information; the storage address information and the network node address information are used for communication interaction between the at least two first processors; each of the first processors is used to: The storage address information and the network node address information are configured to establish the communication connection between the at least two processors.

6. The chip system according to any one of claims 1 to 5, characterized in that: The first program firmware further includes at least one shared program firmware, the at least one shared program firmware being program firmware required by the one first processor and at least one shared first processor, or being program firmware required by the at least one shared first processor; the at least one shared first processor being one or more first processors other than the one first processor; wherein: The control circuit is specifically configured to: output a second storage gating control signal to the storage gating circuit during the operation phase of the at least two first processors, wherein the second storage gating control signal is configured to instruct the storage gating circuit to select the one first processor to establish a data interactive connection with the memory; The selected one first processor is used for: reading the at least one shared program firmware from the memory when establishing a data interaction connection with the memory based on the second storage selection control signal; and outputting the shared program firmware to the shared first processor.

7. The chip system according to any one of claims 1 to 6, characterized in that: Each of the first processors includes a first interface circuit; the shared program firmware is transmitted between the at least two first processors based on the first interface circuit.

8. The chip system according to any one of claims 1 to 7, characterized in that: Each of the first processors further includes a verification circuit, and the first processor is configured to parse and verify the read first program firmware based on the verification circuit.

9. The chip system according to claim 8, characterized in that: The verification circuit includes a verification processing circuit and a verification information buffer; wherein: The verification information buffer is used to: store the verification code element information required for parsing and verifying the first program firmware; The verification processing circuit is used to parse and verify the first program firmware based on the verification code element information.

10. The chip system according to any one of claims 1 to 9, characterized in that: Each of the first processors further includes a second interface circuit; the first processor is coupled to the memory through the memory strobe circuit based on the second interface circuit.

11. The chip system according to any one of claims 1 to 10, characterized in that: The chip system further includes at least one second processor; the at least one second processor is coupled to the memory via the memory gating circuit; wherein: The control circuit is further configured to: output a third storage gating control signal to the storage gating circuit, wherein the third storage gating control signal is configured to instruct the storage gating circuit to select one of the at least one second processor to establish a data interaction connection with the memory; The selected second processor is used to: read second program firmware from the memory through the memory selection circuit when establishing a data interaction connection with the memory, and the second program firmware is used for the functional operation of the selected second processor.

12. The chip system according to any one of claims 1 to 11, characterized in that: The control circuit is a hardware digital logic circuit.

13. An operating method, characterized in that: Applicable to a chip system, the chip system comprising a memory, a memory gating circuit and at least two first processors; The at least two first processors are coupled to the memory via the memory gating circuit; the method comprising: Outputting a storage gating control signal to the storage gating circuit, wherein the storage gating control signal is used to instruct the storage gating circuit to select one of the at least two first processors to establish a data interactive connection with the memory; When the selected first processor establishes a data interaction connection with the memory, the first program firmware is read from the memory through the memory selection circuit. The first program firmware is used for the functional operation of one or more of the at least two first processors.

14. The operating method according to claim 13, characterized in that: The first program firmware includes communication program firmware, and the communication program firmware is used to establish a communication connection between the at least two first processors; wherein: Outputting the storage gating control signal to the storage gating circuit includes: in response to the at least two first processors being powered on, sequentially outputting at least two first storage gating control signals to the storage gating circuit, the at least two first storage gating control signals corresponding to the at least two first processors one-to-one, each first storage gating control signal being used to instruct the storage gating circuit to select the corresponding first processor as the selected first processor to establish a data interactive connection with the memory; The reading of the first program firmware from the memory through the storage selection circuit includes: the selected first processor reading the communication program firmware from the memory when establishing a data interaction connection with the memory based on the corresponding first storage selection control signal.

15. The operating method according to claim 14, characterized in that: The step of sequentially outputting at least two first storage gating control signals to the storage gating circuit includes: outputting one of the first storage gating control signals to the storage gating circuit, and outputting a corresponding feedback signal to the currently selected first processor, wherein the feedback signal is used to instruct the currently selected first processor to read the communication program firmware; and outputting a next of the first storage gating control signals to the storage gating circuit after the currently selected first processor completes reading the communication program firmware. The reading of the communication program firmware from the memory through the memory selection circuit includes: the selected one first processor reading the communication program firmware from the memory in response to the corresponding feedback signal.

16. The operating method according to claim 15, characterized in that: The first processor includes a status interface; and the reading of the communication program firmware from the memory includes: In response to the corresponding first processor being powered on, setting the status interface to a first level state, the first level state being used to instruct outputting the corresponding first storage selection control signal to the memory; In response to the feedback signal, the communication program firmware is read from the memory through the storage selection circuit, and the status interface is set to a second level state, which is used to indicate that the corresponding one first processor completes the reading of the communication program firmware.

17. The operating method according to any one of claims 14 to 16, characterized in that: The communication program firmware includes storage address information and network node address information; The storage address information and the network node address information are used for communication interaction between the at least two first processors; The method further comprises: Each of the first processors configures the storage address information and the network node address information, and establishes the communication connection between the at least two processors.

18. The operating method according to any one of claims 13 to 17, characterized in that: The first program firmware further includes at least one shared program firmware, the at least one shared program firmware being program firmware required by the one first processor and at least one shared first processor, or being program firmware required by the at least one shared first processor; the at least one shared first processor being one or more first processors other than the one first processor; wherein: Outputting the storage gating control signal to the storage gating circuit includes: outputting a second storage gating control signal to the storage gating circuit during the operation phase of the at least two first processors, wherein the second storage gating control signal is used to instruct the storage gating circuit to select the one first processor to establish a data interactive connection with the memory; The reading of the first program firmware from the memory through the storage strobe circuit includes: the selected one of the first processors reading the at least one shared program firmware from the memory when establishing a data interaction connection with the memory based on the second storage strobe control signal; The method further includes: the selected one first processor outputting the shared program firmware to the at least one shared first processor.

19. The operating method according to any one of claims 13 to 18, characterized in that: Each of the first processors further includes a verification circuit, and the method further includes: The first processor parses and verifies the read first program firmware based on the verification circuit.

20. The operating method according to claim 19, characterized in that: The parsing and verifying the read first program firmware includes: The first program firmware is parsed and verified based on the verification code element information.

21. The operating method according to any one of claims 13 to 20, characterized in that: The chip system also includes at least one second processor; The at least one second processor is coupled to the memory via the memory gating circuit; the method further comprising: outputting a third storage gating control signal to the storage gating circuit, wherein the third storage gating control signal is used to instruct the storage gating circuit to select one of the at least one second processors to establish a data interactive connection with the memory; When the selected second processor establishes a data interactive connection with the memory, the second program firmware is read from the memory through the memory gating circuit, where the second program firmware is used for the functional operation of the second processor.

22. A data processing board, characterized in that: It comprises a liner and a chip system as described in any one of claims 1 to 12, wherein the chip system is processed on the liner.

23. An electronic device, characterized in that: It comprises a shell and the data processing board as claimed in claim 22, wherein the data processing board is partially or completely arranged in the shell.

24. A computer-readable storage medium, characterized in that The computer-readable storage medium includes instructions, and when the instructions are executed on a server, the server executes the operation method according to any one of claims 13 to 21.

Images