Method for producing a stacked structure of the strained silicon-on-insulator type using a layer transfer technique based on 2d material

Abstract

The invention relates to a method for producing a stacked structure comprising a layer of semiconductor material bonded to a substrate, which comprises: producing a heterostructure by: • forming an intermediate layer made of a two-dimensional material on a growth substrate (1); patterning the intermediate layer with a plurality of openings to form a patterned intermediate layer (3); growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a handling substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from transferring the continuous epitaxial layer (4) from the heterostructure to the handling substrate (6).

Description

[0001] DESCRIPTION

[0002] METHOD OF MANUFACTURING A STACKED STRUCTURE OF THE STRAINED SILICON-ON-INSULATOR TYPE USING A TECHNIQUE

[0003] 2D MATERIAL BASED LAYER TRANSFER

[0004] Technical field

[0005] The field of the invention is that of methods for manufacturing a stacked structure comprising a layer of semiconductor material adhering to a substrate. More particularly, the invention relates to methods which implement a 2D material-based layer transfer technique in order, for example, to manufacture a stacked structure of the strained silicon on insulator type.

[0006] DESCRIPTION OF THE ASSOCIATED TECHNIQUE

[0007] Remote epitaxy is an emerging technology for the production of free-standing single-crystal thin films and structures. The method uses 2D van der Walls materials as semitransparent interlayers that enable epitaxy and exfoliation of epitaxial layers at the 2D layer interface by mechanical delamination, a technique known as 2D material-based layer transfer (2DLT).

[0008] As described, for example, in WO 2019 / 099461 A1, the 2DLT method may use a patterned 2D layer with a plurality of openings therein and the layer transfer is achieved by first depositing a stress layer made of nickel on the epitaxial layer previously grown on the patterned 2D material layer and then applying a ribbon layer to the stress layer. The stack consisting of the ribbon layer, the stress layer and the epitaxial layer may then be exfoliated after detachment induced at the patterned 2D layer by mechanical energy. After exfoliation, the ribbon layer and the stress layer are respectively detached and etched away using an Fe-Cl3 solution. However, iron is generally an undesirable contaminant for the production of semiconductor devices.

[0009] BRIEF DESCRIPTION OF THE INVENTION

[0010] The invention aims to provide a 2DLT technique that would not require the use of a stress layer and would therefore be free from the associated contamination. To this end, a method for manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate is provided, comprising: manufacturing a heterostructure by:

[0011] • formation of an intermediate layer made of a two-dimensional material on a growth substrate;

[0012] • shaping the intermediate layer with a plurality of openings to form a shaped intermediate layer;

[0013] • growing a semiconductor material on the patterned intermediate layer by epitaxial lateral overgrowth to form a continuous epitaxial layer on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a manipulation substrate, the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer so as to obtain a second assembly resulting from the transfer of the continuous epitaxial layer from the heterostructure to the manipulation substrate. The patterning of the intermediate layer is carried out so that 1% to 10% of a surface of the growth substrate on which the patterned intermediate layer is located is uncovered, the remainder being covered by the two-dimensional material.

[0014] The bonding of the heterostructure to the handling substrate includes one of surface activation bonding, atomic diffusion bonding and hydrophilic bonding accompanied by bonding strength strengthening annealing.

[0015] Some preferred, but not limiting, aspects of the method are: the handling substrate has a top oxide layer that is located at the bonding interface during formation of the first set; the handling substrate further has a trap-rich layer beneath the top oxide layer; it further comprises planarizing the top oxide layer prior to formation of the first set; the continuous epitaxial layer is a relaxed layer and fabricating the heterostructure further comprises epitaxially depositing a strained layer on the continuous epitaxial layer; it further comprises removing the continuous epitaxial layer from the second set; the strained layer is a strained silicon layer;the growth substrate comprises a gradient buffer and a relaxed growth layer on the gradient buffer, the gradient buffer having a gradient lattice parameter between a first lattice parameter and a second lattice parameter and the relaxed growth layer having the second lattice parameter; further comprising, after separating the first set at the patterned intermediate layer, recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer; the continuous epitaxial layer is a relaxed layer; further comprising planarizing the continuous epitaxial layer before forming the first set; patterning the intermediate layer leaves a peripheral ring of the two-dimensional material on the growth substrate;two neighboring openings of the modeled intermediate layer are separated by a distance which is less than 40 micrometers, preferably less than 20 micrometers.;

[0016] BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other aspects, purposes, advantages and characteristics of the invention will appear more clearly on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and implemented with reference to the appended drawings, in which: Figure 1, Figure 2, Figure 3, Figure 4, Figure 5 Figure

[0018] 6, Figure 7, Figure 8 and Figure 9 illustrate a possible embodiment of a method according to the invention; Figure 10 and Figure 11 represent two different embodiments of a heterostructure which can be used in a method according to the invention.

[0019] DETAILED DESCRIPTION OF THE INVENTION

[0020] A method of fabricating a stacked structure comprising a layer of semiconductor material adhered to a substrate is provided, which method implements a 2DLT process. More particularly, the 2DLT process utilizes a 2D material layer patterned with a plurality of openings therein.

[0021] This method involves the fabrication of a heterostructure. Referring to Figure 1, this fabrication begins with the provision of a growth substrate 1.

[0022] Next, with reference to Figure 2, the fabrication of the heterostructure comprises the formation of an intermediate layer 2 made of a two-dimensional material on the growth substrate 1. This formation can be carried out after the planarization of the surface of the growth substrate 1, for example, by means of chemical-mechanical polishing. This formation can include the deposition of the two-dimensional material on the growth substrate 1. In a non-exhaustive manner, this deposition can be carried out by MBE (molecular beam epitaxy), CVD (chemical vapor deposition) or ALD (atomic layer epitaxy).

[0023] The two-dimensional material can be hexagonal boron nitride h-BN, graphene or, more generally, any 2D "van der Walls" material allowing remote epitaxy. The intermediate layer 2 of two-dimensional material is thus made up of monoatomic sheets having weak interactions between them and whose number is limited to allow remote epitaxy of a layer of semiconductor material.

[0024] Referring to Figure 3, fabricating the heterostructure further comprises shaping the intermediate layer 2 with a plurality of openings to form a shaped intermediate layer 3.

[0025] Patterning the interlayer offers several advantages, such as those discussed, for example, in Kim, H., Lee, S., Shin, J. et al., Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction. Nat. Nanotechnol. 17, 1054- 1059 (2022). https: / / doi.org / 10.1038 / s41565-022-01200-6. In particular, patterning the interlayer can reduce the interface toughness between the growth substrate 1 and a continuous epitaxial layer 4 grown on the patterned interlayer as discussed below.

[0026] The openings can be made by etching the 2D material using a lithographic process. The openings can be trenches that delimit strips of 2D material. The trenches can be parallel to each other. A width of the trenches can be between several tens of nanometers and several micrometers. Two neighboring openings of the modeled intermediate layer are separated by a distance (the width of the strips in case of parallel trenches) that is less than 40 micrometers, preferably less than 20 micrometers. This distance between the openings is calibrated with respect to a difference between the lateral growth rate and the vertical growth rate and the correspondence of the thermal expansion coefficients of the materials so as to avoid the appearance of curvature, warping or cracks.

[0027] In a preferred embodiment, the patterning of the intermediate layer is carried out such that the patterned intermediate layer 3 has an openness ratio of between 1% and 10%, i.e., 1% to 10% of a surface of the growth substrate on which the patterned intermediate layer is located is uncovered, the remainder being covered by the two-dimensional material. In other words, the growth substrate has a 2D material coverage percentage of between 90% and 99%.

[0028] The lower limit of 1% is calibrated for a preferred embodiment described later (where a strained Si layer is grown on a continuous epitaxial layer 4 made of relaxed SiGe which is itself grown on a 2D material patterned with parallel trenches) and allows coalescence to be achieved for thicknesses that do not pose any problem of mismatch of thermal expansion coefficients. The upper limit of 10% allows operation in the exfoliation regime, and not in the other two regimes, namely flaking or delamination.

[0029] In one possible embodiment, the patterning of the intermediate layer is carried out so as to leave a peripheral ring of the two-dimensional material on the growth substrate. The presence of such a peripheral ring facilitates the initiation of subsequent separation at the patterned intermediate layer.

[0030] Referring to Figure 4, the fabrication of the heterostructure further comprises growing a semiconductor material on the patterned intermediate layer by epitaxial lateral overgrowth to form a continuous epitaxial layer 4 on the patterned intermediate layer s. More particularly, the growth of the semiconductor material begins with the localized growth of seeds in the patterned openings in the 2D material. Lateral growth of these seeds is then activated, which results in lateral growth of the seeds on the 2D material and, finally, coalescence to produce the continuous epitaxial layer 4.

[0031] In a preferred embodiment, the continuous epitaxial layer 4 is then planarized, for example, by means of chemical-mechanical polishing CMP, to improve its morphological quality and more particularly to obtain a uniform and controllable thickness and fewer coalescence defects.

[0032] In another embodiment shown in Figure 5, the fabrication of the heterostructure may further comprise performing the epitaxial deposition of one (or more) additional layer(s) 5 on the continuous epitaxial layer 4. It is thus possible to form a bilayer which is separated from the growth substrate 1 by the patterned intermediate layer 3. The additional layer 5 may be a strained layer, as will be illustrated below.

[0033] Once the heterostructure has been manufactured, with reference to Figure 6, the method of the invention comprises the formation of a first assembly by bonding the heterostructure to a handling substrate 6, the continuous epitaxial layer 4 being located at the bonding interface. In the case where an additional layer 5 has been previously formed on the continuous epitaxial layer, the bilayer which comprises the continuous epitaxial layer 4 is located at the bonding interface.

[0034] In a preferred embodiment, the handling substrate 6 comprises an upper oxide layer 7 which is located at the bonding interface during the formation of the first assembly. The handling substrate 6 may further comprise a trap-rich layer beneath the upper oxide layer.

[0035] The top oxide layer 7 may be planarized, for example, by means of chemical mechanical polishing CMP, before the formation of the first set. In particular, such planarization proves advantageous in reducing the surface toughness of the top oxide layer when it is grown on a trap-rich layer.

[0036] In an exemplary embodiment, the handling substrate 6 is a silicon substrate and the upper oxide layer 7 may have been formed by thermal oxidation of the silicon handling substrate.

[0037] The bonding of the heterostructure to the manipulation substrate 6 is performed so as to obtain an interface bonding energy at the bonding interface between the heterostructure and the manipulation substrate that is greater than the interface toughness, via the patterned interface 3, between the growth substrate 1 and the continuous epitaxial layer 4. In other words, the bonding strength is such that, relative to the patterned interface toughness, subsequent application of mechanical disassembly forces to the first assembly results in separation of the first assembly at the patterned interface rather than at the bonding interface.When the growth of the continuous epitaxial layer 4 takes place in the openings, the resulting interface energy is quite high, since it is related to the binding energy between the atoms of the 2D material and the overgrown layer, whereas, when the growth of the continuous epitaxial layer 4 takes place on the 2D material between the openings, the resulting interface energy is quite low, since no bond is formed between the 2D material and the overgrown layer, only a weak van der Waals interaction occurring.Therefore, the aperture ratio is a compromise between the overall interface energy required to enable subsequent separation and the processing time needed to achieve lateral epitaxial overgrowth of the continuous epitaxial layer (this processing time being all the greater the larger the apertures, and of course, the larger the apertures, the greater the growth thickness must be to achieve coalescence).

[0038] In one possible embodiment, the bonding of the heterostructure to the handling substrate comprises SAB surface activation bonding or ADB atomic diffusion bonding. In this way, high bond strength is achieved without the need for bond strength enhancing annealing. This is advantageous compared to the Smart Cut™ process implemented with trap-rich layers for which, during a heat treatment (such as that for strengthening a hydrophilic bond), grains are reorganized, giving rise to localized deformation at the bonding interface and, consequently, to low localized bonding energy. Later, during separation, the separation wave will tend to pass through the weakly bonded area and no layer transfer occurs around these regions. Due to the use of a 2D layer, there is no separation wave.Furthermore, no heat treatment is required for the SAB and ADB techniques. In another possible embodiment, the bonding of the heterostructure to the handling substrate comprises a hydrophilic bond and the formation of the first assembly further comprises carrying out an annealing to enhance the bond strength, for example between 900°C and 1100°C. Plasma treatment of the surfaces that have not yet been bonded can further be implemented, which allows for increased bond strength.

[0039] Once the first assembly is formed by bonding the heterostructure to the bonding substrate 6, with reference to Figure 7, the method of the invention comprises separating the first assembly at the patterned intermediate layer 3 so as to obtain a second assembly (shown in Figure 8) resulting from the transfer of the continuous epitaxial layer 4 from the heterostructure to the manipulation substrate 6. This separation may be a mechanical detachment at the patterned intermediate layer induced by separation of the heterostructure and the manipulation substrate, for example by insertion of a blade at the interface. Advantageously, this separation may be carried out at room temperature.

[0040] When the heterostructure comprises a bilayer, with reference to FIG. 9, the method may further comprise removing the continuous epitaxial layer 4 from the second set. This removal may comprise wet or dry etching of the continuous epitaxial layer 4 in which the additional layer 5 acts as an etch stop layer.

[0041] Figures 10 and 11 show two possible embodiments of a heterostructure which comprises a bilayer 4, 5 in which the additional layer 5 is a strained layer grown by heteroepitaxy on the continuous epitaxial layer 4. The additional layer may be a strained layer for the following reasons: the continuous epitaxial layer 4 is a relaxed layer, its thickness is greater than a critical thickness which is the thickness up to which relaxation does not occur and beyond which relaxation occurs by plastic deformation; the additional layer 5 is made of a material which has a lattice parameter different from the material of the epitaxial layer and its thickness is less than the critical thickness.

[0042] These two embodiments allow the transfer of such a constrained layer onto the manipulation substrate by detachment at the modeled 2D interface 3. The transferred layer remains constrained after its transfer onto the manipulation substrate.

[0043] As shown in Figure 10, the growth substrate 1 may be a silicon substrate on which a 2D intermediate layer, for example made of graphene, is formed. The 2D intermediate layer is patterned and the continuous epitaxial layer 4 is formed on the patterned 2D intermediate layer 3. The continuous epitaxial layer 4 may be a relaxed layer having a constant lattice parameter plateau, such as a relaxed SiGe layer with, for example, a Ge content of 20%. The additional layer 5 may be a strained silicon layer.

[0044] As shown in FIG. 11, the growth substrate 1 may be a silicon substrate on which a gradient buffer 8 and a relaxed growth layer 9 are formed on the gradient buffer 8. The gradient buffer has a gradient lattice parameter between a first lattice parameter and a second lattice parameter and the relaxed growth layer has the second lattice parameter. The gradient buffer may be a SiGe gradient buffer whose Ge content increases as the distance from the growth substrate 1 increases, for example from a Ge content of 0% to 20%. The relaxed growth layer 9 may be a SiGe layer with a Ge content of 20%. A 2D intermediate layer, for example made of graphene, is formed on the relaxed growth layer 9. The 2D intermediate layer is patterned and the continuous epitaxial layer 4 is formed on the patterned 2D intermediate layer 3.The continuous epitaxial layer 4 may be a relaxed layer having a constant lattice parameter plateau, such as a relaxed SiGe layer with, for example, a Ge content of 20%. The additional layer 5 may be a strained silicon layer.

[0045] Once separated at the patterned 2D intermediate layer, the heterostructure can be recycled in the following manner, to be used again in the method of the invention. First, remaining parts of the patterned intermediate layer can be removed, for example, by oxygen treatment in the case of graphene. Then, in the case of Figure 10, grinding and polishing of the growth substrate can be carried out before it can be used in a new cycle starting with the formation of a new 2D intermediate layer. In the case of Figure 11, polishing of the relaxed growth layer 9 can be carried out before a new 2D intermediate layer is formed thereon. In a preferred embodiment, the initial thickness of the relaxed growth layer 9 is several micrometers, thus allowing several recycling cycles to be carried out.Indeed, polishing the relaxed growth layer 9 in a recycling cycle can remove a thickness of between 3 μm and 4 μm. Carrying out several recycling cycles may require carrying out CTE compensation as disclosed, for example, in US 2008 / 017952 A1 by including a constrained transition layer in the gradient buffer.

[0046] In addition to enabling the transfer of the continuous epitaxial layer onto the handling substrate without requiring a strain layer, the invention is also advantageous in that it provides a method for transferring a strained layer onto a handling substrate that overcomes the disadvantages of prior art solutions. Considering the transfer of the strained silicon layer, a prior art solution that uses the Smart Cut™ process to fabricate a strained silicon-on-insulator structure is, for example, disclosed in WO 2007 / 019260 A1. It comprises forming a donor substrate by growing a strained Si layer on a relaxed SiGe layer and forming a cleavage plane in the relaxed SiGe layer by implanting ionic species.The donor substrate is then bonded to a handling substrate before being separated at the cleavage plane, thereby transferring the strained Si layer onto the handling substrate. Subsequently, the transferred strained Si layer is annealed to repair the damage caused by implantation, thus improving its crystallinity. However, a high number of dislocations is still observed and it becomes difficult to reduce the through-dislocation density below 10. 5 / cm 2 . In addition, many macroscopic defects are present in the final structure, especially inside the buried thin oxide layer. It should also be noted that this prior art solution hinders the integration of a trap-rich layer into the manipulation substrate due to the sensitivity of the transfer to the nanotopology / roughness of the bonded substrates.

[0047] Unlike this prior art solution, the present invention has the following advantages. The number of dislocations in the strained Si film is reduced by performing epitaxy through the patterned interlayer. Furthermore, since the detachment of the heterostructure at the 2D interface layer is completely different from the Smart Cut™ separation, the defectivity in the transferred layer is improved. Another advantage is also the fact that the 2D material covers the entire surface of the substrate (Figure 2), thus enabling a full wafer layer transfer without an unbonded edge crown, which also simplifies the recycling process. Another advantage is that it is compatible with the presence of a trap-rich layer.And finally, since the invention does not rely on implantation of ionic species, an annealing treatment is not necessary to repair the damage caused by the implantation and the invention can be carried out with a very low thermal budget.

Claims

Claims 1. A method of manufacturing a stacked structure comprising a layer of semiconductor material bonded to a substrate, comprising: manufacturing a heterostructure by: • formation of an intermediate layer (2) made of a two-dimensional material on a growth substrate (1); • shaping the intermediate layer with a plurality of openings to form a shaped intermediate layer (3); • growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a manipulation substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from the transfer of the continuous epitaxial layer (4) from the heterostructure to the manipulation substrate (6); wherein the patterning of the intermediate layer (2) is carried out so that 1% to 10% of a surface of the growth substrate on which the patterned intermediate layer is located is uncovered, the remainder being covered by the two-dimensional material;wherein bonding the heterostructure to the manipulation substrate comprises one of surface activation bonding, a; atomic diffusion bonding and hydrophilic bonding accompanied by annealing to strengthen the bonding strength.

2. Method according to claim 1, in which the handling substrate comprises an upper oxide layer (7) which is located at the bonding interface during the formation of the first assembly.

3. The method of claim 2, wherein the manipulation substrate further comprises a trap-rich layer beneath the upper oxide layer.

4. A method according to claim 3, further comprising planarizing the upper oxide layer (7) before forming the first assembly.

5. Method according to one of claims 1 to 4, in which the continuous epitaxial layer (4) is a relaxed layer and in which the fabrication of the heterostructure further comprises the epitaxial deposition of a strained layer (5) on the continuous epitaxial layer (4).

6. The method of claim 5, further comprising removing the continuous epitaxial layer (4) from the second assembly.

7. Method according to one of claims 5 and 6, in which the strained layer is a strained silicon layer.

8. A method according to any one of claims 1 to 7, wherein the growth substrate comprises a gradient pad (8) and a relaxed growth layer (9) on the gradient pad, the gradient pad having a gradient mesh parameter between a first mesh parameter and a second mesh parameter and the relaxed growth layer having the second mesh parameter.

9. A method according to claim 8, further comprising, after separating the first assembly at the patterned intermediate layer (3), recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer (9).

10. Method according to one of claims 1 to 9, in which the continuous epitaxial layer (4) is a relaxed layer.

11. Method according to one of claims 1 to 10, further comprising planarizing the continuous epitaxial layer (4) before forming the first assembly.

12. Method according to one of claims 1 to 11, in which the modeling of the intermediate layer (2) leaves a peripheral ring of the two-dimensional material on the growth substrate.

13. Method according to one of claims 1 to 12, in which two neighboring openings of the modeled intermediate layer are separated by a distance which is less than 40 micrometers, preferably less than 20 micrometers.

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