Display device

Abstract

A display device according to an embodiment comprises: a display area in which unit pixels each including a first light emitting area, a second light emitting area, and a third light emitting area are arranged; a first unit pixel disposed in a first column of the display area; and a second unit pixel disposed in a second column of the display area and adjacent to the first unit pixel in a first direction. Only the first light emitting area and the second light emitting area among the first light emitting area, the second light emitting area, and the third light emitting area of the first unit pixel may be disposed in a first edge portion located at one end of the first unit pixel in a second direction intersecting the first direction, and the first light emitting area, the second light emitting area, and the third light emitting area of the second unit pixel may be disposed in a second edge portion adjacent to the first edge portion in the first direction and located at one end of the second unit pixel in the second direction.

Description

display device

[0001] Embodiments of the present invention relate to a display device.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. In response, various types of display devices, including light-emitting displays, are being developed.

[0003] A display device may include pixels that emit light of different colors. For example, the display device may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. Accordingly, the display device can display full-color images.

[0004] The problem to be solved by the present invention is to provide a display device that can improve the image quality by improving the light-emitting area or aperture ratio of pixels while preventing or reducing the color fading phenomenon.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] A display device according to one embodiment includes a display area in which unit pixels, each of which includes a first light-emitting area, a second light-emitting area, and a third light-emitting area, are arranged; a first unit pixel arranged in a first column of the display area; and a second unit pixel arranged in a second column of the display area and adjacent to the first unit pixel in a first direction. In a first edge portion located at one end of the first unit pixel in a second direction intersecting the first direction, only the first light-emitting area and the second light-emitting area among the first light-emitting area, the second light-emitting area, and the third light-emitting area of ​​the first unit pixel may be arranged, and in a second edge portion adjacent to the first edge portion in the first direction and located at one end of the second unit pixel in the second direction, the first light-emitting area, the second light-emitting area, and the third light-emitting area of ​​the second unit pixel may be arranged.

[0007] In one embodiment, the first light-emitting region, the second light-emitting region, and the third light-emitting region of the first unit pixel may be arranged at a third edge portion located at the other end of the first unit pixel in the second direction.

[0008] In one embodiment, the first row of the display area may further include a first pad electrode disposed at the first edge portion.

[0009] In one embodiment, each of the unit pixels includes a first pixel electrode disposed in the first light-emitting region, a second pixel electrode disposed in the second light-emitting region, and a third pixel electrode disposed in the third light-emitting region, and the first pad electrode may be disposed between the first pixel electrode and the second pixel electrode of the first unit pixel at the first edge portion.

[0010] In one embodiment, the first pad electrode may overlap the first light-emitting area and the second light-emitting area of ​​the first unit pixel at the first edge portion.

[0011] In one embodiment, the size of the third light-emitting region is smaller than the size of each of the first light-emitting region and the second light-emitting region, and in the unit pixel region where the first unit pixel is arranged, the third light-emitting region may be arranged at a position spaced apart from the first edge portion.

[0012] In one embodiment, each of the unit pixels further includes a light-emitting layer and a common electrode disposed on the first pixel electrode, the second pixel electrode, and the third pixel electrode, wherein the common electrode can be electrically connected to the first pad electrode through a drilling hole disposed on the first pad electrode.

[0013] In one embodiment, the light-emitting layer and the common electrode are disposed across the entire display area, and the drilling hole can penetrate the light-emitting layer on the first pad electrode.

[0014] In one embodiment, the display device may further include a power line electrically connected to the first pad electrode and to which a common voltage is applied.

[0015] In one embodiment, in a fourth edge portion adjacent to the third edge portion in the first direction and located at the other end of the second unit pixel in the second direction, only the first light-emitting region and the second light-emitting region among the first light-emitting region, the second light-emitting region, and the third light-emitting region of the second unit pixel may be arranged.

[0016] In one embodiment, the first pixel electrode, the second pixel electrode, and the third pixel electrode of the second unit pixel may be electrically connected to respective pixel circuits through respective connection holes located in the fourth edge portion.

[0017] In one embodiment, the first row of the display area may further include a second pad electrode disposed at the third edge portion.

[0018] In one embodiment, the second pad electrode is disposed between the first light-emitting area and the second light-emitting area of ​​the first unit pixel in the third edge portion, and may overlap with the third light-emitting area of ​​the first unit pixel.

[0019] In one embodiment, the display area may further include a first group of pixel columns including the first row, each of which has a first light-emitting region, a second light-emitting region, and a third light-emitting region arranged in the same structure as the first unit pixel in each unit pixel area; and a second group of pixel columns including the second row, each of which has a first light-emitting region, a second light-emitting region, and a third light-emitting region arranged in the same structure as the second unit pixel in each unit pixel area.

[0020] In one embodiment, the pixel columns of the first group are arranged in the display area in a period of N (where N is a natural number greater than or equal to 2) pixel columns, and the pixel columns of the second group can be arranged between the pixel columns of the first group.

[0021] In one embodiment, the pixel columns of the first group and the pixel columns of the second group may be alternately arranged in the display area along the first direction.

[0022] In one embodiment, the display area may further include a plurality of pad electrodes arranged in the pixel columns of the first group.

[0023] In one embodiment, the pixel columns of the second group may not include pad electrodes.

[0024] In one embodiment, the first light-emitting region may be a red light-emitting region that emits red light, the second light-emitting region may be a green light-emitting region that emits green light, and the third light-emitting region may be a blue light-emitting region that emits blue light.

[0025] In one embodiment, the first direction may be a horizontal direction of the display area, and the second direction may be a vertical direction of the display area.

[0026] Specific details of other embodiments are included in the detailed description and drawings.

[0027] According to embodiments, by efficiently arranging the light-emitting areas and pad electrodes of the unit pixels in the display area, the light-emitting area or aperture ratio of the pixels and the unit pixels including the same can be improved. In addition, according to embodiments, edge portions located at both ends of the unit pixels, for example, an edge portion in which only the first light-emitting area and the second light-emitting area of ​​each of the unit pixels are arranged and an edge portion in which the first light-emitting area, the second light-emitting area, and the third light-emitting area of ​​each of the unit pixels are arranged, among the upper edge portion and the lower edge portion, can be arranged in an alternating manner. For example, a second edge portion in which the first light-emitting area, the second light-emitting area, and the third light-emitting area of ​​the second unit pixel are arranged can be arranged on one side of the first edge portion in which only the first light-emitting area and the second light-emitting area of ​​the first unit pixel are arranged. Accordingly, a color cast phenomenon that may occur in the upper edge portion or the lower edge portion of the pixel rows can be prevented or reduced, thereby improving the picture quality of the display device.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] FIG. 1 is a plan view showing a display device according to one embodiment.

[0030] Figure 2 is a plan view showing the display panel of Figure 1.

[0031] Figure 3 is a circuit diagram showing a pixel according to one embodiment.

[0032] Figure 4 is a plan view showing a display area according to one embodiment.

[0033] FIG. 5 is a cross-sectional view showing a display panel according to one embodiment.

[0034] FIG. 6 is a cross-sectional view showing a display panel according to one embodiment.

[0035] Fig. 7 is a cross-sectional view showing a display panel according to one embodiment.

[0036] Figure 8 is an enlarged view of area A1 of Figure 5.

[0037] Fig. 9 is a plan view showing a display area according to one embodiment.

[0038] Fig. 10 is a plan view showing a display area according to one embodiment.

[0039] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0040] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0041] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0042] Specific embodiments are described below with reference to the attached drawings.

[0043] Fig. 1 is a plan view showing a display device (100) according to one embodiment. Fig. 2 is a plan view showing a display panel (110) of Fig. 1.

[0044] Referring to FIGS. 1 and 2, the display device (100) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), and the like, as well as a television, a laptop, a monitor, a billboard, and the Internet of Things (IOT). These are presented only as examples, and the display device (100) can be employed in other electronic devices. For example, the display device (100) can be included in various forms or types of electronic devices capable of displaying images. In one embodiment, an electronic device including a display device (100) may further include a display device storage portion in which the display device (100) is stored, and / or a case or cover for protecting the display device (100).

[0045] In one embodiment, the display device (100) may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device including an ultra-small light-emitting diode such as a micro or nano light emitting diode (micro LED or nano LED), but is not limited thereto. For example, the display device (100) may be a type of display device other than a light-emitting display device. Hereinafter, embodiments in which the display device (100) is a light-emitting display device (for example, an organic light-emitting display device) are disclosed.

[0046] The display device (100) may include a display panel (110) including pixels (PX), and a first driving unit (120) and a second driving unit (130) that supply driving signals to the pixels (PX). The display device (100) may further include additional components. For example, the display device (100) may further include a power supply unit for supplying power voltages to the pixels (PX), the first driving unit (120) and the second driving unit (130), and a timing control unit for controlling the operations of the first driving unit (120) and the second driving unit (130).

[0047] The display panel (110) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area that displays an image by including pixels (PX). For example, the display area (DA) may include pixel areas in which each pixel (PX) is arranged. The non-display area (NDA) is an area excluding the display area (DA), and an image may not be displayed in the non-display area (NDA). In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0048] In FIGS. 1 and 2, a first direction (D1), a second direction (D2), and a third direction (D3) are defined. In one embodiment, the first direction (D1) may be a horizontal direction of the display panel (110) (or the display area (DA)), the second direction (D2) may be a vertical direction of the display panel (110) (or the display area (DA)), and the third direction (D3) may be a thickness direction of the display panel (110).

[0049] In one embodiment, the display panel (110) may be formed in a rectangular shape on a plane. Although FIGS. 1 and 2 illustrate a display panel (110) whose horizontal length is longer than its vertical length, the shape of the display panel (110) is not limited thereto. For example, the display panel (110) may have a shape in which the vertical length is longer than the horizontal length, or may have a square shape, etc. The display panel (110) may include angled corners or rounded corners.

[0050] The planar shape of the display panel (110) is not limited to the illustrated rectangular shape, and may be applied in other shapes. For example, the display panel (110) may have a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes in addition to the planar shape.

[0051] In one embodiment, the display panel (110) may be substantially flat on a plane defined by the first direction (D1) and the second direction (D2), and may have a uniform thickness in the third direction (D3). Alternatively, the display panel (110) may be provided in a three-dimensional shape having a curved surface, etc.

[0052] The display panel (110) may be provided as a rigid panel that is substantially not deformed, or may be provided as a flexible panel that can be deformed in a form such as by folding, bending, or rolling at least in one portion. The display panel (110) may be provided to the display device (100) in an unbent state, or may be provided to the display device (100) in a bent state in some sections.

[0053] A display panel (110) may include a substrate (SUB) (e.g., a lower substrate) and pixels (PX) arranged on the substrate (SUB). The pixels (PX) may be arranged in a display area (DA) on the substrate (SUB).

[0054] The substrate (SUB) is a base member for manufacturing or providing a display panel (110) and may constitute a base surface of the display panel (110). The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA).

[0055] The display area (DA) may have various shapes depending on the embodiments. For example, the display area (DA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes. In one embodiment, the display area (DA) may have a shape that matches the shape of the display panel (110).

[0056] Pixels (PX) may be provided and / or arranged in the display area (DA). For example, the display area (DA) may include a plurality of pixel areas in which pixels (PX) are arranged, respectively. Each pixel area may include a light-emitting area in which light is emitted from each pixel (PX).

[0057] In one embodiment, the display device (100) may be a light-emitting display device, and each pixel (PX) may include a light-emitting element positioned in each light-emitting area and a pixel circuit connected to the light-emitting element. In describing the embodiments, the term "connection" may include the meaning of electrical connection and / or physical connection. Each pixel circuit may include transistors (e.g., transistors including a driving transistor that generates a driving current corresponding to a data signal, and at least one switching transistor) and at least one capacitor (e.g., a storage capacitor).

[0058] The display area (DA) may further be provided with wires connected to the pixels (PX). For example, the display area (DA) may include signal lines and power lines connected to the pixels (PX). The signal lines and power lines may extend to the non-display area (NDA) and be connected to the first driver (120) or respective pads (PD). For example, some of the signal lines may be connected to the first driver (120) to transmit scan signals or control signals output from the first driver (120) to the pixels (PX), and other of the signal lines may be connected to the second driver (130) via the respective pads (PD) to transmit data signals output from the second driver (130) to the pixels (PX). The power lines may be connected to the respective pads (PD) to transmit pixel voltages supplied from a power supply unit or the like via a circuit board (140) or the like to the pixels (PX).

[0059] In FIG. 2, a second power line (VSL) connected to a common electrode (CE) is illustrated as an example of wires that can be arranged in a display area (DA), etc. In one embodiment, the common electrode (CE) may be one electrode (for example, a cathode electrode) of light-emitting elements provided to pixels (PX) and may be formed over the entire display area (DA). In one embodiment, the common electrode (CE) may have a shape and / or size corresponding to the display area (DA) and may extend outside the display area (DA) while having an area larger than the display area (DA).

[0060] In one embodiment, a second power line (VSL) may be provided in a panel circuit layer located below a light-emitting element layer on which a common electrode (CE) is disposed. The second power line (VSL) and the common electrode (CE) may be electrically connected to each other through a plurality of pad electrodes disposed in the display area (DA).

[0061] The second power line (VSL) can be connected to at least one pad (PD) (e.g., a power pad supplying a common voltage) located in the pad area (PA). For example, the second power line (VSL) can extend from the display area (DA) to the non-display area (NDA) and be directly connected to the at least one pad (PD), or can be connected to the at least one pad (PD) through a connection wire formed in the non-display area (NDA).

[0062] In one embodiment, the second power line (VSL) may include a low-resistance conductive material. By supplying a common voltage to the common electrode (CE) through the second power line (VSL), a voltage drop of the common voltage can be prevented, reduced, and / or minimized. Accordingly, a change in brightness due to a voltage drop of the common voltage can be prevented or reduced, and the image quality of the display device (100) can be improved.

[0063] In one embodiment, the second power line (VSL) may be a mesh-type wire arranged in a mesh shape in the display area (DA), but is not limited thereto. For example, depending on the design space available in the display area (DA), the position, shape, and / or size of the second power line (VSL) may be variously changed. For example, the second power line (VSL) may be composed only of horizontal wires extending in the first direction (D1) in the display area (DA), or may be composed only of vertical wires extending in the second direction (D2) in the display area (DA).

[0064] The non-display area (NDA) may include a pad area (PA) where pads (PD) are arranged. In one embodiment, the non-display area (NDA) may further include a driving circuit area located at least on one side of the display area (DA). At least one driving unit, pads (PD), and / or wiring may be arranged in the non-display area (NDA).

[0065] Pads (PD) may be arranged in the pad area (PA). At least one circuit board (140) may be arranged and / or bonded on the pad area (PA). In one embodiment, a plurality of circuit boards (140) connected to different pads (PD) may be arranged on the pad area (PA). The pads (PD) may include signal pads and power pads for transmitting driving signals and power voltages required for driving the pixels (PX) and / or the first driving unit (120) to the inside of the display panel (110).

[0066] The first driving unit (120) and the second driving unit (130) can generate driving signals for controlling the operation timing and brightness of the pixels (PX) and supply the driving signals to the pixels (PX). For example, the first driving unit (120) can be a gate driving unit including a scan driving unit and can be connected to the pixels (PX) through respective gate lines (e.g., scan lines and / or control lines). The first driving unit (120) can supply respective gate signals (e.g., control signals for controlling the operation timing of the pixels (PX) including scan signals and / or control signals) to the pixels (PX). The second driving unit (130) can be a data driving unit including source driving circuits and can be connected to the pixels (PX) through respective data lines. The second driving unit (130) can supply respective data signals to the pixels (PX).

[0067] In one embodiment, at least one of the first driving unit (120) and the second driving unit (130), or a portion of the at least one driving unit, may be built into the display panel (110). For example, the first driving unit (120) or a portion of the first driving unit (120) may be disposed on the substrate (SUB) of the display panel (110) and may be disposed and / or formed in a non-display area (NDA).

[0068] In FIG. 1, the first driving unit (120) is exemplified as being formed on one side of the display area (DA) (for example, the non-display area (NDA) on the right side of the display area (DA), but the embodiments are not limited thereto. For example, the first driving unit (120) may be positioned only on the other side of the display area (DA) (for example, the non-display area (NDA) on the left side of the display area (DA)) or on both sides of the display area (DA) (for example, the non-display areas (NDA) on the left and right sides of the display area (DA). Alternatively, a part of the first driving unit (120) may be positioned in the non-display area (NDA), and another part of the first driving unit (120) may be positioned in a non-emitting area (for example, an area between the emitting areas of the pixels (PX)) within the display area (DA).

[0069] In one embodiment, the other driving unit among the first driving unit (120) and the second driving unit (130), or a portion of the other driving unit, may be disposed or formed outside the display panel (110) and electrically connected to the display panel (110). For example, the second driving unit (130) may be implemented with a plurality of integrated circuit chips and may be disposed on circuit boards (140) that are electrically connected to the pixels (PX) of the display panel (110). The second driving unit (130) may also be implemented with at least one integrated circuit chip and mounted on a non-display area (NDA) of the display panel (110).

[0070] The circuit board (140) may be connected to the display panel (110) via pads (PD). In one embodiment, the circuit board (140) may be, but is not limited to, a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF). In one embodiment, the circuit board (140) may be connected to a timing control unit and / or a power supply unit via another circuit board or a connector.

[0071] Fig. 3 is a circuit diagram showing a pixel (PX) according to one embodiment. For example, Fig. 3 shows a pixel (PX) of a light-emitting display device including a light-emitting element (EL). The type and / or structure of the pixel (PX) that may be included in the display device (100) may vary depending on the embodiments.

[0072] Referring to FIG. 3, a pixel (PX) may include a light-emitting element (EL) and a pixel circuit (PXC) connected to the light-emitting element (EL). The light-emitting element (EL) is a light source of the pixel (PX), and may be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit (PXC) may control the light emission of the light-emitting element (EL).

[0073] The pixel circuit (PXC) may include transistors (T) and a capacitor (Cst). For example, the pixel circuit (PXC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a capacitor (Cst). Although FIG. 3 illustrates an embodiment in which all of the transistors (T) are N-type transistors, the types of the transistors (T) are not limited thereto. For example, at least one transistor (T) may be formed as a P-type transistor.

[0074] The pixel circuit (PXC) can supply driving current to the light emitting element (EL) in response to driving signals supplied from the first driving unit (120) and the second driving unit (130). For example, the pixel circuit (PXC) can supply driving current to the light emitting element (EL) in response to a scan signal (SC) and a control signal (SS) supplied from the first driving unit (120) through a scan line (SL) and a control line (CL), and a data signal (Vd) supplied from the second driving unit (130) through a data line (DL).

[0075] Although FIG. 3 illustrates an embodiment in which the scan line (SL) and the control line (CL) are separated from each other, the embodiments are not limited thereto. For example, the control line (CL) may be a portion of the scan line (SL) and may branch off from the scan line (SL), and the control signal (SS) may be a scan signal (SC).

[0076] The first transistor (T1) may be a driving transistor of a pixel (PX), in which the magnitude of a drain-source current (e.g., a driving current) is determined according to a gate-source voltage. The second and third transistors (T2, T3) may be switching transistors that are turned on or off according to their respective gate-source voltages. Depending on the type of each of the transistors (T) (e.g., a P-type or N-type transistor) and / or operating conditions, the first electrode of each of the transistors (T) may be a drain electrode (or a drain region) or a source electrode (or a source region), and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0077] A pixel (PX) may be connected to a scan line (SL) for transmitting a scan signal (SC), a control line (CL) for transmitting a control signal (SS) (e.g., a sensing control signal or an initialization control signal), and a data line (DL) for transmitting a data signal (Vd). In addition, the pixel (PX) may be connected to a first power line (VDL) for transmitting a driving voltage (ELVDD) (also referred to as a “first pixel voltage”), and a second power line (VSL) for transmitting a common voltage (ELVSS) (also referred to as a “second pixel voltage”). A voltage level of the common voltage (ELVSS) may be lower than a voltage level of the driving voltage (ELVDD). In one embodiment, the pixel (PX) may further be connected to an initialization power line (VIL) for transmitting an initialization voltage (VINT) (also referred to as a “third pixel power voltage”).

[0078] In one embodiment, the transistors (T) may be positioned in each pixel area and may be oxide transistors including an oxide semiconductor (also referred to as “oxide semiconductor transistors”). For example, the active layer of each of the first, second, and third transistors (T1, T2, T3) may include an oxide semiconductor. However, the embodiments are not limited thereto. For example, at least one transistor (T) may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polysilicon).

[0079] In one embodiment, a light-blocking layer or a light-blocking electrode may be disposed under the active layer of at least one of the first, second, and third transistors (T1, T2, T3). For example, a bottom electrode (or back-gate electrode) that blocks external light may be disposed under the active layer of the first transistor (T1). Accordingly, the operating characteristics of the first transistor (T1) can be stabilized.

[0080] A first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode (e.g., a drain electrode) connected to a first power line (VDL), and a second electrode (e.g., a source electrode) connected to a second node (N2). The second node (N2) may be a node to which a pixel circuit (PXC) and a light-emitting element (EL) are connected. The first transistor (T1) may control a driving current of a pixel (PX) in response to a data signal (Vd) transmitted to the first node (N1).

[0081] In one embodiment, the first transistor (T1) may further include a bottom electrode (for example, the bottom electrode (BE) of FIG. 5) connected to the second node (N2). By connecting the bottom electrode of the first transistor (T1) to the second node (N2) to form the first transistor (T1) into a double-gate structured transistor (for example, a double-gate transistor with a source-sync structure), the operating characteristics of the first transistor (T1) can be improved.

[0082] The second transistor (T2) may include a gate electrode connected to the scan line (SL), a first electrode connected to the data line (DL), and a second electrode connected to the first node (N1). The second transistor (T2) may be turned on by a scan signal (SC) of a gate-on voltage applied to the scan line (SL) to connect the data line (DL) and the first node (N1). Accordingly, a data signal (Vd) applied to the data line (DL) may be transmitted to the first node (N1).

[0083] The third transistor (T3) may include a gate electrode connected to a control line (CL) (or scan line (SL)), a first electrode connected to a second node (N2), and a second electrode connected to an initialization voltage line (VIL). The third transistor (T3) may be turned on by a control signal (SS) (or scan signal (SC)) of a gate-on voltage applied to the control line (CL) (or scan line (SL)) to connect the initialization voltage line (VIL) and the second node (N2).

[0084] A capacitor (Cst) can be connected between a first node (N1) and a second node (N2). The capacitor (Cst) can store a voltage (e.g., a difference between a gate voltage and a source voltage of a first transistor (T1)) corresponding to a data signal (Vd) (e.g., a data voltage) transmitted to the first node (N1).

[0085] The light emitting element (EL) may be connected between the pixel circuit (PXC) and the second power line (VSL). For example, the light emitting element (EL) may include a pixel electrode (e.g., a first electrode or an anode electrode of the light emitting element (EL)) connected to the pixel circuit (PXC) via a second node (N2), a common electrode (e.g., a second electrode or a cathode electrode of the light emitting element (EL)) facing the first electrode and connected to the second power line (VSL), and a light emitting layer interposed between the pixel electrode and the common electrode. In one embodiment, the pixel electrode of the light emitting element (EL) may be individually provided to each pixel (PX), and the common electrode of the light emitting element (EL) may be commonly provided to a plurality of pixels (PX). The light emitting element (EL) may emit light with a brightness corresponding to the driving current during a period in which the driving current is supplied from the pixel circuit (PXC).

[0086] Fig. 4 is a plan view showing a display area (DA) according to one embodiment. For example, Fig. 4 shows a portion of a display area (DA) in which four adjacent unit pixels (UPX) are arranged.

[0087] Referring to FIG. 4, unit pixels (UPX) may be arranged in the display area (DA). In one embodiment, the unit pixels (UPX) may be arranged in a matrix form in the display area (DA) along the first direction (D1) and the second direction (DR2). For example, the unit pixels (UPX) may be arranged in pixel columns arranged along the first direction (D1) in the display area (DA), such as a first column (COL1) and a second column (COL2). In each pixel column, the unit pixels (UPX) may be arranged along the second direction (D2).

[0088] In Fig. 4, as representative unit pixels (UPX) arranged in the display area (DA), a first unit pixel (UPX1) and a third unit pixel (UPX3) sequentially arranged along a second direction (D2) in a first column (COL1), and a second unit pixel (UPX2) and a fourth unit pixel (UPX4) sequentially arranged along a second direction (D2) in a second column (COL2) adjacent to the first column (COL1) in the first direction (D1) are illustrated. For example, the first unit pixel (UPX1) and the second unit pixel (UPX2) may be adjacent to each other in the first direction (D1), and the first unit pixel (UPX1) and the third unit pixel (UPX3) may be adjacent to each other in the second direction (D2). The third unit pixel (UPX3) and the fourth unit pixel (UPX4) may be adjacent to each other in the first direction (D1), and the second unit pixel (UPX2) and the fourth unit pixel (UPX4) may be adjacent to each other in the second direction (D2).

[0089] The display area (DA) may include an emission area (EA) of each pixel (PX) and a non-emission area (NEA) located around the emission area (EA). For example, the non-emission area (NEA) may be located between and / or around the emission areas (EA) and may surround each emission area (EA).

[0090] Each unit pixel (UPX) may include a plurality of pixels (PX) that emit light of different colors in their respective light-emitting areas (EA). For example, each unit pixel (UPX) may include a first pixel (PX1) including a first light-emitting area (EA1), a second pixel (PX2) including a second light-emitting area (EA2), and a third pixel (PX3) including a third light-emitting area (EA3).

[0091] Although the positions of the pixels (PX) are indicated based on the light-emitting area (EA) of each pixel (PX) in FIG. 4, the embodiments are not limited thereto. For example, the pixel area provided by each pixel (PX) may include a light-emitting area (EA) in which light-emitting elements (EL) and the like are arranged and a pixel circuit area in which circuit elements of a pixel circuit (PXC) are arranged. In one embodiment, the light-emitting area (EA) and the pixel circuit area of ​​each pixel (PX) may overlap each other.

[0092] In addition, although FIG. 4 discloses an embodiment in which each unit pixel (UPX) includes a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3), the embodiments are not limited thereto. For example, the types, numbers, and / or ratios of pixels (PX) included in each unit pixel (UPX) may vary depending on the embodiments.

[0093] The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be light-emitting areas that emit a first color of light, a second color of light, and a third color of light, respectively. In one embodiment, the first color of light, the second color of light, and the third color of light may be red light, green light, and blue light, respectively. For example, the first light-emitting area (EA1) may be a red light-emitting area that emits red light, the second light-emitting area (EA2) may be a green light-emitting area that emits green light, and the third light-emitting area (EA3) may be a blue light-emitting area that emits blue light. In this case, the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be a red pixel, a green pixel, and a blue pixel, respectively. However, the embodiments are not limited thereto. For example, the color (or wavelength) of the light emitted from each light-emitting area (EA), the type of each pixel (PX), and the like may vary depending on the embodiments.

[0094] The first pixel (PX1) may include a light-emitting element (EL) that emits light of a first color (e.g., a red light-emitting element), or may include a light-emitting element (EL) that emits light of a specific color (e.g., blue or white) and a wavelength shifter that converts light of the specific color into light of the first color. Accordingly, light of the first color may be emitted from the first light-emitting area (EA1).

[0095] The second pixel (PX2) may include a light-emitting element (EL) that emits light of a second color (for example, a green light-emitting element), or may include a light-emitting element (EL) that emits light of a specific color and a wavelength shifter that converts the light of the specific color into light of the second color. Accordingly, light of the second color may be emitted from the second light-emitting area (EA2).

[0096] The third pixel (PX3) may include a light-emitting element (EL) that emits light of a third color (e.g., a blue light-emitting element), or may include a light-emitting element (EL) that emits light of a specific color and a wavelength shifter that converts the light of the specific color into light of the third color. Accordingly, light of the third color may be emitted from the third light-emitting area (EA3).

[0097] In one embodiment, color filters (CF) that transmit light of a color to be emitted from each pixel (PX) may be arranged in the light-emitting areas (EA). For example, a first color filter (e.g., a red color filter) that transmits light of a first color may be arranged in the first light-emitting area (EA1), a second color filter (e.g., a green color filter) that transmits light of a second color may be arranged in the second light-emitting area (EA2), and a third color filter (e.g., a blue color filter) that transmits light of a third color may be arranged in the third light-emitting area (EA3).

[0098] Each of the light-emitting areas (EA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, or any other shape. The light-emitting areas (EA) may have substantially the same shape and size, or may have different shapes and / or sizes.

[0099] For example, the shape, size, ratio and / or arrangement of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be determined or changed depending on various factors such as the aperture ratio (e.g., the area or ratio of the light-emitting area in which light generated from each pixel (PX) passes through the color filter of each color provided in the color filter layer and is emitted to the outside), transmittance, luminous efficiency, lifespan, visibility, white balance, or color coordinates of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). In one embodiment, the first light-emitting area (EA1) and the second light-emitting area (EA2) may have the same or similar sizes, and the third light-emitting area (EA3) may have a smaller size than each of the first light-emitting area (EA1) and the second light-emitting area (EA2). In one embodiment, the third light-emitting area (EA3) may be positioned between the first light-emitting area (EA1) and the second light-emitting area (EA2) in the first direction (D1), but is not limited thereto.

[0100] Each pixel (PX) may include a light-emitting element (EL) arranged in each light-emitting area (EA). For example, each pixel (PX) may include a pixel electrode (AE) arranged in each light-emitting area (EA), and a light-emitting layer (e.g., the light-emitting layer (OL) of FIGS. 5 to 7) and a common electrode (CE) (e.g., the common electrode (CE) of FIGS. 2 and 5 to 7) sequentially arranged on the pixel electrode (AE). The pixel electrode (AE), the light-emitting layer, and the common electrode (CE) arranged in each light-emitting area (EA) may form each light-emitting element (EL).

[0101] For example, a first pixel (PX1) may include a first pixel electrode (AE1) disposed in a first emission area (EA1) and a light-emitting element (EL) including a light-emitting layer and a common electrode (CE) disposed on the first pixel electrode (AE1) (for example, the first light-emitting element (EL1) of FIG. 5). A second pixel (PX2) may include a second pixel electrode (AE2) disposed in a second emission area (EA2) and a light-emitting element (EL) including a light-emitting layer and a common electrode (CE) disposed on the second pixel electrode (AE2) (for example, the second light-emitting element (EL2) of FIG. 6). A third pixel (PX3) may include a third pixel electrode (AE3) disposed in a third emission area (EA3) and a light-emitting element (EL) including a light-emitting layer and a common electrode (CE) disposed on the third pixel electrode (AE3) (for example, the third light-emitting element (EL3) of FIG. 7).

[0102] Each pixel electrode (AE) may be primarily positioned in each light-emitting area (EA). Each pixel electrode (AE) may have a shape and / or size corresponding to each light-emitting area (EA), but is not limited thereto. In one embodiment, a portion (for example, at least a portion of an edge portion) of at least one pixel electrode (AE) may be positioned outside the light-emitting area (EA). In addition, the edge portion of each pixel electrode (AE) may be covered with a pixel defining layer (PDL).

[0103] In one embodiment, a common electrode (CE) may be disposed across the entire display area (DA). The common electrode (CE) may be electrically connected to the pad electrodes (DPD) through drilling holes (DH) disposed on the pad electrodes (DPD).

[0104] In one embodiment, the light-emitting layer is interposed between the pixel electrodes (AE) and the common electrode (CE) and can be arranged over the entire display area (DA). Each drilling hole (DH) can penetrate the light-emitting layer on each pad electrode (DPD).

[0105] The display device (100) may further include a pixel defining layer (PDL) disposed at least in the display area (DA) and covering edge portions of the pixel electrodes (AE) and the pad electrodes (DPD). The pixel defining layer (PDL) may be opened to expose the pixel electrodes (AE) in each of the light-emitting areas (EA). For example, the pixel defining layer (PDL) may include openings corresponding to the light-emitting areas (EA) of the pixels (PX). The openings of the pixel defining layer (PDL) may have a shape and / or size similar to or identical to the shape and / or size of the light-emitting areas (EA), but are not limited thereto. In one embodiment, the pixel defining layer (PDL) may be disposed on edge portions of the light-emitting areas (EA) and / or edge portions of the pixel electrodes (AE) in the non-light-emitting area (NEA). The pixel defining layer (PDL) may be opened to expose the pad electrodes (DPDs) in each drilling area (or connection area) where each pad electrode (DPD) is positioned. For example, the pixel defining layer (PDL) may include an opening that exposes each pad electrode (DPD) in an area where a drilling hole (DH) is positioned.

[0106] Each pixel electrode (AE) may be electrically connected to a pixel circuit (PXC) of each pixel (PX) (e.g., at least one circuit element constituting each pixel circuit (PXC), including the first transistor (T1) of FIG. 3) through a respective connection hole (CNT) (e.g., each contact hole or via hole). In one embodiment, each connection hole (CNT) may be covered with a pixel defining layer (PDL).

[0107] In one embodiment, each pixel electrode (AE) may be electrically connected to a pixel circuit (PXC) of each pixel (PX) at an edge portion located at one end of each unit pixel (UPX) or around the edge portion. For example, a first pixel electrode (AE1) of a first unit pixel (UPX1) may be electrically connected to a circuit element constituting the pixel circuit (PXC) of the first pixel (PX1) through a first connection hole (CNT1) at a third edge portion (EDG3) located at one end (for example, a bottom) of the first unit pixel (UPX1). A second pixel electrode (AE2) of the first unit pixel (UPX1) may be electrically connected to a circuit element constituting the pixel circuit (PXC) of the second pixel (PX2) through a second connection hole (CNT2) at a third edge portion (EDG3) of the first unit pixel (UPX1). The third pixel electrode (AE3) of the first unit pixel (UPX1) can be electrically connected to a circuit element constituting a pixel circuit (PXC) of the third pixel (PX3) through a third connection hole (CNT3) at the periphery of the third edge portion (EDG3) of the first unit pixel (UPX1) (or inside the third edge portion (EDG3)). The first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3) of the second unit pixel (UPX2) can be electrically connected to circuit elements constituting the pixel circuit (PXC) of the first pixel (PX1), the pixel circuit (PXC) of the second pixel (PX2), and the pixel circuit (PXC) of the third pixel (PX3), respectively, through the first connection hole (CNT1), the second connection hole (CNT2), and the third connection hole (CNT3), respectively, at the fourth edge portion (EDG4) located at one end (e.g., the bottom) of the second unit pixel (UPX2).

[0108] The display device (100) may further include pad electrodes (DPD) located only in some of the pixel columns (COL) of the display area (DA). For example, the display device (100) may include a plurality of pad electrodes (DPD) located in some of the pixel columns (COL) including the first column (COL1) (for example, the pixel columns of the first group). Pad electrodes (DPD) may not be located in the remaining pixel columns (COL) including the second column (COL2) (for example, the pixel columns of the second group).

[0109] Each pad electrode (DPD) (also referred to as a “connection electrode” or a “drilling pad”) may be electrically connected to a second power line (VSL) (e.g., the second power line (VSL) of FIG. 2) to which a common voltage (ELVSS) is applied through each fourth connection hole (CNT4). In one embodiment, each fourth connection hole (CNT4) may be covered with a pixel defining layer (PDL). The pixel defining layer (PDL) may include openings that expose a portion of each of the pad electrodes (DPD) and may cover a different portion of each of the pad electrodes (DPD). For example, the pixel defining layer (PDL) may expose a portion of each of the pad electrodes (DPD) including an area in which each of the drilling holes (DH) is arranged and cover the remaining portion (e.g., an edge portion) of each of the pad electrodes (DPD). In one embodiment, each drilling hole (DH) may be, but is not limited to, a laser drilling hole formed by a laser drilling method using a laser. Each pad electrode (DPD) may be electrically connected to the common electrode (CE) through each drilling hole (DH). For example, each pad electrode (DPD) may be a connection electrode connected between the second power line (VSL) and the common electrode (CE). In one embodiment, each pad electrode (DPD) may be, but is not limited to, a laser drilling pad connected to the common electrode (CE) through a laser drilling hole.

[0110] In one embodiment, at least one pad electrode (DPD) may be arranged in each of the pixel columns (COL) including pad electrodes (DPD). For example, the first column (COL1) may include a plurality of pad electrodes (DPD) including a first pad electrode (DPD1), a second pad electrode (DPD2), and a third pad electrode (DPD3) located around the first unit pixel (UPX1) and the third unit pixel (UPX3). Although FIG. 4 illustrates an embodiment in which pad electrodes (DPD) are arranged at both ends of each unit pixel (UPX) located in the pixel column (COL) including pad electrodes (DPD) (for example, the first pixel column (COL1)) (for example, the first edge portion (EDG1) corresponding to the upper end and the third edge portion (EDG3) corresponding to the lower end among both ends of each unit pixel (UPX) in the second direction (D2), the embodiments are not limited thereto. For example, pad electrodes (DPD) may be arranged only on at least one side of unit pixels (UPX) located in some pixel rows, and may not be arranged around unit pixels (UPX) located in the remaining pixel rows. The arrangement period or arrangement form of pad electrodes (DPD) may vary depending on the embodiments.

[0111] In one embodiment, the shape of the unit pixels (UPX) arranged in the pixel columns (COL) including the pad electrodes (DPD) may be different from the shape of the unit pixels (UPX) arranged in the pixel columns (COL) not including the pad electrodes (DPD). For example, the arrangement shape of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of each of the unit pixels (UPX) arranged in the first pixel column (COL1) may be different from the arrangement shape of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of each of the unit pixels (UPX) arranged in the second pixel column (COL2).

[0112] The first unit pixel (UPX1) may include a first edge portion (EDG1) and a third edge portion (EDG3) located at opposite ends in the second direction (D2). For example, the first edge portion (EDG1) may be an upper edge portion of the first unit pixel (UPX1), and the third edge portion (EDG3) may be a lower edge portion of the first unit pixel (UPX1).

[0113] In one embodiment, only the first emission area (EA1) and the second emission area (EA2) among the first emission area (EA1), the second emission area (EA2), and the third emission area (EA3) of the first unit pixel (UPX1) may be arranged in the first edge portion (EDG1) of the first unit pixel (UPX1). For example, the upper edge portions of the first emission area (EA1) and the second emission area (EA2) may be arranged adjacent to each other in the first edge portion (EDG1) of the first unit pixel (UPX1).

[0114] In one embodiment, the third light-emitting area (EA3) of the first unit pixel (UPX1) may be disposed at a position spaced apart from the first edge portion (EDG1) in the unit pixel area where the first unit pixel (UPX1) is disposed. For example, the upper edge portion of the third light-emitting area (EA3) of the first unit pixel (UPX1) may be disposed between the first edge portion (EDG1) and the third edge portion (EDG3). In one embodiment, the third light-emitting area (EA3) may be disposed between the first light-emitting area (EA1) and the second light-emitting area (EA2) in the first direction (D1) based on the central portion between the first edge portion (EDG1) and the third edge portion (EDG3) of the first unit pixel (UPX1). In one embodiment, the first light-emitting area (EA1) and the second light-emitting area (EA2) may be positioned to the right and left of the third light-emitting area (EA3), respectively, but this is not limited thereto. For example, the positions of the first light-emitting area (EA1) and the second light-emitting area (EA2) may be reversed.

[0115] A first pad electrode (DPD1) may be further disposed on a first edge portion (EDG1) of a first unit pixel (UPX1). For example, a portion of the first pad electrode (DPD1) may be disposed between the first pixel electrode (AE1) and the second pixel electrode (AE2) of the first unit pixel (UPX1). In one embodiment, the first pad electrode (DPD1) may be disposed on the same layer as the pixel electrodes (AE) and spaced apart from the pixel electrodes (AE).

[0116] In one embodiment, in the first edge portion (EDG1) of the first unit pixel (UPX1), the first pad electrode (DPD1) may overlap the first emission area (EA1) and the second emission area (EA2) of the first unit pixel (UPX1). For example, when viewed on a plane defined by the first direction (D1) and the second direction (D2), the first emission area (EA1) and the second emission area (EA2) of the first unit pixel (UPX1) may extend from the periphery of the first pad electrode (DPD1) to the outside of the first pixel electrode (AE1) and the second pixel electrode (AE2) of the first unit pixel (UPX1), respectively, so as to overlap a portion of the first pad electrode (DPD1).

[0117] In one embodiment, the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the first unit pixel (UPX1) may all be arranged at the third edge portion (EDG3) of the first unit pixel (UPX1). For example, the lower edge portions of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be arranged at the third edge portion (EDG3) of the first unit pixel (UPX1).

[0118] In one embodiment, a second pad electrode (DPD2) may be further disposed at a third edge portion (EDG3) of the first unit pixel (UPX1). For example, a portion of the second pad electrode (DPD2) may be disposed between the first pixel electrode (AE1) and the second pixel electrode (AE2) of the first unit pixel (UPX1) at the third edge portion (EDG3) of the first unit pixel (UPX1).

[0119] In one embodiment, the third pixel electrode (AE3) of the first unit pixel (UPX1) may be disposed inward of the second pad electrode (DPD2) in the first unit pixel area where the first unit pixel (UPX1) is disposed. When viewed on a plane defined by the first direction (D1) and the second direction (D2), the third light-emitting area (EA3) of the first unit pixel (UPX1) may extend outside the third pixel electrode (AE3) of the first unit pixel (UPX1) and overlap with a portion of the second pad electrode (DPD). In the third edge portion (EDG3) of the first unit pixel (UPX1), the second pad electrode (DPD2) may be disposed between the first light-emitting area (EA1) and the second light-emitting area (EA2) of the first unit pixel (UPX1) and may overlap with the third light-emitting area (EA3) of the first unit pixel (UPX1).

[0120] The second unit pixel (UPX2) may include a second edge portion (EDG2) and a fourth edge portion (EDG4) located at opposite ends in the second direction (D2). For example, the second edge portion (EDG2) may be an upper edge portion of the second unit pixel (UPX2), and the fourth edge portion (EDG4) may be a lower edge portion of the second unit pixel (UPX2). The second edge portion (EDG2) of the second unit pixel (UPX2) may be adjacent to the first edge portion (EDG3) of the first unit pixel (UPX1) in the first direction (D1). The fourth edge portion (EDG4) of the second unit pixel (UPX2) may be adjacent to the third edge portion (EDG3) of the first unit pixel (UPX1) in the first direction (D1).

[0121] In one embodiment, the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the second unit pixel (UPX2) may all be arranged in the second edge portion (EDG2) of the second unit pixel (UPX2). For example, the upper edge portions of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be arranged in the second edge portion (EDG2) of the second unit pixel (UPX2).

[0122] In one embodiment, in the second edge portion (EDG2) of the second unit pixel (UPX2), the third light-emitting area (EA3) may be positioned between the first light-emitting area (EA1) and the second light-emitting area (EA2). For example, the first light-emitting area (EA1) and the second light-emitting area (EA2) may be positioned on the right and left sides of the third light-emitting area (EA3), respectively. The positions of the first light-emitting area (EA1) and the second light-emitting area (EA2) may also be reversed.

[0123] In one embodiment, only the first light-emitting area (EA1) and the second light-emitting area (EA2) among the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the second unit pixel (UPX2) may be arranged in the fourth edge portion (EDG4) of the second unit pixel (UPX2). For example, the lower edge portions of the first light-emitting area (EA1) and the second light-emitting area (EA2) may be arranged adjacent to each other in the fourth edge portion (EDG4) of the second unit pixel (UPX2).

[0124] In one embodiment, the third light-emitting area (EA3) of the second unit pixel (UPX2) may be positioned at a position spaced apart from the fourth edge portion (EDG4) in the unit pixel area where the second unit pixel (UPX2) is positioned. For example, the lower edge portion of the third light-emitting area (EA3) of the second unit pixel (UPX2) may be positioned between the second edge portion (EDG2) and the fourth edge portion (EDG4).

[0125] In one embodiment, the first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3) of the second unit pixel (UPX2) may be electrically connected to respective pixel circuits (PXC) through respective connection holes (CNT) located in the fourth edge portion (EDG4) of the second unit pixel (UPX2). For example, the third pixel electrode (AE3) of the second unit pixel (UPX2) may extend outside the third light-emitting area (EA3) and may be connected to the pixel circuit (PXC) provided to the third pixel (PX3) of the second unit pixel (UPX2) through the third connection hole (CNT3) in the fourth edge portion (EDG4).

[0126] In FIG. 4, an embodiment is disclosed in which only the first light-emitting area (EA1) and the second light-emitting area (EA2) of the first unit pixel (UPX1) are exposed at the first edge portion (EDG1) of the first unit pixel (UPX1), and all of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the first unit pixel (UPX1) are exposed at the third edge portion (EDG3) of the first unit pixel (UPX1), but the embodiments are not limited thereto. For example, in another embodiment, the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the first unit pixel (UPX1) may all be exposed at the first edge portion (EDG1) of the first unit pixel (UPX1), and only the first light-emitting area (EA1) and the second light-emitting area (EA2) of the first unit pixel (UPX1) may be exposed at the third edge portion (EDG3) of the first unit pixel (UPX1). As an example, the first unit pixel (UPX1) may have a shape that is flipped upside down in FIG. 4. In this case, the shape of the second unit pixel (UPX2) may also be changed. For example, only the first light-emitting area (EA1) and the second light-emitting area (EA2) of the second unit pixel (UPX2) may be exposed at the second edge portion (EDG2) of the second unit pixel (UPX2), and the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the second unit pixel (UPX2) may all be exposed at the fourth edge portion (EDG4) of the second unit pixel (UPX2). As an example, the second unit pixel (UPX2) may have a shape that is upside-down reversed in FIG. 4.

[0127] In one embodiment, the light emitting areas (EA) that emit light of the color with the best visibility among the light emitting areas (EA) of each unit pixel (UPX) can be positioned at both edge portions located at both ends of each unit pixel (UPX). For example, the second light emitting area (EA2) that emits green light among the light emitting areas (EA) of the first unit pixel (UPX1) can be positioned at both the first edge portion (EDG1) and the third edge portion (EDG3) of the first unit pixel (UPX1).

[0128] In one embodiment, the unit pixels (UPX) arranged in each pixel column (COL) may have substantially the same shape and / or structure. For example, the first unit pixel (UPX1) and the third unit pixel (UPX3) arranged in the first column (COL1) may have substantially the same shape and / or structure, and the second unit pixel (UPX2) and the fourth unit pixel (UPX) arranged in the second column (COL2) may have substantially the same shape and / or structure.

[0129] Fig. 5 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 6 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 7 is a cross-sectional view showing a display panel (110) according to one embodiment.

[0130] For example, FIGS. 5, 6, and 7 show one embodiment of a cross-section of a first pixel (PX1) corresponding to a line X1 to X1' of FIG. 4, a cross-section of a second pixel (PX2) corresponding to a line X2 to X2' of FIG. 4, and a cross-section of a third pixel (PX3) corresponding to a line X3 to X3' of FIG. 4, respectively. FIGS. 5 to 7 show a light-emitting display panel including a light-emitting element (EL) (for example, a tandem organic light-emitting diode) as an example of a display panel (110) to which the embodiments can be applied. As an example, FIGS. 5 to 7 show a part of a light-emitting display panel including a light-emitting element (EL).

[0131] In addition to FIGS. 1 to 4 and referring to FIGS. 5 to 7, the display panel (110) may include a substrate (SUB) (or lower substrate (SUB1)), a panel circuit layer (PCL), a light emitting element layer (LEL), and an encapsulation layer (ENL). In one embodiment, the display panel (110) may further include a light conversion layer (WCL), a color filter layer (CFL), and a protective layer (PRL). The panel circuit layer (PCL), the light emitting element layer (LEL), the encapsulation layer (ENL), the light conversion layer (WCL), the color filter layer (CFL), and the protective layer (PRL) may be arranged to overlap each other on the substrate (SUB). For example, the panel circuit layer (PCL), the light emitting element layer (LEL), the encapsulation layer (ENL), the light conversion layer (WCL), the color filter layer (CFL), and the protective layer (PRL) may be sequentially arranged on the substrate (SUB) along a third direction (D3). The positions and configurations of the panel circuit layer (PCL), light emitting element layer (LEL), encapsulation layer (ENL), light conversion layer (WCL), color filter layer (CFL), and / or protective layer (PRL) may vary depending on the embodiments.

[0132] In one embodiment, the protective layer (PRL) may be an upper substrate (SUB2), and at least one of a light conversion layer (WCL) and a color filter layer (CFL) may be formed on the upper substrate (SUB2). For example, a lower substrate (SUB1) on which a panel circuit layer (PCL), a light emitting element layer (LEL), an encapsulation layer (ENL), and a light conversion layer (WCL) are formed, and an upper substrate (SUB2) on which a color filter layer (CFL) is formed may be bonded to each other with a filler (FIL) interposed therebetween.

[0133] The substrate (SUB) is a base member for forming the display panel (110), and may be a rigid or flexible substrate (or film). In one embodiment, the substrate (SUB) may be a substrate having rigid properties, including an insulating material such as glass, and may not be bent. Alternatively, the substrate (SUB) may be a flexible substrate including polyimide or another insulating material, and capable of deformation, such as bending, folding, or rolling, and may or may not be bent. The type and / or material of the substrate (SUB) may vary depending on the embodiments.

[0134] A panel circuit layer (PCL) (e.g., a pixel circuit layer or a thin film transistor layer) may be disposed on a substrate (SUB). The panel circuit layer (PCL) may include circuit elements including transistors (T) and capacitors (Cst) of pixels (PX), and wires (e.g., signal lines and power lines). In one embodiment, the panel circuit layer (PCL) may further include circuit elements of the first driving unit (120) (e.g., driving unit transistors and / or driving unit capacitors provided to the first driving unit (120)) and / or additional conductive patterns (e.g., bridge patterns).

[0135] FIGS. 5 to 7 show a first transistor (T1) and a capacitor (Cst) of each pixel (PX) as examples of circuit elements that may be provided in a panel circuit layer (PCL). In addition, FIGS. 5 to 7 show a portion of a second power line (VSL) and a pad electrode (DPD) (for example, a second pad electrode (DPD2)) connected to the power line (VSL) as examples of wiring elements that may be provided in a panel circuit layer (PCL).

[0136] Although FIGS. 5 to 7 disclose embodiments in which the panel circuit layer (PCL) is disposed directly on the substrate (SUB), the embodiments are not limited thereto. For example, the display panel (110) may further include a barrier layer disposed on the substrate (SUB), and the panel circuit layer (PCL) may be disposed on the barrier layer.

[0137] A panel circuit layer (PCL) may include a plurality of conductive layers and at least one semiconductor layer (SCL). The conductive layers may include electrodes constituting circuit elements of the panel circuit layer (PCL) (e.g., transistors (T) and capacitors (Cst) constituting each pixel circuit (PXC)), conductive patterns (e.g., bridge electrodes) connected to the circuit elements, and / or wirings. The semiconductor layer (SCL) may include active layers (ACT) of transistors (T) provided in the panel circuit layer (PCL).

[0138] In one embodiment, the panel circuit layer (PCL) may include a first conductive layer (CDL1) (e.g., a bottom conductive layer), a semiconductor layer (SCL), a second conductive layer (CDL2) (e.g., a gate conductive layer), and a third conductive layer (CDL3) (e.g., a source-drain conductive layer or a data conductive layer) sequentially disposed on the substrate (SUB) along a third direction (D3). In one embodiment, the panel circuit layer (PCL) may further include at least one conductive layer disposed on the third conductive layer (CDL3), and at least one insulating layer covering the at least one conductive layer. The at least one conductive layer may include a bridge electrode connecting a light-emitting element (EL) of each pixel (PX) to a pixel circuit (PXC) (e.g., a first transistor (T1)), and / or at least one wiring.

[0139] Patterns included in each conductive layer of the panel circuit layer (PCL) (e.g., electrodes, conductive patterns, and / or wires of each conductive layer) may include a conductive material. For example, the patterns provided in each of the first conductive layer (CDL1), the second conductive layer (CDL2), and the third conductive layer (CDL3) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, patterns included in the same conductive layer may be simultaneously formed using the same conductive material.

[0140] In one embodiment, each pattern provided on each conductive layer of the panel circuit layer (PCL) may have a single-layer or multi-layer structure. For example, the patterns provided on each of the first conductive layer (CDL1), the second conductive layer (CDL2), and the third conductive layer (CDL3) may have a single-layer or multi-layer structure. In one embodiment, patterns included in the same conductive layer may have the same cross-sectional structure.

[0141] The panel circuit layer (PCL) may further include a plurality of insulating layers and / or insulating patterns arranged on the substrate (SUB). For example, the panel circuit layer (PCL) may include a first insulating layer (INS1), a gate insulating layer (GI), a second insulating layer (INS2), and a third insulating layer (INS3) sequentially arranged on the substrate (SUB) along a third direction (D3).

[0142] In one embodiment, at least one insulating layer provided on the panel circuit layer (PCL) may be disposed over the entire display area (DA). For example, the first insulating layer (INS1), the second insulating layer (INS2), and the third insulating layer (INS3) may be disposed over the entire display area (DA).

[0143] The first insulating layer (INS1) may be disposed on the first conductive layer (CDL1). For example, the first insulating layer (INS1) may be disposed on the substrate (SUB) to cover the patterns of the first conductive layer (CDL1). The first insulating layer (INS1) may include at least one inorganic insulating layer including an inorganic insulating material (for example, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material).

[0144] The gate insulating layer (GI) may be disposed on the first insulating layer (INS1) and the semiconductor layer (SCL). The gate insulating layer (GI) may cover a portion of each of the first insulating layer (INS1) and the semiconductor layer (SCL). The gate insulating layer (GI) may include at least one inorganic insulating layer including an inorganic insulating material.

[0145] In one embodiment, the gate insulating layer (GI) may be partially disposed only on each pixel area and a portion of the display area (DA) including the pixel area. However, the embodiments are not limited thereto. For example, the gate insulating layer (GI) may be disposed over the entire display area (DA) to entirely cover the first insulating layer (INS1) and the semiconductor layer (SCL).

[0146] In one embodiment, the gate insulating layer (GI) may include a first gate insulating layer (GI1) (also referred to as a “first gate insulating pattern”) disposed on a portion of each active layer (ACT) provided on the semiconductor layer (SCL), a second gate insulating layer (GI2) (also referred to as a “second gate insulating pattern”) disposed on the first insulating layer (INS1) and not overlapping with the active layer (ACT), and a third gate insulating layer (GI3) (also referred to as a “third gate insulating pattern”). For example, the first gate insulating layer (GI1) may be disposed between a portion of the active layer (ACT) including the channel region (CH) and the gate electrode (GE), and the second gate insulating layer (GI2) may be disposed between the first insulating layer (INS1) and the first capacitor electrode (CE1). The first gate insulating layer (GI1) and the second gate insulating layer (GI2) may be an integral insulating pattern that is connected to each other when viewed in a plan view, or may be individual insulating patterns that are separated from each other. The third gate insulating layer (GI3) may be arranged between the first insulating layer (INS1) and the second wiring layer (VSL2) of the second power line (VSL).

[0147] The second insulating layer (INS2) may be disposed on the first insulating layer (INS1), the semiconductor layer (SCL), the gate insulating layer (GI), and the second conductive layer (CDL2). For example, the second insulating layer (INS2) may be disposed on the first insulating layer (INS1) to cover the patterns of the semiconductor layer (SCL), the gate insulating layer (GI), and the second conductive layer (CDL2). The second insulating layer (INS2) may include at least one inorganic insulating layer including an inorganic insulating material.

[0148] The third insulating layer (INS3) may be disposed on the third conductive layer (CDL3). For example, the third insulating layer (INS3) may be disposed on the second insulating layer (INS2) to cover the patterns of the third conductive layer (CDL3).

[0149] The third insulating layer (INS3) may include at least one organic insulating layer including an organic insulating material (e.g., an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or another organic insulating material). A surface of the third insulating layer (INS3) (e.g., an upper surface of the second layer (INS3b)) may be substantially flat. The third insulating layer (INS3) may include an inorganic insulating layer or may not include an inorganic insulating layer.

[0150] In one embodiment, the third insulating layer (INS3) may be formed as a multilayer including a first layer (INS3a) and a second layer (INS3b) sequentially disposed on the second insulating layer (INS2) and the third conductive layer (CDL3). The first layer (INS3a) of the third insulating layer (INS3) may be an inorganic insulating layer including an inorganic insulating material. The second layer (INS3b) of the third insulating layer (INS3) may be an organic insulating layer including an organic insulating material.

[0151] A first transistor (T1) may include an active layer (ACT) and a gate electrode (GE) (e.g., a top-gate electrode) disposed on a portion of the active layer (ACT). In one embodiment, the first transistor (T1) may further include at least one of a source electrode (SE) and a drain electrode (DE). For example, the first transistor (T1) may further include a source electrode (SE) connected to a source region (SR) of the active layer (ACT) and a drain electrode (DE) connected to a drain region (DR) of the active layer (ACT). Alternatively, the first transistor (T1) may not include separate source electrodes and / or drain electrodes, and the source region (SR) and / or drain region (DR) of the active layer (ACT) may be connected to other circuit elements, wiring, and / or conductive patterns to function as the source electrode and / or the drain electrode of the first transistor (T1).

[0152] In one embodiment, the first transistor (T1) may further include a bottom electrode (BE) (or a light-shielding layer) disposed under the active layer (ACT). In one embodiment, the bottom electrode (BE) may be connected to one electrode (for example, the source electrode (SE) or the gate electrode (GE)) of the first transistor (T1) and may be utilized as a back-gate electrode (BG) that adjusts the characteristics of the first transistor (T1). For example, the bottom electrode (BE) may be connected to the source electrode (SE) of the first transistor (T1) through at least one connecting hole penetrating the first insulating layer (INS1) and the second insulating layer (INS2). By disposing the bottom electrode (BE) under the active layer (ACT), external light may be blocked from entering the channel region (CH) of the active layer (ACT), thereby stabilizing the operating characteristics of the first transistor (T1).

[0153] In one embodiment, the first transistor (T1) may be an oxide transistor. For example, the first transistor (T1) may be an N-type oxide transistor.

[0154] A bottom electrode (BE) may be provided on a first conductive layer (CDL1) disposed on a substrate (SUB). The first conductive layer (CDL1) may be covered with a first insulating layer (INS1).

[0155] The bottom electrode (BE) may overlap with the active layer (ACT) and the gate electrode (GE). For example, the bottom electrode (BE) may be positioned below the active layer (ACT) so as to overlap at least a portion of the active layer (ACT) including the channel region (CH), and may face the gate electrode (GE) with the active layer (ACT) interposed therebetween.

[0156] The active layer (ACT) may be provided on a semiconductor layer (SCL). The semiconductor layer (SCL) may be disposed on a first insulating layer (INS1) and may be covered by a gate insulating layer (GI) and a second insulating layer (INS2).

[0157] The active layer (ACT) may include a channel region (CH) and a source region (SR) and a drain region (DR) spaced apart from each other with the channel region (CH) therebetween. For example, the source region (SR) and the drain region (DR) may be located on both sides of the channel region (CH). The source region (SR) and the drain region (DR) may be conductive regions that have a higher carrier concentration (e.g., electron concentration) than the channel region (CH).

[0158] The active layer (ACT) may overlap with the bottom electrode (BE) and the gate electrode (GE). For example, a portion of the active layer (ACT) including the channel region (CH) may overlap with the bottom electrode (BE) and the gate electrode (GE) in the third direction (D3).

[0159] In one embodiment, the active layer (ACT) can include an oxide semiconductor. For example, the active layer (ACT) can include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or another oxide semiconductor. For example, the active layer (ACT) can include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or another oxide semiconductor.

[0160] A first gate insulating layer (GI1) may be disposed on the active layer (ACT). For example, the first gate insulating layer (GI1) may be disposed between the active layer (ACT) and the gate electrode (GE).

[0161] In one embodiment, the first gate insulating layer (GI1) may cover a portion of the active layer (ACT) including a portion overlapping the gate electrode (GE) and expose another portion of the active layer (ACT). For example, the first gate insulating layer (GI1) may be disposed on a portion of the active layer (ACT) including the channel region (CH) and expose a source region (SR) and a drain region (DR) of the active layer (ACT).

[0162] As the first gate insulating layer (GI1) exposes the source region (SR) and the drain region (DR), the source region (SR) and the drain region (DR) can be appropriately and / or easily made conductive during the manufacturing process of the display panel (110). For example, in the step of etching the gate insulating layer (GI) so that at least a portion of each of the source region (SR) and the drain region (DR) is exposed, oxygen vacancies may occur in the source region (SR) and the drain region (DR). Accordingly, the source region (SR) and the drain region (DR) can be appropriately made conductive in a subsequent process (for example, a process of forming the second insulating layer (INS2)) without performing a separate doping process.

[0163] A gate electrode (GE) may be disposed on a first gate insulating layer (GI1). The gate electrode (GE) may be provided on a second conductive layer (CDL2). The second conductive layer (CDL2) may be disposed on the first insulating layer (INS1) and the gate insulating layer (GI), and may be covered by the second insulating layer (INS2).

[0164] The gate electrode (GE) may be disposed on the active layer (ACT). For example, the gate electrode (GE) may be disposed on the first gate insulating layer (GI1) covering the channel region (CH) of the active layer (ACT). The gate electrode (GE) and the active layer (ACT) may be separated from each other with the first gate insulating layer (GI1) interposed therebetween.

[0165] A second insulating layer (INS2) may be disposed on the gate electrode (GE). The second insulating layer (INS2) may cover the first insulating layer (INS1), the active layer (ACT), the gate insulating layer (GI), and the second conductive layer (CDL2).

[0166] A source electrode (SE) and a drain electrode (DE) may be disposed on the second insulating layer (INS2). The source electrode (SE) and the drain electrode (DE) may be provided on the third conductive layer (CDL3). The third conductive layer (CDL3) may be disposed between the second insulating layer (INS2) and the third insulating layer (INS3).

[0167] The source electrode (SE) may be connected to a portion of the active layer (ACT). For example, the source electrode (SE) may be electrically connected to the source region (SR) of the active layer (ACT) through at least one connection hole penetrating the second insulating layer (INS2). In one embodiment, the source electrode (SE) may also be electrically connected to the bottom electrode (BE).

[0168] The drain electrode (DE) may be connected to another portion of the active layer (ACT). For example, the drain electrode (DE) may be connected to the drain region (DR) of the active layer (ACT) through at least one connecting hole penetrating the second insulating layer (INS2).

[0169] The first transistor (T1) of each pixel (PX) may be electrically connected to the light-emitting element (EL) of each pixel (PX). For example, the first transistor (T1) disposed in each pixel area may be electrically connected to the pixel electrode (AE) of the light-emitting element (EL) disposed in each pixel area in the light-emitting element layer (LEL).

[0170] The capacitor (Cst) may include capacitor electrodes that form electrostatic capacitance. For example, the capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2).

[0171] In one embodiment, the first capacitor (C1) may include multilayer electrodes. For example, at least one of the first capacitor electrode (CE1) and the second capacitor electrode (CE2) may have a multilayer structure including a plurality of sub-electrodes.

[0172] In one embodiment, the first capacitor electrode (CE1) may be a single-layer electrode provided on the second conductive layer (CDL2). However, embodiments are not limited thereto. For example, the first capacitor electrode (CE1) may further include at least one sub-electrode provided on another conductive layer.

[0173] In one embodiment, the first capacitor electrode (CE1) may be connected to the gate electrode (GE) of the first transistor (T1) located in each pixel area. For example, the first capacitor electrode (CE1) may be provided integrally with the gate electrode (GE) of the first transistor (T1) on the second conductive layer (CDL2). For example, the first capacitor electrode (CE1) and the gate electrode (GE) of the first transistor (T1) may be formed as an integral electrode that is connected to each other when viewed on a plane defined by the first direction (D1) and the second direction (D2). In this case, the first gate insulating layer (GI1) located under the gate electrode (GE) of the first transistor (T1) and the second gate insulating layer (GI2) located under the first capacitor electrode (CE1) may be connected to each other.

[0174] In one embodiment, the second capacitor electrode (CE2) may include a first sub-electrode (CE2a) provided on the first conductive layer (CDL1) and a second sub-electrode (CE2b) provided on the third conductive layer (CDL3). The first sub-electrode (CE2a) and the second sub-electrode (CE2b) of the second capacitor electrode (CE2) may overlap the first capacitor electrode (CE1). The first sub-electrode (CE2a) and the second sub-electrode (CE2b) of the second capacitor electrode (CE2) may be electrically connected to each other through at least one connecting hole penetrating the first insulating layer (INS1) and the second insulating layer (INS2). By forming the second capacitor electrode (CE2) in a multi-layer structure, a pixel area of ​​a limited size can be efficiently utilized to appropriately secure the capacitance of the capacitor (Cst).

[0175] In another embodiment, the second capacitor electrode (CE2) may be formed as a single electrode provided on the first conductive layer (CDL1) or the third conductive layer (CDL3). Alternatively, the second capacitor electrode (CE2) may be formed as a triple-layer or more electrode including at least one sub-electrode provided on another conductive layer (for example, a fourth conductive layer additionally formed between the third insulating layer (INS3) and the light emitting element layer (LEL)).

[0176] In one embodiment, the second capacitor electrode (CE2) may be connected to the source electrode (SE) of the first transistor (T1) located in each pixel area. For example, the first sub-electrode (CE2a) of the second capacitor electrode (CE2) may be provided on the first conductive layer (CDL1) integrally with the bottom electrode (BE) of the first transistor (T1) and may be connected to the source electrode (SE) of the first transistor (T1) through at least one connection hole. The second sub-electrode (CE2b) of the second capacitor electrode (CE2) may be formed integrally with the source electrode (SE) of the first transistor (T1) located in each pixel area, or may be formed separately from the source electrode (SE).

[0177] The second power line (VSL) may be a single-layer or multi-layer wiring provided on at least one conductive layer. For example, the second power line (VSL) may include a first wiring layer (VSL1) (also referred to as a "first sub-wiring") provided on a third conductive layer (CDL3).

[0178] In one embodiment, the second power line (VSL) may be a multilayer wiring provided on a plurality of conductive layers. For example, the second power line (VSL) may further include at least one of a second wiring layer (VSL2) (also referred to as a “second sub-wiring”) provided on the second conductive layer (CDL2) and a third wiring layer (VSL3) (also referred to as a “third sub-wiring”) provided on the first conductive layer (CDL1). The second wiring layer (VSL2) may overlap the first wiring layer (VSL1) and be electrically connected to the first wiring layer (VSL1) through at least one connection hole penetrating the second insulating layer (VSL2). A third gate insulating layer (GI3) may be disposed below the second wiring layer (VSL2) (for example, between the first insulating layer (INS1) and the second wiring layer (VSL2). The third wiring layer (VSL3) may overlap the first wiring layer (VSL1) and be electrically connected to the first wiring layer (VSL1) through at least one connecting hole penetrating the first insulation layer (INS1) and the second insulation layer (INS2). Alternatively, the third wiring layer (VSL3) may not be directly connected to the first wiring layer (VSL1) but may be electrically connected to the first wiring layer (VSL1) through the second wiring layer (VSL2).

[0179] A light emitting element layer (LEL) may be disposed on the panel circuit layer (PCL). For example, the light emitting element layer (LEL) may be disposed on the third insulating layer (INS3) and may be located at least in the display area (DA).

[0180] The light emitting element layer (LEL) may include light emitting elements (EL) of each pixel (PX). For example, the light emitting element layer (LEL) may include light emitting elements (EL) arranged in light emitting areas (EA) of the pixels (PX) and a pixel defining layer (PDL) arranged around the light emitting elements (EL). When viewed on a plane defined by the first direction (D1) and the second direction (D2), the pixel defining layer (PDL) may surround the light emitting elements (EL) of each pixel (PX).

[0181] Each light emitting element (EL) may include a pixel electrode (AE) positioned in each light emitting area (EA), and a light emitting layer (OL) and a common electrode (CE) sequentially arranged on the pixel electrode (AE). One of the pixel electrode (AE) and the common electrode (CE) of the light emitting element (EL) may be an anode electrode, and the other may be a cathode electrode. For example, the pixel electrode (AE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode.

[0182] In one embodiment, the pixel electrodes (AE) may be individually formed for each light-emitting area (EA). For example, a first pixel electrode (AE1) may be disposed in a first light-emitting area (EA1) of a first pixel (PX1). A second pixel electrode (AE2) may be disposed in a second light-emitting area (EA2) of a second pixel (PX2). A third pixel electrode (AE3) may be disposed in a third light-emitting area (EA3) of a third pixel (PX3). The first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3) may be separated from each other.

[0183] Each pixel electrode (AE) can be connected to at least one transistor (T) (for example, a first transistor (T1)) included in the corresponding pixel (PX). For example, the first pixel electrode (AE1) can be electrically connected to the first transistor (T1) of the first pixel (PX1) through a first connection hole (CNT1) (or a first via hole) penetrating the third insulating layer (INS3). The second pixel electrode (AE2) can be electrically connected to the first transistor (T1) of the second pixel (PX2) through a second connection hole (CNT2) (or a second via hole) penetrating the third insulating layer (INS3). The third pixel electrode (AE3) can be electrically connected to the first transistor (T1) of the third pixel (PX3) through a third connection hole (CNT3) (or a third via hole) penetrating the third insulating layer (INS3).

[0184] In one embodiment, the display panel (110) may be a front-emitting display panel, and the pixel electrode (AE) may include a metal layer including a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr. In one embodiment, the pixel electrode (AE) may further include a metal oxide layer overlapping the metal layer. For example, the pixel electrode (AE) may have a double-layer structure of ITO / Ag, Ag / ITO, ITO / Mg, ITO / MgF, or a triple-layer structure such as ITO / Ag / ITO.

[0185] In one embodiment, the display panel (110) may further include pad electrodes (DPD) arranged on the same layer as the pixel electrodes (AE). For example, the pad electrodes (DPD) may be arranged on the panel circuit layer (PCL). In one embodiment, the pixel electrodes (AE) and the pad electrodes (DPD) may be arranged to be spaced apart from each other and may be formed simultaneously. For example, the pixel electrodes (AE) and the pad electrodes (DPD) may be formed simultaneously on the same layer of the light emitting element layer (LEL) using the same conductive material. For example, the pixel electrodes (AE) and the pad electrodes (DPD) may be formed separately from each other by forming a single-layer or multi-layer conductive film on the third insulating layer (INS3) and etching the conductive film by an etching process using a mask.

[0186] Each pad electrode (DPD) may overlap a portion of the second power line (VSL) and may be electrically connected to the second power line (VSL) through a fourth connection hole (CNT4) (or fourth via hole) penetrating the third insulating layer (INS3).

[0187] A pixel defining layer (PDL) may be disposed on the pixel electrodes (AE) and the pad electrodes (DPD). For example, the pixel defining layer (PDL) may be disposed on a portion of the pixel electrodes (AE) and the pad electrodes (DPD). For example, the pixel defining layer (PDL) may cover an edge portion of each pixel electrode (AE) and may include an opening that exposes a remaining portion of the pixel electrode (AE). For example, the pixel defining layer (PDL) may include a first opening (POPN1) that exposes a portion of a first pixel electrode (AE1), a second opening (POPN2) that exposes a portion of a second pixel electrode (AE2), and a third opening (POPN3) that exposes a portion of a third pixel electrode (AE3). Additionally, the pixel defining layer (PDL) may cover an edge portion of each pad electrode (DPD) and may include a fourth opening (POPN4) that exposes the remaining portion of the pad electrode (DPD).

[0188] The pixel defining layer (PDL) is mainly disposed in the non-emission area (NEA) and may have openings (for example, a first opening (POPN1), a second opening (POPN2), and a third opening (POPN3)) corresponding to the emission areas (EA). In one embodiment, the pixel defining layer (PDL) may also be disposed at an edge portion of each emission area (EA). For example, the first opening (POPN1) of the pixel defining layer (PDL) may have a size smaller than that of the first emission area (EA1) and may be located inside the first emission area (EA1). Similarly, the second opening (POPN2) of the pixel defining layer (PDL) may have a size smaller than that of the second emission area (EA2) and may be located inside the second emission area (EA2). The third opening (POPN3) of the pixel defining layer (PDL) has a smaller size than the third light-emitting area (EA3) and may be located inside the third light-emitting area (EA3).

[0189] However, the embodiments are not limited thereto. For example, the pixel defining layer (PDL) may include an opening having a size greater than the size of the light emitting area (EA) at a location corresponding to at least one light emitting area (EA).

[0190] The pixel defining layer (PDL) may have a fourth opening (POPN4) corresponding to each drilling area. In one embodiment, the pixel defining layer (PDL) may be opened wider than a drilling hole (DH) located in each drilling area. For example, the fourth opening (POPN4) of the pixel defining layer (PDL) may overlap the drilling hole (DH), and the drilling hole (DH) may be located inside (for example, at the center) of the fourth opening (POPN4) of the pixel defining layer (PDL).

[0191] However, the embodiments are not limited thereto. For example, the fourth opening (POPN4) of the pixel defining layer (PDL) may be integrated with the drilling hole (DH). For example, instead of first opening the pixel defining layer (PDL) in the drilling area prior to forming the drilling hole (DH), the drilling hole (DH) may be formed so as to penetrate the pixel defining layer (PDL) and the light emitting layer (OL) in the step of forming the drilling hole (DH).

[0192] The pixel defining layer (PDL) can overlap with the bank (BNK) of the light conversion layer (WCL) and the light-shielding pattern (LBP) of the color filter layer (CFL) in the third direction (D3). For example, the pixel defining layer (PDL) can overlap with the bank (BNK) and the light-shielding pattern (LBP) in the non-emission area (NEA).

[0193] In one embodiment, the pixel defining layer (PDL) may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer (PDL) may include an organic insulating material such as, but not limited to, polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides rein, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, or benzocyclobutene (BCB).

[0194] The light-emitting layer (OL) may be disposed on each pixel electrode (AE). In one embodiment, the light-emitting layer (OL) may have a shape of a continuous film formed over a plurality of light-emitting areas (EA) and non-light-emitting areas (NEA). In one embodiment, the light-emitting layer (OL) may be locally removed by a drilling hole (DH) on each pad electrode (DPD). For example, each drilling hole (DH) may be formed by removing the light-emitting layer (OL) on each pad electrode (DPD) using a laser.

[0195] However, the embodiments are not limited thereto. For example, the light-emitting layer (OL) may be individually formed in each light-emitting area (EA). For example, the light-emitting layers (OL) of the light-emitting elements (EL) located in each light-emitting area (EA) may be formed separately from each other.

[0196] In one embodiment, the light-emitting layer (OL) can emit light of a third color, for example, blue light. However, embodiments are not limited thereto. For example, the light-emitting layer (OL) can also emit white light, etc.

[0197] The light-emitting layer (OL) may be positioned only within the display area (DA), but is not limited thereto. For example, a portion of the light-emitting layer (OL) may also be positioned within at least a portion of the non-display area (NDA).

[0198] The light-emitting layer (OL) of the light-emitting element (EL) may include a polymer material or a low-molecular material. Light emitted from the light-emitting layer (OL) may contribute to image display. A detailed description of the light-emitting layer (OL) will be provided below.

[0199] A common electrode (CE) may be disposed on the light-emitting layer (OL). In one embodiment, the common electrode (CE) may be a common electrode shared by a plurality of pixels (PX). For example, the common electrode (CE) may be formed over the entire display area (DA) (or a portion of the display area (DA)) including a plurality of light-emitting areas (EA).

[0200] In embodiments, the common electrode (CE) may overlap each pad electrode (DPD) and may be electrically connected to each pad electrode (DPD) by a drilling hole (DH) formed on each pad electrode (DPD) (for example, a drilling hole (DH) penetrating the light emitting layer (OL), etc.). For example, the common electrode (CE) may contact the pad electrode (DPD) exposed by the drilling hole (DH). The common electrode (CE) may be electrically connected to the second power line (VSL) of the panel circuit layer (PCL) through the pad electrode (DPD). Accordingly, the common voltage (ELVSS) applied to the second power line (VSL) may be applied to the common electrode (CE).

[0201] In one embodiment, the display panel (110) may be a front-emitting display panel, and the common electrode (CE) may be semi-transparent or transmissive. In one embodiment, the common electrode (CE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or compounds or mixtures thereof, for example, a mixture of Ag and Mg, and may be semi-transmissive. In one embodiment, the common electrode (CE) may include W x O x It may include (tungsten oxide), TiO2 (titanium oxide), ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), MgO (magnesium oxide), etc., and may have transparency.

[0202] The pixel electrode (AE), the light-emitting layer (OL), and the common electrode (CE) arranged in each light-emitting area (EA) can form each light-emitting element (EL). For example, the first pixel electrode (AE1), the light-emitting layer (OL), and the common electrode (CE) arranged in the first light-emitting area (EA1) can form the light-emitting element (EL) of the first pixel (PX1) (for example, the first light-emitting element (EL1)). The second pixel electrode (AE2), the light-emitting layer (OL), and the common electrode (CE) arranged in the second light-emitting area (EA2) can form the light-emitting element (EL) of the second pixel (PX2) (for example, the second light-emitting element (EL2)). The third pixel electrode (AE3), the light-emitting layer (OL), and the common electrode (CE) arranged in the third light-emitting area (EA3) can form the light-emitting element (EL) of the third pixel (PX3) (for example, the third light-emitting element (EL3)).

[0203] In one embodiment, the light-emitting elements (EL) of the pixels (PX) can emit light of the same color. For example, the first light-emitting element (EL1), the second light-emitting element (EL2), and the third light-emitting element (EL3) can be blue organic light-emitting diodes that emit blue light.

[0204] In one embodiment, the light emitting element layer (LEL) may further include a capping layer covering the common electrode (CE). For example, the light emitting element layer (LEL) may further include a capping layer disposed on the common electrode (CE) and including at least one of an inorganic material or an organic material having light transparency. The capping layer may improve the viewing angle characteristics of the display panel (110) and improve external light emission efficiency.

[0205] An encapsulation layer (ENL) may be disposed on a light-emitting element layer (LEL). The encapsulation layer (ENL) covers the light-emitting element layer (LEL) in a display area (DA) and may extend to a non-display area (NDA) to be in contact with a panel circuit layer (PCL). The encapsulation layer (ENL) may block the penetration of oxygen or moisture into the light-emitting element layer (LEL) and may mitigate electrical and / or physical impacts on the panel circuit layer (PCL) and the light-emitting element layer (LEL). In one embodiment, the encapsulation layer (ENL) may include a first encapsulation layer (ENL1), a second encapsulation layer (ENL2), and a third encapsulation layer (ENL3) sequentially disposed on the light-emitting element layer (LEL).

[0206] Each of the first encapsulating layer (ENL1) and the third encapsulating layer (ENL3) may be an inorganic encapsulating layer including an inorganic material. For example, each of the first encapsulating layer (ENL1) and the third encapsulating layer (ENL3) may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, lithium fluoride, or the like.

[0207] The second encapsulating layer (ENL2) may be an organic encapsulating layer containing an organic material. For example, the second encapsulating layer (ENL2) may contain an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a perylene resin, and the like.

[0208] The light conversion layer (WCL) may be disposed on the encapsulation layer (ENL). In one embodiment, the light conversion layer (WCL) may be formed on the encapsulation layer (ENL), but is not limited thereto. For example, the light conversion layer (WCL) may be formed on a protective layer (PRL) (e.g., the upper substrate (SUB2)) and then disposed on the encapsulation layer (ENL).

[0209] The light conversion layer (WCL) may include light-transmitting members arranged in the light-emitting areas (EA) and banks (BNK) arranged in the non-light-emitting areas (NEA). The light-transmitting members may include a first light-transmitting member (WCL1) arranged in the first light-emitting area (EA1) (also referred to as a “first light-conversion layer”), a second light-transmitting member (WCL2) arranged in the second light-emitting area (EA2) (also referred to as a “second light-conversion layer”), and a third light-transmitting member (TPL) arranged in the third light-emitting area (EA3) (also referred to as a “light-transmitting layer”).

[0210] In one embodiment, the light conversion layer (WCL) may further include at least one capping layer. For example, the light conversion layer (WCL) may further include a first capping layer (CPL1) covering the lower surface of the light-transmitting members and the bank (BNK), and a second capping layer (CPL2) covering the upper surface of the light-transmitting members and the bank (BNK).

[0211] The first capping layer (CPL1) may be disposed on the encapsulating layer (ENL). The first capping layer (CPL1) may be formed of an inorganic material, such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0212] A first light-transmitting member (WCL1), a second light-transmitting member (WCL2), a third light-transmitting member (TPL), and a bank (BNK) may be arranged on the first capping layer (CPL1).

[0213] The first light-transmitting member (WCL1) can convert a portion of light of a third color (e.g., blue light) incident from the first light-emitting element (EL1) arranged in the first light-emitting area (EA1) into light of a first color (e.g., red light). The light of the first color converted by the first light-transmitting member (WCL1) can be emitted to the upper portion of the display panel (110) by transmitting through the first color filter (CF1) or the like.

[0214] The first light-transmitting member (WCL1) may include a first base resin (BRS1) and a first wavelength shifter (WS1). The first base resin (BRS1) may include a light-transmitting organic material. For example, the first base resin (BRS1) may include an epoxy-based resin, an acrylic resin, a cardo-based resin, or an imide-based resin. The first wavelength shifter (WS1) may convert light of a third color incident from the first light-emitting element (EL1) into light of a first color. The first wavelength shifter (WS1) may be a quantum dot (for example, a red quantum dot), a quantum rod, a fluorescent material, or a phosphorescent material. In one embodiment, the first light-transmitting member (WCL1) may further include a light diffusing agent (SCT), such as titanium dioxide (TiO2).

[0215] The second light-transmitting member (WCL2) can convert a portion of the third color light (e.g., blue light) incident from the second light-emitting element (EL2) arranged in the second light-emitting area (EA2) into a second color light (e.g., green light). The second color light converted by the second light-transmitting member (WCL2) can be emitted to the upper portion of the display panel (110) by transmitting through the second color filter (CF2) or the like.

[0216] The second light-transmitting member (WCL2) may include a second base resin (BRS2) and a second wavelength shifter (WS2). The second base resin (BRS2) may include a light-transmitting organic material. For example, the second base resin (BRS2) may include an epoxy-based resin, an acrylic resin, a cardo-based resin, or an imide-based resin. The second wavelength shifter (WS2) may convert light of a third color incident from the second light-emitting element (EL2) into light of a second color. The second wavelength shifter (WS2) may be a quantum dot (for example, a green quantum dot), a quantum rod, a fluorescent material, or a phosphorescent material. In one embodiment, the second light-transmitting member (WCL2) may further include a light diffusing agent (SCT), such as titanium dioxide (TiO2).

[0217] The third light-transmitting member (TPL) can diffuse and / or transmit third color light (e.g., blue light) incident from the third light-emitting element (EL3) arranged in the third light-emitting area (EA3). The third color light transmitted through the third light-transmitting member (TPL) can be emitted to the upper portion of the display panel (110) through the third color filter (CF3) or the like.

[0218] The third light-transmitting member (TPL) may include a third base resin (BRS3). The third base resin (BRS3) may include a light-transmitting organic material. For example, the third base resin (BRS3) may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. In one embodiment, the third light-transmitting member (TPL) may further include a light diffusing agent (SCT), such as titanium dioxide (TiO2).

[0219] A bank (BNK) may be arranged in a non-emissive area (NEA) to define or define light-emitting areas (EA) in which light-transmitting elements are provided. For example, the bank (BNK) may include openings corresponding to the light-emitting areas (EA) of the pixels (PX) and may surround the light-emitting areas (EA).

[0220] In one embodiment, the bank (BNK) may be formed with a relatively thick thickness to provide a space in which the light-transmitting elements are formed. For example, the thickness of the bank (BNK) may be, but is not limited to, 1 μm to 10 μm.

[0221] In one embodiment, the bank (BNK) may include an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material). In one embodiment, the bank (BNK) may further include a light-blocking material. For example, the bank (BNK) may include a dye or pigment having light-blocking properties (e.g., an inorganic black pigment such as carbon black or an organic black pigment). Accordingly, the bank (BNK) may have light-blocking properties.

[0222] A second capping layer (CPL2) may be disposed on the first light-transmitting member (WCL1), the second light-transmitting member (WCL2), the third light-transmitting member (TPL), and the bank (BNK). The second capping layer (CPL2) may protect the light-transmitting members of the wavelength conversion layer (WCL) and the bank (BNK) from moisture, foreign substances, etc. In one embodiment, the second capping layer (CPL2) may include an inorganic material. In one embodiment, the second capping layer (CPL2) may include the same material as the first capping layer (CPL1), but is not limited thereto.

[0223] A color filter layer (CFL) may be disposed on the second capping layer (CPL2). In one embodiment, the light conversion layer (WCL) and the color filter layer (CFL) may be formed on different substrate members (for example, the lower substrate (SUB1) and the upper substrate (SUB2)) and then bonded to face each other, and a filler (FIL) may be disposed between the light conversion layer (WCL) and the color filter layer (CFL).

[0224] A filler (FIL) can fill a space between a light conversion layer (WCL) and a color filter layer (CFL). The filler (FIL) can be made of a material having an extinction coefficient of substantially 0. The refractive index and the extinction coefficient are correlated, and as the refractive index decreases, the extinction coefficient can also decrease. In addition, when the refractive index is 1.7 or less, the extinction coefficient can converge to substantially 0. In one embodiment, the filler (500) can be made of a material having a refractive index of 1.7 or less, thereby preventing or minimizing light emitted from the light emitting element (EL) from being absorbed while passing through the filler (FIL). In one embodiment, the filler (FIL) can be made of an organic material having a refractive index of 1.4 to 1.6.

[0225] The color filter layer (CFL) may include color filters (CF) arranged in each of the light-emitting areas (EA). For example, the color filter layer (CFL) may include a first color filter (CF1) arranged in a first light-emitting area (EA1), a second color filter (CF2) arranged in a second light-emitting area (EA2), and a third color filter (CF3) arranged in a third light-emitting area (EA3). The color filter layer (CFL) may further include a light-shielding pattern (LBP) arranged in a non-light-emitting area (NEA).

[0226] The first color filter (CF1) can transmit light of a first color and absorb or block light of a third color. For example, the first color filter (CF1) can transmit light of a first color converted by the first light-transmitting member (WCL1) among light of a third color emitted from the first light-emitting element (EL1), and absorb or block light of a third color not converted by the first light-transmitting member (WCL1). Accordingly, light of a first color can be emitted from the first light-emitting area (EA1). For example, the first color filter (CF1) can be a red color filter, and red light can be emitted from the first light-emitting area (EA1).

[0227] The second color filter (CF2) can transmit light of a second color and absorb or block light of a third color. For example, the second color filter (CF2) can transmit light of a second color converted by the second light-transmitting member (WCL2) among light of a third color emitted from the second light-emitting element (EL2), and absorb or block light of a third color not converted by the second light-transmitting member (WCL2). Accordingly, light of a second color can be emitted from the second light-emitting area (EA2). For example, the second color filter (CF2) can be a green color filter, and green light can be emitted from the second light-emitting area (EA2).

[0228] The third color filter (CF3) can transmit light of a third color. For example, the third color filter (CF3) can transmit light of a third color that is emitted from the third light-emitting element (EL3) and passes through the third light-transmitting member (TPL). Accordingly, light of a third color can be emitted from the third light-emitting area (EA3). For example, the third color filter (CF3) can be a blue color filter, and blue light can be emitted from the third light-emitting area (EA3).

[0229] Each of the first, second, and third color filters (CF1, CF2, CF3) can block external light incident from the outside. For example, the first color filter (CF1) can block the second color light, which is light in the green wavelength band, and the third color light, which is light in the blue wavelength band, incident from the outside, thereby increasing the purity (color purity) of the color corresponding to the first color light, which is light in the red wavelength band.

[0230] The shading pattern (LBP) can overlap with the bank (BNK). The shading pattern (LBP) can be formed as a single-layer or multi-layer shading layer.

[0231] In one embodiment, the light-shielding pattern (LBP) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) arranged to overlap each other in the non-emission area (NEA). For example, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) arranged in each of the light-emitting areas (EA) may extend into the non-emission area (NEA) and overlap each other, thereby forming the light-shielding pattern (LBP).

[0232] In another embodiment, the light-shielding pattern (LBP) may include a black matrix pattern disposed in the non-emission area (NEA). For example, the color filter layer (CFL) may include individual color filters (CF) that are individually patterned in each of the emission areas (EA) and a black matrix pattern disposed in the non-emission area (NEA). At least a portion of the black matrix pattern may be disposed between adjacent color filters (CF).

[0233] In one embodiment, the color filter layer (CFL) may further include a low-refractive-index layer (LRL) covering one surface of the color filters (CF). For example, the low-refractive-index layer (LRL) may cover one surface of the color filters (CF) facing the light-emitting element layer (LEL), etc.

[0234] In one embodiment, the low refractive index layer (LRL) may have a lower refractive index than the light-transmitting elements of the light conversion layer (WCL) (e.g., the first light-transmitting element (WCL1), the second light-transmitting element (WCL2), and the third light-transmitting element (TPL)). Accordingly, total reflection of light traveling from the light-transmitting elements of the light conversion layer (WCL) to the low refractive index layer (LRL) may be induced, thereby recycling the light and increasing the light efficiency of the pixels (PX).

[0235] In one embodiment, the refractive index of the low refractive layer (LRL) may be 1.3 or less. When the refractive index of the low refractive layer (LRL) is 1.3 or less, the difference in refractive index between the light-transmitting elements of the light conversion layer (WCL) is large, so that total reflection of light can sufficiently occur. In addition, the low refractive layer (LRL) can compensate for the step caused by the light-shielding pattern (LBP) of the color filter layer (CFL) to flatten the surface of the color filter layer (CFL).

[0236] A protective layer (PRL) may be disposed on a substrate (SUB) to cover elements disposed on the substrate (SUB) (e.g., a panel circuit layer (PCL), a light emitting element layer (LEL), an encapsulation layer (ENL), a light conversion layer (WCL), and / or a color filter layer (CFL)). In one embodiment, the protective layer (PRL) may be an upper substrate (SUB2) on which a color filter layer (CFL) is formed.

[0237] The protective layer (PRL) may be a rigid or flexible substrate or film. In one embodiment, the protective layer (PRL) may include an insulating material such as glass and may have rigid properties and may not be bendable. Alternatively, the protective layer (PRL) may include polyimide or another insulating material and may have flexible properties that allow for deformation such as bending, folding, and rolling, and may or may not be bendable.

[0238] Fig. 8 is an enlarged view of area A1 of Fig. 5. For example, Fig. 8 shows in detail a light-emitting layer (OL) according to one embodiment. Although Fig. 8 illustrates the light-emitting layer (OL) of the first light-emitting element (EL1) of Fig. 5, the description below can be equally applied to the second light-emitting element (EL2) of Fig. 6 and / or the third light-emitting element (EL3) of Fig. 7.

[0239] Referring to FIGS. 5 to 8, the light-emitting layer (OL) may be formed in a structure in which a plurality of light-emitting material layers are overlapped, for example, in a tandem structure. In one embodiment, the light-emitting layer (OL) may include a first stack (ST1) including a first light-emitting material layer (EML1), a second stack (ST2) positioned on the first stack (ST1) and including a second light-emitting material layer (EML2), a third stack (ST3) positioned on the second stack (ST2) and including a third light-emitting material layer (EML3), a first charge generation layer (CGL1) positioned between the first stack (ST1) and the second stack (ST2), and a second charge generation layer positioned between the second stack (ST2) and the third stack (ST3). The first stack (ST1), the second stack (ST2), and the third stack (ST3) may overlap each other.

[0240] The first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may overlap each other. In one embodiment, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may all emit light of a third color, for example, blue light. For example, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may each be a blue light-emitting layer and may include an organic material.

[0241] In one embodiment, at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) can emit first blue light having a first peak wavelength, and at least another one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) can emit second blue light having a second peak wavelength different from the first peak wavelength. In one embodiment, one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) can emit first blue light having a first peak wavelength, and the remaining two of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) can emit second blue light having a second peak wavelength. For example, the light (LE) finally emitted from the light-emitting layer (OL) may be a mixed light in which a first component (LE1) and a second component (LE2) are mixed, and the first component (LE1) may be a first blue light having a first peak wavelength, and the second component (LE2) may be a second blue light having a second peak wavelength.

[0242] In one embodiment, one of the first peak wavelength and the second peak wavelength may be in a range of 440 nm to 460 nm, and the other of the first peak wavelength and the second peak wavelength may be in a range of 460 nm to 480 nm. However, the range of the first peak wavelength and the range of the second peak wavelength are not limited thereto. For example, the range of the first peak wavelength and the range of the second peak wavelength may both include 460 nm. In one embodiment, one of the first blue light and the second blue light may be a deep blue color light, and the other of the first blue light and the second blue light may be a sky blue color light.

[0243] In one embodiment, the light emitting layer (OL) emits blue light (LE) and may include a long wavelength component and a short wavelength component. Accordingly, the light emitting layer (OL) can emit blue light having a more widely distributed emission peak as the light emitting layer (LE). This has the advantage of improving color visibility at a side viewing angle compared to a display panel (110) using another light emitting element that emits blue light having a sharper emission peak.

[0244] In one embodiment, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may each include a host and a dopant. The hosts are Alq3 (tris(8-hydroxyquinolino)aluminum), CBP (4,4'-bis(N-carbazolyl)-1,1'-biphenyl), PVK (poly(n-vinylcabazole)), ADN (9,10-di(naphthalene-2-yl)anthracene), TCTA(4,4',4''-Tris(carbazol-9-yl)-triphenylamine), TPBi(1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN(3-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP (4,4'-bis(9-carbazolyl)-2,2''-dimethyl-biphenyl), MADN (2-Methyl-9,10-bis(naphthalen-2-yl)anthracene) You can use the back, but it is not limited to this.

[0245] In one embodiment, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may each include a fluorescent material selected from the group consisting of spiro-DPVBi, spiro-6P, distyryl-benzene (DSB), distyryl-arylene (DSA), polyfluorene (PFO) polymers, and poly(p-phenylene vinylene) polymers. In another embodiment, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may each include a phosphorescent material including an organometallic complex such as (4,6-F2ppy)2Irpic. The first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may each include a material other than the exemplified materials.

[0246] As described above, at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) emits blue light in a different wavelength range from at least another one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3). In one embodiment, in order to emit blue light in a different wavelength range, the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may include the same material, and a method of controlling a resonance distance may be used. Alternatively, in order to emit blue light of different wavelength ranges, at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) and at least another one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may include different materials.

[0247] However, the embodiments are not limited thereto. For example, the blue light emitted by each of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may all have a peak wavelength of 440 nm to 480 nm, and may be made of the same material.

[0248] In another embodiment, at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may emit first blue light having a first peak wavelength, another one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may emit second blue light having a second peak wavelength different from the first peak wavelength, and the remaining one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may emit third blue light having a third peak wavelength different from the first peak wavelength and the second peak wavelength.

[0249] In one embodiment, the range of any one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be greater than or equal to 440 nm and less than or equal to 460 nm. The range of another one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be greater than or equal to 460 nm and less than or equal to 470 nm, and the range of the remaining one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be greater than or equal to 470 nm and less than or equal to 480 nm.

[0250] In one embodiment, the light emitting layer (OL) emits blue light (LE) and may include a long wavelength component, a medium wavelength component, and a short wavelength component. Accordingly, the light emitting layer (OL) can emit blue light having a more widely distributed emission peak as the light emitting layer (LE), thereby improving color visibility at a side viewing angle of the display panel (110).

[0251] The light emitting element (EL) of the tandem structure described above has the advantage of increased light efficiency and improved lifespan of the display device (100) compared to a light emitting element of a non-tandem structure.

[0252] In one embodiment, at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may emit light of a third color, for example, blue light, and at least another one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may emit light of a second color, for example, green light. A peak wavelength of the blue light emitted by at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may range from 440 nm to 480 nm or from 460 nm to 480 nm. The peak wavelength of green light emitted by at least one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may range from 510 nm to 550 nm.

[0253] For example, one of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may be a green light-emitting layer that emits green light, and the other two of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may be blue light-emitting layers that emit blue light. When the other two of the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) are blue light-emitting layers, the peak wavelength ranges of the blue light emitted by the two blue light-emitting layers may be the same as or different from each other.

[0254] In another embodiment, the light LE emitted from the light-emitting layer (OL) may be a mixed light in which a first component (LE1) of blue light and a second component (LE2) of green light are mixed. For example, when the first component (LE1) is a deep blue light and the second component (LE2) is a green light, the light LE may be a sky blue color light. Similar to the embodiments described above, the light LE emitted from the light-emitting layer (OL) is a mixed light of blue light and green light, and includes a long wavelength component and a short wavelength component. Accordingly, the light emitting layer (OL) may emit blue light having a more widely distributed emission peak as the light LE, thereby improving color visibility at a side viewing angle. In addition, when the second component (LE2) of the emitted light (LE) is green light, the green light component of the light provided externally from the display device (100) can be supplemented, and thus the color reproducibility of the display device (100) can be improved.

[0255] In one embodiment, the green light-emitting layer among the first light-emitting material layer (EML1), the second light-emitting material layer (EML2), and the third light-emitting material layer (EML3) may include a host and a dopant. The hosts of the green emission layer are Alq3 (tris(8-hydroxyquinolino)aluminum), CBP (4,4'-bis(N-carbazolyl)-1,1'-biphenyl), PVK (poly(n-vinylcabazole)), ADN (9,10-di(naphthalene-2-yl)anthracene), TCTA(4,4',4''-Tris(carbazol-9-yl)-triphenylamine), TPBi(1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN(3-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP (4,4'-bis(9-carbazolyl)-2,2''-dimethyl-biphenyl), MADN(2-Methyl-9,10-bis(naphthalen-2-yl)anthracene) may be, but is not limited to. The dopant of the green light-emitting layer is a fluorescent material or phosphorescent material containing Alq3(tris-(8-hydroyquinolato) aluminum(III)), such as Ir(ppy)3(fac tris(2-phenylpyridine)iridium), Ir(ppy)2(acac)(Bis(2-phenylpyridine)(acetylacetonate)iridium(III)), Ir(mpyp)3(2-phenyl-4-methyl-pyridine iridium), etc., but is not limited to these.

[0256] The first charge generation layer (CGL1) may be positioned between the first stack (ST1) and the second stack (ST2). The first charge generation layer (CGL1) may inject charges into each light-emitting layer (OL). The first charge generation layer (CGL1) may control a charge balance between the first stack (ST1) and the second stack (ST2). The first charge generation layer (CGL1) may include an n-type charge generation layer (CGL11) and a p-type charge generation layer (CGL12). The p-type charge generation layer (CGL12) may be disposed on the n-type charge generation layer (CGL11) and may be positioned between the n-type charge generation layer (CGL11) and the second stack (ST2).

[0257] The first charge generation layer (CGL1) may have a structure in which an n-type charge generation layer (CGL11) and a p-type charge generation layer (CGL12) are in contact with each other. The n-type charge generation layer (CGL11) may be closer to the pixel electrode (AE) of the light-emitting element (EL) than the p-type charge generation layer (CGL12). The p-type charge generation layer (CGL12) may be closer to the common electrode (CE) of the light-emitting element (EL) than the n-type charge generation layer (CGL11). The n-type charge generation layer (CGL11) may supply electrons to the first light-emitting material layer (EML1) adjacent to the pixel electrode (AE), and the p-type charge generation layer (CGL12) may supply holes to the second light-emitting material layer (EML2) included in the second stack (ST2). By placing a first charge generation layer (CGL1) between a first stack (ST1) and a second stack (ST2) to provide charges to the light-emitting material layer of each stack, the light-emitting efficiency of the light-emitting element (EL) can be increased and the driving voltage can be lowered.

[0258] The first stack (ST1) may be positioned on pixel electrodes (AE) of light-emitting elements (EL) arranged in light-emitting areas (EA). The first stack (ST1) may further include a first hole transport layer (HTL1), a first electron blocking layer (BIL1), and a first electron transport layer (ETL1).

[0259] The first hole transport layer (HTL1) may be positioned on the pixel electrodes (AE) of the light-emitting elements (EL). The first hole transport layer (HTL1) facilitates the transport of holes and may include a hole transport material. The hole transport material may include, but is not limited to, carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), NPB (N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine), TAPC (4,4′-Cyclohexylidene bis[N,N-bis(4-methylphenyl)benzenamine]), etc.

[0260] The first electron blocking layer (BIL1) may be positioned on the first hole transport layer (HTL1). For example, the first electron blocking layer (BIL1) may be positioned between the first hole transport layer (HTL1) and the first light-emitting material layer (EML1). The first electron blocking layer (BIL1) may include a hole transport material and a metal or a metal compound to prevent electrons generated in the first light-emitting material layer (EML1) from flowing to the first hole transport layer (HTL1). In one embodiment, the first hole transport layer (HTL1) and the first electron blocking layer (BIL1) may also be formed as a single layer in which respective materials are mixed.

[0261] The first electron transport layer (ETL1) may be positioned on the first light-emitting material layer (EML1). For example, the first electron transport layer (ETL1) may be positioned between the first charge generation layer (CGL1) and the first light-emitting material layer (EML1). In one embodiment, the first electron transport layer (ETL1) is Alq3 (Tris(8-hydroxyquinolinato)aluminum), TPBi (1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)phenyl), BCP (2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen(4,7-Diphenyl-1,10-phenanthroline), TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), Electron transport materials may include, but are not limited to, BAlq (Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), Bebq2 (berylliumbis(benzoquinolin-10-olate), ADN (9,10-di(naphthalene-2-yl)anthracene) and mixtures thereof.

[0262] The second stack (ST2) may be positioned on the first charge generation layer (CGL1). The second stack (ST2) may further include a second hole transport layer (HTL2), a second electron blocking layer (BIL2), and a second electron transport layer (ETL2).

[0263] The second hole transport layer (HTL2) may be positioned on the first charge generation layer (CGL1). The second hole transport layer (HTL2) may be formed of the same material as the first hole transport layer (HTL1), or may include one or more materials selected from the materials exemplified as materials included in the first hole transport layer (HTL1). The second hole transport layer (HTL2) may be formed of a single layer or multiple layers.

[0264] The second electron blocking layer (BIL2) may be positioned on the second hole transport layer (HTL2). For example, the second electron blocking layer (BIL2) may be positioned between the second hole transport layer (HTL2) and the first light-emitting material layer (EML1). The second electron blocking layer (BIL2) may be formed of the same material and structure as the first electron blocking layer (BIL1), or may include one or more materials selected from the materials exemplified as the materials included in the first electron blocking layer (BIL1).

[0265] The second electron transport layer (ETL2) may be positioned on the second light-emitting material layer (EML2). For example, the second electron transport layer (ETL2) may be positioned between the second charge generation layer (CGL2) and the second light-emitting material layer (EML2). The second electron transport layer (ETL2) may be formed of the same material and the same structure as the first electron transport layer (ETL1), or may include one or more materials selected from the materials exemplified as the materials included in the first electron transport layer (ETL1). The second electron transport layer (ETL2) may be formed of a single layer or multiple layers.

[0266] The second charge generation layer (CGL2) may be positioned on the second stack (ST2). For example, the second charge generation layer (CGL2) may be positioned between the second stack (ST2) and the third stack (ST3). The second charge generation layer (CGL2) may have the same structure as the first charge generation layer (CGL1). For example, the second charge generation layer (CGL2) may include an n-type charge generation layer (CGL21) and a p-type charge generation layer (CGL22). The p-type charge generation layer (CGL22) may be positioned on the n-type charge generation layer (CGL21).

[0267] The second charge generation layer (CGL2) may be formed in a structure in which an n-type charge generation layer (CGL21) and a p-type charge generation layer (CGL22) are in contact with each other. The first charge generation layer (CGL1) and the second charge generation layer (CGL2) may be formed of the same material or may be formed of different materials.

[0268] The third stack (ST3) may be positioned on the second charge generation layer (CGL2). The third stack (ST3) may further include a third hole transport layer (HTL3) and a third electron transport layer (ETL3).

[0269] The third hole transport layer (HTL3) may be positioned on the second charge generation layer (CGL2). The third hole transport layer (HTL3) may be formed of the same material as the first hole transport layer (HTL1), or may include one or more materials selected from the materials exemplified as materials included in the first hole transport layer (HTL1). The third hole transport layer (HTL3) may be formed of a single layer or multiple layers. When the third hole transport layer (HTL3) is formed of multiple layers, each layer may include different materials.

[0270] The third electron transport layer (ETL3) may be positioned on the third light-emitting material layer (EML3). For example, the third electron transport layer (ETL3) may be positioned between the common electrode (CE) of the light-emitting element (EL) and the third light-emitting material layer (EML3). The third electron transport layer (ETL3) may be formed of the same material and the same structure as the first electron transport layer (ETL1), or may include one or more materials selected from the materials exemplified as materials included in the first electron transport layer (ETL1). The third electron transport layer (ETL3) may be formed of a single layer or multiple layers. When the third electron transport layer (ETL3) is formed of multiple layers, each layer may include different materials.

[0271] Although not shown in FIG. 8, a hole injection layer may be further positioned between the pixel electrode (AE) of each of the light emitting elements (EL) and the first stack (ST1), between the first charge generation layer (CGL1) and the second stack (ST2), and between the second charge generation layer (CGL2) and the third stack (ST3). The hole injection layer may serve to more smoothly inject holes into the first light emitting material layer (EML1), the second light emitting material layer (EML2), and the third light emitting material layer (EML3). In one embodiment, the hole injection layer may be formed of, but is not limited to, one or more selected from the group consisting of cupper phthalocyanine (CuPc), poly(3,4)-ethylenedioxythiophene (PEDOT), polyaniline (PANI), and N,N-dinaphthyl-N,N'-diphenyl benzidine (NPD).

[0272] In addition, an electron injection layer may be further positioned between the first stack (ST1) and the first charge generation layer (CGL1), between the second stack (ST2) and the second charge generation layer (CGL2), and between the third electron transport layer (ETL3) and the common electrode (CE) of the light emitting elements (EL). The electron injection layer serves to facilitate electron injection, and may be formed of, but is not limited to, Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, or SAlq. In addition, the electron injection layer may be a metal halide compound, and may be formed of, but is not limited to, any one or more selected from the group consisting of, for example, MgF2, LiF, NaF, KF, RbF, CsF, FrF, LiI, NaI, KI, RbI, CsI, FrI, and CaF2. Additionally, the electron injection layer may include a lanthanide material such as Yb, Sm, or Eu. Alternatively, the electron injection layer may include both a metal halide material and a lanthanide material, such as RbI:Yb or KI:Yb. When the electron injection layer includes both a metal halide material and a lanthanide material, the electron injection layer may be formed by co-deposition of the metal halide material and the lanthanide material.

[0273] In one embodiment, the light-emitting layer (OL) may not include a red light-emitting material layer, and thus may not emit light of the third color, such as red light. For example, the emitted light (LE) may not include a light component having a peak wavelength in the range of about 610 nm to about 650 nm, and the emitted light (LE) may only include a light component having a peak wavelength in the range of about 440 nm to 550 nm.

[0274] Fig. 9 is a plan view showing a display area (DA) according to one embodiment. Fig. 10 is a plan view showing a display area (DA) according to one embodiment. For example, Figs. 9 and 10 show a portion of a display area (DA) in which four adjacent pixel columns (COL) are arranged, and show different embodiments with respect to the arrangement cycle of the pixel columns (GR1) of the first group and the pixel columns (GR2) of the second group.

[0275] In addition to FIG. 4, referring to FIGS. 9 and 10, the display area DA may include a first group of pixel columns GR1 and a second group of pixel columns GR2, which include unit pixels UPX of different shapes. For example, the first group of pixel columns GR1 may include a first column COL1, and each of the first group of pixel columns GR1 may have the same shape as the first column COL1. The second group of pixel columns GR2 may include a second column COL2, and each of the second group of pixel columns GR2 may have the same shape as the second column COL2.

[0276] In each unit pixel area located in the pixel columns (GR1) of the first group, a first light-emitting area (EA1), a second light-emitting area (EA2), and a third light-emitting area (EA3) may be arranged in the same structure as the first unit pixel (UPX1). In addition, in each unit pixel area located in the pixel columns (GR1) of the first group, a first pixel electrode (AE1), a second pixel electrode (AE2), and a third pixel electrode (AE3) may be arranged in the same structure as the first unit pixel (UPX1).

[0277] Each of the pixel columns (GR1) of the first group may include at least one pad electrode (DPD). For example, each of the pixel columns (GR1) of the first group may include a plurality of pad electrodes (DPD) arranged between adjacent unit pixels (UPX) in the second direction (D2).

[0278] In each unit pixel area located in the pixel columns (GR2) of the second group, a first light-emitting area (EA1), a second light-emitting area (EA2), and a third light-emitting area (EA3) may be arranged in the same structure as the second unit pixel (UPX2). In addition, in each unit pixel area located in the pixel columns (GR2) of the second group, a first pixel electrode (AE1), a second pixel electrode (AE2), and a third pixel electrode (AE3) may be arranged in the same structure as the second unit pixel (UPX2). The pixel columns (GR2) of the second group may not include a pad electrode (DPD).

[0279] The pixel columns (GR1) of the first group can be arranged in the display area (DA) in N (where N is a natural number greater than or equal to 2) pixel column cycles. The pixel columns (GR2) of the second group can be arranged between the pixel columns (GR1) of the first group.

[0280] In one embodiment, the pixel columns (GR1) of the first group may be arranged in the display area (DA) in a two-pixel column cycle as illustrated in FIG. 9. For example, the pixel columns (GR1) of the first group and the pixel columns (GR2) of the second group may be alternately arranged in the display area (DA) along the first direction (D1). For example, odd-numbered pixel columns of the display area (DA), including the first column (COL1) and the third column (COL3), may be composed of pixel columns (GR1) of the first group, and even-numbered pixel columns of the display area (DA), including the second column (COL2) and the fourth column (COL4), may be composed of pixel columns (GR2) of the second group. Alternatively, odd-numbered pixel columns of the display area (DA) may be composed of pixel columns (GR2) of the second group, and even-numbered pixel columns of the display area (DA) may be composed of pixel columns (GR1) of the first group.

[0281] In another embodiment, the pixel columns (GR1) of the first group may be arranged in the display area (DA) in a three-pixel column cycle as illustrated in FIG. 10. For example, the pixel columns (GR1) of the first group and the pixel columns (GR2) of the second group may be arranged alternately in the display area (DA) in a ratio of approximately 1:2.

[0282] In addition to the embodiments illustrated in FIGS. 9 and 10, the arrangement cycle and / or ratio of the pixel columns (GR1) of the first group and the pixel columns (GR2) of the second group may be varied in various ways depending on the embodiments. In addition, the arrangement cycle of the pad electrodes (DPD) and / or the drilling holes (DH) arranged in each of the pixel columns (GR1) of the first group may also be varied in various ways depending on the embodiments.

[0283] According to the display device (100) according to the above-described embodiments, the space consumption due to the pad electrodes (DPD) can be reduced or minimized through efficient arrangement of the light-emitting areas (EA) of the unit pixels (UPX) (or the pixel electrodes (AE) arranged in the light-emitting areas (EA)) and the pad electrodes (DPD), and the pad electrodes (DPD) and the pixel electrodes (AE) can be arranged more closely. Accordingly, the light-emitting area of ​​the pixels (PX) (for example, the size of the light-emitting areas (EA) of the pixels (PX)) or the aperture ratio (for example, the area of ​​the light-transmitting areas of the color filter layer (CFL) corresponding to the light-emitting areas (EA) of the pixels (PX) or the aperture ratio of the color filter layer (CFL)) can be improved, and the space utilization rate and light efficiency of the display device (100) can be improved.

[0284] In addition, according to the display device (100) according to the embodiments, edge portions including only the first light-emitting areas (EA1) and the second light-emitting areas (EA2) of the unit pixels (UPX) (for example, the first edge portion (EDG1) of the first unit pixel (UPX1) and the fourth edge portion (EDG4) of the second unit pixel (UPX2)) may be arranged to be staggered from each other. For example, in each unit pixel (UPX), only the first light-emitting area (EA1) and the second light-emitting area (EA2) of the unit pixel (UPX) may be exposed in one of the edge portions located at both ends of the unit pixel (UPX) in the second direction (D2), and the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) of the unit pixel (UPX) may all be exposed in the other. In addition, around the edge portion where only the first emission area (EA1) and the second emission area (EA2) of each unit pixel (UPX) are exposed, the edge portion where all of the first emission area (EA1), the second emission area (EA2), and the third emission area (EA3) of the edge portions of the adjacent unit pixel (UPX) are exposed may be arranged. Accordingly, the emission areas (EA) of each color may be relatively evenly arranged in the upper edge portion or the lower edge portion of the pixel rows throughout the display area (DA). Accordingly, the color cast phenomenon, in which a specific color pattern (for example, a horizontal line pattern of a specific color) is recognized along the edge portion or the lower edge portion of the pixel rows, may be prevented or minimized. The color cast phenomenon may be observed, for example, in the upper edge portion or the lower edge portion of a full white box pattern having a predetermined size when the box pattern is displayed on a full black background. The display device (100) according to the embodiments can prevent or minimize such color cast phenomenon. For example, the display device (100) according to the embodiments can have a color cast index of less than 1 at each of the upper edge portion and the lower edge portion.

[0285] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A display area in which unit pixels are arranged, each including a first light-emitting area, a second light-emitting area, and a third light-emitting area; A first unit pixel arranged in a first column of the above display area; and A second unit pixel is disposed in the second column of the display area and is adjacent to the first unit pixel in the first direction, In a first edge portion located at one end of the first unit pixel in a second direction intersecting the first direction, only the first light-emitting area and the second light-emitting area among the first light-emitting area, the second light-emitting area, and the third light-emitting area of ​​the first unit pixel are arranged, A display device, wherein the first light-emitting region, the second light-emitting region, and the third light-emitting region of the second unit pixel are arranged in a second edge portion adjacent to the first edge portion in the first direction and located at one end of the second unit pixel in the second direction.

2. In paragraph 1, A display device, wherein the first light-emitting region, the second light-emitting region, and the third light-emitting region of the first unit pixel are arranged on a third edge portion located at the other end of the first unit pixel in the second direction.

3. In paragraph 2, A display device, wherein the first column of the display area further includes a first pad electrode disposed on the first edge portion.

4. In paragraph 3, Each of the above unit pixels includes a first pixel electrode arranged in the first light-emitting area, a second pixel electrode arranged in the second light-emitting area, and a third pixel electrode arranged in the third light-emitting area. A display device, wherein the first pad electrode is disposed between the first pixel electrode and the second pixel electrode of the first unit pixel in the first edge portion.

5. In paragraph 4, A display device wherein the first pad electrode overlaps the first light-emitting area and the second light-emitting area of ​​the first unit pixel in the first edge portion.

6. In paragraph 4, The size of the third light-emitting region is smaller than the size of each of the first light-emitting region and the second light-emitting region, A display device, wherein, in the unit pixel area where the first unit pixel is arranged, the third light-emitting area is arranged at a position spaced apart from the first edge portion.

7. In paragraph 4, Each of the above unit pixels further includes a light-emitting layer and a common electrode disposed on the first pixel electrode, the second pixel electrode, and the third pixel electrode, A display device, wherein the common electrode is electrically connected to the first pad electrode through a drilling hole disposed on the first pad electrode.

8. In paragraph 7, The above light-emitting layer and the above common electrode are arranged across the entire display area, A display device in which the drilling hole penetrates the light-emitting layer on the first pad electrode.

9. In paragraph 7, A display device further comprising a power line electrically connected to the first pad electrode and to which a common voltage is applied.

10. In paragraph 4, A display device in which only the first emission area and the second emission area among the first emission area, the second emission area, and the third emission area of ​​the second unit pixel are arranged in a fourth edge area adjacent to the third edge area in the first direction and located at the other end of the second unit pixel in the second direction.

11. In paragraph 10, A display device, wherein the first pixel electrode, the second pixel electrode, and the third pixel electrode of the second unit pixel are electrically connected to respective pixel circuits through respective connection holes located in the fourth edge portion.

12. In paragraph 3, A display device, wherein the first column of the display area further includes a second pad electrode arranged in the third edge portion.

13. In paragraph 12, A display device wherein the second pad electrode is disposed between the first light-emitting area and the second light-emitting area of ​​the first unit pixel in the third edge portion and overlaps with the third light-emitting area of ​​the first unit pixel.

14. In paragraph 2, The above display area is, A first group of pixel columns including the first column, each of which has a first light-emitting region, a second light-emitting region, and a third light-emitting region arranged in the same structure as the first unit pixel in each unit pixel area; and A display device further comprising a second group of pixel columns, each of which includes a first light-emitting region, a second light-emitting region, and a third light-emitting region, each having a structure similar to that of the second unit pixel, and each of which includes the second column.

15. In paragraph 14, The pixel columns of the first group are arranged in the display area in a cycle of N (N is a natural number greater than or equal to 2) pixel columns, A display device wherein the pixel columns of the second group are arranged between the pixel columns of the first group.

16. In paragraph 14, A display device, wherein the pixel columns of the first group and the pixel columns of the second group are alternately arranged in the display area along the first direction.

17. In paragraph 14, A display device, wherein the display area further includes a plurality of pad electrodes arranged in the pixel columns of the first group.

18. In paragraph 17, The pixel columns of the second group are a display device that does not include pad electrodes.

19. In paragraph 1, The above first light-emitting region is a red light-emitting region where red light is emitted, The above second light-emitting region is a green light-emitting region that emits green light, The display device, wherein the third light-emitting region is a blue light-emitting region that emits blue light.

20. In paragraph 1, The above first direction is the horizontal direction of the display area, A display device wherein the second direction is a vertical direction of the display area.

Images