Display device and electronic device comprising same

Abstract

This display device comprises: an anode electrode; a light-emitting element disposed on the anode electrode; and a cathode electrode covering at least the upper surface of the light-emitting element. The light-emitting element comprises: a bonding electrode electrically connected to the anode electrode; a light-emitting laminate which is disposed on the bonding electrode, and which includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least the side surface of the active layer; and a reflective electrode layer covering the side surface of the second semiconductor layer, which is not covered by the insulating film, wherein the reflective electrode layer is in an electrical contact with the cathode electrode.

Description

Display device and electronic device including the same

[0001] The present invention relates to a display device and an electronic device including the display device.

[0002] A display device is a device that displays images by combining light emitted from multiple pixels. Improving pixel efficiency can enhance the display quality of a display device.

[0003] An object of the present invention is to provide a display device with improved display quality.

[0004] A display device according to embodiments of the present invention may include an anode electrode; a light-emitting element disposed on the anode electrode; and a cathode electrode covering at least an upper surface of the light-emitting element. The light-emitting element may include a bonding electrode electrically connected to the anode electrode; a light-emitting laminate disposed on the bonding electrode, the light-emitting laminate including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least a side surface of the active layer; and a reflective electrode layer covering a side surface of the second semiconductor layer that is not covered by the insulating film, wherein the reflective electrode layer may be in electrical contact with the cathode electrode.

[0005] In one embodiment, the side surface of the second semiconductor layer not covered by the insulating film may have a reverse tapered shape, and the width of the reverse tapered shape may gradually increase in a direction away from the anode electrode.

[0006] In one embodiment, the second semiconductor layer includes a first region adjacent to the active layer and a second region above the first region, and the reflective electrode layer can cover a side surface of the second semiconductor layer in the second region.

[0007] In one embodiment, the insulating film may cover a side surface of the second semiconductor layer in the first region.

[0008] In one embodiment, the second semiconductor layer includes a first doped region, a second doped region, and a third doped region in that order in a direction away from the anode electrode, and a first average doping concentration in the first doped region may be greater than a second average doping concentration in the second doped region.

[0009] In one embodiment, the second average doping concentration in the second doping region may be greater than the third average doping concentration in the third doping region.

[0010] In one embodiment, the reflective electrode layer can be in direct contact with at least a portion of a side surface of the second semiconductor layer in the first doped region.

[0011] In one embodiment, the reflective electrode layer may not cover the upper surface of the light-emitting laminate.

[0012] In one embodiment, the reflective electrode layer may include at least one selected from the group consisting of aluminum (Al), titanium (Ti), and chromium (Cr).

[0013] In one embodiment, the upper surface of the light-emitting laminate may have a rough shape.

[0014] In one embodiment, the reflective electrode layer may further cover at least a portion of the insulating film.

[0015] A display device according to embodiments of the present invention may include an anode electrode; a cathode electrode spaced apart from the anode electrode; and a light-emitting element disposed on the anode electrode and the cathode electrode. The light-emitting element may include a light-emitting laminate including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least a side surface of the active layer; a first bonding electrode electrically connected to each of the first semiconductor layer and the anode electrode; and a second bonding electrode extending from the insulating film covering a lower surface of the first semiconductor layer, contacting a side surface of the second semiconductor layer not covered by the insulating film, and electrically connected to the cathode electrode.

[0016] In one embodiment, the active layer may completely overlap the second semiconductor layer.

[0017] In one embodiment, the second semiconductor layer includes a first doped region, a second doped region, and a third doped region in that order in a direction away from the anode electrode, and a first average doping concentration in the first doped region may be greater than a second average doping concentration in the second doped region.

[0018] In one embodiment, the second average doping concentration in the second doping region may be greater than the third average doping concentration in the third doping region.

[0019] In one embodiment, the second bonding electrode can be in direct contact with at least a portion of a side surface of the second semiconductor layer in the first doped region.

[0020] In one embodiment, the insulating film may be disposed between the second bonding electrode and the first semiconductor layer.

[0021] In one embodiment, the upper surface of the light-emitting laminate may have a rough shape.

[0022] In one embodiment, the insulating film entirely covers the side surface of the first semiconductor layer and the lower surface of the first semiconductor layer, and defines an open portion exposing a portion of the lower surface of the first semiconductor layer, and the first bonding electrode can be electrically connected to the lower surface of the first semiconductor layer through the open portion.

[0023] In one embodiment, the first bonding electrode may overlap the anode electrode, and the second bonding electrode may overlap the cathode electrode.

[0024] An electronic device according to embodiments of the present invention may include: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device may include: an anode electrode; a light-emitting element disposed on the anode electrode; and a cathode electrode covering at least an upper surface of the light-emitting element. The light-emitting element may include: a bonding electrode electrically connected to the anode electrode; a light-emitting laminate disposed on the bonding electrode, the light-emitting laminate including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least a side surface of the active layer; and a reflective electrode layer covering a side surface of the second semiconductor layer that is not covered by the insulating film. The reflective electrode layer may be in electrical contact with the cathode electrode.

[0025] A display device according to embodiments of the present invention includes an anode electrode, a cathode electrode, and a light-emitting element, wherein the light-emitting element may include a light-emitting laminate including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer, and a reflective electrode layer covering a side surface of the second semiconductor layer that is not covered by an insulating film. The reflective electrode layer may be in electrical contact with the cathode electrode, and thus, an additional electrical connection path may be provided between the cathode electrode and the second semiconductor layer through the reflective electrode layer. Accordingly, the display quality of the display device may be improved.

[0026] A display device according to embodiments of the present invention may include an anode electrode, a cathode electrode, and a light-emitting element, wherein the light-emitting element may include a light-emitting laminate including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer, a first bonding electrode electrically connected to each of the first semiconductor layer and the anode electrode, and a second bonding electrode extending from an insulating film covering a lower surface of the first semiconductor layer, contacting a side surface of the second semiconductor layer that is not covered by the insulating film, and electrically connected to the cathode electrode. In this way, as the second bonding electrode electrically contacts the side surface of the second semiconductor layer, the area of ​​the active layer providing a recombination region of electrons and holes (i.e., a light-emitting region) can be secured to the maximum extent. Accordingly, the display quality of the display device can be improved.

[0027] FIG. 1 is a schematic block diagram illustrating a display device according to embodiments of the present invention.

[0028] FIG. 2 is a schematic block diagram for explaining one of the sub-pixels included in the display device of FIG. 1.

[0029] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0030] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0031] FIG. 5 is a schematic cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0032] FIG. 6 is a schematic plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0033] Figures 7 and 8 are schematic cross-sectional views for explaining the pixels of Figure 6.

[0034] FIGS. 9 to 19 are schematic drawings for explaining a method of manufacturing a light-emitting element included in a pixel of FIG. 7.

[0035] FIGS. 20 to 23 are schematic drawings for explaining a method of manufacturing a light-emitting element included in a pixel of FIG. 8.

[0036] FIG. 24 is a schematic plan view illustrating another embodiment of one of the pixels included in the display panel of FIG. 3.

[0037] Figures 25 to 27 are schematic cross-sectional views for explaining the pixels of Figure 24.

[0038] FIGS. 28 to 40 are schematic drawings for explaining a method of manufacturing a light-emitting element included in the pixel of FIG. 25.

[0039] Figure 41 is a schematic block diagram illustrating a display system according to one embodiment.

[0040] Figures 42 to 45 are schematic drawings for explaining application examples of the display system of Figure 41.

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. It should be noted that in the following description, only the parts necessary for understanding the operation of the present invention will be described, and the description of other parts will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the art to easily practice it.

[0042] When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. Throughout the specification, when a part is said to “comprise” a certain component, this does not exclude other components, but rather includes other components, unless specifically stated to the contrary. “At least one of X, Y, and Z,” and “at least one selected from the array consisting of X, Y, and Z” can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Herein, “and / or” includes any combination of one or more of the configurations.

[0043] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0044] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0045] Various embodiments are described with reference to drawings illustrating the embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the embodiments are not limited thereto.

[0046] The terms "about" or "approximately" as used herein include the stated value and mean within an acceptable range of deviation from the stated value, as determined by a person skilled in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" could mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0047] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which this disclosure pertains. Terms defined in commonly used dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0048] FIG. 1 is a schematic block diagram illustrating a display device according to embodiments of the present invention.

[0049] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and / or a controller (150).

[0050] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0051] Sub-pixels (SP) can generate light of two or more colors. For example, each sub-pixel (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0052] Two or more sub-pixels among the sub-pixels (SP) can constitute a pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in the pixel (PXL).

[0053] The gate driver (120) may be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0054] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and these drivers may be arranged on one side of the display panel (DP) and the other side opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0055] The data driver (130) can be connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) can receive image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) can operate in response to the data control signal (DCS). In embodiments, the data control signal (DCS) can include a source start signal, a source shift clock, a source output enable signal, and the like.

[0056] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn) using the received voltages. When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0057] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0058] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate the voltages by receiving an input voltage from outside the display device (DD) and regulating the received voltage.

[0059] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In another embodiment, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0060] The voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a reference voltage (e.g., a preset or selectable reference voltage) can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) may provide pixel control signals to the sub-pixels (SP) through pixel control lines (PXCL). In FIG. 1, the pixel control lines (PXCL) are illustrated as being connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, the pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0061] The controller (150) can control all operations of the display device (DD). The controller (150) can receive input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and / or a voltage control signal (VCS).

[0062] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by arranging the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0063] In one embodiment, two or more of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on an integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within the driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0064] Fig. 2 is a schematic block diagram for explaining one of the sub-pixels included in the display device of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated as an example.

[0065] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0066] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher level than the second power supply voltage.

[0067] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0068] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0069] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0070] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0071] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0072] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0073] A display panel (DP) may include sub-pixels (SP) arranged in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0074] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but the embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1, SP2, SP3).

[0075] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. In the following, for clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) is configured to generate blue color light.

[0076] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate red light, green light, and blue light, respectively.

[0077] As a display panel (DP), a self-luminous display panel can be used, such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements.

[0078] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and / or the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0079] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as an integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0080] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0081] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In these cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0082] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0083] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0084] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. In another example, the substrate (SUB) may include a polyimide (PI) substrate. In another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0085] In the embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0086] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0087] Circuit elements of the pixel circuit layer (PCL) can constitute a sub-pixel circuit (SPC) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) can be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0088] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0089] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0090] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0091] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In some embodiments, the color filter layer may be omitted.

[0092] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded (or connected) to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an adhesive process using an adhesive layer. All or a portion of the window may be flexible.

[0093] FIG. 5 is a schematic cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0094] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured to be substantially the same as (or similar to) the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Therefore, description of overlapping content will be omitted.

[0095] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0096] FIG. 6 is a schematic plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0097] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0098] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 2) included in a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0099] One or more first light-emitting elements (LD1), one or more second light-emitting elements (LD2), and one or more third light-emitting elements (LD3) may be respectively disposed on the first to third anode electrodes (AE1, AE2, AE3). The first light-emitting elements (LD1) may be connected to the first anode electrode (AE1). The second light-emitting elements (LD2) may be connected to the second anode electrode (AE2). The third light-emitting elements (LD3) may be connected to the third anode electrode (AE3). When light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a specific direction, such as the second direction (DR2), and the light-emitting elements connected thereto may be arranged in the same direction.

[0100] The first light-emitting elements (LD1) may be provided as light-emitting elements (LD, see FIG. 2) included in the first sub-pixel (SP1). The second light-emitting elements (LD2) may be provided as light-emitting elements (LD) included in the second sub-pixel (SP2). The third light-emitting elements (LD3) may be provided as light-emitting elements (LD) included in the third sub-pixel (SP3). When light-emitting elements are provided in one sub-pixel, the light-emitting elements may be connected in parallel between the anode electrode and the cathode electrode to be provided as light-emitting elements (LD) of FIG. 2.

[0101] The first light-emitting elements (LD1), the second light-emitting elements (LD2), and the third light-emitting elements (LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0102] Figures 7 and 8 are schematic cross-sectional views for explaining the pixels of Figure 6. Figures 7 and 8 are schematic cross-sectional views taken along the line X1-X1' of Figure 6.

[0103] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0104] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. For example, the conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0105] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1, SP2, SP3) may include a sub-pixel circuit (SPC, see FIG. 2) of transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). The conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXLC) of FIG. 1.

[0106] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0107] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0108] On a buffer layer (BFL), first to third transistors (T_SP1, T_SP2, T_SP3) corresponding to first to third sub-pixels (SP1, SP2, SP3) may be arranged, respectively. The first transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). The second transistor (T_SP2) may be any one of the transistors of the sub-pixel circuit (SPC) included in the second sub-pixel (SP2). The third transistor (T_SP3) may be any one of the transistors of the sub-pixel circuit (SPC) included in the third sub-pixel (SP3). Each of the first to third transistors (T_SP1, T_SP2, T_SP3) may be understood as a transistor connected to an anode electrode among the transistors of the corresponding sub-pixel.

[0109] A first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and / or a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0110] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the first transistor (T_SP1). The channel region may be a semiconductor pattern that is substantially not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurities, for example, p-type impurities may be used, but embodiments are not limited thereto.

[0111] The semiconductor pattern (SCP) may include at least one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0112] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0113] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the semiconductor pattern (SCP) is spaced apart from the gate electrode (GE). In embodiments, the gate insulating layer (GI) may be provided entirely over the semiconductor pattern (SCP) and the buffer layer (BFL), thereby covering the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0114] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0115] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0116] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), the embodiments are not limited thereto. In the embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of the channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0117] In embodiments, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of each sub-pixel may include transistors of different types. For example, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and another transistor included in the sub-pixel circuit (SPC) of the first sub-pixel (SP1) may be formed of an oxide semiconductor transistor. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the first transistor (T_SP1) is formed.

[0118] In the embodiments, the first transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be a transistor having a bottom gate structure. The structure of the first transistor (T_SP1) may be changed in various ways.

[0119] Each of the second and third transistors (T_SP2, T_SP3) can be configured similarly to the first transistor (T_SP1). Therefore, description of overlapping content is omitted.

[0120] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0121] A first passivation layer (PSV1) may be disposed over the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed beneath the first passivation layer (PSV1) and may provide a flat upper surface.

[0122] First to third connection patterns (CP1, CP2, CP3) may be arranged on a first passivation layer (PSV1). The first to third connection patterns (CP1, CP2, CP3) may penetrate the first passivation layer (PSV1) and be connected to first terminals (ET1) of the first to third transistors (T_SP1, T_SP2, T_SP3), respectively. For example, the first to third connection patterns (CP1, CP2, CP3) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0123] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0124] A second passivation layer (PSV2) may be disposed on the first to third connection patterns (CP1, CP2, CP3) and the first passivation layer (PSV1). The second passivation layer (PSV2) may protect components disposed beneath the second passivation layer (PSV2) and provide a flat upper surface.

[0125] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0126] Either of the first and second passivation layers (PSV1, PSV2) and the interlayer insulating layers (ILD) may comprise the same material, but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0127] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include first to third anode electrodes (AE1, AE2, AE3), a first bank (BNK1), first to third light-emitting elements (LD1, LD2, LD3), an overcoat layer (OCL), a cathode electrode (CE), and a capping layer (CPL).

[0128] On the pixel circuit layer (PCL), first to third anode electrodes (AE1, AE2, AE3) can be arranged on the first to third sub-pixels (SP1, SP2, SP3), respectively.

[0129] The first anode electrode (AE1) may be electrically connected to the first connection pattern (CP1) through a contact hole penetrating the second passivation layer (PSV2). The second anode electrode (AE2) may be electrically connected to the second connection pattern (CP2) through another contact hole penetrating the second passivation layer (PSV2). The third anode electrode (AE3) may be electrically connected to the third connection pattern (CP3) through another contact hole penetrating the second passivation layer (PSV2). In this way, the first to third anode electrodes (AE1, AE2, AE3) may be electrically connected to the first to third transistors (T_SP1, T_SP2, T_SP3), respectively.

[0130] A first bank (BNK1) may be disposed on the first to third anode electrodes (AE1, AE2, AE3). The first bank (BNK1) may have first openings (OP1) exposing portions of the first to third anode electrodes (AE1, AE2, AE3). The first to third light-emitting elements (LD1, LD2, LD3) may be disposed in the first openings (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines areas where the first to third light-emitting elements (LD1, LD2, LD3) are positioned.

[0131] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin. According to some embodiments, in order to further improve light emission efficiency, a reflective layer including a reflective material may be further disposed on a side of the first bank (BNK1) adjacent to the first openings (OP1).

[0132] The first to third light-emitting elements (LD1, LD2, LD3) may be respectively disposed on the first to third anode electrodes (AE1, AE2, AE3). The first to third light-emitting elements (LD1, LD2, LD3) may be respectively bonded and connected to the first to third anode electrodes (AE1, AE2, AE3).

[0133] The first light-emitting element (LD1) may include a bonding electrode (BDE), a light-emitting stack (EST), an insulating film (50), and a reflective electrode layer (60). The light-emitting stack (EST) may include a first semiconductor layer (10), an active layer (20), and a second semiconductor layer (30). The first light-emitting element (LD1) may be implemented as a vertical light-emitting stack in which the bonding electrode (BDE), the first semiconductor layer (10), the active layer (20), and the second semiconductor layer (30) are sequentially stacked along a third direction (DR3).

[0134] The first semiconductor layer (10) may be configured to provide holes. The first semiconductor layer (10) may have a first polarity. For example, the first semiconductor layer (10) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (10) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first semiconductor layer (10) is not limited thereto, and various other materials may constitute the first semiconductor layer (10). In one embodiment of the present invention, the first semiconductor layer (10) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0135] The second semiconductor layer (30) is disposed on the first semiconductor layer (10) and may be configured to provide electrons. The second semiconductor layer (30) may have a second polarity different from the first polarity. For example, the second semiconductor layer (30) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (30) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (30) is not limited thereto, and various other materials may constituting the second semiconductor layer (30). In one embodiment of the present invention, the second semiconductor layer (30) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0136] In embodiments, the second semiconductor layer (30) may include a first doped region (31), a second doped region (32), and a third doped region (33) sequentially along the third direction (DR3). The first doped region (31) may be a region doped with a relatively high concentration of dopant, and the third doped region (33) may be a region that is substantially not doped with dopant or is doped with a relatively low concentration of dopant. The second doped region (32) may be a region doped with a lower concentration of dopant than the first doped region (31) and doped with a higher concentration than the third doped region (33).

[0137] The first average doping concentration of the dopant doped into the second semiconductor layer (30) in the first doping region (31) may be greater than the second average doping concentration of the dopant doped into the second semiconductor layer (30) in the second doping region (32). For example, the first average doping concentration may be about 8 times or more the second average doping concentration. The second average doping concentration of the dopant doped into the second semiconductor layer (30) in the second doping region (32) may be greater than the third average doping concentration of the dopant doped into the second semiconductor layer (30) in the third doping region (33). For example, the second average doping concentration may be about 8 times or more the third average doping concentration.

[0138] The active layer (20) is interposed (or arranged) between the first semiconductor layer (10) and the second semiconductor layer (30), and can provide a region where electrons and holes recombine. As electrons and holes recombine in the active layer (20), they transition to a lower energy level, and light having a corresponding wavelength can be generated. The active layer (20) can be formed in a single or multiple quantum well structure. When the active layer (20) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked to form the active layer (20). However, the active layer (20) is not limited to the above-described structure.

[0139] A bonding electrode (BDE) may be disposed under the first semiconductor layer (10). The bonding electrode (BDE) may be electrically connected to the first semiconductor layer (10). In embodiments, the bonding electrode (BDE) of the first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1). The bonding electrode (BDE) may include a eutectic metal.

[0140] The insulating film (50) may cover a portion of the outer surface of the light emitting stack (EST). In this case, the insulating film (50) may cover at least a side surface of the active layer (20). The insulating film (50) may serve to prevent an electrical short circuit that may occur when the active layer (20) comes into contact with a conductive material other than the first and second semiconductor layers (10, 30). The insulating film (50) may include a transparent insulating material. The insulating film (50) may be configured to expose at least a portion of the bonding electrode (BDE).

[0141] In the embodiments, the insulating film (50) may be configured to cover the entire outer surface of the first semiconductor layer (10) and the outer surface of the active layer (20), while covering the side surface of the second semiconductor layer (30) in the first region (AR1). Here, the first region (AR1) may be a region adjacent to the active layer (20) in the second semiconductor layer (30). The first region (AR1) may be a region adjacent to the active layer (20) among the first doped regions (31).

[0142] In this case, the insulating film (50) may be configured so as not to cover the second region (AR2) of the second semiconductor layer (30). Here, the second region (AR2) is a region above the first region (AR1), and may include a region of the first doped region (31) excluding a region adjacent to the active layer (20), and the second and third doped regions (32, 33).

[0143] In embodiments, an auxiliary electrode (40) may be further disposed between the bonding electrode (BDE) and the first semiconductor layer (10). According to embodiments, the auxiliary electrode (40) may be formed of a conductive material having a reflectivity (e.g., a preset or selectable reflectivity). The conductive material may include an opaque metal. The opaque metal may include, for example, a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. Accordingly, light emitted from the first light-emitting element (LD1) may be more efficiently output toward the light-functional layer (LFL). However, the material of the auxiliary electrode (40) is not limited thereto.

[0144] The reflective electrode layer (60) can cover the side surface of the second semiconductor layer (30) that is not covered by the insulating film (50). For example, the reflective electrode layer (60) can entirely cover the side surface of the second semiconductor layer (30) in the second region (AR2). In this case, the reflective electrode layer (60) can be in electrical contact with the cathode electrode (CE) described below. Accordingly, the second power voltage applied to the cathode electrode (CE) can be transmitted to the second semiconductor layer (30) through the reflective electrode layer (60).

[0145] The reflective electrode layer (60) may be composed of a conductive material having a reflectivity (e.g., a preset or selectable reflectivity). For example, the reflective electrode layer (60) may include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. Accordingly, light emitted from the first light-emitting element (LD1) may be more efficiently output toward the light-functional layer (LFL). In this case, the reflective electrode layer (60) may include at least one selected from the group consisting of aluminum (Al), titanium (Ti), and chromium (Cr), which have relatively low work functions. In this way, when the reflective electrode layer (60) includes a material having a relatively low work function, the contact resistance between the reflective electrode layer (60) and the second semiconductor layer (30) can be relatively lowered, so that the efficiency of the first light-emitting element (LD1) can be further improved.

[0146] In embodiments, the reflective electrode layer (60) may not cover the upper surface of the light-emitting stack (EST). For example, the reflective electrode layer (60) may be configured to expose the upper surface of the second semiconductor layer (30). Accordingly, light emitted from the first light-emitting element (LD1) and directed toward the light-functional layer (LFL) may not be substantially blocked by the reflective electrode layer (60).

[0147] In embodiments, the reflective electrode layer (60) may be in direct contact with at least a portion of a side surface of the second semiconductor layer (30) in the first doped region (31). For example, the second semiconductor layer (30) and the reflective electrode layer (60) may be in electrical contact in the first doped region (31) having a relatively high doping concentration. Accordingly, the efficiency of the first light-emitting element (LD1) may be further improved.

[0148] In embodiments, the side surface of the second semiconductor layer (30) that is not covered by the insulating film (50) may have a reverse tapered shape whose width gradually increases along the third direction (DR3). For example, in the second region (AR2), the side surface of the second semiconductor layer (30) may have a reverse tapered shape. Accordingly, the reflection efficiency of the reflective electrode layer (60) covering the side surface of the second semiconductor layer (30) may be further improved, so that light emitted from the first light-emitting element (LD1) may be more efficiently output toward the light functional layer (LFL).

[0149] In embodiments, the upper surface of the light-emitting stack (EST) may have a rough shape. For example, the upper surface of the second semiconductor layer (30) may have a rough shape, and the rough shape may be implemented in the third doped region (33) of the second semiconductor layer (30). However, the embodiments are not limited thereto, and the rough shape may also be implemented in the second and third doped regions (32, 33) of the second semiconductor layer (30). In this way, as the upper surface of the light-emitting stack (EST) has a rough shape, the light emission efficiency of light emitted from the first light-emitting element (LD1) may be improved.

[0150] Each of the second and third light-emitting elements (LD2, LD3) can be configured similarly to the first light-emitting element (LD1). Therefore, description of overlapping content is omitted.

[0151] An overcoat layer (OCL) may be disposed within the first openings (OP1) in which the first to third light-emitting elements (LD1, LD2, LD3) are disposed. The overcoat layer (OCL) may fix the first to third light-emitting elements (LD1, LD2, LD3) bonded to the first to third anode electrodes (AE1, AE2, AE3) so as not to move. The overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. The overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0152] In embodiments, the overcoat layer (OCL) may not be disposed on the upper surfaces of the first to third light-emitting elements (LD1, LD2, LD3). The first to third light-emitting elements (LD1, LD2, LD3) may protrude into the light-functional layer (LFL). The first to third light-emitting elements (LD1, LD2, LD3) may be at least partially positioned within the second openings (OP2) of the second bank (BNK2). For example, the height of the upper surface of each of the first to third light-emitting elements (LD1, LD2, LD3) from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first to third light-emitting elements (LD1, LD2, LD3) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0153] A cathode electrode (CE) may be disposed on the first to third light-emitting elements (LD1, LD2, LD3). The cathode electrode (CE) may be disposed entirely on the first bank (BNK1), the first to third light-emitting elements (LD1, LD2, LD3), and the overcoat layer (OCL). The cathode electrode (CE) may contact the upper surface of the second semiconductor layer (30) and the reflective electrode layer (60) of each of the first to third light-emitting elements (LD1, LD2, LD3). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. The second power voltage applied to the second power voltage node (VSSN) may be transmitted to the first to third light-emitting elements (LD1, LD2, LD3) through the cathode electrode (CE).

[0154] The cathode electrode (CE) may be configured to be substantially transparent or translucent to satisfy a light transmittance (e.g., a preset or selectable light transmittance). In embodiments, the cathode electrode (CE) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the cathode electrode (CE) is not limited thereto.

[0155] As described above, since the cathode electrode (CE) includes a material that satisfies light transmittance (e.g., preset or selectable light transmittance), the contact resistance between the cathode electrode (CE) and the second semiconductor layer (30) may become relatively high. In this case, assuming that the reflective electrode layer (60) of the first to third light-emitting elements (LD1, LD2, LD3) is absent, the driving efficiency of the first to third light-emitting elements (LD1, LD2, LD3) may be reduced.

[0156] In the present invention, since the first to third light-emitting elements (LD1, LD2, LD3) include a reflective electrode layer (60), an additional electrical connection path between the cathode electrode (CE) and the second semiconductor layer (30) can be provided through the reflective electrode layer (60). Here, the contact resistance between the reflective electrode layer (60) and the second semiconductor layer (30) can be relatively low. Accordingly, the driving efficiency of the first to third light-emitting elements (LD1, LD2, LD3) can be improved.

[0157] A capping layer (CPL) may be disposed on the cathode electrode (CE). The capping layer (CPL) may protect components under the capping layer (CPL), such as the cathode electrode (CE) and the first to third light-emitting elements (LD1, LD2, LD3), from external moisture and humidity. The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0158] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a third passivation layer (PSV3), first and second light conversion patterns (CCP1, CCP2), a light scattering pattern (LSP), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0159] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have second openings (OP2) that overlap the first openings (OP1).

[0160] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent pixels and the first to third sub-pixels (SP1, SP2, SP3). In embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0161] A reflective layer (RFL) may be disposed on the side surfaces of the second bank (BNK2) adjacent to the second openings (OP2). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. For example, the reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0162] It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the second bank (BNK2). The area overlapping the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The area overlapping the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA).

[0163] A third passivation layer (PSV3) may be disposed on the capping layer (CPL) and within the second openings (OP2). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) and at least one of the first and second passivation layers (PSV1, PSV2) may include the same material, but embodiments are not limited thereto.

[0164] On the third passivation layer (PSV3), first and second optical conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) can be arranged within the second openings (OP2).

[0165] The first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0166] In the embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light output efficiency. Accordingly, the first to third sub-pixels (SP1, SP2, SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0167] In embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit red, green, and blue light, respectively. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the color of the light emitted from the first to third light-emitting elements (LD1, LD2, LD3).

[0168] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0169] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on the incident angle of the light. The low-refractive-index layer (LRL) can provide light that has passed through the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) back to the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP), and thus, the light conversion efficiency and light scattering efficiency of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) can be improved. In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0170] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0171] The first to third color filters (CF1, CF2, CF3) may overlap the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP), respectively. Each of the first to third color filters (CF1, CF2, CF3) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, the embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low refractive index layer (LRL).

[0172] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0173] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0174] Referring to FIGS. 6 and 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0175] In the following, the differences between this embodiment and the embodiment described with reference to FIGS. 6 and 7 will be mainly explained, and the parts omitted will be replaced with the previous content.

[0176] The reflective electrode layer (60) may further cover a portion of the insulating film (50). For example, the reflective electrode layer (60) may further cover the insulating film (50) that covers the side surface of the first semiconductor layer (10), the side surface of the active layer (20), and the side surface of the second semiconductor layer (30) in the first region (AR1). Accordingly, light emitted from the first light-emitting element (LD1) may be output more efficiently toward the light functional layer (LFL).

[0177] FIGS. 9 to 19 are schematic drawings for explaining a method of manufacturing a light-emitting element included in a pixel of FIG. 7.

[0178] Referring to FIG. 9, in order to manufacture a light emitting element (LD), a preparation step (ST0) and first to ninth steps (ST1, ST2, ST3, ST4, ST5, ST6, ST7a, ST8a, ST9a) can be performed.

[0179] Referring to FIG. 10, after forming a second semiconductor layer (30), an active layer (20), and a first semiconductor layer (10) sequentially on a substrate (S1), an auxiliary electrode (40) can be formed on the first semiconductor layer (10) (ST0).

[0180] The substrate (S1) may be, for example, a sapphire substrate. In embodiments, the substrate (S1) may have a concave-convex structure formed thereon corresponding to the shape of the upper surface of the light-emitting elements (LD1, LD2, LD3) described with reference to FIG. 7.

[0181] The method for forming the second semiconductor layer (30), the active layer (20), and the first semiconductor layer (10) on the substrate (S1) is not limited. For example, an epitaxial process may be performed to sequentially form the second semiconductor layer (30), the active layer (20), and the first semiconductor layer (10).

[0182] In this case, the second semiconductor layer (30) may include a first doped region (31), a second doped region (32), and a third doped region (33). The first to third doped regions (31, 32, 33) may be formed, for example, by varying the doping concentration of the dopant when performing the epitaxial process.

[0183] Referring to Fig. 11, the first semiconductor layer (10), the active layer (20), and the second semiconductor layer (30) can be etched for the first time using the auxiliary electrode (40) as a mask (ST1).

[0184] In the embodiments, the first etching may be dry etching. Accordingly, the first surface (A1) defined by the first semiconductor layer (10), the active layer (20), and the second semiconductor layer (30) being removed by the first etching may be provided as an inclined surface.

[0185] In the embodiments, only a portion of the first doped region (31) of the second semiconductor layer (30) may be removed by the first etching.

[0186] Referring to Fig. 12, the first semiconductor layer (10), the active layer (20), and the second semiconductor layer (30) can be etched for the second time using the auxiliary electrode (40) as a mask (ST2).

[0187] In the embodiments, the secondary etching may be wet etching. Accordingly, by additionally removing the first semiconductor layer (10), the active layer (20), and the second semiconductor layer (30) through the secondary etching, a first surface (A1') in which the slope of the first surface (A1, see FIG. 11) is removed may be provided.

[0188] Referring to FIG. 13, an insulating film (50) can be formed (ST3). The insulating film (50) can be appropriately patterned. Accordingly, the insulating film (50) can entirely cover the first surface (A1', see FIG. 12) and a portion of the auxiliary electrode (40).

[0189] According to embodiments, a step of removing the auxiliary electrode (40) may be further performed after performing the second step (ST2, see FIG. 12). In this case, an insulating film (50) may be provided to cover a portion of the first semiconductor layer (10).

[0190] Referring to Fig. 14, a bonding electrode (BDE) can be formed on an exposed auxiliary electrode (40) that is not covered by an insulating film (50) (ST4). The bonding electrode (BDE) can be electrically connected to the first semiconductor layer (10) through the auxiliary electrode (40).

[0191] According to embodiments, when the auxiliary electrode (40) is removed, the bonding electrode (BDE) may be provided to be in direct contact with the first semiconductor layer (10).

[0192] Referring to Fig. 15, an etching protection layer (EPL) can be formed to cover an insulating film (50) covering an auxiliary electrode (40) and a bonding electrode (BDE) (ST5). The etching protection layer (EPL) can serve to prevent components positioned beneath the etching protection layer (EPL) from being etched by the tertiary etching described below.

[0193] Referring to Fig. 16, the second semiconductor layer (30) can be etched a third time using the etch protection layer (EPL) as a mask (ST6).

[0194] In the embodiments, the third etching may be dry etching. Accordingly, the second surface (A2) defined by the removal of the second semiconductor layer (30) by the third etching may be provided as an inclined surface.

[0195] In the embodiments, the first to third doping regions (31, 32, 33) of the second semiconductor layer (30) may be removed by the third etching, thereby exposing the substrate (S1).

[0196] Referring to Fig. 17, the reflective electrode layer (60) can be formed by anisotropic deposition (ST7a). As the reflective electrode layer (60) is formed by the anisotropic deposition, the reflective electrode layer (60) can be provided to cover the second surface (A2), which is an inclined surface, and the upper surface of the etching protection layer (EPL), but expose the side surface of the etching protection layer (EPL) and the side surface of the insulating film (50).

[0197] Referring to Fig. 18, the etching protection layer (EPL) can be removed (ST8a). Accordingly, the reflective electrode layer (60) covering the upper surface of the etching protection layer (EPL) can be removed.

[0198] Referring to Fig. 19, the light emitting element (LD) can be separated from the substrate (S1) (ST9a). For example, a laser or the like can be irradiated to the boundary between the light emitting element (LD) and the substrate (S1). The separated light emitting element (LD) can be provided on the pixel circuit layer (PCL) described with reference to Fig. 7 using various known transfer means (or methods).

[0199] FIGS. 20 to 23 are schematic drawings for explaining a method of manufacturing a light-emitting element included in a pixel of FIG. 8.

[0200] Referring to FIG. 20, in order to manufacture a light emitting element (LD), a preparation step (ST0) and first to ninth steps (ST1, ST2, ST3, ST4, ST5, ST6, ST7b, ST8b, ST9b) can be performed.

[0201] The preparation stage (ST0) and the first to sixth stages (ST1, ST2, ST3, ST4, ST5, ST6) may be substantially the same as those described with reference to FIGS. 9 to 16. Therefore, description of overlapping content is omitted.

[0202] Referring to Fig. 21, the reflective electrode layer (60) can be formed by isotropic deposition (ST7b). As the reflective electrode layer (60) is formed by the isotropic deposition, the reflective electrode layer (60) can be provided to entirely cover the second surface (A2, see Fig. 16), the etching protection layer (EPL), and the insulating film (50).

[0203] Referring to Fig. 22, the etching protection layer (EPL) can be removed (ST8b). Accordingly, the reflective electrode layer (60) covering the etching protection layer (EPL) can be removed.

[0204] Referring to Fig. 23, the light emitting element (LD) can be separated from the substrate (S1) (ST9b). For example, a laser or the like can be irradiated to the boundary between the light emitting element (LD) and the substrate (S1). The separated light emitting element (LD) can be provided on the pixel circuit layer (PCL) described with reference to Fig. 8 using various known transfer means (or methods).

[0205] FIG. 24 is a schematic plan view illustrating another embodiment of one of the pixels included in the display panel of FIG. 3.

[0206] Referring to FIG. 24, the pixel (PXL') may include first to third sub-pixels (SP1', SP2', SP3'). The first to third sub-pixels (SP1', SP2', SP3') may be arranged in the first direction (DR1). However, the arrangement of the pixels (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1', SP2', SP3') may be arranged in a zigzag pattern.

[0207] First to third anode electrodes (AE1', AE2', AE3') may be respectively disposed in the first to third sub-pixels (SP1', SP2', SP3'). The first anode electrode (AE1') may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1'). The second anode electrode (AE2') may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2'). The third anode electrode (AE3') may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3').

[0208] The cathode electrode (CE') may be spaced apart from the first to third anode electrodes (AE1', AE2', AE3'). The cathode electrode (CE') and the first to third anode electrodes (AE1', AE2', AE3') may be arranged at substantially the same height. The cathode electrode (CE') may be spaced apart from the first to third anode electrodes (AE1', AE2', AE3') in a second direction (DR2). In embodiments, the cathode electrode (CE') may extend in the first direction (DR1) and be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not shown, the cathode electrode (CE') may extend not only in the first direction (DR1) but also in the second direction (DR2) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. In this way, the cathode electrode (CE') can have various shapes.

[0209] First to third light-emitting elements (LD1', LD2', LD3') may be disposed on first to third anode electrodes (AE1', AE2', AE3') and cathode electrodes (CE'). The first light-emitting element (LD1') may be electrically connected to the first anode electrode (AE1') and the cathode electrode (CE'). The first light-emitting element (LD1') may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of a first sub-pixel (SP1'). The second light-emitting element (LD2') may be electrically connected to the second anode electrode (AE2') and the cathode electrode (CE'). The second light-emitting element (LD2') may be provided as a light-emitting element (LD) connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2'). The third light-emitting element (LD3') may be electrically connected to the third anode electrode (AE3') and the cathode electrode (CE'). The third light-emitting element (LD3') may be provided as a light-emitting element (LD) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3').

[0210] The first to third light-emitting elements (LD1', LD2', LD3') may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0211] Figures 25 to 27 are schematic cross-sectional views for explaining the pixels of Figure 24. Figures 25 and 26 are schematic cross-sectional views taken along the Y1-Y1' line of Figure 24, and Figure 27 is a schematic cross-sectional view taken along the X2-X2' line of Figure 24.

[0212] Referring to FIGS. 24 and 25, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0213] The pixel circuit layer (PCL) can be configured substantially the same as described with reference to Fig. 7. Therefore, description of overlapping content is omitted.

[0214] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1'), a cathode electrode (CE'), a first bank (BNK1), first and second reflective electrodes (RFE1, RFE2), a first light-emitting element (LD1'), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0215] A first anode electrode (AE1') and a cathode electrode (CE') may be disposed on the pixel circuit layer (PCL).

[0216] The first anode electrode (AE1') can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1) can be electrically connected to a transistor constituting a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1).

[0217] The cathode electrode (CE') may be spaced apart from the first anode electrode (AE1') in the second direction (DR2). The cathode electrode (CE') may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE').

[0218] A first bank (BNK1) may be disposed on a first anode electrode (AE1') and a cathode electrode (CE'). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode electrode (AE1') and the cathode electrode (CE'). A first light-emitting element (LD1') may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1') is positioned.

[0219] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0220] A first reflective electrode (RFE1) may be disposed on an exposed portion of a first anode electrode (AE1') and a side surface of a first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of a cathode electrode (CE') and a side surface of a first bank (BNK1) adjacent thereto. The first and second reflective electrodes (RFE1, RFE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1') may be improved. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0221] The first light-emitting element (LD1') may be electrically connected to the first anode electrode (AE1') via the first reflective electrode (RFE1). The first light-emitting element (LD1') may be electrically connected to the cathode electrode (CE') via the second reflective electrode (RFE2). The first light-emitting element (LD1') may be bonded to the first and second reflective electrodes (RFE1, RFE2).

[0222] The first light-emitting element (LD1') may include a first bonding electrode (BDE1), a second bonding electrode (BDE2), an insulating film (50'), and a light-emitting stack (EST'). The light-emitting stack (EST') may include a first semiconductor layer (10'), an active layer (20'), and a second semiconductor layer (30') that are sequentially stacked. The first light-emitting element (LD1') may be a flip chip type light-emitting element.

[0223] The first semiconductor layer (10') may be configured to provide holes. The first semiconductor layer (10') may have a first polarity. For example, the first semiconductor layer (10') may include at least one p-type semiconductor layer. For example, the first semiconductor layer (10') may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first semiconductor layer (10') is not limited thereto, and various other materials may constituting the first semiconductor layer (10'). In one embodiment of the present invention, the first semiconductor layer (10') may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0224] The second semiconductor layer (30') is disposed on the first semiconductor layer (10') and may be configured to provide electrons. The second semiconductor layer (30') may have a second polarity different from the first polarity. For example, the second semiconductor layer (30') may include at least one n-type semiconductor layer. For example, the second semiconductor layer (30') may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (30') is not limited thereto, and various other materials may constituting the second semiconductor layer (30'). In one embodiment of the present invention, the second semiconductor layer (30') may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0225] In embodiments, the second semiconductor layer (30') may include a first doped region (31'), a second doped region (32'), and a third doped region (33') sequentially along the third direction (DR3). The first doped region (31') may be a region doped with a relatively high concentration of dopant, and the third doped region (33') may be a region that is substantially not doped with dopant or is doped with a relatively low concentration of dopant. The second doped region (32') may be a region doped with a lower concentration of dopant than the first doped region (31') and doped with a higher concentration than the third doped region (33').

[0226] The first average doping concentration of the dopant doped into the second semiconductor layer (30') in the first doping region (31') may be greater than the second average doping concentration of the dopant doped into the second semiconductor layer (30') in the second doping region (32'). For example, the first average doping concentration may be about 8 times or more the second average doping concentration. The second average doping concentration of the dopant doped into the second semiconductor layer (30') in the second doping region (32') may be greater than the third average doping concentration of the dopant doped into the second semiconductor layer (30') in the third doping region (33'). For example, the second average doping concentration may be about 8 times or more the third average doping concentration.

[0227] The active layer (20') is interposed between the first semiconductor layer (10') and the second semiconductor layer (30') and can provide a region where electrons and holes recombine. As electrons and holes recombine in the active layer (20'), they transition to a lower energy level, and light having a corresponding wavelength can be generated. The active layer (20') can be formed in a single or multiple quantum well structure. When the active layer (20') is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked to form the active layer (20'). However, the active layer (20') is not limited to the above-described structure.

[0228] The insulating film (50') may cover a portion of the outer surface of the light-emitting stack (EST'). In this case, the insulating film (50') may cover at least a side surface of the active layer (20'). The insulating film (50') may serve to prevent an electrical short circuit that may occur when the active layer (20') comes into contact with a conductive material other than the first and second semiconductor layers (10', 30'). The insulating film (50') may include a transparent insulating material. The insulating film (50') may be configured to expose a portion of the lower surface of the first semiconductor layer (10') for electrical connection with the first bonding electrode (BDE1).

[0229] In the embodiments, the insulating film (50') may be configured to entirely cover the outer surface of the first semiconductor layer (10') and the outer surface of the active layer (20'), while covering the side surface of the second semiconductor layer (30') in a portion of the first doped region (31') adjacent to the active layer (20'). In this case, the insulating film (50') may be configured not to cover the side surface of the second semiconductor layer (30') in the second and third doped regions (32', 33'), and not to cover the side surface of the second semiconductor layer (20') in at least a portion of the first doped region (31') that is not adjacent to the active layer (20').

[0230] The first bonding electrode (BDE1) may be disposed below the first semiconductor layer (10'). The first bonding electrode (BDE1) may be electrically connected to the first semiconductor layer (10') through an open portion that exposes a portion of the lower surface of the first semiconductor layer (10') defined in the insulating film (50'). In embodiments, the first bonding electrode (BDE1) may be disposed on the first anode electrode (AE1') so as to overlap with the first anode electrode (AE1'). The first bonding electrode (BDE1) may be electrically connected to the first anode electrode (AE1'). For example, the first bonding electrode (BDE1) may be electrically connected to the first anode electrode (AE1') through the first reflective electrode (RFE1). The first bonding electrode (BDE1) may include a eutectic metal.

[0231] The second bonding electrode (BDE2) may extend from the insulating film (50') covering the lower surface of the first semiconductor layer (10') to contact a side surface of the second semiconductor layer (30') that is not covered by the insulating film (50'). Accordingly, the second bonding electrode (BDE2) may be electrically connected to the second semiconductor layer (30'). In embodiments, the second bonding electrode (BDE2) may be disposed on the cathode electrode (CE') so as to overlap with the cathode electrode (CE'). The second bonding electrode (BDE2) may be electrically connected to the cathode electrode (CE'). For example, the second bonding electrode (BDE2) may be electrically connected to the cathode electrode (CE') via the second reflective electrode (RFE2). The second bonding electrode (BDE2) may include a eutectic metal.

[0232] In embodiments, the second bonding electrode (BDE2) may be in direct contact with at least a portion of a side surface of the second semiconductor layer (30') in the first doped region (31'). For example, the second semiconductor layer (30') and the reflective electrode layer (60') may be in electrical contact in the first doped region (31') having a relatively high doping concentration. Accordingly, the efficiency of the first light-emitting element (LD1') may be further improved.

[0233] In the embodiments, an insulating film (50') may be interposed between the second bonding electrode (BDE2) and the first semiconductor layer (10'), and between the second bonding electrode (BDE2) and the active layer (20'). Accordingly, an electrical short circuit that may occur when the second bonding electrode (BDE2) comes into contact with the first semiconductor layer (10') and the active layer (20') can be prevented.

[0234] At least a portion of the second bonding electrode (BDE2) may be disposed between the cathode electrode (CE') and the first semiconductor layer (10'). In this case, as described above, the second bonding electrode (BDE2) may extend from the insulating film (50') to electrically contact the side surface of the second semiconductor layer (30'). Accordingly, for electrical connection between the second bonding electrode (BDE2) and the second semiconductor layer (30'), a portion of the first semiconductor layer (10') and the active layer (20') need not be removed (e.g., mesa-etching, etc.). Therefore, in the present invention, the area of ​​the active layer (20') providing a recombination region of electrons and holes (e.g., a light-emitting region) can be secured to the greatest extent possible. For example, the active layer (20') may completely overlap the second semiconductor layer (30'). In other words, the active layer (20') and the second semiconductor layer (30') can have substantially the same planar shape.

[0235] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which first and second reflective electrodes (RFE1, RFE2) and a first light-emitting element (LD1') are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1') bonded to the first and second reflective electrodes (RFE1, RFE2) so as not to move. The overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0236] A third passivation layer (PSV3) may be disposed on the first bank (BNK1) and the overcoat layer (OCL). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) and one of the first and second passivation layers (PSV1, PSV2) may include substantially the same material, but embodiments are not limited thereto.

[0237] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of the first light-emitting element (LD1'). The first light-emitting element (LD1') may protrude into the light-functional layer (LFL). The first light-emitting element (LD1') may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface of the first light-emitting element (LD1') from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1') may be provided to the light-functional layer (LFL) at a relatively high rate.

[0238] The capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first light-emitting element (LD1'), from external moisture and humidity. In some embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1'). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1') and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0239] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1') have been described. Each of the second and third sub-pixels (SP2', SP3') of FIG. 24 can also be configured similarly to the first sub-pixel (SP1'), to the extent not otherwise described herein.

[0240] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0241] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1).

[0242] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0243] A reflective layer (RFL) may be disposed on side surfaces of the second bank (BNK2) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0244] A fourth passivation layer (PSV4) may be disposed on the capping layer (CPL) within the second opening (OP2). The fourth passivation layer (PSV4) may protect components disposed beneath the fourth passivation layer (PSV4) and provide a flat upper surface. The fourth passivation layer (PSV4) and any one of the first to third passivation layers (PSV1, PSV2, PSV3) may include substantially the same material, but embodiments are not limited thereto.

[0245] On the fourth passivation layer (PSV4), a first photo-conversion pattern (CCP1) can be arranged within the second opening (OP2).

[0246] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0247] The first sub-pixel (SP1') may be a red sub-pixel. When the first light-emitting element (LD1') emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1') emits red light, the first light conversion patterns (CCP1) may include scattering particles. In this way, the particles included in the first light conversion pattern (CCP1) may be variously changed depending on the color of the light emitted by the first light-emitting element (LD1').

[0248] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0249] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1') is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0250] Referring to FIG. 24 and FIG. 26, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0251] In the following, the differences between this embodiment and the embodiment described with reference to FIGS. 24 and 25 will be mainly explained, and the parts where the explanation is omitted will be replaced with the previous content.

[0252] In embodiments, the upper surface of the light-emitting stack (EST') may have an uneven shape. For example, the upper surface of the second semiconductor layer (30') may have an uneven shape, and the uneven shape may be implemented in the third doped region (33') of the second semiconductor layer (30'). However, the embodiments are not limited thereto, and the uneven shape may also be implemented in the second and third doped regions (32', 33') of the second semiconductor layer (30'). In this way, as the upper surface of the light-emitting stack (EST') has an uneven shape, the light emission efficiency of light emitted from the first light-emitting element (LD1') may be improved.

[0253] Referring to FIGS. 24, 25, and 27, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0254] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 25. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1', LD2', LD3') corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. The first to third light-emitting elements (LD1', LD2', LD3') may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1') may be connected between a cathode electrode (CE', see FIG. 25) and a transistor included in the sub-pixel circuit of the first sub-pixel (SP1'). The second light-emitting element (LD2') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2'). The third light-emitting element (LD3') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3'). Hereinafter, descriptions of overlapping contents are omitted.

[0255] A light-functional layer (LFL) may be provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 25. Hereinafter, description of overlapping content is omitted.

[0256] The second bank (BNK2) may have second openings (OP2). It may be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1', SP2', SP3') are defined by the second bank (BNK2). The area overlapping with the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The area overlapping with the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA) of the first to third sub-pixels (SP1', SP2', SP3').

[0257] A fourth passivation layer (PSV4) may be disposed within the second openings (OP2) on the capping layer (CPL). First and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the second openings (OP2) on the fourth passivation layer (PSV4).

[0258] In the embodiments, the first to third light-emitting elements (LD1', LD2', LD3') may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1', SP2', SP3') may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0259] In the embodiments, the first to third light-emitting elements (LD1', LD2', LD3') may be configured to emit red, green, and blue light, respectively. In this case, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may each include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the color of the light emitted from the first to third light-emitting elements (LD1', LD2', LD3').

[0260] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0261] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3').

[0262] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0263] The first to third color filters (CF1, CF2, CF3) may overlap the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP), respectively. Each of the first to third color filters (CF1, CF2, CF3) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1') is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2') is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3') is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, the embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low refractive index layer (LRL).

[0264] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1', SP2', SP3') are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0265] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0266] FIGS. 28 to 40 are schematic drawings for explaining a method of manufacturing a light-emitting element included in the pixel of FIG. 25.

[0267] Referring to FIG. 28, a preparation step (ST0') and steps 1 to 11 (ST1', ST2', ST3', ST4', ST5', ST6', ST7', ST8', ST9', ST10', ST11') can be performed.

[0268] Referring to FIG. 29, a second semiconductor layer (30'), an active layer (20'), and a first semiconductor layer (10') are sequentially formed on a substrate (S1'), and then an auxiliary electrode (40') can be formed on the first semiconductor layer (10') (ST0').

[0269] The substrate (S1') may be, for example, a sapphire substrate. In embodiments, one surface of the substrate (S1') facing the second semiconductor layer (30') may be substantially flat. In another embodiment, when the upper surface of the light-emitting element has a rough shape, the substrate (S1) described with reference to FIG. 10 or the like may be used instead of the substrate (S1').

[0270] The method for forming the second semiconductor layer (30'), the active layer (20'), and the first semiconductor layer (10') on the substrate (S1') is not limited. For example, an epitaxial process may be performed to sequentially form the second semiconductor layer (30'), the active layer (20'), and the first semiconductor layer (10').

[0271] In this case, the second semiconductor layer (30') may include a first doped region (31'), a second doped region (32'), and a third doped region (33'). The first to third doped regions (31', 32', 33') may be formed, for example, by varying the doping concentration of the dopant during the epitaxial process.

[0272] Referring to Fig. 30, the first semiconductor layer (10'), the active layer (20'), and the second semiconductor layer (30') can be etched for the first time using the auxiliary electrode (40') as a mask (ST1').

[0273] In the embodiments, the first etching may be dry etching. Accordingly, the third surface (A3) defined by the removal of the first semiconductor layer (10'), the active layer (20'), and the second semiconductor layer (30') by the first etching may be provided as an inclined surface.

[0274] In the embodiments, only a portion of the first doped region (31') of the second semiconductor layer (30') may be removed by the first etching.

[0275] Referring to Fig. 31, the first semiconductor layer (10'), the active layer (20'), and the second semiconductor layer (30') can be etched for the second time using the auxiliary electrode (40') as a mask.

[0276] In the embodiments, the secondary etching may be wet etching. Accordingly, by additionally removing the first semiconductor layer (10'), the active layer (20'), and the second semiconductor layer (30') through the secondary etching, a third surface (A3') in which the slope of the third surface (A3, see FIG. 30) is removed may be provided.

[0277] Referring to FIG. 32, optionally, the auxiliary electrode (40') can be removed (ST3'). There is no limitation on the method for removing the auxiliary electrode (40'), and various known methods can be used.

[0278] Referring to Fig. 33, an insulating film (50') can be formed (ST4'). The insulating film (50') can be appropriately patterned. Accordingly, the insulating film (50') can cover the entire third surface (A3', see Fig. 31) and the first semiconductor layer (10'), but can define an open portion that exposes a portion of the first semiconductor layer (10').

[0279] Referring to FIG. 34, an etching protection layer (EPL') can be formed (ST5') to cover an insulating film (50') covering a first semiconductor layer (10') and a first semiconductor layer (10') that is exposed and not covered by the insulating film (50'). The etching protection layer (EPL') can serve to prevent components placed under the etching protection layer (EPL') from being etched by the third etching described below.

[0280] Referring to Figure 35, the second semiconductor layer (30') can be etched a third time (ST6') using the etching protection layer (EPL') as a mask.

[0281] In the embodiments, the third etching may include dry etching and wet etching performed after the dry etching. Accordingly, the fourth surface (A4) defined by the removal of the second semiconductor layer (30') by the third etching may be a flat surface with the slope removed.

[0282] In the embodiments, the first to third doped regions (31', 32', 33') of the second semiconductor layer (30') may be removed by the third etching, thereby exposing the substrate (S1').

[0283] Referring to Fig. 36, the etch protection layer (EPL') can be removed (ST7').

[0284] Referring to Fig. 37, a photoresist layer (PR) can be formed (ST8'). The photoresist layer (PR) can be appropriately patterned. Accordingly, the photoresist layer (PR) can have an open portion defined in the insulating film (50') that exposes a portion of the first semiconductor layer (10') and a first opening (PR_OP1) that exposes a portion of the insulating film (50') adjacent to the open portion. The photoresist layer (PR) can have an insulating film (50') and a second opening (PR_OP2) that exposes at least a portion of a side surface of the second semiconductor layer (30') in a region adjacent to the insulating film (50'). In this case, a portion of the side surface of the second semiconductor layer (30') exposed by the second opening (PR_OP2) can be configured to include at least a portion of the first doped region (31').

[0285] Referring to Fig. 38, the bonding electrode layer (BDEL) can be formed by isotropic deposition (ST9'). As the bonding electrode layer (BDEL) is formed by the isotropic deposition, the bonding electrode layer (BDEL) can be formed along the profile of the components exposed by the photoresist layer (PR) and the first and second openings (PR_OP1, PR_OP2) defined therein.

[0286] Referring to FIG. 39, the photoresist layer (PR) can be removed (ST10'). Accordingly, a portion of the bonding electrode layer (BDEL) that covered the photoresist layer (PR) can be removed, and the remaining portions of the bonding electrode layer (BDEL) that are not removed can form a first bonding electrode (BDE1) and a second bonding electrode (BDE2).

[0287] Referring to Fig. 40, the light-emitting element (LD') can be separated from the substrate (S1') (ST11'). For example, a laser or the like can be irradiated to the boundary between the light-emitting element (LD') and the substrate (S1'). The separated light-emitting element (LD') can be provided on the pixel circuit layer (PCL) described with reference to Figs. 25 and 27 using various known transfer means (or methods).

[0288] Figure 41 is a schematic block diagram illustrating a display system according to one embodiment.

[0289] Referring to FIG. 41, the display system (1000) may include a processor (1100) and a display device (1200).

[0290] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0291] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0292] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0293] Figures 42 to 45 are schematic perspective views illustrating application examples of the display system of Figure 41.

[0294] Referring to FIG. 42, the display system (1000) of FIG. 41 can be applied to a smart watch (2000) including a display portion (2100) and a strap portion (2200).

[0295] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0296] Referring to FIG. 43, the display system (1000) of FIG. 41 can be applied to an automotive display system (3000). Here, the automotive display system (3000) can include a computing system provided inside and / or outside a vehicle to provide image data.

[0297] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0298] Referring to FIG. 44, the display system (1000) of FIG. 41 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0299] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0300] The frame (4100) may include a battery, a touch pad, a microphone, a camera, etc. The frame (4100) may include a projector that outputs light, a processor that controls light signals, etc.

[0301] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0302] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface of the lens unit (4200) facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). In this case, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0303] Referring to FIG. 45, the display system (1000) of FIG. 41 can be applied to a head-mounted display device (500).

[0304] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0305] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0306] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0307] The above description is merely an example of the technical features of the present disclosure. Those skilled in the art will appreciate various modifications and variations. Accordingly, the embodiments of the present disclosure described above may be implemented individually or in combination with one another.

[0308] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical concept of this disclosure, but rather to illustrate the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included within the scope of this disclosure.

Claims

1. Anode electrode; A light emitting element disposed on the anode electrode; and A cathode electrode covering at least the upper surface of the light-emitting element is included, The above light emitting element, A bonding electrode electrically connected to the anode electrode; A light-emitting laminate disposed on the bonding electrode, comprising a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least a side surface of the active layer; and Including a reflective electrode layer covering the side of the second semiconductor layer that is not covered by the insulating film, A display device in which the reflective electrode layer is in electrical contact with the cathode electrode.

2. In paragraph 1, A display device, wherein the side surface of the second semiconductor layer not covered by the insulating film has a reverse taper shape, and the width of the reverse taper shape gradually increases in a direction away from the anode electrode.

3. In paragraph 1, The second semiconductor layer includes a first region adjacent to the active layer and a second region above the first region, A display device, wherein the reflective electrode layer covers a side surface of the second semiconductor layer in the second region.

4. In paragraph 3, A display device in which the insulating film covers a side surface of the second semiconductor layer in the first region.

5. In paragraph 1, The second semiconductor layer includes a first doped region, a second doped region, and a third doped region in that order in a direction away from the anode electrode, A display device, wherein the first average doping concentration in the first doping region is greater than the second average doping concentration in the second doping region.

6. In paragraph 5, A display device, wherein the second average doping concentration in the second doping region is greater than the third average doping concentration in the third doping region.

7. In paragraph 5, A display device, wherein the reflective electrode layer is in direct contact with at least a portion of a side surface of the second semiconductor layer in the first doped region.

8. In paragraph 1, A display device in which the reflective electrode layer does not cover the upper surface of the light-emitting laminate.

9. In paragraph 1, A display device, wherein the reflective electrode layer comprises at least one selected from the group consisting of aluminum (Al), titanium (Ti), and chromium (Cr).

10. In paragraph 1, A display device in which the upper surface of the above light-emitting laminate has a rough shape.

11. In paragraph 1, A display device wherein the reflective electrode layer further covers at least a portion of the insulating film.

12. Anode electrode; a cathode electrode spaced apart from the anode electrode; and It includes a light emitting element disposed on the anode electrode and the cathode electrode, The above light emitting element, A light-emitting laminate comprising a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; An insulating film covering at least a side surface of the active layer; A first bonding electrode electrically connected to each of the first semiconductor layer and the anode electrode; and A display device comprising a second bonding electrode extending from the insulating film covering the lower surface of the first semiconductor layer, contacting a side surface of the second semiconductor layer not covered by the insulating film, and electrically connected to the cathode electrode.

13. In paragraph 12, A display device wherein the active layer completely overlaps the second semiconductor layer.

14. In paragraph 12, The second semiconductor layer includes a first doped region, a second doped region, and a third doped region in that order in a direction away from the anode electrode, A display device, wherein the first average doping concentration in the first doping region is greater than the second average doping concentration in the second doping region.

15. In paragraph 14, A display device, wherein the second average doping concentration in the second doping region is greater than the third average doping concentration in the third doping region.

16. In paragraph 14, A display device, wherein the second bonding electrode is in direct contact with at least a portion of a side surface of the second semiconductor layer in the first doped region.

17. In paragraph 12, A display device, wherein the insulating film is disposed between the second bonding electrode and the first semiconductor layer.

18. In paragraph 12, A display device in which the upper surface of the above light-emitting laminate has a rough shape.

19. In paragraph 12, The insulating film entirely covers the side surface of the first semiconductor layer and the lower surface of the first semiconductor layer, and defines an open portion that exposes a portion of the lower surface of the first semiconductor layer. A display device in which the first bonding electrode is electrically connected to the lower surface of the first semiconductor layer through the open portion.

20. In paragraph 12, The above first bonding electrode overlaps the above anode electrode, A display device wherein the second bonding electrode overlaps the cathode electrode.

21. A processor providing input image data; and A display device that displays an image based on the above input image data is included, The above display device: anode electrode; A light emitting element disposed on the anode electrode; and A cathode electrode covering at least the upper surface of the light-emitting element is included, The above light emitting element, A bonding electrode electrically connected to the anode electrode; A light-emitting laminate disposed on the bonding electrode, comprising a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating film covering at least a side surface of the active layer; and Including a reflective electrode layer covering the side of the second semiconductor layer that is not covered by the insulating film, An electronic device wherein the reflective electrode layer is in electrical contact with the cathode electrode.

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