Display substrate and display apparatus

Abstract

A display substrate, comprising: a base substrate (10), a plurality of sub-pixels (PX) located in a display area (A1) and located on a side of the base substrate (10), a plurality of first-type data lines (DL1) located in an effective area (AA) and arranged around a hole area (A2), a plurality of first-type data fan-out lines (411, 412, 413) located in a fan-out area and electrically connected to the plurality of first-type data lines (DL1), and a first data signal capacitance compensation structure located in the fan-out area, at least one insulating layer being provided between the first data signal capacitance compensation structure and the plurality of first-type data fan-out lines (411, 412, 413), and the orthographic projection of the first data signal capacitance compensation structure on the base substrate (10) and the orthographic projection of at least one of the first-type data fan-out lines (411, 412, 413) on the base substrate (10) at least partially overlapping each other.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first data signal capacitance compensation structure. The substrate comprises an effective area and a first bezel area located at least one side of the effective area; the effective area comprises: an aperture area and a display area located around the aperture area; the first bezel area comprises: a signal access area and a fan-out area located between the signal access area and the display area. The plurality of sub-pixels are located in the display area and at one side of the substrate. The plurality of data lines are located in the effective area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the plurality of data lines at least comprise: a plurality of first type data lines arranged along the aperture area. The plurality of data fan-out lines are located in the fan-out area, and the plurality of data fan-out lines at least comprise: a plurality of first type data fan-out lines, which are electrically connected to the plurality of first type data lines. The first data signal capacitance compensation structure is located in the fan-out area and at a side of the plurality of data fan-out lines away from the substrate, and at least one insulating layer is arranged between the first data signal capacitance compensation structure and the plurality of data fan-out lines; the orthographic projection of the first data signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first type data fan-out lines on the substrate.

[0007] In some example embodiments, the plurality of data lines further include a plurality of second type data lines located in the display region and extending along the first direction; the plurality of data fan-out lines further include a plurality of second type data fan-out lines, the plurality of second type data fan-out lines being electrically connected with the plurality of second type data lines; a number of sub-pixels connected with at least one of the plurality of first type data lines is less than a number of sub-pixels connected with at least one of the plurality of second type data lines.

[0008] In some example embodiments, at least two of the plurality of first type data fan-out lines have different overlapping areas with the first data signal capacitance compensation structure in the orthographic projection of the substrate.

[0009] In some example embodiments, the first bezel region further includes a bending region, the fan-out region includes a first fan-out region located between the display region and the bending region; the plurality of first type data fan-out lines includes a plurality of first type first data fan-out lines located in the first fan-out region. The first data signal capacitance compensation structure includes a first capacitance compensation plate located in the first fan-out region, the first capacitance compensation plate at least partially overlaps with at least one of the plurality of first type first data fan-out lines in the orthographic projection of the substrate.

[0010] In some example embodiments, the display substrate further includes a first peripheral power line located in the first fan-out region; the first capacitance compensation plate is located on a side of the first peripheral power line away from the display region and is electrically connected with the first peripheral power line.

[0011] In some example embodiments, the first capacitance compensation plate and the first peripheral power line are an integrated structure connected with each other.

[0012] In some example embodiments, the first capacitance compensation plate has a non-symmetrical shape in the orthographic projection of the substrate.

[0013] In some example embodiments, the first border area further includes a bending area and a circuit arrangement area between the bending area and the signal access area. The fan-out area includes a first fan-out area between the display area and the bending area, a second fan-out area between the bending area and the circuit arrangement area, and a third fan-out area between the circuit arrangement area and the signal access area. The plurality of first-type data fan-out lines includes a plurality of third-type first data fan-out lines in the third fan-out area. The first data signal capacitance compensation structure includes a second capacitance compensation plate in the third fan-out area, the second capacitance compensation plate at least partially overlaps at least one of the plurality of third-type first data fan-out lines in the substrate.

[0014] In some example embodiments, the display substrate further includes a first peripheral power supply line in the first fan-out area, and a first power supply lead-out line in at least the second fan-out area and the third fan-out area; the first power supply lead-out line is connected to the first peripheral power supply line; and the second capacitance compensation plate is electrically connected to the first power supply lead-out line through a compensation connection line.

[0015] In some example embodiments, the second capacitance compensation plate has a first edge and a second edge in the substrate, the second edge is located on a side of the first edge away from the bending area in a first direction, the first edge is a straight line extending in a second direction, and the second edge is a broken line extending in the second direction, the second direction intersecting the first direction.

[0016] In some example embodiments, the effective area further includes a wire winding area between the hole area and the display area. The display substrate further includes at least one first compensation resistor in the wire winding area, and at least one of the plurality of first-type data lines is connected in series to the at least one first compensation resistor.

[0017] In some example embodiments, the effective area further includes a wire winding area between the hole area and the display area. The display substrate further includes a second data signal capacitance compensation structure in the wire winding area, at least one insulating layer is arranged between the second data signal capacitance compensation structure and the plurality of first-type data lines, and the second data signal capacitance compensation structure partially overlaps at least one of the plurality of first-type data lines in the substrate.

[0018] In some exemplary embodiments, the second data signal capacitance compensation structure includes: at least one third capacitance compensation plate, wherein the orthographic projection of the third capacitance compensation plate on the substrate overlaps with the orthographic projection portion of at least one of the plurality of first-type data lines on the substrate, and the third capacitance compensation plate is located on the side of the at least one first-type data line closer to the substrate.

[0019] In some exemplary embodiments, the display substrate further includes: a plurality of gate lines and a gate signal capacitance compensation structure. The plurality of gate lines are located in the effective region and are electrically connected to the plurality of sub-pixels. The plurality of gate lines include at least a plurality of first-type gate lines arranged along the aperture region. The gate signal capacitance compensation structure is located in the effective region, and at least one insulating layer is disposed between the gate signal capacitance compensation structure and the plurality of gate lines. The orthographic projection of the gate signal capacitance compensation structure onto the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first-type gate lines onto the substrate.

[0020] In some exemplary embodiments, the first border region is located on one side of the effective region along a first direction, and the substrate further includes a second border region and a third border region located on both sides of the effective region along a second direction; the second direction intersects the first direction. The display substrate further includes a plurality of gate driving circuits. At least one first-type gate line is connected to two gate driving circuits that transmit the same signal, and one of the two gate driving circuits is located in the second border region, and the other is located in the third border region.

[0021] On the other hand, this embodiment provides a display device including a display substrate as described above.

[0022] On the other hand, this embodiment provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of gate lines, and a gate signal capacitance compensation structure. The substrate includes an effective region and a border region surrounding the effective region. The effective region includes: an aperture region, a display region surrounding the aperture region, and a winding region between the aperture region and the display region. The plurality of sub-pixels are located in the display region and on one side of the substrate. The plurality of gate lines are located in the effective region and are electrically connected to the plurality of sub-pixels. The plurality of gate lines include at least a plurality of first-type gate lines wound along the aperture region. The gate signal capacitance compensation structure is located in the winding region, and at least one insulating layer is disposed between the gate signal capacitance compensation structure and the plurality of gate lines. The orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first-type gate lines on the substrate.

[0023] In some example embodiments, the plurality of first type gate lines at least include a plurality of first type first scan lines and a plurality of first type second scan lines, the plurality of first type first scan lines are configured to provide first scan signals to data write transistors of pixel circuits of the plurality of sub-pixels, the plurality of first type second scan lines are configured to provide second scan signals to compensation transistors of the pixel circuits of the plurality of sub-pixels, and the data write transistors and the compensation transistors are of different transistor types. The gate signal capacitance compensation structure at least includes a first gate signal capacitance compensation plate, a projection of the first gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of at least one of the plurality of first type second scan lines on the substrate, and the first gate signal capacitance compensation plate is located on a side of the plurality of first type second scan lines away from the substrate.

[0024] In some example embodiments, in a direction perpendicular to the display substrate, an active area of the display substrate at least includes a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source-drain metal layer, which are sequentially arranged on the substrate. The first type second scan line is located on the first gate metal layer in the wire winding area, and the first gate signal capacitance compensation plate is located on the third gate metal layer or the first source-drain metal layer.

[0025] In some example embodiments, in a direction perpendicular to the display substrate, an active area of the display substrate at least includes a bottom shielding metal layer, a first gate metal layer, and a second gate metal layer, which are sequentially arranged on the substrate. The gate signal capacitance compensation structure includes a second gate signal capacitance compensation plate located on the bottom shielding metal layer, a projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of a plurality of first type gate lines located on the first gate metal layer on the substrate, or a projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of a plurality of first type gate lines located on the first gate metal layer and the second gate metal layer on the substrate.

[0026] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0027] SUMMARY

[0028] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0029] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] FIG. 2A is a schematic diagram of a partial cross-section of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0031] FIG. 2B is another schematic diagram of a partial cross-section of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0032] FIG. 3 is a schematic diagram of a first border region according to at least one embodiment of the present disclosure;

[0033] FIG. 4 is a schematic diagram of partial traces of the first border region according to at least one embodiment of the present disclosure;

[0034] FIG. 5A is a schematic diagram of a first fan-out region according to at least one embodiment of the present disclosure;

[0035] FIG. 5B is a schematic diagram of a first source-drain metal layer in FIG. 5A according to at least one embodiment of the present disclosure;

[0036] FIG. 6 is another schematic diagram of the first border region according to at least one embodiment of the present disclosure;

[0037] FIG. 7A is a schematic diagram of a partial cross-section of the first border region according to at least one embodiment of the present disclosure;

[0038] FIG. 7B is a schematic diagram of a second capacitance compensation plate in FIG. 7A according to at least one embodiment of the present disclosure;

[0039] FIG. 7C is another schematic diagram of the second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0040] FIG. 7D is another schematic diagram of the second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0041] FIG. 7E is another schematic diagram of the second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0042] FIG. 8 is another schematic diagram of a partial cross-section of the first border region according to at least one embodiment of the present disclosure;

[0043] FIG. 9 is another schematic diagram of the first border region according to at least one embodiment of the present disclosure;

[0044] FIG. 10 is a schematic diagram of a partial cross-section along the P-P’ direction in FIG. 1 according to at least one embodiment of the present disclosure;

[0045] FIG. 11 is a schematic diagram of a partial structure of the region S1 in FIG. 1 according to at least one embodiment of the present disclosure;

[0046] FIG. 12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0047] FIG. 13 is a schematic diagram of a gate line in FIG. 12 according to at least one embodiment of the present disclosure;

[0048] FIG. 14 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] FIG. 15 is a schematic view of a gate drive circuit according to an embodiment of the present disclosure;

[0050] FIG. 16 is a schematic view of a partial cross section along the Q-Q' direction in FIG. 13;

[0051] FIG. 17 is a schematic view of another partial cross section along the Q-Q' direction in FIG. 13;

[0052] FIG. 18 is a schematic view of another partial cross section along the Q-Q' direction in FIG. 13;

[0053] FIG. 19 is a schematic view of another partial cross section along the Q-Q' direction in FIG. 13;

[0054] FIG. 20 is a schematic view of a display device according to an embodiment of the present disclosure.

[0055] DETAILED DESCRIPTION

[0056] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following description. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as they do not conflict with each other.

[0057] In the drawings, the size, the thickness, or the region of one or more constituent elements in the drawings, the layer thickness, or the region is sometimes exaggerated for the purpose of explanation and is not necessarily to scale. Therefore, the present disclosure should not be construed as being limited to the shape, the number, the region, or the like illustrated in the drawings. The present disclosure is not limited to the shape or the numerical value illustrated in the drawings, and the like.

[0058] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements and are not intended to indicate the order or the number of the constituent elements. The "plurality" in the present disclosure indicates two or more.

[0059] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation of the specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0060] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.

[0061] In this specification, "electrically connected" includes the case where the components are connected together by an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like.

[0062] In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0063] In this specification, the first pole can be a drain, and the second pole can be a source, or the first pole can be a source, and the second pole can be a drain. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other. In addition, the gate can also be referred to as the control pole.

[0064] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0065] In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly so, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformations due to tolerances, such as a fillet, an arc edge, and a deformation.

[0066] In the present disclosure, "about" or "approximately" means not strictly limited to the limit, and allows for a range of process and measurement errors. In the present disclosure, "substantially the same" means a difference of 10% or less in the numerical value.

[0067] In the present disclosure, "A extends along the direction of B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the secondary portion extending along another direction. In the present disclosure, "A extends along the direction of B" means "the main portion of A extends along the direction of B".

[0068] In the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B. In the present disclosure, "the shape of A" refers to the shape of the orthographic projection of A on the substrate.

[0069] With the development of display technology, the demand for full screen is increasing. In order not to lose the effect of taking pictures, the display substrate needs to be specially designed to meet the purpose of exposing the rear camera. Among them, the display area through hole (AA hole) design is one of the main solutions of full screen. Since no sub-pixel is arranged in the display area through hole, the data line originally passing through the display area through hole needs to bypass the display area through hole to connect the sub-pixels on both sides of the display area through hole. Therefore, the signal loading of the data line bypassing the display area through hole is different from that of the data line not needing to bypass the display area through hole, thereby causing display defects (Mura) and the like. Similarly, the gate line originally passing through the display area through hole needs to bypass the display area through hole to connect the sub-pixels on both sides of the display area through hole. Therefore, the signal loading of the gate line bypassing the display area through hole is different from that of the gate line not needing to bypass the display area through hole, thereby causing display defects (Mura) and the like. In particular, for the display substrate designed with a super large display area through hole (for example, the diameter of the through hole can range from 6 mm to 20 mm), the number of data lines and gate lines that need to bypass the display area through hole is large, and the display defects caused by the difference in signal loading of the lines are more obvious.

[0070] The embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first data signal capacitance compensation structure. The substrate comprises an effective area and a first frame area located on at least one side of the effective area; the effective area comprises a hole area and a display area located around the hole area; the first frame area comprises a signal access area and a fan-out area located between the signal access area and the display area. The plurality of sub-pixels are located in the display area and on one side of the substrate. The plurality of data lines are located in the effective area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the plurality of data lines at least comprise a plurality of first type data lines arranged along the hole area. The plurality of data fan-out lines are located in the fan-out area, and the plurality of data fan-out lines at least comprise a plurality of first type data fan-out lines, which are electrically connected to the plurality of first type data lines. The first data signal capacitance compensation structure is located in the fan-out area and on a side of the plurality of data fan-out lines away from the substrate, and at least one insulating layer is arranged between the first data signal capacitance compensation structure and the plurality of data fan-out lines; the orthographic projection of the first data signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first type data fan-out lines on the substrate. For example, the orthographic projection of the first data signal capacitance compensation structure on the substrate can partially overlap with the orthographic projection of the plurality of first type data fan-out lines on the substrate.

[0071] The display substrate provided by the embodiment can compensate the signal load of the first data lines connected to the first data fan-out lines by compensating the capacitance of the first data fan-out lines through the first data signal capacitance compensation structure arranged in the fan-out area, so as to improve the display uniformity of the display area.

[0072] In some example embodiments, the plurality of data lines can further include a plurality of second data lines located in the display area and extending along the first direction. The plurality of data fan-out lines can further include a plurality of second data fan-out lines electrically connected to the plurality of second data lines. The number of sub-pixels connected to the at least one first data line is less than the number of sub-pixels connected to the at least one second data line. The present example can reduce the difference in signal load between the first data lines and the second data lines by compensating the capacitance of the first data fan-out lines through the first data signal capacitance compensation structure, thereby improving the display effect of the display area.

[0073] In some example embodiments, the overlapping area of the at least two first data fan-out lines and the first data signal capacitance compensation structure in the orthographic projection of the substrate can be different. The present example can adjust the compensation capacitance of the first data lines by adjusting the overlapping area of the first data fan-out lines and the first data signal capacitance compensation structure in the substrate.

[0074] In some example embodiments, the first frame area can further include a bending area, and the fan-out area can include a first fan-out area located between the display area and the bending area. The plurality of first data fan-out lines can include a plurality of first data fan-out lines located in the first fan-out area. The first data signal capacitance compensation structure can include a first capacitance compensation electrode plate located in the first fan-out area, and the orthographic projection of the first capacitance compensation electrode plate in the substrate at least partially overlaps with the orthographic projection of the at least one first data fan-out line in the substrate. For example, the orthographic projection of the first capacitance compensation electrode plate in the substrate can partially overlap with the orthographic projection of the plurality of first data fan-out lines in the substrate. The present example compensates the signal load of the first data lines connected to the first data fan-out lines by compensating the capacitance of the first data fan-out lines through the first capacitance compensation electrode plate arranged in the first fan-out area.

[0075] In some example embodiments, the display substrate can further include a first peripheral power line located in the first fan-out area. The first capacitance compensation electrode plate can be located on the side of the first peripheral power line away from the display area and electrically connected to the first peripheral power line. For example, the first capacitance compensation electrode plate and the first peripheral power line can be an integrated structure connected to each other. The present example can avoid the adverse effects caused by the floating of the first capacitance compensation electrode plate by electrically connecting the first capacitance compensation electrode plate and the first peripheral power line.

[0076] In some example embodiments, the first border area can further include a bending area, and a circuit arrangement area between the bending area and the signal access area. The fan-out area can include a first fan-out area between the display area and the bending area, a second fan-out area between the bending area and the circuit arrangement area, and a third fan-out area between the circuit arrangement area and the signal access area. The plurality of first-type data fan-out lines can include a plurality of third-type first data fan-out lines in the third fan-out area. The first data signal capacitance compensation structure can include a second capacitance compensation plate in the third fan-out area. A projection of the second capacitance compensation plate on the substrate at least partially overlaps a projection of at least one third-type first data fan-out line on the substrate. For example, the projection of the second capacitance compensation plate on the substrate can partially overlap the projections of the plurality of third-type first data fan-out lines on the substrate. This example utilizes the second capacitance compensation plate in the third fan-out area to capacitively compensate the first-type data fan-out lines, to compensate for the signal load of the first-type data lines connected by the first-type data fan-out lines. In other examples, the first data signal capacitance compensation structure can include a first capacitance compensation plate in the first fan-out area and a second capacitance compensation plate in the third fan-out area. The signal load of the first-type data lines connected by the first-type data fan-out lines can be compensated by the cooperation of the first capacitance compensation plate and the second capacitance compensation plate.

[0077] In some example embodiments, the display substrate can further include a first power supply lead line at least in the second fan-out area and the third fan-out area. The first power supply lead line can be connected with the first peripheral power supply line. The second capacitance compensation plate is electrically connected with the first power supply lead line through a compensation connection line. For example, the compensation connection line can be on the side of the second capacitance compensation plate close to the substrate. The second capacitance compensation plate and the first power supply lead line can be a same layer structure, or can be a different layer structure. This example is not limited thereto. This example can avoid the adverse effects of floating of the second capacitance compensation plate by electrically connecting the second capacitance compensation plate with the first power supply lead line.

[0078] The following examples are provided to illustrate the schemes of the embodiments.

[0079] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the display substrate can include an active area AA and a frame area BB around the active area AA. The active area AA can include a hole region A2, a display region A1 on at least two sides of the hole region A2, and a wire winding region A3 between the hole region A2 and the display region A1. The hole region A2 can not be provided with sub-pixels and can not be used for display; in other words, the hole region A2 can be a non-display region. In some examples, the wire winding region A3 can not be provided with sub-pixels and can not be used for display. However, the present embodiments are not limited thereto. In other examples, a separate wire winding region can not be provided, and the wires in the wire winding region can be arranged in the display region.

[0080] In some examples, the hole region A2 can have a circular shape in orthographic projection; and the active area AA can have a circular-rectangular shape in orthographic projection. For example, the hole region A2 can have a diameter ranging from 6 mm to 20 mm, such as about 12 mm. In other examples, the hole region can have a circular-rectangular or elliptical shape in orthographic projection. In other examples, the active area can have a circular, elliptical, or polygonal shape in orthographic projection.

[0081] In some examples, the hole region A2 can have an inner edge of the wire winding region A3, and the wire winding region A3 can have an outer edge connected to the display region A1. For example, the hole region A2 can have a circular shape in orthographic projection, and the wire winding region A3 can have a circular ring shape in orthographic projection. However, the present embodiments are not limited thereto. In other examples, the wire winding region can have a rectangular ring or an elliptical ring shape in orthographic projection to match the shape of the hole region.

[0082] In some examples, the hole region A2 can be located at a middle position of the active area AA, such that the display region A1 can surround the hole region A2 on four sides. In other examples, the hole region A2 can be adjacent to a left edge or a right edge of the active area AA, such that the display region A1 can surround at least the top side and the bottom side of the hole region A2. In other examples, the hole region A2 can be adjacent to a top edge or a bottom edge of the active area AA, such that the display region A1 can surround at least the left side and the right side of the hole region A2.

[0083] In some examples, the border region BB can include: a first border region B1 and a fourth border region B4 located on both sides of the active region AA along the first direction Y, and a second border region B2 and a third border region B3 located on both sides of the active region AA along the second direction X. The first border region B1 can be in communication with the second border region B2 and the third border region B3, and connected with the display region A1. The fourth border region B4 can be in communication with the second border region B2 and the third border region B3, and connected with the display region A1. The first border region B1, the second border region B2, the fourth border region B4 and the third border region B3 can surround the display region A1 after being in communication. For example, the first border region B1 can be a lower border region of the display substrate, the second border region B2 can be a left border region of the display substrate, the third border region B3 can be a right border region of the display substrate, and the fourth border region B4 can be an upper border region of the display substrate. However, the present embodiment is not limited thereto.

[0084] In some examples, the display region A1 can include a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX can be configured to display dynamic pictures or still images. For example, the display substrate can adopt a flexible substrate, so that the display substrate can be deformable, such as being curled, bent, folded or rolled up.

[0085] In some examples, the active region AA can include: a plurality of gate lines (not shown in the figure) and a plurality of data lines. The orthogonal projections of the plurality of gate lines and the plurality of data lines on the substrate can cross to form a plurality of sub-pixel regions, and one sub-pixel PX is arranged in each sub-pixel region. The plurality of data lines are electrically connected with the plurality of sub-pixels PX, and the plurality of data lines can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines are electrically connected with the plurality of sub-pixels PX, and the plurality of gate lines can be configured to provide gate driving signals to the plurality of sub-pixels PX. For example, the gate driving signals can include scan signals, or can include scan signals and light-emitting control signals, or can include scan signals, reset control signals and light-emitting control signals.

[0086] In some examples, as shown in FIG. 1, the plurality of data lines of the active region AA can include: a plurality of first type data lines DL1 and a plurality of second type data lines DL2. The plurality of first type data lines DL1 can be arranged along the hole region A2, and the plurality of second type data lines DL2 can extend along the first direction Y and be arranged along the second direction X. In the second direction X, the plurality of second type data lines DL2 can be divided into two groups, and the plurality of first type data lines DL1 can be located in the middle of the two groups of second type data lines DL2.

[0087] In some examples, since the sub-pixels are not arranged in the hole region A2, the data line originally passing through the hole region A2 needs to bypass the hole region A2. In this example, the data line that needs to bypass the hole region A2 is the first type of data line DL1. The first type of data line DL1 can bypass the hole region A2 by being arranged in the winding region A3. Each data line can be connected to a column of sub-pixels arranged in the first direction Y. Since the hole region A2 does not have sub-pixels arranged therein, the number of sub-pixels connected by at least one first type of data line DL1 can be less than the number of sub-pixels connected by at least one second type of data line DL2, and the signal load of the at least one first type of data line DL1 can be less than the signal load of the at least one second type of data line DL2.

[0088] In some examples, as shown in FIG. 1, the first type of data line DL1 can include a first data extension segment DL1-1, a second data extension segment DL1-2, and a data winding segment DL1-3. One end of the data winding segment DL1-3 is connected to the first data extension segment DL1-1, and the other end is connected to the second data extension segment DL1-2. The first data extension segment DL1-1 and the second data extension segment DL1-2 can be substantially straight line segments extending in the first direction Y and located at least in the display region A1. The data winding segment DL1-3 can be substantially an arcuate segment or a polyline segment extending in the first direction Y and located at least in the winding region A3. For example, the first data extension segment DL1-1, the second data extension segment DL1-2, and the data winding segment DL1-3 of the first type of data line DL1 can be an integral structure connected to each other; or the first data extension segment DL1-1 and the second data extension segment DL1-2 of the first type of data line DL1 can be located in the same conductive layer, and the conductive layer in which the data winding segment DL1-3 is located can be different from the conductive layer in which the first data extension segment DL1-1 is located. The present embodiment is not limited in this regard.

[0089] In some examples, the plurality of first type of data lines DL1 can be divided into two groups. The data winding segments DL1-3 of the first group of first type of data lines DL1 can be located on one side of the hole region A2 along the second direction X, and the data winding segments DL1-3 of the second group of first type of data lines DL1 can be located on the opposite side of the hole region A2 along the second direction X. The number of first type of data lines DL1 in the first group of first type of data lines DL1 can be the same as or different from the number of first type of data lines DL1 in the second group of first type of data lines DL1.

[0090] In some examples, the first direction Y can be the extension direction (e.g., the column direction) of the data lines in the display region A1, and the second direction X can be the extension direction (e.g., the row direction) of the gate lines in the display region A1. The first direction Y and the second direction X can intersect each other, for example, can be perpendicular to each other.

[0091] In some examples, one pixel unit of the display area A1 can include three sub-pixels, which can be a first sub-pixel emitting a first color light (for example, red light), a second sub-pixel emitting a second color light (for example, green light), and a third sub-pixel emitting a third color light (for example, blue light). However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which can be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, one pixel unit can include four sub-pixels, which can include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0092] In some examples, one sub-pixel can include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit can be P-type transistors or can be N-type transistors, and the use of the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0093] In some examples, the shape of the light emitting element of the sub-pixel can be rectangular, rhombic, pentagonal or hexagonal. When one pixel unit includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner; when one pixel unit includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner. However, the present embodiment is not limited thereto.

[0094] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiments are not limited thereto.

[0095] FIG. 2A is a schematic view of a partial cross-section of a display area of a display substrate according to at least one embodiment of the present disclosure. In FIG. 2A, the structure of one sub-pixel of the display area is taken as an example for illustration. In the present example, the transistor types of the plurality of pixel transistors in the pixel circuit can be different, for example, can include low-temperature polysilicon thin film transistors and oxide thin film transistors.

[0096] In some examples, as shown in FIG. 2A, in a direction perpendicular to the display substrate, the display area of the display substrate can include a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, and an encapsulation structure layer 14 arranged in sequence on the substrate. The circuit structure layer 12 can at least include the pixel circuit of a plurality of sub-pixels, and each sub-pixel of the pixel circuit can include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 can at least include the light emitting element of a plurality of sub-pixels. In other examples, the display substrate can further include a touch structure layer on the side of the encapsulation structure layer away from the substrate. For example, the touch structure layer can include at least one touch conductive layer.

[0097] In some examples, FIG. 2A takes one first transistor 21, one second transistor 22, and one capacitor 23 included in each sub-pixel as an example for illustration. The transistor types of the first transistor 21 and the second transistor 22 can be different. Among them, the first transistor 21 can be a low-temperature polysilicon thin film transistor, and the second transistor 22 can be an oxide thin film transistor. Alternatively, the first transistor 21 can be an oxide thin film transistor, and the second transistor 22 can be a low-temperature polysilicon thin film transistor.

[0098] In some examples, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 can be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 can be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 can be disposed between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (may also be referred to as a passivation layer) and a seventh insulating layer 107 (may also be referred to as a first planarization layer) can be disposed between the first source-drain metal layer and the second source-drain metal layer, the seventh insulating layer 107 can be located on a side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (may also be referred to as a second planarization layer) can be disposed on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can also be disposed on a side of the first semiconductor layer close to the substrate, which can prevent harmful substances in the substrate from invading the inside of the display substrate, and also increase the adhesion of the film layers in the display substrate on the substrate. In other examples, a bottom shielding metal layer (BSM) can also be disposed on a side of the buffer layer close to the substrate, which can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid the influence of external light on the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the seventh insulating layer can be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0099] In some examples, as shown in FIG. 2A, the first semiconductor layer of the display region can include at least: a first active layer 210 of a first transistor 21. The first active layer 210 of the first transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can include at least: a first gate 213 of the first transistor 21, and a first plate 231 of a capacitor 23. The first gate 213 of the first transistor 21 can cover the channel region 2100 of the first active layer 210 in the orthographic projection of the substrate 10. The second gate metal layer can include at least: a second plate 232 of the capacitor 23. The second plate 232 and the first plate 231 of the capacitor 23 can at least partially overlap in the orthographic projection of the substrate 10, e.g., the two can coincide. The second semiconductor layer can include at least: a second active layer 220 of a second transistor 22. The third gate metal layer can include at least: a second gate 223 of the second transistor 22. The second gate 223 of the second transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10.

[0100] In some examples, as shown in FIG. 2A, the first source-drain metal layer can at least include: the first source 211 and the first drain 212 of the first transistor 21, the second source 221 and the second drain 222 of the second transistor 22. The fifth insulating layer 105 can be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105 and the fourth insulating layer 104 in the third pixel via and the fourth pixel via can be removed to expose at least part of the surface of both ends of the second active layer 220. The first source 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can at least include: the first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through the fifth pixel via provided by the sixth insulating layer 106 and the seventh insulating layer 107. The present example can realize the electrical connection between the pixel circuit and the light emitting element through the first transfer electrode 241.

[0101] In some examples, as shown in FIG. 2A, the light-emitting structure layer 13 can include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be electrically connected to the first transfer electrode 241 through a sixth pixel via hole of the eighth insulating layer 108 provided on the eighth insulating layer 108. The pixel definition layer 134 is provided on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 131. At least part of the organic light-emitting layer 132 can be provided in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be provided on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0102] In some examples, the organic light-emitting layer 132 of the light-emitting element can include an emitting layer (EML) and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting element can emit light according to the required gray scale by utilizing the light-emitting characteristics of the organic material.

[0103] In some examples, the light-emitting layers of the light-emitting elements of different colors can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and the isolation can be realized by the surface step of the formed film layer or by surface treatment and the like. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by an inkjet process.

[0104] In some examples, as shown in FIG. 2A, the encapsulation structure layer 14 can include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. The first encapsulation layer 141 and the third encapsulation layer 143 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high compactness and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 142 can be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light-emitting element. The second encapsulation layer 142 can be made of organic materials, such as a high polymer material containing a desiccant or a high polymer material capable of blocking water vapor, etc., or a high polymer resin, etc. to perform a planarization treatment on the surface of the display substrate, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and can also include a water-absorbing material such as a desiccant to absorb water, oxygen, etc. invading the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0105] FIG. 2B is another partial cross-sectional schematic view of a display area of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2B, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 10. An eighth insulating layer 108 can be disposed between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 can be disposed on a side of the third source-drain metal layer away from the substrate. The ninth insulating layer 109 can be an organic insulating layer, which can also be referred to as a third planarization layer. The third source-drain metal layer can include at least a second transfer electrode 242, which can be connected to a first transfer electrode 241 in the second source-drain metal layer. The first transfer electrode 241 and the second transfer electrode 242 can be used to electrically connect the pixel circuit to the first electrode 131 of the light-emitting element in this example. The remaining structures of the display area of the display substrate in this example can be the same as those described with reference to the example shown in FIG. 2A, and thus will not be described again here.

[0106] FIG. 3 is a schematic view of a first bezel area according to at least one embodiment of the present disclosure. FIG. 4 is a partial wiring schematic view of the first bezel area according to at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 3 and 4, the first bezel area B1 can include, in order along a side away from the active area AA in the first direction Y, a first fan-out area B01, a bending area B02, a second fan-out area B03, a circuit arrangement area B04, a third fan-out area B05, a first signal access area B06, and a second signal access area B07. In this example, the fan-out areas in the first bezel area B1 can include the first fan-out area B01, the second fan-out area B03, and the third fan-out area B05. The first fan-out area B01 is located between the active area AA and the bending area B02, the second fan-out area B03 is located between the bending area B02 and the circuit arrangement area B04, and the third fan-out area B05 is located between the circuit arrangement area B04 and the first signal access area B06. The signal access areas in the first bezel area B1 can include the first signal access area B06 and the second signal access area B07. However, this example is not limited thereto. In other examples, the first bezel area B1 can include, in order along a side away from the active area AA in the first direction Y, the first fan-out area B01, the bending area B02, the second fan-out area B03, the first signal access area B06, and the second signal access area B07.

[0107] In some examples, the bending region B02 can be configured to bend the second fan-out region B03, the circuit arrangement region B04, the third fan-out region B05, the first signal access region B06 and the second signal access region B07 to the back of the display region A1. A plurality of bending connection lines (for example, including a plurality of data bending lines, a first power bending line and a second power bending line) can be arranged in the bending region B02 to realize electrical connection between the traces transmitting the same signals in the first fan-out region B01 and the second fan-out region B03.

[0108] In some examples, the circuit arrangement region B04 can be arranged with a plurality of test circuits arranged along the second direction X. In other examples, a plurality of anti-static circuits can be arranged on the side of the plurality of test circuits close to the bending region B02, and a plurality of data selection circuits can be arranged on the side of the plurality of test circuits away from the bending region B02. The present embodiment is not limited in this regard.

[0109] In some examples, the first signal access region B06 can be arranged with a plurality of first contact pads configured to connect a driving integrated circuit (IC). The second signal access region B07 can be arranged with a plurality of second contact pads configured to be bonded with an external flexible circuit board (FPC). At least one first contact pad in the first signal access region B06 and at least one second contact pad in the second signal access region B07 can be connected by a lead-out connection line.

[0110] In some examples, as shown in FIG. 4, the fan-out region can be arranged with a plurality of data fan-out lines. The plurality of data fan-out lines can include a plurality of first data fan-out lines 411 in the first fan-out region B01, a plurality of second data fan-out lines 412 in the second fan-out region B03, and a plurality of third data fan-out lines 413 in the third fan-out region B05. The plurality of first data fan-out lines 411 can be configured to connect a plurality of data lines in the display region A1 in a fan-out trace manner. For example, the plurality of first data fan-out lines 411 can be electrically connected to the plurality of data lines one by one, or at least one first data fan-out line can be electrically connected to at least two data lines. The plurality of first data fan-out lines 411 can be connected to the plurality of second data fan-out lines 412 in the second fan-out region B03 through the plurality of data bending lines 421 arranged in the bending region B02. For example, the plurality of first data fan-out lines 411 can be electrically connected to the plurality of data bending lines 421 one by one, and the plurality of data bending lines 421 can be electrically connected to the plurality of second data fan-out lines 412 one by one. The plurality of second data fan-out lines 412 in the second fan-out region B03 can be connected to circuits (for example, including test circuits, or including test circuits, anti-static circuits and data selection circuits) in the circuit arrangement region B04 to receive data signals or test data signals.

[0111] In some examples, the plurality of third data fan-out lines 413 in the third fan-out region B05 can be connected with the plurality of second data fan-out lines 412 through the circuit in the circuit setting region B04, for example, at least one third data fan-out line 413 can be configured to transmit data signals to at least two second data fan-out lines 412. The plurality of third data fan-out lines 413 can be connected with the plurality of first contact pads in the first signal access region B06, so as to receive data signals from the driving integrated circuit.

[0112] In some examples, the plurality of data fan-out lines in the fan-out region can be divided into a plurality of first type data fan-out lines and a plurality of second type data fan-out lines according to the type of the connected data lines. The plurality of first type data fan-out lines can be configured to transmit data signals to the plurality of first type data lines DL1, and the plurality of second type data fan-out lines can be configured to transmit data signals to the plurality of second type data lines DL2. For example, the plurality of first type data fan-out lines can include a plurality of first type first data fan-out lines (i.e. the plurality of first data fan-out lines connected with the plurality of first type data lines DL1), a plurality of first type second data fan-out lines (i.e. the plurality of second data fan-out lines connected with the plurality of first type data lines DL1), and a plurality of first type third data fan-out lines (i.e. the plurality of third data fan-out lines connected with the plurality of first type data lines DL1); and the plurality of second type data fan-out lines can include a plurality of second type first data fan-out lines (i.e. the plurality of first data fan-out lines connected with the plurality of second type data lines DL2), a plurality of second type second data fan-out lines (i.e. the plurality of second data fan-out lines connected with the plurality of second type data lines DL2), and a plurality of second type third data fan-out lines (i.e. the plurality of third data fan-out lines connected with the plurality of second type data lines DL2).

[0113] In some examples, the plurality of first data fan-out lines 411 in the first fan-out region B01 can be arranged alternately in the first gate metal layer and the second gate metal layer; the plurality of second data fan-out lines 412 in the second fan-out region B03 can be arranged alternately in the first gate metal layer and the second gate metal layer; and the plurality of third data fan-out lines 413 in the third fan-out region B05 can be arranged alternately in the first gate metal layer and the second gate metal layer. However, the present embodiment is not limited thereto. In other examples, the plurality of first data fan-out lines can be located in the first gate metal layer or the second gate metal layer; the plurality of second data fan-out lines can be located in the first gate metal layer or the second gate metal layer; and the plurality of third data fan-out lines can be located in the first gate metal layer or the second gate metal layer.

[0114] In some examples, as shown in FIG. 4, the first fan-out area B01 can be further provided with a first peripheral power line 311, a second peripheral power line 321a and 321b. Within the first fan-out area B01, the first peripheral power line 311 can extend at least along the second direction X, and the first peripheral power line 311 can be located on a side of the plurality of first data fan-out lines 411 away from the substrate. The orthogonal projection of the first peripheral power line 311 on the substrate can partially overlap the orthogonal projection of the plurality of first data fan-out lines 411 on the substrate, for example, the orthogonal projection of the first peripheral power line 311 on the substrate can partially overlap the orthogonal projection of each of the first data fan-out lines on the substrate.

[0115] In some examples, the second peripheral power line 321a can be located on a side of the first peripheral power line 311 in the opposite direction of the second direction X, and the second peripheral power line 321b can be located on a side of the first peripheral power line 311 along the second direction X. The second peripheral power line 321a can extend towards the second bezel area, and the second peripheral power line 321b can extend towards the third bezel area.

[0116] In some examples, the first peripheral power line 311 can be configured to be electrically connected with the first power line of the display area A1, and the second peripheral power line 321a and 321b can be configured to be electrically connected with the second power line of the display area A1 or the cathode of the light emitting element. The first voltage signal transmitted by the first power line can be greater than the second voltage signal transmitted by the second power line, for example, the first voltage signal can be a positive voltage signal, and the second voltage signal can be a negative voltage signal.

[0117] In some examples, as shown in FIG. 4, the first border region can also be provided with a first power supply lead-out line 312 and second power supply lead-out lines 322a and 322b. The first power supply lead-out line 312 can include a power supply body portion 3120 extending along the second direction X, and a first power supply connecting portion 3121 and a second power supply connecting portion 3122 extending along the first direction Y. The first power supply connecting portion 3121 is connected with one end of the power supply body portion 3120, and the second power supply connecting portion 3122 is connected with the other end of the power supply body portion 3120. The power supply body portion 3120 can be located within the second fan-out region B03, and the power supply body portion 3120 can have an overlap with the plurality of second data fan-out lines 412 in the substrate in the orthographic projection. The power supply body portion 3120 can be electrically connected with the first perimeter power supply line 311 within the first fan-out region B01 through at least one first power supply bending line of the bending region B02. The first power supply connecting portion 3121 can extend from the second fan-out region B03 to the second signal access region B07, can bypass the first signal access region B06 from one side (e.g., the left side) of the first signal access region B06, and be connected with at least one second contact pad within the second signal access region B07. The second power supply connecting portion 3122 can extend from the second fan-out region B03 to the second signal access region B07, can bypass the first signal access region B06 from the other side (e.g., the right side) of the first signal access region B06, and be connected with at least one second contact pad within the second signal access region B07. The power supply body portion 3120, the first power supply connecting portion 3121, and the second power supply connecting portion 3122 can be an integrated structure connected with each other.

[0118] In some examples, the second power supply lead-out line 322a can be located on the side opposite to the first power supply lead-out line 312 in the second direction X, and the second power supply lead-out line 322b can be located on the side of the first power supply lead-out line 312 in the second direction X. The second power supply lead-out line 322a can extend from the second fan-out region B03 to the second signal access region B07, and be connected with at least one second contact pad within the second signal access region B07. The second power supply lead-out line 322b can extend from the second fan-out region B03 to the second signal access region B07, and be connected with at least one second contact pad within the second signal access region B07. The second power supply lead-out line 322a can be electrically connected with the second perimeter power supply line 321a within the first fan-out region B01 through at least one second power supply bending line of the bending region B02, and the second power supply lead-out line 322b can be electrically connected with the second perimeter power supply line 321b within the first fan-out region B01 through at least one second power supply bending line of the bending region B02.

[0119] In some examples, the first data signal capacitance compensation structure can include a first capacitance compensation plate 511 located at the first fan-out area B01. The first capacitance compensation plate 511 can be located at a side of the first perimeter power supply line 311 away from the display area A1. At least one insulating layer can be provided between the first capacitance compensation plate 511 and the plurality of first data fan-out lines 411. The orthographic projection of the first capacitance compensation plate 511 on the substrate can partially overlap the orthographic projection of the plurality of first data fan-out lines 411 on the substrate. The first capacitance compensation plate 511 and the first perimeter power supply line 311 can be a same layer structure. However, the present embodiment is not limited thereto. In other examples, the first capacitance compensation plate and the first perimeter power supply line can be a different layer structure.

[0120] FIG. 5A is a partial schematic view of a first fan-out area according to at least one embodiment of the present disclosure. FIG. 5B is a schematic view of a first source-drain metal layer in FIG. 5A. The plurality of first-type data fan-out lines 411a of the first fan-out area B01 are schematically shown as a whole in FIG. 5A. The film layer structure of the present example is taken as an example of the film layer structure of the embodiment shown in FIG. 2A.

[0121] In some examples, as shown in FIG. 5A and FIG. 5B, the plurality of first-type data fan-out lines 411a can include a first group of first-type data fan-out lines 411a-1 and a second group of first-type data fan-out lines 411a-2. For example, the first-type data lines DL1 connected by the first group of first-type data fan-out lines 411a-1 can be routed from the left side of the aperture area A2, and the first-type data lines DL1 connected by the second group of first-type data fan-out lines 411a-2 can be routed from the right side of the aperture area A2.

[0122] In some examples, the plurality of first-type first data fan-out lines 411a can be alternately arranged in the first gate metal layer and the second gate metal layer. Adjacent first-type first data fan-out lines 411a can be located at different film layers and can not overlap in orthographic projection on the substrate. However, the present embodiment is not limited thereto. For example, the plurality of first data fan-out lines can all be located in the first gate metal layer or the second gate metal layer.

[0123] In some examples, the first peripheral power line 311 can be a single-layered trace located at the first source-drain metal layer. The first capacitance compensation plate 511 can be located at the first source-drain metal layer and can be an integral structure connected with the first peripheral power line 311. In other examples, the first peripheral power line 311 can include a first sub-trace located at the first source-drain metal layer and a second sub-trace located at the second source-drain metal layer, and the first sub-trace and the second sub-trace are electrically connected. The second sub-trace can be connected with the first power fold line of the bending area B02 located at the second source-drain metal layer, and the first sub-trace can be electrically connected with the first power line of the display area A1. For example, the first power line of the display area A1 can be located at the first source-drain metal layer or the second source-drain metal layer. The first capacitance compensation plate can be an integral structure connected with the first sub-trace located at the first source-drain metal layer, or the first capacitance compensation plate can be connected with the second sub-trace located at the second source-drain metal layer. However, the present embodiment is not limited thereto. In other examples, the first peripheral power line 311 can be a single-layered trace located at the second source-drain metal layer, and the first capacitance compensation plate 511 can be located at the second source-drain metal layer and electrically connected with the first peripheral power line 311.

[0124] In some examples, the first capacitance compensation plate 511 can have a first edge 511-1 and a second edge 511-2 in the orthographic projection of the substrate. The second edge 511-2 is located on the side of the first edge 511-1 away from the first peripheral power line 311 in the first direction Y. The first edge 511-1 can coincide with the edge of the first peripheral power line 311 away from the display area A1. The first edge 511-1 can be a straight line extending along the second direction X, and the second edge 511-2 can be a broken line extending along the second direction X. For example, the second edge 511-2 can be approximately an inverted V-shaped. The first capacitance compensation plate 511 can have an asymmetric shape in the orthographic projection of the substrate. However, the present embodiment is not limited thereto. In other examples, the first capacitance compensation plate 511 can have an inverted trapezoidal, triangular, or rectangular shape in the orthographic projection of the substrate.

[0125] In some examples, the first capacitance compensation plate 511 can not overlap with the projection of the plurality of second-type first data fan-out lines on the substrate. The overlapping area of the first capacitance compensation plate 511 and the projection of at least two first-type first data fan-out lines 411a on the substrate can be different. The overlapping area of the first capacitance compensation plate 511 and the projection of the first-type first data fan-out lines 411a on the substrate can be related to the signal load of the first-type data lines connected to the first-type first data fan-out lines 411a. For example, the overlapping area of the first capacitance compensation plate 511 and the projection of the first group of first-type first data fan-out lines 411a-1 on the substrate can gradually decrease along the second direction X; the overlapping area of the first capacitance compensation plate 511 and the projection of the second group of first-type first data fan-out lines 411a-2 on the substrate can gradually increase along the second direction X. However, the present embodiment is not limited thereto. In other examples, the overlapping area of the first capacitance compensation plate and the first-type first data fan-out lines can be adjusted according to the signal load of the first-type data lines.

[0126] The present example can compensate the load of the first-type data lines connected to the first-type first data fan-out lines by arranging the first capacitance compensation plate overlapping with the projection of the first-type first data fan-out lines on the substrate in the first fan-out area, so that the signal load of the first-type data lines is substantially the same as that of the second-type data lines, thereby improving the display defects caused by the difference in signal load of the data lines, and ensuring the display effect of the display area.

[0127] FIG. 6 is another schematic view of the first bezel area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 6, the first data signal capacitance compensation structure can include a second capacitance compensation plate 512 located in the third fan-out area B05. The second capacitance compensation plate 512 and the plurality of third data fan-out lines 413 are arranged with at least one insulating layer therebetween. For example, the plurality of third data fan-out lines 413 can be alternately arranged in the first gate metal layer and the second gate metal layer, and adjacent third data fan-out lines 413 can be located in different conductive layers and can not overlap on the projection of the substrate. The plurality of third data fan-out lines 413 can include a plurality of first-type third data fan-out lines and a plurality of second-type third data fan-out lines.

[0128] In some examples, the second capacitance compensation plate 512 can be located in the first source-drain metal layer, or the second source-drain metal layer, or the third source-drain metal layer. The projection of the second capacitance compensation plate 512 on the substrate can partially overlap with the projection of the plurality of first-type third data fan-out lines on the substrate. For example, the projection of each first-type third data fan-out line on the substrate can partially overlap with the projection of the second capacitance compensation plate 512 on the substrate.

[0129] FIG. 7A is a schematic diagram of a first border area according to at least one embodiment of the present disclosure. FIG. 7A illustrates partial routing structures of the second fan-out area and the third fan-out area. In FIG. 7A, the second data fan-out lines 412 of the second fan-out area B03 and the third data fan-out lines 413 of the third fan-out area B05 are schematically illustrated as a whole. FIG. 7B is a schematic diagram of the second capacitor compensation plate in FIG. 7A. The film layer structure of the present example is taken as an example of the film layer structure of the embodiment shown in FIG. 2A.

[0130] In some examples, as shown in FIG. 7A and FIG. 7B, the third data fan-out lines 413 can include: a first group of first-type third data fan-out lines 413a-1, a second group of first-type third data fan-out lines 413a-2, a first group of second-type third data fan-out lines 413b-1, and a second group of second-type third data fan-out lines 413b-2. For example, the first group of first-type third data fan-out lines 413a-1 can be configured to provide data signals to the first group of first-type data lines of the display area A1, and the second group of first-type third data fan-out lines 413a-2 can be configured to provide data signals to the second group of first-type data lines of the display area A1. The first group of second-type third data fan-out lines 413b-1 can be configured to provide data signals to the first group of second-type data lines of the display area A1, and the second group of second-type third data fan-out lines 413b-2 can be configured to provide data signals to the second group of second-type data lines of the display area A1. The first group of first-type data lines can be routed from the left side of the aperture area A2, the second group of first-type data lines can be routed from the right side of the aperture area A2, the first group of second-type data lines can be located on the side of the first group of first-type data lines close to the edge of the display area, and the second group of second-type data lines can be located on the side of the second group of first-type data lines close to the edge of the display area. In the third fan-out area B05, the first group of second-type third data fan-out lines 413b-1, the first group of first-type third data fan-out lines 413a-1, the second group of first-type third data fan-out lines 413a-2, and the second group of second-type third data fan-out lines 413b-2 can be sequentially arranged along the second direction X.

[0131] In some examples, the third data fan-out lines 413 can be alternately arranged in the first gate metal layer and the second gate metal layer. However, the present embodiment is not limited thereto. In other examples, the third data fan-out lines can all be located in the first gate metal layer or the second gate metal layer.

[0132] In some examples, the test circuitry within the circuitry arrangement region B04 can be connected with the plurality of second contact pads within the second signal access region B07 through a plurality of test control lines 62, or connected with a separate test contact pad, or connected with both the plurality of second contact pads within the second signal access region B07 and the separate test contact pad. The plurality of test control lines 62 can be located in the first source-drain metal layer. The plurality of third data fan-out lines 413 can be provided with a plurality of control fan-out lines 61 along one side of the second direction X, which can extend to the first signal access region B06 and be connected with the plurality of first contact pads within the first signal access region B06. The plurality of control fan-out lines 61 can be configured to provide driving signals (e.g., including clock signals, start signals, etc.) to the plurality of gate driving circuitry. At least one control fan-out line 61 can be located in the first gate metal layer, or can adopt a double-layer routing design of the first gate metal layer and the second gate metal layer.

[0133] In some examples, at least one insulating layer is provided between the second capacitor compensation plate 512 and the plurality of third data fan-out lines 413 in the third fan-out region B05. The second capacitor compensation plate 512 can partially overlap with the plurality of first-type third data fan-out lines in the substrate. For example, the second capacitor compensation plate 512 can partially overlap with each first-type third data fan-out line in the substrate, and can not overlap with the second-type third data fan-out lines in the substrate.

[0134] In some examples, as shown in FIG. 7B, the second capacitor compensation plate 512 can have a first edge 512-1 and a second edge 512-2 in the substrate. The second edge 512-2 can be located on the side of the first edge 512-1 away from the circuitry arrangement region B04 in the first direction Y. The first edge 512-1 can be a straight line extending along the second direction X, and the second edge 512-2 can be a broken line extending along the second direction X. For example, the second edge 512-2 can be approximately W-shaped. For example, the second edge 512-2 can include a first slanted segment 5131, a first straight segment 5141, a second slanted segment 5132, a third slanted segment 5133, a second straight segment 5142, and a fourth slanted segment 5134 connected in sequence along the second direction X; the second slanted segment 5132 and the third slanted segment 5133 can be connected to form a recessed portion recessed towards the first edge 512-1. The first straight segment 5141 can be located on the side of the first slanted segment 5131 and the second slanted segment 5132 away from the first direction Y, and the second straight segment 5142 can be located on the side of the third slanted segment 5133 and the fourth slanted segment 5134 away from the first direction Y.

[0135] In some examples, the overlapping area of the at least two third data fan-out lines of the first type and the second capacitance compensation plate 512 in the orthographic projection of the substrate can be different. The size of the overlapping area of the second capacitance compensation plate 512 and the plurality of third data fan-out lines of the first type in the substrate is related to the signal load that needs to be compensated by the first type data line connected to the third data fan-out line of the first type. For example, the overlapping area of the second capacitance compensation plate 512 and the left half of the first group of third data fan-out lines of the first type 413a-1 in the orthographic projection of the substrate can gradually increase along the second direction X; the overlapping area of the second capacitance compensation plate 512 and the right half of the first group of third data fan-out lines of the first type 413a-1 in the orthographic projection of the substrate can gradually decrease along the second direction X. The overlapping area of the second capacitance compensation plate 512 and the left half of the second group of third data fan-out lines of the first type 413a-2 in the orthographic projection of the substrate can gradually increase along the second direction X; the overlapping area of the second capacitance compensation plate 512 and the right half of the second group of third data fan-out lines of the first type 413a-1 in the orthographic projection of the substrate can gradually decrease along the second direction X. However, the present embodiment is not limited thereto.

[0136] The present example can compensate the load of the first type data line connected to the third data fan-out line of the first type by setting the second capacitance compensation plate overlapping with the orthographic projection of the plurality of third data fan-out lines of the first type in the third fan-out area, so that the signal load of the first type data line and the signal load of the second type data line are substantially the same, thereby improving the display defects caused by the difference in signal load of the data line, and ensuring the display effect of the display area.

[0137] FIG. 7C is another schematic view of the second capacitance compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7C, the second edge 512-2 of the second capacitance compensation plate 512 can be a zigzag shape extending along the second direction X. The second edge 512-2 can include a third straight line segment 5143, a fifth slanted line segment 5135, a sixth slanted line segment 5136, and a fourth straight line segment 5144 connected in sequence along the second direction X. The fifth slanted line segment 5135 and the sixth slanted line segment 5136 can connect to form a recessed portion recessed toward the first direction Y. For example, the overlapping area of the second capacitance compensation plate 512 and the left half of the first group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can be substantially the same; the overlapping area of the second capacitance compensation plate 512 and the right half of the first group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can gradually decrease along the second direction X. The overlapping area of the second capacitance compensation plate 512 and the left half of the second group of the first type of third data fan-out lines 413a-2 in the orthographic projection of the substrate can gradually increase along the second direction X; the overlapping area of the second capacitance compensation plate 512 and the right half of the second group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can be substantially the same.

[0138] FIG. 7D is another schematic view of the second capacitance compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7D, the second edge 512-2 of the second capacitance compensation plate 512 can be a zigzag shape extending along the second direction X. The second edge 512-2 can include a seventh slanted line segment 5137, a fifth straight line segment 5145, and an eighth slanted line segment 5138 connected in sequence along the second direction X. The fifth straight line segment 5145 can be located on the side of the seventh slanted line segment 5137 and the eighth slanted line segment 5138 in the opposite direction of the first direction Y. For example, the overlapping area of the second capacitance compensation plate 512 and the left half of the first group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can gradually increase along the second direction X; the overlapping area of the second capacitance compensation plate 512 and the right half of the first group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can be substantially the same. The overlapping area of the second capacitance compensation plate 512 and the left half of the second group of the first type of third data fan-out lines 413a-2 in the orthographic projection of the substrate can be substantially the same; the overlapping area of the second capacitance compensation plate 512 and the right half of the second group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can gradually decrease along the second direction X.

[0139] FIG. 7E is another schematic view of the second capacitance compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7E, the second edge 512-2 of the second capacitance compensation plate 512 can be a zigzag shape extending along the second direction X. The second edge 512-2 can include a ninth slanted segment 5139 and a tenth slanted segment 5140 connected in sequence along the second direction X. The ninth slanted segment 5139 and the tenth slanted segment 5140 can connect to form a recessed portion recessed toward the first direction Y. For example, the overlapping area of the second capacitance compensation plate 512 and the first group of the first type of third data fan-out lines 413a-1 in the orthographic projection of the substrate can gradually decrease along the second direction X; the overlapping area of the second capacitance compensation plate 512 and the second group of the first type of third data fan-out lines 413a-2 in the orthographic projection of the substrate can gradually increase along the second direction X.

[0140] FIG. 8 is another partial schematic view of the first border region according to at least one embodiment of the present disclosure. FIG. 8 schematically shows partial traces of the second fan-out region B03 and the third fan-out region B05. FIG. 8 schematically shows a plurality of second data fan-out lines 412 and a plurality of third data fan-out lines 413 as a whole. In some examples, as shown in FIG. 8, the second capacitance compensation plate 512 located in the third fan-out region B05 can be electrically connected to the first power lead-out line 312 through a compensation connection line 45. The first edge of the second capacitance compensation plate 512 can extend along the second direction X and be electrically connected to the compensation connection line 45. The compensation connection line 45 can be located on the side of the second capacitance compensation plate 512 close to the substrate.

[0141] In some examples, the first power lead-out line 312 can be a single-layer trace located in the first source-drain metal layer. The second capacitance compensation plate 512 can be located in the first source-drain metal layer. The compensation connection line 45 can be located in the first gate metal layer or the second gate metal layer. The compensation connection line 45 can extend substantially along the second direction X and be connected to the second power connection portion 3122 of the first power lead-out line 312 to achieve electrical connection between the first power lead-out line 312 and the second capacitance compensation plate 512. The compensation connection line 45 can be located on the side of the plurality of control lead-out lines 61 close to the bending region B02. In other examples, the second capacitance compensation plate 512 can be located in the second source-drain metal layer and be connected to the first power lead-out line 312 located in the first source-drain metal layer through the compensation connection line located in the first gate metal layer or the second gate metal layer.

[0142] In other examples, the first power lead-out line 312 can be a single-layer trace located in the second source-drain metal layer. The second capacitance compensation plate 512 can be located in the first source-drain metal layer or the second source-drain metal layer and be connected to the first power lead-out line 312 through the compensation connection line located in the first gate metal layer or the second gate metal layer.

[0143] In some examples, the first power supply lead 312 can be a double-layered trace located in the first source-drain metal layer and the second source-drain metal layer. The second capacitance compensation electrode plate 512 can be located in the first source-drain metal layer or the second source-drain metal layer, and electrically connected to the sub-trace of the first power supply lead 312 located in the first source-drain metal layer or the sub-trace of the first power supply lead 312 located in the second source-drain metal layer through the compensation connection line located in the first gate metal layer or the second gate metal layer.

[0144] The present example can avoid the adverse effects caused by the floating of the second capacitance compensation electrode plate by electrically connecting the second capacitance compensation electrode plate to the first power supply lead. The remaining structures of the present example can refer to the descriptions of the foregoing embodiments, and thus will not be described here again.

[0145] FIG. 9 is another schematic view of the first bezel area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 9, the first data signal capacitance compensation structure can include the first capacitance compensation electrode plate 511 located in the first fan-out area B01 and the second capacitance compensation electrode plate 512 located in the third fan-out area B05. The shape of the first capacitance compensation electrode plate 511 in the orthographic projection of the substrate can be as shown in FIG. 5A, or can be as shown in one of FIGS. 7B to 7D. The shape of the second capacitance compensation electrode plate 512 in the orthographic projection of the substrate can be as shown in one of FIGS. 7B to 7E.

[0146] The present example can compensate the load of the first type of data line connected to the first type of data fan-out line by providing the first capacitance compensation electrode plate and the second capacitance compensation electrode plate, so that the signal load of the first type of data line and the signal load of the second type of data line are substantially the same, thereby improving the display defects caused by the difference in signal load of the data lines, and ensuring the display effect of the display area. The remaining structures of the present example can refer to the descriptions of the foregoing embodiments, and thus will not be described here again.

[0147] In some examples, by adjusting the length of the power supply body portion of the first power supply lead in the first direction in the second fan-out area, a space for arranging the capacitance compensation electrode plate in the second fan-out area can be left; or by changing the edge shape of the power supply body portion of the first power supply lead away from the side of the bending area in the second fan-out area to change the overlapping area of the power supply body portion and the plurality of second data fan-out lines, thereby realizing the differential capacitance compensation for the plurality of first type of second data fan-out lines.

[0148] In some examples, the first capacitance compensation electrode plate located in the first fan-out area can be connected to the second perimeter power supply line, or can be connected to other traces providing a constant voltage signal.

[0149] In some examples, the second capacitance compensation electrode plate located in the third fan-out area can be connected to the second power supply lead, or can be connected to other traces providing a constant voltage signal.

[0150] FIG. 10 is a schematic view of a partial cross section along the direction of P-P’ in FIG. 1. The film layer structure of the display substrate in this example is taken as an example of the film layer structure shown in FIG. 2B. In some examples, as shown in FIG. 1 and FIG. 10, the plurality of first-type data lines DL1 can be alternately arranged in the second source-drain metal layer and the third source-drain metal layer at the data wire-wound segments DL1-3 of the wire-wound region A3. Adjacent data wire-wound segments DL1-3 can be located in different film layers and do not overlap in the orthographic projection of the substrate. For example, the plurality of data wire-wound segments DL1-3 of the wire-wound region A3 can include a plurality of data wire-wound segments DL1-3a located in the second source-drain metal layer and a plurality of data wire-wound segments DL1-3b located in the third source-drain metal layer.

[0151] In some examples, the wire-wound region A3 can be provided with a second capacitance compensation structure. The second capacitance compensation structure can include third capacitance compensation plates 521 and 522 located in different conductive layers. The third capacitance compensation plate 521 can at least partially overlap at least one data wire-wound segment DL1-3a located in the second source-drain metal layer in the orthographic projection of the substrate, and the third capacitance compensation plate 522 can at least partially overlap at least one data wire-wound segment DL1-3b located in the third source-drain metal layer in the orthographic projection of the substrate. For example, the third capacitance compensation plate 521 can be located in the third gate metal layer, and the third capacitance compensation plate 522 can be located in the first source-drain metal layer. The third capacitance compensation plate 521 and the data wire-wound segment DL1-3a located in the second source-drain metal layer are separated by at least a seventh insulating layer 107, and the third capacitance compensation plate 522 and the data wire-wound segment DL1-3b located in the third source-drain metal layer are separated by at least an eighth insulating layer 108 and the seventh insulating layer 107.

[0152] In some examples, the third capacitance compensation plates 521 and 522 of the wire-wound region A3 can be configured to receive a constant voltage signal, for example, can be connected to a constant voltage signal line such as a first power supply line or a second power supply line. However, the present embodiment is not limited thereto. In other examples, a wire located in the third gate metal layer and overlapping at least one data wire-wound segment DL1-3a in the orthographic projection of the substrate within the wire-wound region A3 can serve as the third capacitance compensation plate 521, and a wire located in the first source-drain metal layer and overlapping at least one data wire-wound segment DL1-3b in the orthographic projection of the substrate within the wire-wound region A3 can serve as the third capacitance compensation plate 522.

[0153] In the present example, in the winding area, the third capacitor compensation electrode plate located in the third gate metal layer is overlapped with the data winding segment located in the second source-drain metal layer to realize signal load compensation of the first type of data line; and the third capacitor compensation electrode plate located in the first source-drain metal layer is overlapped with the data winding segment located in the third source-drain metal layer to realize signal load compensation of the first type of data line. The setting mode of the present example can ensure the signal compensation effect of different first type of data lines.

[0154] In some other examples, a first data signal capacitor compensation structure (for example, including at least one of the first capacitor compensation electrode plate and the second capacitor compensation electrode plate) can be arranged in the first frame area, and a second data signal capacitor compensation structure (for example, including the third capacitor compensation electrode plate) can be arranged in the winding area to realize signal load compensation of the first type of data line.

[0155] FIG. 11 is a schematic diagram of the partial structure of the region S1 in FIG. 1. In some examples, as shown in FIG. 1 and FIG. 11, the winding area A3 can be provided with at least one first compensation resistance 53, and at least one first type of data line DL1 can be connected in series with the at least one first compensation resistance 53. For example, the first compensation resistance 53 can be connected in series between the first data extension segment DL1-1 and the data winding segment DL1-3 of the first type of data line DL1. The first compensation resistance 53 can be a serpentine trace. For example, the trace extends in one direction for a distance, then bends and meanders in the opposite direction for a distance, bends and meanders again in the original direction, and so on, to form a serpentine trace. In some other examples, the first compensation resistance can be connected in series between the second data extension segment and the data winding segment of the first type of data line; or the data winding segment of the first type of data line can include two sub-segments, and the first compensation resistance can be connected in series between the two sub-segments. The present embodiment is not limited thereto.

[0156] The present example can increase the trace length of the first type of data line by arranging the first compensation resistance, thereby increasing the resistance and compensating the signal load of the first type of data line.

[0157] In some other examples, the resistance of the first type of data line can be increased by thinning the data winding segment of the first type of data line. Alternatively, the resistance can be increased by increasing the number of jumpers between the line segments of the first type of data line. Alternatively, the data winding segment of the first type of data line can be arranged in a conductive layer with a higher resistivity to increase the resistance of the first type of data line.

[0158] In some examples, the resistance of the first type of data line can be reduced by increasing the line width of the first type of data line. Alternatively, the resistance of the first type of data line can be reduced by arranging the first type of data line in two or more layers. Alternatively, the resistance of the first type of data line can be reduced by arranging the first type of data line in a conductive layer with a low resistivity.

[0159] The resistance compensation of the first type of data line in the present example can be determined according to the signal load difference between the first type of data line and the second type of data line. The signal load difference between the first type of data line and the second type of data line can be reduced by increasing or reducing the resistance of the first type of data line, thereby improving the display effect.

[0160] In some examples, the first bezel region can be provided with at least one second compensation resistance. The at least one first type of data fan-out line can be connected in series with the at least one second compensation resistance. For example, the second compensation resistance can be arranged in the first fan-out region and connected in series with the first type of first data fan-out line. However, the present embodiment is not limited thereto. For example, the second compensation resistance can be arranged in the second fan-out region or the third fan-out region. The resistance compensation of the first type of data fan-out line in the first bezel region can refer to the resistance compensation of the first type of data line, and thus will not be described herein. The present example improves the signal load difference between the first type of data line and the second type of data line by resistance compensation of the first type of data fan-out line, thereby improving the display effect.

[0161] FIG. 12 is another schematic view of a display substrate according to at least one embodiment of the present disclosure. FIG. 13 is a schematic view of the gate lines in FIG. 12. In some examples, as shown in FIGS. 12 and 13, the active area AA can be provided with a plurality of gate lines extending along the second direction X. The plurality of gate lines can include a plurality of first type of gate lines GL1 arranged along the aperture area A2, and a plurality of second type of gate lines GL2 arranged in the display area A1 and extending along the second direction X. The plurality of second type of gate lines GL2 can extend along the second direction X and arranged along the first direction Y. Along the first direction Y, the plurality of second type of gate lines GL2 can be divided into two groups, and the plurality of first type of gate lines GL1 can be arranged in the middle of the two groups of second type of gate lines GL2.

[0162] In some examples, since the aperture area A2 is not provided with sub-pixels, the gate lines originally passing through the aperture area A2 need to bypass the aperture area. In the present example, the gate lines that need to bypass the aperture area A2 are the first type of gate lines GL1, which can bypass the aperture area A2 by being arranged in the wire bypass area A3. Each gate line can be connected to a row of sub-pixels arranged along the second direction X. Since the aperture area A2 is not provided with sub-pixels, the number of sub-pixels connected by at least one first type of gate line GL1 can be less than the number of sub-pixels connected by at least one second type of gate line GL2. The signal load of at least one first type of gate line GL1 is less than the signal load of at least one second type of gate line GL2.

[0163] In some examples, as shown in FIG. 13, the first type of gate line GL1 can include a first gate extension GL1-1, a second gate extension GL1-2, and a gate winding segment GL1-3. One end of the gate winding segment GL1-3 is connected to the first gate extension GL1-1, and the other end is connected to the second gate extension GL1-2. The first gate extension GL1-1 and the second gate extension GL1-2 can be substantially straight line segments extending along the second direction X, and at least located in the display area A1. The gate winding segment GL1-3 can be substantially an arcuate segment or a polyline segment extending along the second direction X, and at least located in the winding area A3. For example, the first gate extension GL1-1, the second gate extension GL1-2, and the gate winding segment GL1-3 of the first type of gate line GL1 can be an integrated structure connected to each other; or the first gate extension GL1-1 and the second gate extension GL1-2 can be located in the same conductive layer, and the conductive layer where the gate winding segment GL1-3 is located can be different from the conductive layer where the first gate extension GL1-1 and the second gate extension GL1-2 are located. The present embodiment is not limited in this regard.

[0164] In some examples, the plurality of first type of gate lines GL1 can be divided into two groups. The gate winding segment GL1-3 in the first group of first type of gate lines can be located on one side of the hole area A2 along the first direction Y, for example, winding from the upper side of the hole area A2; and the gate winding segment GL1-3 in the second group of first type of gate lines can be located on the side of the hole area A2 along the opposite direction of the first direction Y, for example, winding from the lower side of the hole area A2. The number of first type of gate lines GL1 in the first group of first type of gate lines can be different from the number of first type of gate lines GL1 in the second group of first type of gate lines.

[0165] FIG. 14 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of the present example is described by taking an 8T1C structure as an example. In some examples, as shown in FIG. 14, the pixel circuit of the present example can include eight pixel transistors (i.e., a first pixel transistor T1 to an eighth pixel transistor T8) and a storage capacitor Cst. The first pixel transistor T1 can also be referred to as a first reset transistor, the second pixel transistor T2 can also be referred to as a compensation transistor, the third pixel transistor T3 can also be referred to as a drive transistor, the fourth pixel transistor T4 can also be referred to as a data writing transistor, the fifth pixel transistor T5 can also be referred to as a first light emitting control transistor, the sixth pixel transistor T6 can also be referred to as a second light emitting control transistor, the seventh pixel transistor T7 can also be referred to as a second reset transistor, and the eighth pixel transistor T8 can also be referred to as a third reset transistor. The light emitting element EL can include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0166] In some examples, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 can be first type transistors, for example, can be P-type transistors, and the second pixel transistor T2 can be a second type transistor, for example, can be an N-type transistor. However, the present embodiment is not limited thereto. For example, the plurality of pixel transistors of the pixel circuit can all be P-type transistors, or can all be N-type transistors.

[0167] In some examples, the first type transistors (for example, including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) of the pixel circuit can adopt low temperature poly-silicon thin film transistors, and the second type transistor (for example, including the second pixel transistor T2) of the pixel circuit can adopt oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-oxide (LTPS+Oxide) display substrate, which can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0168] In some examples, as shown in FIG. 14, the pixel circuit can be electrically connected with a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0169] In some examples, as shown in FIG. 14, the gate of the third pixel transistor T3 is electrically connected with the first node N1, the first electrode of the third pixel transistor T3 is electrically connected with the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected with the third node N3. The gate of the fourth pixel transistor T4 is electrically connected with the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected with the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected with the second node N2. The gate of the second pixel transistor T2 is electrically connected with the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected with the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected with the first node N1. The gate of the fifth pixel transistor T5 is electrically connected with the light-emitting control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected with the first power supply line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected with the second node N2. The gate of the sixth pixel transistor T6 is electrically connected with the light-emitting control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected with the fourth node N4. The gate of the first pixel transistor T1 is electrically connected with the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected with the third node N3. The first pixel transistor T1 can be configured to reset the third node N3. The gate of the seventh pixel transistor T7 is electrically connected with the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected with the fourth node N4. The seventh pixel transistor T7 can be configured to reset the fourth node N4. The gate of the eighth pixel transistor T8 is electrically connected with the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected with the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected with the second node N2. The eighth pixel transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected with the first node N1, and the second electrode of the storage capacitor Cst is electrically connected with the first power supply line PL1.

[0170] In the present example, the first node N1 is a connection point of the storage capacitor Cst, the second pixel transistor T2, and the third pixel transistor T3, the second node N2 is a connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8, and the third pixel transistor T3, the third node N3 is a connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2, and the sixth pixel transistor T6, and the fourth node N4 is a connection point of the sixth pixel transistor T6, the seventh pixel transistor T7, and the light-emitting element EL.

[0171] The working process of the pixel circuit shown in FIG. 14 is described below. Among them, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 of the pixel circuit are P-type transistors, and the second pixel transistor T2 is an N-type transistor.

[0172] In some examples, the working process of the pixel circuit in a frame display period can at least include: a first stage, a second stage, a third stage and a fourth stage.

[0173] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, so that the seventh pixel transistor T7 and the eighth pixel transistor T8 are turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, so that the second pixel transistor T2 is turned on. The eighth pixel transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. The seventh pixel transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected. The light emitting element EL does not emit light in this stage.

[0174] The second stage is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, and the first pixel transistor T1 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. The first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected. The light emitting element EL does not emit light in this stage.

[0175] In the third stage, referred to as a data writing stage or threshold compensation stage, the first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. In this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on. The second pixel transistor T2, the fourth pixel transistor T4 and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3 and the turned-on second pixel transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged to the storage capacitor Cst, so that the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third pixel transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned off.

[0176] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, so that the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, so that the second pixel transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1 and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, so that the fourth pixel transistor T4, the first pixel transistor T1, the seventh pixel transistor T7 and the eighth pixel transistor T8 are turned off. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light emitting element EL through the turned-on fifth pixel transistor T5, the third pixel transistor T3 and the sixth pixel transistor T6, so as to drive the light emitting element EL to emit light.

[0177] In the driving process of the pixel circuit, the driving current flowing through the third pixel transistor T3 is determined by the voltage difference between the gate and the first electrode thereof. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third pixel transistor T3 is: I=K×(Vgs-Vth) 2= K x [(VDD - Vdata + |Vth|) - Vth] 2 = K x [VDD - Vdata] 2 ;

[0178] wherein I is a driving current flowing through the third pixel transistor T3, that is, a driving current for driving the light emitting element, K is a constant, Vgs is a voltage difference between the gate and the first electrode of the third pixel transistor T3, Vth is a threshold voltage of the third pixel transistor T3, Vdata is a data voltage output by the data line DL, and VDD is a first voltage signal output by the first power supply line PL1.

[0179] It can be seen from the above formula that the current flowing through the light emitting element is independent of the threshold voltage of the third pixel transistor T3. Therefore, the pixel circuit of the embodiment can compensate for the threshold voltage of the third pixel transistor T3. Moreover, the pixel circuit provided by the embodiment can improve the display effect of the light emitting element and improve the display effect of the light emitting element.

[0180] In some examples, the plurality of gate lines of the display substrate can include a plurality of first scan lines, a plurality of second scan lines, a plurality of first reset control lines, a plurality of second reset control lines, and a plurality of light emitting control lines. The plurality of first type gate lines can include first scan lines (may also be referred to as first type first scan lines) that need to bypass the aperture area, second scan lines (may also be referred to as first type second scan lines) that need to bypass the aperture area, first reset control lines (may also be referred to as first type first reset control lines) that need to bypass the aperture area, second reset control lines (may also be referred to as first type second reset control lines) that need to bypass the aperture area, and light emitting control lines (may also be referred to as first type light emitting control lines) that need to bypass the aperture area.

[0181] In some examples, a first type gate line (such as denoted as first type gate line A) that extends through the center of the aperture area and a first type gate line (such as denoted as first type gate line B) that extends away from the edge of the aperture area are taken as examples for compensation simulation comparison. In the compensation simulation process, the first type gate lines A and B are respectively capacitively compensated, so that the product of the resistance and the capacitance of the part of the first type gate line in the wire wrapping area is substantially the same as the product of the resistance and the capacitance of the corresponding part of the second type gate line. According to the compensation simulation results, the first type first scan line is most affected by the wire wrapping and needs to be highlighted for capacitive compensation. The first type first scan line can be capacitively compensated alone, or all first type gate lines can be capacitively compensated. The embodiment is not limited thereto.

[0182] FIG. 15 is a schematic diagram of the arrangement of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, the frame region can be provided with a plurality of gate driving circuits, which can include two first scan driving circuits 21a and 21b, two second scan driving circuits 22a and 22b, two first reset driving circuits 23a and 23b, two second reset driving circuits 24a and 24b, and two light emitting driving circuits 25a and 25b. The first scan driving circuits 21a and 21b can be configured to provide a first scan signal to the plurality of pixel circuits of the display region Al. The second scan driving circuits 22a and 22b can be configured to provide a second scan signal to the plurality of pixel circuits of the display region Al. The light emitting driving circuits 25a and 25b can be configured to provide a light emitting control signal to the plurality of pixel circuits of the display region Al. The first reset driving circuits 23a and 23b can be configured to provide a first reset control signal to the plurality of pixel circuits of the display region Al. The second reset driving circuits 24a and 24b can be configured to provide a second reset control signal to the plurality of pixel circuits of the display region Al. In the present example, the first scan signal, the second scan signal, the light emitting control signal, the first reset control signal, and the second reset control signal can all be double-sided driving, which improves the signal load difference between the first type of gate lines and the second type of gate lines by increasing the driving capability. However, the present embodiment is not limited thereto. In other examples, the second scan signal and the second reset control signal can be double-sided driving, and the first scan signal, the light emitting control signal, and the first reset control signal can be single-sided driving.

[0183] In some examples, the display region A1 includes M rows of pixel circuits, where M is a positive integer. The rows of pixel circuits within the display region A1 can be sequentially labeled as the 1st row to the Mth row along a direction from the fourth border region B4 to the first border region B1. The plurality of gate driving circuits can include a first group of gate driving circuits located at the second border region B2 and a second group of gate driving circuits located at the third border region B3. The first group of gate driving circuits can include the following five gate driving circuits: the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light emitting driving circuit 25a. For example, within the second border region B2, the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light emitting driving circuit 25a can be sequentially arranged along a direction away from the display region A1. The second group of gate driving circuits can include the following five gate driving circuits: the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light emitting driving circuit 25b. For example, within the third border region B3, the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light emitting driving circuit 25b can be sequentially arranged along a direction away from the display region A1. However, the present embodiment is not limited thereto.

[0184] In some examples, the first scan driving circuits 21a and 21b can each include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(M)). Each first scan driving unit can be configured to provide a first scan signal to one row of pixel circuits of the display region A1. For example, the first first scan driving unit GP(1) can be configured to provide a first scan signal to the 1st row of pixel circuits of the display region A1; the Mth first scan driving unit GP(M) can be configured to provide a first scan signal to the Mth row of pixel circuits of the display region A1.

[0185] In some examples, the second scan driving circuits 22a and 22b can each include a plurality of cascaded second scan driving units (e.g., including GN(1) to GN(M)). Each second scan driving unit can be configured to provide a second scan signal to one row of pixel circuits of the display region A1. However, the present embodiment is not limited thereto. In other examples, each second scan driving unit can be configured to provide a second scan signal to two adjacent rows of pixel circuits of the display region A1.

[0186] In some examples, the light emitting driving circuits 25a and 25b can each include a plurality of cascaded light emitting driving units (e.g., including EM(1) to EM(M)). Each stage of light emitting driving unit can be configured to provide a light emitting control signal to one row of pixel circuits of the display area A1. However, the present embodiment is not limited thereto. In other examples, each stage of light emitting driving unit can be configured to provide a light emitting control signal to two adjacent rows of pixel circuits of the display area A1.

[0187] In some examples, the first reset driving circuits 23a and 23b can each include a plurality of cascaded first reset driving units (e.g., including RP(1) to RP(M)). Each stage of first reset driving unit can be configured to provide a first reset control signal to one row of pixel circuits of the display area A1. However, the present embodiment is not limited thereto. In other examples, each stage of first reset driving unit can be configured to provide a first reset control signal to two adjacent rows of pixel circuits of the display area A1.

[0188] In some examples, the second reset driving circuits 24a and 24b can each include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(M)). Each stage of second reset driving unit can be configured to provide a second reset control signal to one row of pixel circuits of the display area A1. However, the present embodiment is not limited thereto. In other examples, each stage of second reset driving unit can be configured to provide a second reset control signal to two adjacent rows of pixel circuits of the display area A1.

[0189] By employing the double-side driving design, the present example can increase the driving capability of the gate signal and improve the display defects caused by the signal load difference between the first type of gate line and the second type of gate line.

[0190] FIG. 16 is a schematic view of a partial cross section along the direction of Q-Q' in FIG. 13. The film layer structure of the display substrate in the present example is taken as an example of the film layer structure shown in FIG. 2A. In some examples, as shown in FIG. 16, the wire winding area A3 can include: a first wire 601 located at the first gate metal layer, a second wire 602 located at the second gate metal layer, a third wire 603 located at the first source-drain metal layer, and a fourth wire 604 located at the second source-drain metal layer. The first wire 601 and the third wire 603 can at least partially overlap in the orthographic projection of the substrate. The first wire 601 can include: a gate wire segment of the first type of second scan line. For example, the gate wire segment of the first type of second scan line and the first gate extension segment and the second gate extension segment can be located at different conductive layers, for example, the first gate extension segment and the second gate extension segment can be located at the third gate metal layer. The third wire 603 can serve as a first gate signal capacitance compensation electrode plate, and can capacitively compensate the first type of second scan line by being arranged to overlap the gate wire segment of the first type of second scan line in the orthographic projection of the substrate. The third wire 603 can be a wire that is separately arranged and receives a constant voltage signal; or, the third wire 603 can be a data wire segment of the first type of data line.

[0191] In some examples, the second wire 602 and the fourth wire 604 can at least partially overlap in the orthographic projection of the substrate. The second wire 602 can include: a gate wire segment of the first type of first scan line. The fourth wire 604 can capacitively compensate the first type of first scan line by being arranged to overlap the gate wire segment of the first type of first scan line in the orthographic projection of the substrate. The fourth wire 604 can be a wire that is separately arranged and receives a constant voltage signal; or, the fourth wire 604 can be a data wire segment of the first type of data line.

[0192] The present example can capacitively compensate the first type of second scan line by arranging the first gate signal capacitance compensation electrode plate at the first source-drain metal layer.

[0193] FIG. 17 is another schematic view of a partial cross section along the direction of Q-Q' in FIG. 13. In some examples, as shown in FIG. 17, the first gate signal capacitance compensation electrode plate 541 of the wire winding area A3 can be located at the third gate metal layer. The first gate signal capacitance compensation electrode plate 541 can at least partially overlap at least one first wire 601 located at the first gate metal layer in the orthographic projection of the substrate. For example, the first wire 601 can at least include: a gate wire segment of the first type of second scan line. The first gate signal capacitance compensation electrode plate 541 can be configured to receive a constant voltage signal, for example, connected to a first voltage signal.

[0194] The present example can capacitively compensate the first type of second scan line by arranging the first gate signal capacitance compensation electrode plate at the third gate metal layer. The remaining structures of the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be described again.

[0195] In some examples, the first gate signal capacitance compensation plate 541 can be located in the bottom shielding metal layer. The first gate signal capacitance compensation plate 541 can be configured to receive a constant voltage signal, for example, connected to the first voltage signal.

[0196] FIG. 18 is another partial cross-sectional view of FIG. 13 along the direction of Q-Q'. In some examples, as shown in FIG. 18, the display substrate can include, in sequence, a bottom shielding metal layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer on the substrate. A buffer layer 110 is disposed between the bottom shielding metal layer and the first semiconductor layer. The remaining film layer structure of the display substrate of the present example can refer to the embodiment shown in FIG. 2A.

[0197] In some examples, as shown in FIG. 18, the display substrate can include a second gate signal capacitance compensation plate 542 located in the wire winding area A3, and the second gate signal capacitance compensation plate 542 in the substrate has a projection that at least partially overlaps with the projection of the plurality of first wires 601 (for example, including the gate wire segments of the plurality of first type second scan lines) in the first gate metal layer. The second gate signal capacitance compensation plate 542 can be located in the bottom shielding metal layer and can be configured to receive a constant voltage signal, for example, connected to the first voltage signal.

[0198] The present example can compensate the first type second scan lines by disposing the second gate signal capacitance compensation plate in the bottom shielding metal layer. The remaining structure of the present example can refer to the description of the foregoing embodiments, and thus will not be described again.

[0199] FIG. 19 is another partial cross-sectional view of FIG. 13 along the direction of Q-Q'. In some examples, the second gate signal capacitance compensation plate 542 located in the bottom shielding metal layer can have a projection in the substrate that at least partially overlaps with the projection of the plurality of first wires 601 located in the first gate metal layer and the plurality of first wires 602 located in the second gate metal layer in the substrate. For example, the second gate signal capacitance compensation plate 542 located in the bottom shielding metal layer can cover the projection of the plurality of first wires 601 located in the first gate metal layer and the plurality of first wires 602 located in the second gate metal layer in the substrate. For example, the second gate signal capacitance compensation plate 542 in the substrate can have a circular ring shape.

[0200] In some examples, the plurality of first wires 601 can include: a plurality of gate winding segments of the first type of second scan lines, a plurality of gate winding segments of the first type of first reset control lines; and the plurality of second wires 602 can include: a plurality of gate winding segments of the first type of first scan lines, a plurality of gate winding segments of the first type of second reset control lines, and a plurality of gate winding segments of the first type of light-emitting control lines. The present embodiment is not limited in this regard.

[0201] The present example can compensate the first type of gate lines corresponding to the wires of the first gate metal layer and the second gate metal layer in the winding area by setting the second gate signal capacitance compensation plate in the bottom shielding metal layer. The present example can prevent the fine wires of the bottom shielding metal layer from affecting the wires of the upper conductive layer by setting the large-area second gate metal capacitance compensation plate. The remaining structures of the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be described again.

[0202] The present embodiment also provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of gate lines, and a gate signal capacitance compensation structure. The substrate includes an effective area and a frame area located around the effective area, the effective area includes: a hole area, a display area located around the hole area, and a winding area located between the hole area and the display area. The plurality of sub-pixels are located in the display area and on one side of the substrate. The plurality of gate lines are located in the effective area, the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines at least include: a plurality of first type of gate lines arranged to wind along the hole area. The gate signal capacitance compensation structure is located in the winding area, at least one insulating layer is arranged between the gate signal capacitance compensation structure and the plurality of gate lines; the orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps the orthographic projection of at least one of the plurality of first type of gate lines on the substrate.

[0203] The display substrate provided by the present embodiment can compensate the first type of gate lines by setting the gate signal capacitance compensation structure in the winding area, so as to compensate the signal load of the first type of data lines connected by the first type of data fan-out lines, thereby improving the display uniformity of the display area.

[0204] In some example embodiments, the plurality of first-type gate lines at least include a plurality of first-type first scan lines and a plurality of first-type second scan lines, the plurality of first-type first scan lines are configured to provide first scan signals to data writing transistors of pixel circuits of the plurality of sub-pixels, the plurality of first-type second scan lines are configured to provide second scan signals to compensation transistors of the pixel circuits of the plurality of sub-pixels, and the data writing transistors and the compensation transistors are of different transistor types. The gate signal capacitance compensation structure at least includes a first gate signal capacitance compensation plate, a projection of the first gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of at least one first-type second scan line on the substrate, and the first gate signal capacitance compensation plate is located on a side of the plurality of first-type second scan lines away from the substrate. In some examples, in a direction perpendicular to the display substrate, an effective area of the display substrate at least includes a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source-drain metal layer arranged in sequence on the substrate. The first-type second scan line is located on the first gate metal layer in the wire winding area, and the first gate signal capacitance compensation plate is located on the third gate metal layer or the first source-drain metal layer.

[0205] In some example embodiments, in a direction perpendicular to the display substrate, an effective area of the display substrate at least includes a bottom shielding metal layer, a first gate metal layer, and a second gate metal layer arranged in sequence on the substrate. The gate signal capacitance compensation structure includes a second gate signal capacitance compensation plate located on the bottom shielding metal layer, a projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of a plurality of first-type gate lines located on the first gate metal layer on the substrate, or a projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of a plurality of first-type gate lines located on the first gate metal layer and the second gate metal layer on the substrate.

[0206] The remaining description of the display substrate of the present example can refer to the description of the foregoing examples, and thus will not be repeated here.

[0207] In other examples, the gate signal capacitance compensation structure can be arranged in a frame area (e.g., including at least one of the second frame area and the third frame area), and the gate signal capacitance compensation structure is arranged to overlap with a peripheral wire connected to the first-type gate lines in the frame area, so as to achieve capacitance compensation for the first-type gate lines.

[0208] FIG. 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 20, the display panel 910 can be an OLED display panel. The display device 91 can be any product or component with display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like. However, the present embodiment is not limited thereto.

[0209] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. The illustrative representation of the above terms in the present specification does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the features of different embodiments or examples described in the present specification and the features of different embodiments or examples, without contradiction.

[0210] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are exemplary, and are not to be construed as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.​​​​

Claims

1. A display substrate comprising: a substrate comprising an effective area and a first bezel area located at least one side of the effective area; the effective area comprising a hole region and a display region located around the hole region; the first bezel area comprising a signal access region and a fan-out region located between the signal access region and the display region; a plurality of sub-pixels located in the display region and at one side of the substrate; a plurality of data lines located in the effective area, the plurality of data lines being electrically connected with the plurality of sub-pixels; the plurality of data lines comprising at least a plurality of first type data lines wound along the hole region; a plurality of data fan-out lines located in the fan-out region, the plurality of data fan-out lines comprising at least a plurality of first type data fan-out lines, the plurality of first type data fan-out lines being electrically connected with the plurality of first type data lines; a first data signal capacitance compensation structure located in the fan-out region and at a side of the plurality of data fan-out lines away from the substrate, at least one insulating layer being provided between the first data signal capacitance compensation structure and the plurality of data fan-out lines; a projection of the first data signal capacitance compensation structure on the substrate at least partially overlaps with a projection of at least one of the plurality of first type data fan-out lines on the substrate. 2.The display substrate of claim 1, wherein, the plurality of data lines further comprising a plurality of second type data lines located in the display region and extending along a first direction; the plurality of data fan-out lines further comprising a plurality of second type data fan-out lines, the plurality of second type data fan-out lines being electrically connected with the plurality of second type data lines; a number of sub-pixels connected with at least one of the plurality of first type data lines is less than a number of sub-pixels connected with at least one of the plurality of second type data lines. 3.The display substrate of claim 1, wherein, areas of overlap between at least two of the plurality of first type data fan-out lines and a projection of the first data signal capacitance compensation structure on the substrate are different. 4.The display substrate of claim 1, wherein, the first bezel area further comprising a bending region, the fan-out region comprising a first fan-out region located between the display region and the bending region; the plurality of first type data fan-out lines comprising a plurality of first type first data fan-out lines located in the first fan-out region; the first data signal capacitance compensation structure comprising a first capacitance compensation plate located in the first fan-out region, a projection of the first capacitance compensation plate on the substrate at least partially overlaps with a projection of at least one of the plurality of first type first data fan-out lines on the substrate. 5.The display substrate of claim 4, further comprising: a first peripheral power supply line located in the first fan-out region; the first capacitance compensation plate is located at a side of the first peripheral power supply line away from the display region and is electrically connected with the first peripheral power supply line. 6.The display substrate of claim 5, wherein, the first capacitance compensation plate and the first peripheral power supply line are an integrated structure connected with each other. 7.The display substrate of claim 4, wherein, a projection of the first capacitance compensation plate on the substrate is an asymmetric shape. 8.The display substrate according to any one of claims 1 to 7, wherein the first bezel area further comprising a bending region and a circuit arrangement region located between the bending region and the signal access region; The fan-out area includes a first fan-out area between the display area and the bending area, a second fan-out area between the bending area and the circuit arrangement area, and a third fan-out area between the circuit arrangement area and the signal access area; The plurality of first-type data fan-out lines includes a plurality of third-type first data fan-out lines in the third fan-out area; The first data signal capacitor compensation structure includes a second capacitor compensation plate in the third fan-out area, and a projection of the second capacitor compensation plate on the substrate at least partially overlaps at least one first-type third data fan-out line in the plurality of first-type third data fan-out lines on a projection of the substrate. 9.The display substrate of claim 8, further comprising: A first peripheral power supply line in the first fan-out area, and a first power supply lead-out line at least in the second fan-out area and the third fan-out area; The first power supply lead-out line is connected with the first peripheral power supply line, and the second capacitor compensation plate is electrically connected with the first power supply lead-out line through a compensation connection line. 10.The display substrate of claim 8, wherein, The projection of the second capacitor compensation plate on the substrate has a first edge and a second edge, the second edge is located on a side of the first edge away from the bending area in a first direction, the first edge is a straight line extending in a second direction, and the second edge is a broken line extending in the second direction, and the second direction intersects the first direction. 11.The display substrate of claim 1, wherein, The effective area further includes a winding area between the hole area and the display area; The display substrate further includes at least one first compensation resistor in the winding area, and at least one first-type data line in the plurality of first-type data lines is connected in series with the at least one first compensation resistor. 12.The display substrate of claim 1, wherein, The effective area further includes a winding area between the hole area and the display area; The display substrate further includes a second data signal capacitor compensation structure in the winding area, at least one insulating layer is arranged between the second data signal capacitor compensation structure and the plurality of first-type data lines, and a projection of the second data signal capacitor compensation structure on the substrate partially overlaps at least one first-type data line in the plurality of first-type data lines on a projection of the substrate. 13.The display substrate of claim 12, wherein, The second data signal capacitor compensation structure includes at least one third capacitor compensation plate, a projection of the third capacitor compensation plate on the substrate partially overlaps at least one first-type data line in the plurality of first-type data lines on a projection of the substrate, and the third capacitor compensation plate is located on a side of the at least one first-type data line close to the substrate.

14. The display substrate of claim 1, further comprising: a plurality of gate lines in the effective area, the plurality of gate lines are electrically connected with the plurality of sub-pixels, and the plurality of gate lines at least include a plurality of first-type gate lines arranged in a winding manner along the hole area. A gate signal capacitance compensation structure is located in the effective area, and at least one insulating layer is arranged between the gate signal capacitance compensation structure and the plurality of gate lines; a projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with a projection of at least one first-type gate line on the substrate. 15.The display substrate of claim 14, wherein, The first frame region is located on one side of the effective area along a first direction, and the substrate further includes: a second frame region and a third frame region located on both sides of the effective area along a second direction; the second direction intersects the first direction; The display substrate further includes: a plurality of gate driving circuits; The at least one first-type gate line is connected with two gate driving circuits that transmit the same signal, and one of the two gate driving circuits is located in the second frame region, and the other is located in the third frame region.

16. A display device, comprising the display substrate according to any one of claims 1 to 15.

17. A display substrate, comprising: A substrate includes an effective area and a frame region located around the effective area, the effective area includes: a hole region, a display region located around the hole region, and a winding region located between the hole region and the display region; A plurality of sub-pixels are located in the display region and on one side of the substrate; A plurality of gate lines are located in the effective area, the plurality of gate lines are electrically connected with the plurality of sub-pixels, and the plurality of gate lines at least include: a plurality of first-type gate lines arranged along the winding of the hole region; A gate signal capacitance compensation structure is located in the winding region, and at least one insulating layer is arranged between the gate signal capacitance compensation structure and the plurality of gate lines; a projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with a projection of at least one first-type gate line on the substrate. 18.The display substrate of claim 17, wherein, The plurality of first-type gate lines at least include: a plurality of first-type first scanning lines and a plurality of first-type second scanning lines, the plurality of first-type first scanning lines are configured to provide first scanning signals to data writing transistors of pixel circuits of the plurality of sub-pixels; the plurality of first-type second scanning lines are configured to provide second scanning signals to compensation transistors of the pixel circuits of the plurality of sub-pixels; the data writing transistors and the compensation transistors are different in transistor type; The gate signal capacitance compensation structure at least includes: a first gate signal capacitance compensation plate, a projection of the first gate signal capacitance compensation plate on the substrate at least partially overlaps with a projection of at least one first-type second scanning line on the substrate; the first gate signal capacitance compensation plate is located on a side of the plurality of first-type second scanning lines away from the substrate.

19. The display substrate of claim 18, wherein, In a direction perpendicular to the display substrate, the effective area of the display substrate at least includes: a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source-drain metal layer arranged in sequence on the substrate; The first-type second scanning line is located in the first gate metal layer in the winding region, and the first gate signal capacitance compensation plate is located in the third gate metal layer or the first source-drain metal layer. 20.The display substrate of claim 17, wherein, In a direction perpendicular to the display substrate, an effective area of the display substrate at least includes: a bottom shielding metal layer, a first gate metal layer and a second gate metal layer which are sequentially arranged on the substrate; The gate signal capacitance compensation structure includes: a second gate signal capacitance compensation pole plate located at the bottom shielding metal layer, a projection of the second gate signal capacitance compensation pole plate on the substrate at least partially overlaps with a projection of a plurality of first type gate lines located at the first gate metal layer on the substrate; or, a projection of the second gate signal capacitance compensation pole plate on the substrate at least partially overlaps with a projection of a plurality of first type gate lines located at the first gate metal layer and the second gate metal layer on the substrate.

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