Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises: a substrate (11); an active layer (C1), located on one side of the substrate (11) and comprising a plurality of active patterns (C11); a first insulating layer, located on the side of the active layer (C1) away from the substrate (11) and having a plurality of first via holes (K3); a first metal layer (M1), located on the side of the first insulating layer away from the active layer (C1) and comprising a plurality of first signal lines (M11) extending in a first direction (X), wherein at least one first signal line (M11) among the plurality of first signal lines (M11) is electrically connected to the corresponding active pattern (C11) by means of the corresponding first via hole (K3); and a plurality of first shielding parts (R1), located on the side of the first metal layer (M1) away from the first insulating layer, wherein the orthographic projection of at least one first shielding part (R1) among the plurality of first shielding parts (R1) on the substrate (11) covers the orthographic projection of the corresponding first via hole (K3) on the substrate (11).

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a display panel and a display device. Background Art

[0002] Virtual reality technology seamlessly integrates real-world and virtual-world information. Compared to conventional display products, the most notable feature of VR display products is their ultra-high resolution. Liquid crystal display (LCD) technology is currently the best choice for achieving ultra-high PPI. This is because the LCD display structure uses only a single switching transistor (TFT) in the pixel area, making it highly suitable for achieving high resolution (pixels per inch, PPI). Existing VR display products have increased their PPI from 773 to 1200, and even 1400.

[0003] However, existing VR display products have light leakage at the via holes connecting the active layer and the data lines, resulting in a decrease in contrast.

[0004] Summary of the Invention

[0005] The present disclosure provides a display panel and a display device. The display panel includes:

[0006] substrate;

[0007] an active layer, located on one side of the substrate, comprising a plurality of active patterns;

[0008] a first insulating layer, located on a side of the active layer facing away from the substrate, and having a plurality of first via holes;

[0009] a first metal layer, located on a side of the first insulating layer away from the active layer, comprising a plurality of first signal lines extending along a first direction; at least one first signal line among the plurality of first signal lines is electrically connected to the active pattern through the first via hole;

[0010] A plurality of first blocking portions are located on a side of the first metal layer facing away from the first insulating layer, and an orthographic projection of at least one of the plurality of first blocking portions on the substrate covers an orthographic projection of the first via on the substrate.

[0011] In a possible implementation manner, the first shielding portion includes: a first sub-shielding portion, and a second sub-shielding portion located outside the first sub-shielding portion;

[0012] The orthographic projection of the first sub-blocking portion on the substrate coincides with the orthographic projection of the first via hole on the substrate; the orthographic projection of the second sub-blocking portion on the substrate does not overlap with the orthographic projection of the first via hole on the substrate.

[0013] In a possible implementation, the second shielding portion includes: a first sub-portion extending along the first direction, and a second sub-portion extending along the second direction;

[0014] The width of the first sub-portion in the second direction is equal to the width of the second sub-portion in the first direction.

[0015] In a possible implementation manner, a minimum distance between an outer edge of the second sub-shielding portion and an outer edge of the first sub-shielding portion is in a range of 1 μm to 3 μm.

[0016] In a possible implementation, the display panel further includes a first conductive layer located on a side of the first metal layer facing away from the first insulating layer; and a second insulating layer located between the first conductive layer and the active layer; the second insulating layer has a plurality of second via holes;

[0017] The first conductive layer includes: a plurality of first electrodes; at least one first electrode among the plurality of first electrodes is electrically connected to the active layer through the second via hole;

[0018] The orthographic projection of the first shielding portion on the substrate has an overlapping area with the orthographic projection of the first electrode on the substrate.

[0019] In one possible embodiment, the display panel includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of pixel light-transmitting area rows extending along a second direction and arranged along the first direction; at least one of the plurality of pixel light-transmitting area rows including: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; a light wavelength range emitted by the third pixel light-transmitting area is smaller than the light wavelength range emitted by the first pixel light-transmitting area, and smaller than the light wavelength range emitted by the second pixel light-transmitting area;

[0020] The display panel further includes a second blocking portion located on one side of the substrate, wherein the orthographic projection of the second blocking portion on the substrate is located in a gap between orthographic projections of at least partially adjacent two third pixel light-transmitting areas in the first direction.

[0021] In a possible implementation, the display panel further includes: a spacer and a third shielding portion; the orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the spacer on the substrate;

[0022] The orthographic projection of the third blocking portion on the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas on the substrate in the second direction; the orthographic projections of the second blocking portion and the third blocking portion on the substrate are alternately distributed along the second direction.

[0023] In a possible implementation manner, the first shielding portion, the second shielding portion, and the third shielding portion are formed in the same layer and made of the same material.

[0024] In a possible implementation, the display panel includes: an array substrate and an opposite substrate disposed opposite to each other; the opposite substrate has a black matrix layer;

[0025] The plurality of first shielding portions are located in the black matrix layer.

[0026] The present disclosure also provides a display panel, comprising:

[0027] substrate;

[0028] an active layer, located on one side of the substrate, comprising a plurality of active patterns;

[0029] a first insulating layer, located on a side of the active layer facing away from the substrate, and having a plurality of first via holes;

[0030] a first metal layer, located on a side of the first insulating layer away from the active layer, comprising a plurality of first signal lines extending along a first direction; at least one first signal line among the plurality of first signal lines is electrically connected to the active pattern through the first via hole;

[0031] The first signal line has a first symmetry axis extending along the first direction, and the first signal line is symmetrical about the first symmetry axis; at least part of the first via hole is located in the central area of ​​the orthographic projection of the substrate and does not coincide with the first symmetry axis.

[0032] In one possible embodiment, the display panel includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of pixel light-transmitting area rows extending along a second direction and arranged along the first direction; at least one of the plurality of pixel light-transmitting area rows includes: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; a light wavelength range emitted by the second pixel light-transmitting area is smaller than the light wavelength range emitted by the first pixel light-transmitting area, and larger than the light wavelength range of the third pixel light-transmitting area;

[0033] The multiple first signal lines include: a first sub-signal line adjacent to the second pixel light-transmitting area; the first via connected to the first sub-signal line is located in the central area of ​​the substrate's orthographic projection and does not coincide with the first symmetry axis of the first sub-signal line.

[0034] In a possible implementation, the first via hole connected to the first sub-signal line is located in the central area of ​​the orthographic projection of the substrate, and is located on a side of the first symmetry axis away from the second pixel light-transmitting area.

[0035] In a possible implementation manner, the plurality of first signal lines further include: a second sub-signal line;

[0036] The first via hole connected to the second sub-signal line is located in a central area of ​​an orthographic projection of the substrate and coincides with the first symmetry axis of the second sub-signal line.

[0037] In a possible implementation manner, the distance between the first via hole connected to the first sub-signal line and the third pixel light-transmitting area in the second direction, which is projected on the substrate, is in a range of 1 μm to 3 μm.

[0038] In a possible implementation manner, the first via hole includes: a hole bottom, and a hole wall connected to the hole bottom;

[0039] A portion of an outer edge on one side of the first signal line is located at the bottom of the hole, and a portion of an outer edge on the other side of the first signal line is located around the via hole.

[0040] In a possible implementation manner, an outer edge of the first signal line is straight at the first via hole.

[0041] In a possible implementation, the first via connected to the Nth first signal line is located in the central area of ​​the orthographic projection of the substrate, on the side of the first symmetry axis of the Nth first signal line facing the N-1th first signal line.

[0042] In a possible implementation, the first via connected to the Nth first signal line is located in the central area of ​​the orthographic projection of the substrate, on the side of the first symmetry axis of the Nth first signal line facing the (N+1)th first signal line.

[0043] In a possible implementation, the display panel further includes: a fourth shielding portion, and a first shielding strip extending along the second direction;

[0044] The first shielding strip is an orthographic projection of the substrate, covering the orthographic projection of the first signal line on the substrate, and covering the part of the orthographic projection of the first via on the substrate; the fourth shielding portion is an orthographic projection of the substrate, covering the part of the first via that exceeds the first shielding strip, and covering the peripheral distribution of the first via.

[0045] In a possible implementation manner, a distance between an outer edge of the fourth shielding portion and an outer edge of the first via hole is in a range of 1 μm to 3 μm.

[0046] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram showing that a data line is elliptical in shape at a via hole;

[0048] FIG2 is a schematic diagram showing the decomposition of polarization states when light passes through the lower polarizer and reaches the boundary of the data line ellipse;

[0049] FIG3 is a schematic diagram of the polarization state decomposition of light after it passes through the elliptical boundary of the data line;

[0050] FIG4 is a schematic diagram of a portion of the film layers of a display panel;

[0051] FIG5A is a schematic diagram of a display panel;

[0052] FIG5B is a schematic diagram of a single film layer of the third metal layer in FIG5A ;

[0053] FIG5C is a schematic diagram of a single film layer of the active layer in FIG5A;

[0054] FIG5D is a schematic diagram of a single film layer of the second metal layer in FIG5A ;

[0055] FIG5E is a schematic diagram of a single film layer of the first metal layer in FIG5A ;

[0056] FIG5F is a schematic diagram of a single film layer of the second conductive layer in FIG5A ;

[0057] FIG5G is a schematic diagram of a single film layer of the first conductive layer in FIG5A ;

[0058] FIG6 is a schematic cross-sectional view along the dotted line A1A2 in FIG2 ;

[0059] FIG7 is a schematic diagram of a black matrix according to an embodiment of the present disclosure;

[0060] FIG8 is a second schematic diagram of a portion of the film layers of a display panel;

[0061] FIG9A is a third schematic diagram of a portion of the film layers of a display panel;

[0062] FIG9B is a fourth schematic diagram of a portion of the film layers of a display panel;

[0063] FIG9C is a schematic cross-sectional view taken along dotted line GH in FIG9A ;

[0064] FIG10 is a fifth schematic diagram of a portion of the film layers of a display panel. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0067] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0068] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0069] The contrast ratio of LCD products is related to L255 brightness and L0 brightness, and L0 light leakage is a major factor affecting contrast ratio (CR). Microscopic observation of the image at grayscale 0 reveals light leakage at the via K (also known as the interlayer dielectric (ILD) hole) connecting the active layer to data line 01. This is because data line 01 overlaps the wall of via K. During the etching process, the data line trace shape follows the elliptical wall of via K, resulting in the data line 01 trace at via K taking on an elliptical shape, as shown in Figure 1.

[0070] As shown in Figures 2 and 3, Figure 2 is a schematic diagram of the polarization state decomposition when the light passes through the lower polarizer and reaches the elliptical boundary of the data line, and Figure 3 is a schematic diagram of the polarization state decomposition of the light after passing the elliptical boundary of the data line. O1 represents the transmission axis direction of the front polarizer (i.e., the lower polarizer), and O2 represents the transmission axis direction of the rear polarizer (i.e., the upper polarizer). When the light passes through the lower polarizer of the LCD, the light is converted into linearly polarized light, and its magnitude is Ex; when the linearly polarized light passes through the elliptical data line 01, due to the diffraction effect, the propagation direction is deflected by an angle of β. During the deflection process, the S light component maintains its original direction unchanged, but the P light component will undergo an angular deflection (become P'). Therefore, after passing through the data line 01, the polarization direction of the light is deflected, so that some light components can pass through the upper polarizer, and its magnitude is E y =E z *cosα*sinα*(1-cosβ), meaning there will be light leakage at grayscale L0, resulting in low contrast. To address this issue, increasing the overall width of the black matrix is ​​often used. However, this significantly reduces the overall pixel opening and also creates the problem of limited exposure to the black matrix openings (spaces).

[0071] In view of this, an embodiment of the present disclosure provides a display panel, as shown in conjunction with FIG. 4 , FIG. 5A to FIG. 5G , and FIG. 6 , wherein FIG. 4 is a schematic diagram of a portion of a film layer of the display panel, FIG. 5A is one of the schematic diagrams of the display panel, and FIG. 6 is a schematic cross-sectional diagram along dotted line A1A2 in FIG. 5A . The display panel includes:

[0072] substrate 11;

[0073] The active layer C1 is located on one side of the substrate 11 and includes a plurality of active patterns C11. The active pattern C11 includes a first portion CA extending along the first direction X and a second portion CB extending from one end of the first portion CA.

[0074] A first insulating layer, located on a side of the active layer C1 facing away from the substrate 11, having a plurality of first via holes K3;

[0075] The first metal layer M1 is located on a side of the first insulating layer away from the active layer C1 and includes a plurality of first signal lines M11 extending along a first direction X; at least one first signal line M11 among the plurality of first signal lines M11 is electrically connected to the active pattern C11 through a first via K3; specifically, the first signal line M11 may be a data line;

[0076] The multiple first blocking portions R1 are located on a side of the first metal layer M1 away from the first insulating layer. The orthographic projection of at least one of the multiple first blocking portions R1 on the substrate 11 covers the orthographic projection of the first via K3 on the substrate 11 .

[0077] In the embodiment of the present disclosure, the display panel has multiple first blocking portions R1, and the orthographic projection of the first blocking portion R1 on the substrate 11 covers the orthographic projection of the first via K3 on the substrate 11. By blocking the first via K3 at the position of the first blocking portion R1, the problem of light leakage in the display panel at the first via K3 can be improved, thereby improving the problem of low contrast of the display panel.

[0078] It should be noted that in order to more clearly illustrate the relationship between the first via and the first blocking portion, Figure 4 only shows a schematic diagram of part of the film layer of the display panel, but the display panel provided by the embodiment of the present disclosure is not limited to this. In a specific implementation, it may have more film layers than shown in Figure 4. For example, the schematic diagram of more film layers of the display panel may be as shown in Figures 5A and 6.

[0079] In a possible embodiment, referring to FIG4 , the first shielding portion R1 includes: a first sub-shielding portion R11, and a second sub-shielding portion R12 located outside the first sub-shielding portion R11; the orthographic projection of the first sub-shielding portion R11 on the substrate 1 coincides with the orthographic projection of the first via K3 on the substrate 11; the orthographic projection of the second sub-shielding portion R12 on the substrate 11 does not overlap with the orthographic projection of the first via K3 on the substrate 11. In the embodiment of the present disclosure, the first shielding portion R1 includes: a first sub-shielding portion R11 and a second sub-shielding portion R12. The orthographic projection of the first sub-shielding portion R11 on the substrate 1 coincides with the orthographic projection of the first via K3 on the substrate 11; the orthographic projection of the second sub-shielding portion R12 on the substrate 11 does not overlap with the orthographic projection of the first via K3 on the substrate 11, that is, the first shielding portion R1 completely covers the first via K3 and covers the peripheral portion of the first via K3, thereby achieving complete shielding of the first via K3 and achieving better light shielding.

[0080] In one possible embodiment, as shown in FIG4 , the second sub-blocking portion R12 includes: a first sub-portion RR1 extending along the first direction X, and a second sub-portion RR2 extending along the second direction Y. The width a1 of the first sub-portion RR1 in the second direction Y is equal to the width a2 of the second sub-portion RR2 in the first direction X. Specifically, the width a1 of the first sub-portion RR1 in the second direction Y may be the distance between the outer edge of the first sub-portion RR1 extending along the first direction X and the outer edge of the first via K3 extending along the first direction X. The width a2 of the second sub-portion RR2 in the first direction X is equal to the width a2 of the second sub-portion RR2 extending along the second direction Y and may be the distance between the outer edge of the second sub-portion RR2 extending along the second direction Y and the outer edge of the first via K3 extending along the second direction Y.

[0081] In a possible embodiment, referring to FIG4 , the minimum distance between the outer edge of the second sub-blocking portion R12 and the outer edge of the first sub-blocking portion R11 is in the range of 1 μm to 3 μm. Specifically, the minimum distance between the outer edge of the second sub-blocking portion R12 and the outer edge of the first sub-blocking portion R11 can be the width a2 of the second sub-portion RR2 in the first direction X, or the width a1 of the first sub-portion RR1 in the second direction Y. In the embodiment of the present disclosure, the minimum distance a between the outer edge of the second sub-blocking portion R12 and the outer edge of the first sub-blocking portion R11 is in the range of 1 μm to 3 μm, which can meet the requirements of blocking the currently measured light leakage range (the measured light leakage distance is about 1 μm), and at the same time, can block less of the pixel light-transmitting area, thereby reducing the impact on the aperture ratio.

[0082] In a specific implementation, when the width a2 of the second sub-section RR2 in the first direction X is 0.35 μm and the width a1 of the first sub-section RR1 in the second direction Y is 1 μm, the CR can be improved by about 70; when the width a2 of the second sub-section RR2 in the first direction X is 1 μm and the width a1 of the first sub-section RR1 in the second direction Y is 1 μm, the CR can be improved by about 100, and compared with the conventional method of increasing the overall width of the black matrix in the data line direction, the aperture ratio of the embodiment of the present disclosure can be improved by more than 15%.

[0083] In a possible embodiment, in combination with Figures 5A to 5G and Figure 6, the display panel also includes a first conductive layer D2 located on the side of the first metal layer M1 away from the first insulating layer 16; and a second insulating layer located between the first conductive layer D2 and the active layer C1; the second insulating layer has a plurality of second vias; the first conductive layer D2: a plurality of first electrodes D21; at least one first electrode D21 of the plurality of first electrodes D21 is electrically connected to the active layer C1 through the second via; the orthographic projection of the first blocking portion R1 on the substrate 11 has an overlapping area with the orthographic projection of the first electrode D21 on the substrate 11.

[0084] Specifically, the first electrode D21 may be a pixel electrode; specifically, the orthographic projection of the first electrode D21 on the substrate 11 may be located between the orthographic projections of adjacent first signal lines M11 on the substrate 11; specifically, the orthographic projection shape of the first electrode D21 on the substrate 11 may be a rectangle.

[0085] In a possible embodiment, referring to Figures 5A-5G and Figure 6, the active pattern C11 includes: a first portion CA extending along the first direction X, and a second portion CB extending from one end of the first portion CA; the orthographic projection of the first portion CA on the substrate 11 is located between the orthographic projections of adjacent first signal lines M11 on the substrate 11, and the orthographic projection of the second portion CB on the substrate 11 overlaps with the orthographic projection of the first signal line M11 on the substrate 11; specifically, the display area AA can have multiple first transistors, and the second portion CB can serve as the first electrode of the first transistor at a position overlapping with the first signal line M11; the second portion CB can be turned on at a position overlapping with the first signal line M11 to achieve electrical connection between the first transistor and the data line.

[0086] In a possible embodiment, referring to Figures 5A-5G and Figure 6, the display panel further includes a second conductive layer D1, and the second conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive portions D11 on the substrate 11 is located between the orthographic projections of adjacent first signal lines M11 on the substrate 11; specifically, the second conductive layer D1 may be a transparent conductive layer, and the conductive portion D11 may serve as the second electrode of the first transistor to connect the first active pattern C11 to the first electrode D21; specifically, the orthographic projection shape of the conductive portion D11 on the substrate 11 may be a rectangle.

[0087] In a possible embodiment, referring to Figures 5A-5G and Figure 6, the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D2, the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y; the first portion CA including: a first sub-portion CA1, a second sub-portion CA2, and a third sub-portion CA3 sequentially distributed along the first direction X; wherein, the orthographic projection of the second sub-portion CA2 on the substrate overlaps with the orthographic projection of the second metal wire M21 on the substrate 11; the first sub-portion CA1 is located on the side of the second sub-portion CA2 facing the second portion CB, and the third sub-portion CA3 is located on the side of the second sub-portion CA2 away from the second portion CB; that is, the portion of the first portion CA that overlaps with the projection of the second metal wire M21 is taken as the second sub-portion CA2; the orthographic projection of the first sub-portion CA1 on the substrate 11 has an overlapping area with the orthographic projection of the conductive portion D11 on the substrate 11.

[0088] In one possible embodiment, referring to Figures 5A-5G and Figure 6, the second portion CB includes: a fourth sub-portion CB1 connected to the first portion CA and extending along a third direction Z, and a fifth sub-portion CB2 connected to the fourth sub-portion CB1, and the first metal wire M11 is electrically connected to the fifth sub-portion CB2; specifically, the angle formed by the third direction Z and the first direction X can be 30° to 60°; specifically, the angle formed by the third direction Z and the first direction X can be 45°.

[0089] In one possible embodiment, referring to Figures 5A-5G and 6 , the display panel further includes a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11. The third metal layer M3 includes a plurality of third metal lines M31 extending along a second direction Y. The orthographic projections of the third metal lines M31 on the substrate 11 overlap the orthographic projections of the second metal lines M21 on the substrate 11. Specifically, the third metal lines M31 can be used to shield at least a portion of the first active pattern C11 of the first transistor to prevent ambient light from illuminating the first active pattern C11 and affecting the characteristics of the first transistor.

[0090] In one possible embodiment, referring to Figures 5A-5G and Figure 6 , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 in the first direction X on the substrate 11. In one possible embodiment, the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the first portion CA of the active pattern C11 on the substrate 11, and the orthographic projection of the fourth sub-portion CB1 of the active pattern C11 on the substrate 11. The orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the conductive portion D11 on the substrate 11.

[0091] In a possible implementation, the second metal line M21 may be a gate line; the third metal layer M3 may be a shielding layer of the array substrate, and may be used to shield at least a portion of an active pattern of a transistor.

[0092] In one possible embodiment, as shown in Figures 5A-5G and Figure 6, the display panel further includes, located in the non-display area BB: a driving active layer C2 located on the side of the first active layer C1 facing the substrate 11, a driving source and drain electrode (including a driving source electrode MQ2 and a driving drain electrode MQ3) located on the side of the driving active layer C2 facing away from the substrate 11, and a driving gate electrode MQ1. Specifically, the array substrate may include a gate driving circuit for the non-display area BB, and the gate driving circuit board includes: a plurality of second transistors, each of which may include: a driving active layer C2, a driving source and drain electrode (including a driving source electrode MQ2 and a driving drain electrode MQ3), and a driving gate electrode MQ1. In the disclosed embodiment, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology, integrating two types of TFTs (Thin Film Transistors)—LTPS (Low Temperature Poly-Silicon) and oxide—to enable AR and VR products to have high resolution (PPI, Pixel Per Inch), high aperture ratio, and high transmittance.

[0093] In one possible embodiment, referring to Figures 5A-5G and Figure 6 , the display panel further includes: a first drive electrode MD1, a second drive electrode MD2, a third drive electrode MD3, and a fourth drive electrode MD4 located in the non-display area BB, wherein the first drive electrode MD1 is electrically connected to the second drive electrode MD2, and the third drive electrode MD3 is electrically connected to the fourth drive electrode MD4. Specifically, the first drive electrode MD1 can serve as a first routing wire, and the third drive electrode MD3 can serve as a second routing wire. The first routing wire can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer; the second routing wire can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer. The first routing wire can include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line. The second routing wire can include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line.

[0094] In one possible embodiment, as shown in Figures 5A-5G and 6, the driving active layer C2 is located between the third metal layer M3 and the substrate 11; the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain electrodes (including the driving source electrode MQ2 and the driving drain electrode MQ3) are located in the first metal layer M1. In the disclosed embodiment, the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain electrodes are located in the first metal layer M1. This allows the corresponding driving gate MQ1 and driving source and drain electrodes in the non-display area to be formed simultaneously with the third metal layer M3 and the first metal layer M1 in the display area AA, thereby simplifying the display panel manufacturing process.

[0095] In a possible embodiment, referring to Figures 5A-5G and Figure 6, the first drive electrode MD1 and the third drive electrode MD3 may be located in the first metal layer M1; the second drive electrode MD2 may be located in the third metal layer M3, and the fourth drive electrode MD4 may be located in the second metal layer M2; and thus, while forming the first metal layer M1 in the display area AA, the first drive electrode MD1 and the third drive electrode MD3 corresponding to the non-display area may be formed; while forming the second metal layer M2 in the display area AA, the fourth drive electrode MD4 corresponding to the non-display area may be formed; and while forming the third metal layer M3 in the display area AA, the second drive electrode MD2 corresponding to the non-display area may be formed, which may simplify the manufacturing process of the display panel.

[0096] In one possible embodiment, at least part of the routing of the second metal layer M2 and at least part of the routing of the third metal layer M3 can be electrically connected by jumping layers in the non-display area BB. For example, the second metal line M21 and the third metal line M31 can be electrically connected in the non-display area BB to enable the transistors in the display area AA to form a dual-gate structure.

[0097] In a possible implementation, referring to FIG. 5A to FIG. 5G and FIG. 6 , the display panel may further include at least one of the following:

[0098] A buffer layer 12 located between the substrate 11 and the driving active layer C2;

[0099] a second gate insulating layer 13 located between the driving active layer C2 and the third metal layer M3;

[0100] a third interlayer dielectric layer 14 located between the third metal layer M3 and the first active layer C1;

[0101] a first gate insulating layer 15 located between the first active layer C1 and the second metal layer M2;

[0102] a first interlayer dielectric layer 16 located between the second metal layer M2 and the first metal layer M1;

[0103] a second interlayer dielectric layer 17 located between the first metal layer M1 and the second conductive layer D1;

[0104] a first planar layer 18 located between the second conductive layer D1 and the first conductive layer D2;

[0105] The second planarization layer 19 is located between the first conductive layer D2 and the fourth metal layer M4.

[0106] In one possible embodiment, the first insulating layer may include: a first gate insulating layer 15, a first interlayer dielectric layer 16; the second insulating layer may include: a first gate insulating layer 15, a first interlayer dielectric layer 16, a second interlayer dielectric layer 17, and a first flat layer 18; in one possible embodiment, the display panel also includes: a first sub-via K1 passing through the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17; and a second sub-via K2 passing through the first flat layer 18; the first electrode D21 is electrically connected to the conductive part D11 through the second sub-via K2, and the conductive part D11 is electrically connected to the active layer C11 through the first sub-via K1; the second via may include: a first sub-via K1, and a second sub-via K2.

[0107] Since virtual reality (VR) head-mounted display products are near-eye displays, and the images displayed on the LCD screen need to be magnified multiple times by the imaging system before they can enter the human eye, even if the current VR display resolution has reached more than 1000PPI, the screen effect caused by the shading structure can still be seen in the whole display. In view of this, as shown in Figure 7, the display panel includes: a plurality of pixel light-transmitting areas P, the plurality of pixel light-transmitting areas P include: a plurality of pixel light-transmitting area rows H extending along the second direction Y and arranged along the first direction X; at least one pixel light-transmitting area row H in the plurality of pixel light-transmitting area rows H includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the light band range emitted by the third pixel light-transmitting area P3 is smaller than the light band range emitted by the first pixel light-transmitting area P1, and The light wavelength range of the first pixel light-transmitting area P1 is smaller than that of the second pixel light-transmitting area P2; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area that emits red light, the second pixel light-transmitting area P2 can be a pixel light-transmitting area that emits green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area that emits blue light; the display panel also includes: a second blocking portion R2, which is located on one side of the substrate 11, and the orthographic projection of the second blocking portion R2 on the substrate 11 is located in the gap between at least part of the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0108] In the embodiment of the present disclosure, the display panel also includes: a second blocking portion R2, the orthographic projection of the second blocking portion R2 on the substrate 11, and the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X. This can reduce the brightness difference of the third pixel light-transmitting areas P3 at different positions, making the distribution of the third pixel light-transmitting areas P3 more uniform in the entire pixel area, thereby reducing the screen window effect and improving the visual effect.

[0109] Specifically, the pixel transparent area P can be understood as the effective display area of ​​the pixel, which can be the area in the pixel area that is not blocked by the blocking structure (such as the shielding layer, gate line, data line, second blocking metal layer, black matrix, etc.).

[0110] In a possible implementation, a length m3 of the third pixel light-transmitting area P3 in the first direction X is smaller than a length m1 of the first pixel light-transmitting area P1 in the first direction X, and smaller than a length m2 of the second pixel light-transmitting area P2 in the first direction X.

[0111] In one possible embodiment, the length m1 of the first pixel light-transmitting area P1 in the first direction X is equal to the length m2 of the second pixel light-transmitting area P2 in the first direction X. In the embodiment of the present disclosure, the second blocking portion R2 is set by setting the length m3 of the third pixel light-transmitting area P3 in the first direction X to be shorter. Moreover, compared with the first pixel light-transmitting area P1 and the second pixel light-transmitting area P2 having a longer output light wavelength range, the brightness of the third pixel light-transmitting area P3 having a smaller output light wavelength range is lower, which can effectively reduce the sensitivity of the human eye to the second blocking portion R2, and can reduce the brightness difference between the position with spacers and the position without spacers between the third pixel light-transmitting area P3, so that the brightness is more evenly distributed in the entire pixel area, thereby reducing the screen door effect and improving the visual effect.

[0112] In a possible embodiment, the display panel further includes: a spacer (not shown in the figure, specifically, the shape and position of the orthographic projection on the substrate 11 can be as shown in the third blocking portion R3 of Figure 7, that is, the shape of the orthographic projection of the spacer on the substrate 11 can be an octagon, and can be located in the gap between the orthographic projections of at least two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X), and a third blocking portion R3; the orthographic projection of the third blocking portion R3 on the substrate 11 covers the orthographic projection of the spacer on the substrate; the orthographic projection of the third blocking portion R3 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y; the orthographic projections of the second blocking portion R2 and the third blocking portion R3 on the substrate 11 are alternately distributed along the second direction Y.

[0113] In the embodiment of the present disclosure, placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels effectively reduces the human eye's sensitivity to compensation for obstructions (such as a black matrix) at the position of the spacer (blue pixels have lower brightness than green and red pixels, so placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels will result in a smaller visual difference between light and dark for the human eye than placing it on green and red pixels).

[0114] In a possible implementation, the first shielding portion R1 , the second shielding portion R2 , and the third shielding portion R3 are made of the same layer and the same material.

[0115] In one possible embodiment, the display panel includes: an array substrate and an opposing substrate arranged relative to each other; the opposing substrate has a black matrix layer; and a plurality of first shielding portions R1 are located in the black matrix layer. In the disclosed embodiment, the display panel can be applied to an LCD panel for VR. The LCD panel for VR has high pixel density requirements (1200+PPI), resulting in thinner metal wires and light-shielding traces. If the first shielding portion R1 is made on a film layer (such as the third metal layer M3) of the array substrate, the shape of the first shielding portion R1 actually produced may be elliptical, and light leakage may still occur. In the disclosed embodiment, the first light-shielding portion R1 is made on the black matrix layer of the opposing substrate, which can completely cover the light leakage at the first via K3.

[0116] The present disclosure also provides another display panel, as shown in FIG8 , including:

[0117] substrate 11;

[0118] The active layer C1 is located on one side of the substrate 11 and includes a plurality of active patterns C11;

[0119] A first insulating layer, located on a side of the active layer C1 facing away from the substrate 11, having a plurality of first via holes K3;

[0120] The first metal layer M1 is located on a side of the first insulating layer away from the active layer C1 and includes a plurality of first signal lines M11 extending along a first direction X; at least one first signal line M11 among the plurality of first signal lines M11 is electrically connected to the active pattern C11 through a first via K3;

[0121] The first signal line M11 has a first symmetry axis k1 extending along the first direction X. The first signal line M11 is symmetrical about the first symmetry axis k1. At least part of the first via K3 is located in the central area of ​​the orthographic projection of the substrate 11 and does not coincide with the first symmetry axis k1.

[0122] In the embodiment of the present disclosure, at least part of the first via K3 is located in the central area of ​​the orthographic projection of the substrate 11 and does not coincide with the first symmetry axis k1 of the first signal line M11. This can also improve the light leakage problem of the display panel at the first via K3, thereby improving the low contrast problem of the display panel.

[0123] It should be noted that FIG8 only shows part of the film layer of the display panel in order to clearly illustrate the relationship between the first via K3 and the first signal line M11. The other film layer structures may be as shown in FIG5A to FIG5G and FIG6, and the embodiments of the present disclosure will not be repeated here.

[0124] In a possible embodiment, as shown in FIG8 , the display panel includes: a plurality of pixel light-transmitting areas P, the plurality of pixel light-transmitting areas P include: a plurality of pixel light-transmitting area rows H extending along the second direction Y and arranged along the first direction X; at least one pixel light-transmitting area row H of the plurality of pixel light-transmitting area rows H includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the light wavelength range emitted by the second pixel light-transmitting area P2 is smaller than the light wavelength range emitted by the first pixel light-transmitting area P1, and is larger than the light wavelength range emitted by the third pixel light-transmitting area P3. The light band range of the light-transmitting area P3; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area that emits red light, the second pixel light-transmitting area P2 can be a pixel light-transmitting area that emits green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area that emits blue light; the multiple first signal lines M11 include: a first sub-signal line MA adjacent to the second pixel light-transmitting area P2; the first via K3 connected to the first sub-signal line MA is in the central area O1 of the positive projection of the substrate 11, and does not coincide with the first symmetry axis k1 of the first sub-signal line MA.

[0125] In the embodiment of the present disclosure, the first signal line M11 adjacent to the second pixel light-transmitting area P2 is used as the first sub-signal line MA, and the first via K3 connected to the first sub-signal line MA is located in the central area O1 of the positive projection of the substrate 11, and does not coincide with the first symmetry axis k1 of the first sub-signal line MA. That is, based on the brightness difference between the three sub-pixels R, G, and B, the G pixel has the highest brightness. The third via K3 adjacent to the second sub-pixel light-transmitting area P2 emitting green light is moved and partially moved into the R and B sub-pixels. This can reduce the L0 light leakage ratio to a certain extent, thereby improving the light leakage problem of the display panel at the first via K3, and further improving the problem of low contrast of the display panel.

[0126] In one possible implementation, as shown in FIG8 , the first via K3 connected to the first sub-signal line MA is located in the center region O1 of the orthographic projection of the substrate 11, on the side of the first symmetry axis k1 away from the second pixel light-transmitting area P2. In other words, by relocating the third via K3, which is adjacent to the second sub-pixel light-transmitting area P2 emitting green light, and partially moving the third via K3 into the R and B sub-pixels, the L0 light leakage ratio can be reduced, thereby improving the light leakage problem of the display panel at the first via K3 and further improving the low contrast of the display panel.

[0127] In a possible embodiment, referring to FIG8 , the plurality of first signal lines M11 further include: a second sub-signal line MB; the remaining first signal lines M11 except the first sub-signal line MA (that is, the first signal line adjacent to the second sub-pixel light-transmitting area P2) in the first signal line M11 can be used as the second sub-signal line MB; the first via K3 connected to the second sub-signal line MB is in the central area O1 of the positive projection of the substrate 11, coinciding with the first symmetry axis k1 of the second sub-signal line MB.

[0128] In a possible embodiment, the first via K3 connected to the first sub-signal line MA is projected on the substrate 11, and the distance from the third pixel light-transmitting area P3 in the second direction Y is in the range of 1μm to 3μm. Specifically, the second sub-pixel light-transmitting area P2 emitting green light is close to the first via K3 of the adjacent first sub-pixel light-transmitting area P1 emitting red light (not shown in the figure), and is moved c1 to the side of the adjacent first sub-pixel light-transmitting area P1 emitting red light. The range of c1 can be 0.3μm to 0.6μm; for example, it moves 0.3μm, 0.35μm, 0.4μm, 0.45μm, 0.5μm, 0.35μm, 0.6μm; at the same time, the second sub-pixel light-transmitting area P2 emitting green light is close to the adjacent third sub-pixel light-transmitting area P3 emitting blue light (not shown in the figure). The first via hole K3 of the G sub-pixel is moved by c2 to the side of the adjacent third sub-pixel light-emitting blue light-transmitting area P3, and the range of c2 can be 0.3μm to 0.6μm; for example, it is moved to the right by 0.3μm, 0.35μm, 0.4μm, 0.45μm, 0.5μm, 0.35μm, and 0.6μm. In this way, the black matrix at the original position of the first signal line M11 (data line) can wrap the first via hole K3 in the G sub-pixel by about 1μm, which can meet the shielding range of the currently measured light leakage (the measured light leakage distance is about 1μm).

[0129] In one possible embodiment, as shown in FIG8 , only some of the first via holes K3 may be shifted (for example, only the first via holes K3 with higher brightness and adjacent to the sub-pixel emitting green light may be shifted) to reduce the degree of light leakage. In another possible embodiment, as shown in FIG9A or FIG9B , all the first via holes K3 may be shifted to one side as a whole. For example, they may be shifted to the left as a whole. As shown in FIG9A , the first via hole K3 connected to the N-th first signal line M11 is located in the central area of ​​the positive projection of the substrate 11, on the side where the first symmetry axis k1 of the N-th first signal line M11 faces the N-1-th first signal line M11. For another example, they may be shifted to the right as a whole. As shown in FIG9B , the first via hole K3 connected to the N-th first signal line M11 is located in the central area of ​​the positive projection of the substrate 11, on the side where the first symmetry axis k1 of the N-th first signal line M11 faces the N+1-th first signal line M11.

[0130] In a possible embodiment, referring to FIG. 9C , FIG. 9C may be a cross-sectional schematic diagram of FIG. 9A along the dotted line GH, and the first via K3 includes: a hole bottom K31, and a hole wall K32 connected to the hole bottom K31; a portion of the outer edge on one side of the first signal line M11 is located at the hole bottom K31, and a portion of the outer edge on the other side of the first signal line M11 is located around the first via K3. In the embodiment of the present disclosure, when the first via hole K3 is shifted as a whole, a portion of the outer edge of one side of the first signal line M11 is located at the bottom K31 of the hole, and a portion of the outer edge of the other side of the first signal line M11 is located around the first via hole K3, so as to ensure that one edge of the first signal line M11 is located at the bottom of the first via hole K3, and the other edge of the first signal line M11 is away from the first via hole K3. Taking the left shift of the first via hole K3 in Figure 9A as an example, the left edge of the first signal line M11 is distributed at the bottom K31 of the first via hole K3, and exposure and etching can form a straight line. At the same time, the right side of the first signal line M11 is away from the first via hole K3, and a straight line can also be formed during the exposure and etching process, thereby avoiding light leakage caused by polarization of light when the first signal line M11 is elliptically distributed.

[0131] In a possible implementation manner, the outer edge of the first signal line M11 is in a straight line shape at the first via hole K3 .

[0132] In a possible embodiment, referring to FIG10 , the display panel further includes: a fourth shielding portion R4, and a first shielding strip G1 extending along the second direction Y; the orthographic projection of the first shielding strip G1 on the substrate 11 covers the orthographic projection of the first signal line M11 on the substrate 11, and covers the portion of the orthographic projection of the first via K3 on the substrate 11; the orthographic projection of the fourth shielding portion R4 on the substrate 11 covers the portion of the first via K3 that exceeds the first shielding strip G1, and covers the peripheral portion of the first via K3.

[0133] In the embodiment of the present disclosure, the display panel also includes a fourth shielding portion R4, and the orthographic projection of the fourth shielding portion R4 on the substrate 11 covers the portion of the first via K3 that extends beyond the first shielding strip G1, as well as the peripheral portion of the first via K3. For example, as shown in FIG10 , the first via K3 is moved to the right as a whole, so that the left edge of the first via K3 can be blocked by the first shielding strip G1, and the right edge of the first via K3 can be compensated and blocked by the fourth shielding portion R4. In this way, the first via K3 can be completely blocked by both sides of the first shielding strip G1 and the fourth shielding portion R4.

[0134] In one possible embodiment, the first shielding strip G1 may be a portion of the black matrix layer used to shield the first signal line M11. In one possible embodiment, the line width of the first shielding strip G1 may be greater than the line width of the first signal line M11 to completely shield the first signal line M11 and partially shield the first via K3.

[0135] In one possible embodiment, as shown in FIG10 , the distance d1 between the outer edge of the fourth shielding portion R4 and the outer edge of the first via K3 is 1 μm to 3 μm. This allows shielding within the currently measured light leakage range (measured light leakage distance is approximately 1 μm).

[0136] Specifically, the distance range d1 between the outer edge of the fourth blocking portion R4 and the outer edge of the first via K3 can be the distance between the outer edge of the fourth blocking portion R4 and the outer edge of the first via K3 in the first direction X or in the second direction Y.

[0137] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0138] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0139] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein: include: substrate; an active layer, located on one side of the substrate, comprising a plurality of active patterns; a first insulating layer, located on a side of the active layer facing away from the substrate, and having a plurality of first via holes; a first metal layer, located on a side of the first insulating layer away from the active layer, comprising a plurality of first signal lines extending along a first direction; at least one first signal line among the plurality of first signal lines is electrically connected to the active pattern through the first via hole; A plurality of first blocking portions are located on a side of the first metal layer facing away from the first insulating layer, and an orthographic projection of at least one of the plurality of first blocking portions on the substrate covers an orthographic projection of the first via on the substrate.

2. The display panel according to claim 1, wherein: The first shielding portion includes: a first sub-shielding portion, and a second sub-shielding portion located outside the first sub-shielding portion; The orthographic projection of the first sub-blocking portion on the substrate coincides with the orthographic projection of the first via hole on the substrate; the orthographic projection of the second sub-blocking portion on the substrate does not overlap with the orthographic projection of the first via hole on the substrate.

3. The display panel according to claim 2, wherein: The second shielding portion includes: a first sub-portion extending along the first direction, and a second sub-portion extending along the second direction; The width of the first sub-portion in the second direction is equal to the width of the second sub-portion in the first direction.

4. The display panel according to claim 2 or 3, wherein: The minimum distance between the outer edge of the second sub-shielding portion and the outer edge of the first sub-shielding portion is in a range of 1 μm to 3 μm.

5. The display panel according to any one of claims 1 to 4, wherein: The display panel further includes a first conductive layer located on a side of the first metal layer facing away from the first insulating layer; and a second insulating layer located between the first conductive layer and the active layer; The second insulating layer has a plurality of second via holes; The first conductive layer includes: a plurality of first electrodes; at least one first electrode among the plurality of first electrodes is electrically connected to the active layer through the second via hole; The orthographic projection of the first shielding portion on the substrate has an overlapping area with the orthographic projection of the first electrode on the substrate.

6. The display panel according to any one of claims 1 to 5, wherein: The display panel includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of pixel light-transmitting area rows extending along a second direction and arranged along the first direction; at least one of the plurality of pixel light-transmitting area rows including: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; a light wavelength range emitted by the third pixel light-transmitting area is smaller than the light wavelength range emitted by the first pixel light-transmitting area, and smaller than the light wavelength range emitted by the second pixel light-transmitting area; The display panel further includes a second blocking portion located on one side of the substrate, wherein the orthographic projection of the second blocking portion on the substrate is located in a gap between orthographic projections of at least partially adjacent two third pixel light-transmitting areas in the first direction.

7. The display panel according to claim 6, wherein: The display panel further includes: a spacer and a third shielding portion; the orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the spacer on the substrate; The orthographic projection of the third blocking portion on the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas on the substrate in the second direction; the orthographic projections of the second blocking portion and the third blocking portion on the substrate are alternately distributed along the second direction.

8. The display panel according to any one of claims 1 to 7, wherein: The first blocking portion, the second blocking portion, and the third blocking portion are formed in the same layer and made of the same material.

9. The display panel according to any one of claims 1 to 8, wherein: The display panel comprises: an array substrate and an opposite substrate arranged opposite to each other; the opposite substrate has a black matrix layer; The plurality of first shielding portions are located in the black matrix layer.

10. A display panel, wherein: include: substrate; an active layer, located on one side of the substrate, comprising a plurality of active patterns; a first insulating layer, located on a side of the active layer facing away from the substrate, and having a plurality of first via holes; a first metal layer, located on a side of the first insulating layer away from the active layer, comprising a plurality of first signal lines extending along a first direction; at least one first signal line among the plurality of first signal lines is electrically connected to the active pattern through the first via hole; Wherein, the first signal line has a first symmetry axis extending along the first direction, and the first signal line is symmetrical about the first symmetry axis; At least part of the first via holes is located in a central area of ​​an orthographic projection of the substrate and does not coincide with the first symmetry axis.

11. The display panel according to claim 10, wherein: The display panel includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of pixel light-transmitting area rows extending along a second direction and arranged along the first direction; at least one of the plurality of pixel light-transmitting area rows including: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; a light wavelength range emitted by the second pixel light-transmitting area is smaller than the light wavelength range emitted by the first pixel light-transmitting area, and larger than the light wavelength range of the third pixel light-transmitting area; The multiple first signal lines include: a first sub-signal line adjacent to the second pixel light-transmitting area; the first via connected to the first sub-signal line is located in the central area of ​​the substrate's orthographic projection and does not coincide with the first symmetry axis of the first sub-signal line.

12. The display panel according to claim 11, wherein: The first via hole connected to the first sub-signal line is located in the central area of ​​the orthographic projection of the substrate, and is located on a side of the first symmetry axis away from the second pixel light-transmitting area.

13. The display panel according to claim 11 or 12, wherein: The plurality of first signal lines further include: a second sub-signal line; The first via hole connected to the second sub-signal line is located in a central area of ​​an orthographic projection of the substrate and coincides with the first symmetry axis of the second sub-signal line.

14. The display panel according to any one of claims 11 to 13, wherein: The first via hole connected to the first sub-signal line is projected on the substrate, and the distance from the third pixel light-transmitting area in the second direction is in a range of 1 μm to 3 μm.

15. The display panel according to claim 10, wherein: The first via hole includes: a hole bottom, and a hole wall connected to the hole bottom; A portion of an outer edge on one side of the first signal line is located at the bottom of the hole, and a portion of an outer edge on the other side of the first signal line is located around the via hole.

16. The display panel according to claim 15, wherein: An outer edge of the first signal line is in a straight line shape at the first via hole.

17. The display panel according to claim 15 or 16, wherein: The first via connected to the Nth first signal line is located in the central area of ​​the orthographic projection of the substrate, on a side of the first symmetry axis of the Nth first signal line facing the N-1th first signal line.

18. The display panel according to claim 15 or 16, wherein: The first via connected to the Nth first signal line is located in the central area of ​​the orthographic projection of the substrate, on a side of the first symmetry axis of the Nth first signal line facing the (N+1)th first signal line.

19. The display panel according to any one of claims 15 to 18, wherein: The display panel further includes: a fourth shielding portion, and a first shielding strip extending along the second direction; The first shielding strip is an orthographic projection of the substrate, covering the orthographic projection of the first signal line on the substrate, and covering the part of the orthographic projection of the first via on the substrate; the fourth shielding portion is an orthographic projection of the substrate, covering the part of the first via that exceeds the first shielding strip, and covering the peripheral distribution of the first via.

20. The display panel according to claim 19, wherein: The distance between the outer edge of the fourth shielding portion and the outer edge of the first via hole is in a range of 1 μm to 3 μm.

21. A display device, wherein: Comprising the display panel according to any one of claims 1-9 or 10-20.

Images