DSP mode configuration method and apparatus, communication system and storage medium

Abstract

The present application relates to the technical field of communications, and provides a DSP mode configuration method and apparatus, a communication system, and a storage medium. The method comprises: on the basis of a SerDes transmission end of a second apparatus supporting multiple first DSP modes, performing at least one test in a data transmission direction from the second apparatus to a first apparatus, and determining a first bit error rate of the first DSP mode to which each test is directed, the first bit error rate being able to evaluate whether the DSP mode being tested matches insertion loss of a link; on the basis of multiple first bit error rates, determining a first target DSP mode, and configuring the SerDes transmission end of the second apparatus to be in the first target DSP mode. In the described method, since the DSP mode can be adjusted, and the first target DSP mode matches the insertion loss of the link, the problems of excessive DSP functionality and increased SerDes power consumption and delay caused by using a DSP mode having excessively high functionality can be avoided.

Description

DSP mode configuration method, device, communication system and storage medium

[0001] This application claims priority to Chinese patent application number 202410231724.0, filed on February 29, 2024, entitled “DSP mode configuration method, device, communication system and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a DSP mode configuration method, device, communication system and storage medium. Background Art

[0003] A serializer / deserializer (SerDes) is used to convert parallel signals into serial signals for transmission and to convert received serial signals into parallel signals. When SerDes rates evolve to 64 gigabits per second (GT / s) and above, the receiving end generally adopts an analog-to-digital converter (ADC) + digital signal processor (DSP) architecture. The ADC samples the analog signal into the digital domain to obtain a digital signal, and the DSP performs digital signal equalization to compensate for the loss of the digital signal transmitted in the link, also known as the link's insertion loss (IL). The insertion loss is related to the link length and transmission rate. The greater the insertion loss, the stronger the DSP's equalization capability is required, while the smaller the link insertion loss, the weaker the DSP's equalization capability is required. In this SerDes architecture, the power consumption and delay caused by DSP account for a large proportion of the overall power consumption and delay of SerDes. The stronger the balancing capability of DPS, the greater the power consumption and delay. Therefore, it is necessary to determine the DSP balancing capability that matches the insertion loss based on the size of the insertion loss. If a larger DSP balancing capability is applied to a scenario with smaller insertion loss, it will result in a waste of DSP balancing capability and a significant increase in SerDes power consumption and delay.

[0004] In the related art, the interconnection application scenarios of SerDes are subdivided into long reach (LR), medium reach (MR), short reach (SR) and extremely short reach (XSR) according to the distance between the transmitter and the receiver. Correspondingly, SerDes is divided into different versions. The DSP in each version of SerDes is configured to a working mode in which the DSP's equalization capability is fixed. According to the application scenario, the SerDes version with the DSP equalization capability matching the application scenario is selected.

[0005] However, in the above method, if the SerDes needs to support multiple interconnected application scenarios, only the SerDes version with the strongest DSP balancing capability can be selected. When this version of the SerDes works in a scenario where less balancing capability is required, it causes excess DSP performance in the SerDes, and increases SerDes power consumption and latency.

[0006] Summary of the Invention

[0007] The present invention provides a DSP mode configuration method, device, communication system, and storage medium. The DSP in a SerDes (SerDes) supports multiple modes and can adaptively control the DSP mode based on link insertion loss, thereby avoiding DSP overperformance when the SerDes is used in various interconnected application scenarios and reducing SerDes power consumption and latency. The technical solution is as follows.

[0008] In a first aspect, a DSP mode configuration method is provided, which is applied to a first device, the method comprising: the SerDes transmitter of the second device supports multiple first DSP modes, and after the first device obtains the multiple first DSP modes, based on the multiple first DSP modes, the data transmission direction from the second device to the first device on the link between the first device and the second device is tested at least once, and the bit error rate (first bit error rate) of the first DSP mode targeted by each test is determined, and the first bit error rate can evaluate whether the tested DSP mode matches the insertion loss of the link; the first device determines a first target DSP mode among the multiple first DSP modes based on the first bit error rate obtained from each test, and sends the first target DSP mode to the second device to instruct the second device to configure the SerDes transmitter of the second device to the first target DSP mode.

[0009] Among them, the first device can configure the DSP mode of the data transmission direction from the second device to the first device on the link between the first device and the second device, including configuring at least one of the DSP mode of the SerDes transmitting end of the second device and the DSP mode of the SerDes receiving end of the first device.

[0010] The second device performs a test on the second data transmission direction of the link, that is, the direction from the first device to the second device, to determine the target DSP mode of the SerDes transmitter of the first device. The testing process of the second device is similar to that of the first device.

[0011] In the above method, since the DSP mode is adjustable and the determined DSP mode matches the insertion loss of the link, it is possible to avoid the problem of DSP overperformance caused by adopting a DSP mode with too high performance, and thus avoid the problem of increased SerDes power consumption and latency caused by the DSP mode with too high performance.

[0012] Optionally, the SerDes receiving end of the first device supports multiple second DSP modes, and the method further includes:

[0013] Based on multiple second DSP modes, perform at least one test on the first data transmission direction of the link to determine a second bit error rate for each test, where the second bit error rate is the bit error rate of the first data transmission direction of the link under the second DSP mode targeted by each test; determine the second target DSP mode of the first device based on the second bit error rate obtained from each test; and configure the SerDes receiving end of the first device to the second target DSP mode.

[0014] Optionally, obtaining multiple first DSP modes supported by the SerDes transmitting end of the second device includes:

[0015] A first training stream block TSB is received, which is sent by the second device through a SerDes transmitting end of the second device, where the first TSB carries the multiple first DSP modes.

[0016] Optionally, the performing at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determining a first bit error rate for each test, includes:

[0017] A second TSB is sent to the SerDes receiving end of the second device, where the second TSB carries the first DSP mode targeted by this test, and is used to instruct the second device to configure the SerDes transmitting end of the second device to the first DSP mode targeted by this test; a third TSB returned by the SerDes transmitting end of the second device is obtained, where the third TSB carries feedback information of the second device on the second TSB; if the feedback information indicates that the second device accepts this test on the SerDes transmitting end of the second device, a first bit error rate of this test is determined; if the feedback information indicates that the second device refuses to perform this test on the SerDes transmitting end of the second device, a next test is performed on the first data transmission direction of the link.

[0018] Optionally, the performing at least one test on the first data transmission direction of the link based on the multiple second DSP modes and determining a second bit error rate of each test includes:

[0019] The SerDes receiving end of the first device is configured to a second DSP mode targeted by this test; and a second bit error rate is determined for each test.

[0020] Optionally, determining the first target DSP mode of the second device based on the first bit error rate obtained in each test includes:

[0021] Based on the first bit error rate obtained in each test, a first test is determined, where the difference between the obtained first bit error rate and the target bit error rate is the smallest; and the first DSP mode targeted by the first test is determined as the first target DSP mode.

[0022] In the above method, whether the DSP performance of the first data transmission direction of the link can meet the requirements is reflected by the relationship between the first bit error rate and the target bit error rate. The first bit error rate is greater than the target bit error rate and the larger the difference is, the less the DSP performance of the first data transmission direction of the link can meet the requirements. The first bit error rate is less than the target bit error rate and the larger the difference is, the more excessive the DSP performance of the first data transmission direction of the link is. Therefore, the first DSP mode for which the difference between the first bit error rate and the target bit error rate is the smallest is determined as the first target DSP mode. On the premise of meeting the requirements for DSP performance, the problem of excess DSP performance caused by adopting a DSP mode with too high performance can be avoided, and the problem of increased SerDes power consumption and delay caused by the DSP mode with too high performance can be avoided.

[0023] Optionally, determining the second target DSP mode of the first device based on the second bit error rate obtained in each test includes:

[0024] Based on the second bit error rate obtained in each test, a second test is determined, where the difference between the obtained second bit error rate and the target bit error rate is the smallest; and the second DSP mode targeted by the second test is determined as the second target DSP mode.

[0025] In the above method, whether the DSP performance of the first data transmission direction of the link can meet the requirements is reflected by the relationship between the second bit error rate and the target bit error rate. The second bit error rate is greater than the target bit error rate and the larger the difference is, the less the DSP performance of the first data transmission direction of the link can meet the requirements. The second bit error rate is less than the target bit error rate and the larger the difference is, the more excessive the DSP performance of the first data transmission direction of the link is. Therefore, the second DSP mode for the test with the smallest difference between the second bit error rate and the target bit error rate is determined as the second target DSP mode. On the premise of meeting the requirements for DSP performance, it can avoid the problem of excessive DSP performance caused by adopting a DSP mode with too high performance, and thus avoid the problem of increased SerDes power consumption and delay caused by the DSP mode with too high performance.

[0026] Optionally, the SerDes transmitting end of the second device maintains a first mapping table, where the first mapping table is used to indicate a correspondence between the multiple first DSP modes and the multiple DSP parameters;

[0027] The process of configuring the SerDes transmitting end of the second device to the first target DSP mode by the second device includes:

[0028] The SerDes transmitter of the second device determines the DSP parameters corresponding to the first target DSP mode based on the first mapping table; the SerDes transmitter of the second device completes the configuration of the SerDes transmitter of the second device based on the DSP parameters corresponding to the first target DSP mode.

[0029] Optionally, the SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and the plurality of DSP parameters;

[0030] The SerDes receiving end of the first device is configured to the second target DSP mode, including:

[0031] The SerDes receiving end of the first device determines the DSP parameters corresponding to the second target DSP mode based on the second mapping table; the SerDes receiving end of the first device completes the configuration of the SerDes receiving end of the first device based on the DSP parameters corresponding to the second target DSP mode.

[0032] In a second aspect, a DSP mode configuration method is provided, the method comprising:

[0033] The second device sends a plurality of first DSP modes supported by the SerDes transmitting end of the second device to the first device;

[0034] The first device obtains the plurality of first DSP modes;

[0035] The first device performs at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determines a first bit error rate for each test, the first bit error rate being a bit error rate for the first data transmission direction of the link under the first DSP mode targeted by each test, the first data transmission direction being a direction from the second device to the first device;

[0036] The first device determines a first target DSP mode of the second device based on a first bit error rate obtained in each test;

[0037] The first device sends the first target DSP mode to the second device;

[0038] The second device configures the SerDes transmitting end of the second device to the first target DSP mode.

[0039] Optionally, the SerDes receiving end of the first device supports multiple second DSP modes, and the method further includes:

[0040] The first device performs at least one test on the first data transmission direction of the link based on the multiple second DSP modes, and determines a second bit error rate for each test, where the second bit error rate is a bit error rate for the first data transmission direction of the link under the second DSP mode targeted by each test;

[0041] The first device determines a second target DSP mode of the first device based on a second bit error rate obtained in each test;

[0042] The first device configures the SerDes receiving end of the first device to the second target DSP mode.

[0043] Optionally, the first device acquires the multiple first DSP modes, including:

[0044] The first device receives a first training stream block TSB sent by the second device through the SerDes transmitting end of the second device through the SerDes receiving end of the first device, where the first TSB carries the multiple first DSP modes.

[0045] Optionally, the first device performs at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determines a first bit error rate for each test, including:

[0046] The first device sends a second TSB to the SerDes receiving end of the second device through the SerDes transmitting end of the first device, where the second TSB carries the first DSP mode targeted by this test;

[0047] The second device configures the SerDes transmitter of the second device to the first DSP mode targeted by this test based on the second TSB;

[0048] The second device returns a third TSB to the SerDes receiving end of the first device through the SerDes transmitting end of the second device, where the third TSB carries feedback information of the SerDes transmitting end of the second device on the second TSB;

[0049] The first device obtains the third TSB through the SerDes receiving end of the first device;

[0050] If the feedback information indicates that the SerDes transmitter of the second device accepts the test, the first device determines a bit error rate of the test;

[0051] If the feedback information indicates that the SerDes transmitter of the second device rejects the current test, the first device performs a next test on the first data transmission direction of the link.

[0052] Optionally, the first device performs at least one test on the first data transmission direction of the link based on the multiple second DSP modes, and determines a second bit error rate of each test, including:

[0053] The first device configures the SerDes receiving end of the first device to a second DSP mode targeted by this test;

[0054] The first device determines a second bit error rate for each test.

[0055] Optionally, the first device determines the first target DSP mode of the second device based on the first bit error rate obtained in each test, including:

[0056] The first device determines a first test based on the first bit error rate obtained in each test, where the first test is a test in which the difference between the obtained first bit error rate and the target bit error rate is the smallest;

[0057] The first device determines a first DSP mode targeted by the first test as the first target DSP mode.

[0058] Optionally, the first device determines a second target DSP mode of the first device based on a second bit error rate obtained in each test, including:

[0059] The first device determines a second test based on the second bit error rate obtained in each test, where the second test is a test in which the difference between the obtained second bit error rate and the target bit error rate is the smallest;

[0060] The first device determines the second DSP mode targeted by the second test as the second target DSP mode.

[0061] Optionally, the SerDes transmitting end of the second device maintains a first mapping table, where the first mapping table is used to indicate a correspondence between the multiple first DSP modes and the multiple DSP parameters;

[0062] The process of configuring the SerDes transmitting end of the second device to the first target DSP mode by the second device includes:

[0063] The SerDes transmitting end of the second device determines the DSP parameters corresponding to the first target DSP mode based on the first mapping table;

[0064] The SerDes transmitting end of the second device completes the configuration of the SerDes transmitting end of the second device based on the DSP parameters corresponding to the first target DSP mode.

[0065] Optionally, the SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and the plurality of DSP parameters;

[0066] The first device configures the SerDes receiving end of the first device to the second target DSP mode, including:

[0067] The SerDes receiving end of the first device determines the DSP parameters corresponding to the second target DSP mode based on the second mapping table;

[0068] The SerDes receiving end of the first device completes the configuration of the SerDes receiving end of the first device based on the DSP parameters corresponding to the second target DSP mode.

[0069] In a third aspect, a DSP mode configuration device is provided, which includes at least one functional module, and the at least one functional module is used to execute the DSP mode configuration method provided by the first aspect or any possible implementation of the first aspect.

[0070] In a fourth aspect, a data transmission device is provided, which includes a SerDes and a high-speed serial interface controller. The SerDes receiving end supports multiple DSP modes, the SerDes transmitting end supports multiple DSP modes, and the high-speed serial interface controller is used to control the DSP modes of the SerDes receiving end and the SerDes transmitting end.

[0071] In a fifth aspect, a communication system is provided, comprising a first device and a second device, wherein a receiving end of a SerDes of the first device supports multiple second DSP modes, and a transmitting end of a SerDes of the second device supports multiple first DSP modes;

[0072] The second device is configured to send, to the first device, a plurality of first DSP modes supported by a SerDes transmitting end of the second device;

[0073] The first device is used to:

[0074] Acquire multiple first DSP modes supported by a SerDes transmitter of the second device;

[0075] Based on the multiple first DSP modes, perform at least one test on a first data transmission direction of a link between the first device and the second device, and determine a first bit error rate for each test, the first bit error rate being a bit error rate for the first data transmission direction of the link under the first DSP mode for each test, the first data transmission direction being a direction from the second device to the first device;

[0076] determining a first target DSP mode of the second device based on a first bit error rate obtained in each test;

[0077] sending the first target DSP mode to the second device;

[0078] The second device is further used for:

[0079] The SerDes transmitting end of the second device is configured to the first target DSP mode.

[0080] Optionally, the SerDes receiving end of the first device supports multiple second DSP modes, and the first device is further configured to:

[0081] Based on the multiple second DSP modes, perform at least one test on the first data transmission direction of the link, and determine a second bit error rate for each test, where the second bit error rate is a bit error rate for the first data transmission direction of the link under the second DSP mode targeted by each test;

[0082] determining a second target DSP mode of the first device based on a second bit error rate obtained in each test;

[0083] The SerDes receiving end of the first device is configured to the second target DSP mode.

[0084] Optionally, the first device is used to:

[0085] The first training stream block TSB sent by the second device through the SerDes transmitting end of the second device is received through the SerDes receiving end of the first device, where the first TSB carries the multiple first DSP modes.

[0086] Optionally, the first device is used to:

[0087] Sending a second TSB to the SerDes receiving end of the second device through the SerDes transmitting end of the first device, where the second TSB carries the first DSP mode targeted by this test;

[0088] Based on the second TSB, configuring the SerDes transmitter of the second device to the first DSP mode targeted by this test;

[0089] Returning a third TSB to the SerDes receiving end of the first device through the SerDes transmitting end of the second device, where the third TSB carries feedback information of the SerDes transmitting end of the second device on the second TSB;

[0090] Acquire the third TSB through the SerDes receiving end of the first device;

[0091] If the feedback information indicates that the SerDes transmitter of the second device accepts the test, determining a bit error rate of the test;

[0092] If the feedback information indicates that the SerDes transmitter of the second device rejects the current test, the next test is performed on the first data transmission direction of the link.

[0093] Optionally, the first device is used to:

[0094] Configuring the SerDes receiving end of the first device to the second DSP mode targeted by this test;

[0095] Determine the second bit error rate for each test.

[0096] Optionally, the first device is used to:

[0097] Determining a first test based on a first bit error rate obtained in each test, where the first test is a test in which a difference between the obtained first bit error rate and a target bit error rate is minimized;

[0098] The first DSP mode targeted by the first test is determined as the first target DSP mode.

[0099] Optionally, the first device is used to:

[0100] Determining a second test based on the second bit error rate obtained in each test, where the second test is a test in which a difference between the obtained second bit error rate and a target bit error rate is minimized;

[0101] The second DSP mode targeted by the second test is determined as the second target DSP mode.

[0102] Optionally, the SerDes transmitting end of the second device maintains a first mapping table, where the first mapping table is used to indicate a correspondence between the multiple first DSP modes and the multiple DSP parameters;

[0103] The second device is used to:

[0104] Determining, by the SerDes transmitting end of the second device based on the first mapping table, DSP parameters corresponding to the first target DSP mode;

[0105] The configuration of the SerDes transmitting end of the second device is completed through the SerDes transmitting end of the second device based on the DSP parameters corresponding to the first target DSP mode.

[0106] Optionally, the SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and the plurality of DSP parameters;

[0107] The first device is used to:

[0108] Determining, by the SerDes receiving end of the first device based on the second mapping table, DSP parameters corresponding to the second target DSP mode;

[0109] The configuration of the SerDes receiving end of the first device is completed based on the DSP parameters corresponding to the second target DSP mode through the SerDes receiving end of the first device.

[0110] In a sixth aspect, a storage medium is provided, in which at least one program code is stored. The at least one program code can be read and executed by a first device to implement the DSP mode configuration method provided in the first aspect or any optional method of the first aspect.

[0111] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] FIG1 is a schematic diagram of a communication system 100 provided in an embodiment of the present application;

[0113] FIG2 is a schematic diagram of a plurality of chip interconnections provided in an embodiment of the present application;

[0114] FIG3 is a schematic structural diagram of a communication device 101 provided in an embodiment of the present application;

[0115] FIG4 is a schematic diagram of a TSB data structure provided in an embodiment of the present application;

[0116] FIG5 is a flow chart of a DSP mode configuration method provided in an embodiment of the present application;

[0117] FIG6 is a schematic diagram of a first chip and a second chip provided in an embodiment of the present application;

[0118] FIG7 is a flow chart of a DSP mode configuration method provided in an embodiment of the present application;

[0119] FIG8 is a flowchart of a DSP mode configuration method provided in an embodiment of the present application;

[0120] FIG9 is a structural diagram of a DSP mode configuration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0121] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0122] First, the implementation environment of this application is introduced.

[0123] FIG1 is a schematic diagram of a communication system 100 provided in an embodiment of the present application. As shown in FIG1 , the communication system 100 includes a plurality of communication devices 101. The communication device 101 may be a device having a network communication function, such as a computing device, a network device, or a terminal device, and the embodiment of the present application does not limit this. The communication device 101 includes at least one chip, on which at least one high-speed serial interface is integrated. The chips in different communication devices 101 can be interconnected through the high-speed serial interface to realize data transmission between the plurality of communication devices 101 in the communication system. The high-speed serial interface may be an input / output (IO) interface, a peripheral component interconnect express (PCIe) interface, or an Ethernet interface, and the embodiment of the present application does not limit this.

[0124] The chip may be a general-purpose central processing unit (CPU), a network processor (NP), a neural processing unit (NPU), a network card chip, a disk chip, or a microprocessor, or may be one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0125] For example, FIG2 is a schematic diagram of a plurality of chip interconnections provided by an embodiment of the present application. FIG2 shows a plurality of chips 201. Among the plurality of chips 201, two chips 201 communicate with each other through a high-speed serial interface on the chip. As shown in FIG2 , taking chip 201 as a CPU as an example, the chip 201 includes chip components such as a central processing unit core (CPU core), memory, a direct memory access controller (DMAC), and at least one high-speed serial interface. These chip components communicate through a system bus on the chip. The high-speed serial interface includes a high-speed serial interface controller (IO controller) and a SerDes.

[0126] The SerDes (SerDes) in this high-speed serial interface includes a SerDes transmitter (TX) and a SerDes receiver (RX). Both the SerDes transmitter and the SerDes receiver include a DSP. The DSP in the SerDes transmitter is used to equalize the signal to be transmitted, while the DSP in the SerDes receiver is used to equalize the received signal to compensate for insertion loss during signal transmission in the link. Exemplarily, in communication device A, the high-speed serial interface controller a1 encapsulates the data to be transmitted to communication device B according to the data transmission protocol to obtain a data packet to be transmitted, and sends the data packet to the SerDes transmitter a2 in the form of a parallel signal; the SerDes transmitter a2 converts the parallel signal into a serial signal, performs equalization processing on the serial signal through the DSP in the SerDes transmitter a2, and sends the equalized serial signal to the SerDes receiver b2 of communication device B; in communication device B, the SerDes receiver b2 performs equalization processing on the received serial signal through the DSP, converts the equalized serial signal into a parallel signal, and sends the parallel signal to the high-speed serial interface controller b1; the high-speed serial interface controller b1 parses the parallel signal to extract the data transmitted by communication device A from the data packet.

[0127] The structure of the communication device 101 is described below. FIG3 is a schematic diagram of the structure of a communication device 101 provided in an embodiment of the present application. As shown in FIG3 , the communication device 101 includes at least one chip 1011 , a communication bus 1012 , and a memory 1013 .

[0128] The chip 1011 has been described in the above implementation environment and will not be described in detail here.

[0129] Communication bus 1012 is used to transmit information between components such as chip 1011 and memory 1013. Communication bus 1012 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0130] Among them, the memory 1013 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a communication device, but is not limited to this. The memory 1013 can exist independently and be connected to the chip 1011 via the communication bus 1012. The memory 1013 can also be integrated with the chip 1011.

[0131] In a specific implementation, as an embodiment, the communication device 101 may include multiple chips 1011. Each of these chips may be a single-core processor or a multi-core processor. The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as program code).

[0132] In a specific implementation, as an embodiment, the memory 1013 is used to store program codes for executing the embodiments of the present application, and the chip 1011 can execute the program codes stored in the memory 1013. That is, the communication device 101 can implement the DSP mode configuration method provided in the embodiments of Figures 5, 7, and 8 below by executing the program codes in the memory 1013 through the chip 1011.

[0133] An embodiment of the present application provides a DSP mode configuration method, in which the SerDes transmitter of the second device supports multiple first DSP modes. After the first device obtains the multiple first DSP modes, based on the multiple first DSP modes, the data transmission direction from the second device to the first device on the link between the first device and the second device is tested at least once, and the bit error rate (first bit error rate) of the first DSP mode targeted by each test is determined. The first bit error rate can evaluate whether the tested DSP mode matches the insertion loss of the link. The first device determines a first target DSP mode among the multiple first DSP modes based on the first bit error rate obtained in each test, and sends the first target DSP mode to the second device to instruct the second device to configure the SerDes transmitter of the second device to the first target DSP mode. Since the DSP mode is adjustable and the determined DSP mode matches the insertion loss of the link, the problem of DSP overperformance caused by adopting a DSP mode with too high performance can be avoided, and the problem of increased SerDes power consumption and latency caused by the DSP mode with too high performance can be avoided.

[0134] The first device and the second device in the above method can be two communication devices that transmit data based on a high-speed serial interface, or two chips that are interconnected based on a high-speed serial interface, etc. The embodiments of this application do not limit the specific form of the first device and the second device. The following example uses the first device as a first chip and the second device as a second chip as an example, and data is transmitted between the first chip and the second chip based on a high-speed serial interface.

[0135] The direction from the second chip to the first chip on the link between the first chip and the second chip is called the first data transmission direction, and the direction from the first chip to the second chip is called the second data transmission direction. Before the first chip and the second chip communicate through the link, the first chip and the second chip negotiate through the TSB to configure the parameters for communication between the first chip and the second chip. The parameters in the first data transmission direction include the DSP mode of the SerDes receiving end of the first chip and the DSP mode of the SerDes transmitting end of the second chip, and the parameters in the second data transmission direction include the DSP mode of the SerDes receiving end of the second chip and the DSP mode of the SerDes transmitting end of the first chip.

[0136] In the above method, the first chip and the second chip negotiate through a training set block (TSB) to complete the configuration process of the DSP mode. The following is an introduction to a TSB provided in an embodiment of the present application. Figure 4 is a schematic diagram of a TSB data structure provided in an embodiment of the present application. As shown in Figure 4, a TSB data structure includes at least one of a TSB identification field, a payload field (payload), and a check field. Among them, the TSB identification field is used to indicate that the data packet is a TSB; the payload field is used to carry negotiation information, and the negotiation information includes at least one of: supported DSP modes, control information (including a request for a DSP mode test and the DSP mode targeted by this test), and feedback information (including receiving this DSP mode test and rejecting this DSP mode test). The length of the payload field can be any value, and the embodiment of the present application does not limit this; the check field is used to carry check information, which is used to check whether the TSB is erroneous and to recover the TSB if the TSB is erroneous. In some embodiments, a cyclic redundancy check (CRC) is used on the TSB, and the check information in the TSB is the cyclic redundancy check code of the TSB. Those skilled in the art may adopt other check methods according to actual needs to generate other check information. The embodiments of the present application do not limit the check information.

[0137] Table 1 below is a schematic diagram of an implementation example of a TSB provided in an embodiment of the present application. The TSB shown in Table 1 includes multiple fields (symbol0-symbol15), each field occupies 1 byte, and the meaning of each symbol is shown in Table 1 below. As shown in Table 1, the symbol0 field is used to carry the TSB identifier. The value of this field is 0xA0, indicating that the data packet is a TSB; the symbol1 field is used to carry the supported DSP mode. The symbol includes 8 bits, each bit corresponds to a DSP mode. For example, bit0 corresponds to DSP mode 0. When the value of bit0 is 1, it indicates that DSP mode 0 is supported. The same applies to other bits in symbol1, which will not be repeated here. The symbol2 field is used to carry control information. The value of bit0-bit3 in symbol2 is 0000, indicating no command (no commond), the value of 0001 indicates a request for DSP mode adjustment of the transmitter (TX DSP adjust REQ), and the value of 0010 indicates acceptance of DSP mode adjustment of the transmitter (TX DSP adjust The symbol field is used to carry the DSP mode for this adjustment. The values ​​of bits 0-3 in symbol3 are 0000-0111, indicating DSP modes 0-7, respectively. A value of 1000 indicates no command. Bits 4-7 are reserved and can be used to carry other information. Symbols 4-13 are reserved and can be used to carry other information. Symbols 14 and 15 are used to carry CRC checksum information for symbol 1-symbol 3. Symbols 1-13 are also the payload field.

[0138] Table 1

[0139] It should be noted that the TSB instance shown in Table 1 above is only exemplary. Those skilled in the art can define the TSB instance according to actual needs based on the TSB data structure provided in the embodiment of the present application. The embodiment of the present application does not limit the specific implementation form of the TSB.

[0140] The following describes in detail the process of a DSP mode configuration method provided in an embodiment of the present application, taking the first data transmission direction of a link between a first chip and a second chip as an example. In this method, the first chip can perform DSP mode configuration for the data transmission direction from the second chip to the first chip on the link between the first chip and the second chip, including configuring at least one of the DSP mode of the SerDes transmitter of the second chip and the DSP mode of the SerDes receiver of the first chip.

[0141] In some embodiments, the configuration strategy of the first chip for the first data transmission direction of the link is: if the SerDes receiving end of the first chip only supports one DSP mode or the SerDes receiving end of the first chip supports multiple DSP modes and the DSP mode is set to fixed, and the SerDes transmitting end of the second chip supports multiple DSP modes and is not set to fixed DSP mode, then the first chip only configures the DSP mode of the SerDes transmitting end of the second chip; if the SerDes receiving end of the first chip supports multiple DSP modes and is not set to fixed DSP mode, and the SerDes transmitting end of the second chip only supports one DSP mode or the SerDes transmitting end of the second chip supports multiple DSP modes and the DSP mode is set to fixed, then the first chip only configures the DSP mode of the SerDes receiving end of the first chip; if both the SerDes receiving end of the first chip and the SerDes transmitting end of the second chip support multiple DSP modes and neither is set to fixed DSP mode, then the first chip configures the DSP mode of both the SerDes transmitting end of the second chip and the SerDes receiving end of the first chip. The manner in which the first chip determines the DSP mode supported by the SerDes receiving end of the first chip and the DSP mode supported by the SerDes transmitting end of the second chip will be described in subsequent embodiments and will not be repeated here. It should be noted that the above embodiment is only an exemplary description of the configuration strategy of the first chip for the first data transmission direction of the link. Those skilled in the art can set other configuration strategies according to actual needs, and the embodiments of this application do not limit this.

[0142] The above method will be introduced below using the following examples: the first chip is configured with only the DSP mode of the SerDes transmitter of the second chip, the first chip is configured with only the DSP mode of the SerDes receiver of the first chip, and the first chip is configured with both the DSP mode of the SerDes transmitter of the second chip and the DSP mode of the SerDes receiver of the first chip.

[0143] First, the example of a first chip configuring only the DSP mode of the SerDes transmitter of the second chip is introduced. FIG5 is a flowchart of a DSP mode configuration method provided by an embodiment of the present application. As shown in FIG5 , this embodiment takes the interaction between the first chip and the second chip as an example and includes the following steps 501 to 512.

[0144] 501. The second chip sends a first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. The first TSB carries multiple first DSP modes supported by the SerDes transmitting end of the second chip.

[0145] The timing when the second chip sends the first TSB to the first chip includes any of the following. In some embodiments, the second chip sends the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip in response to the initialization of the communication device where the second chip is located. In some embodiments, the first chip sends a TSB for acquiring the multiple first DSP modes to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip in response to the initialization of the communication device where the first chip is located; after the second chip receives the TSB, it sends the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. In some embodiments, the second chip detects the link between the first chip and the second chip, and when it detects that the communication device where the first chip is located on the opposite side of the link is online, it sends the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. In other embodiments, the first chip detects the link between the first chip and the second chip, and only sends a TSB for acquiring the multiple first DSP modes to the SerDes receiver of the second chip via the SerDes transmitter of the first chip when it detects that the communication device where the second chip on the opposite side of the link is online. In the above embodiment, the TSB is sent to the chip on the opposite side of the link only when the communication device where the chip on the opposite side of the link is online, which can avoid TSB reception failure caused by the communication device on the opposite side being offline, thereby improving the negotiation efficiency between the first chip and the second chip.

[0146] In some embodiments, the configuration file of the second chip records multiple first DSP modes supported by the SerDes transmitter of the second chip, and the high-speed serial interface controller of the second chip reads the multiple first DSP modes from the configuration file. In other embodiments, the first register of the high-speed serial interface controller of the second chip stores the multiple first DSP modes, and the high-speed serial interface controller of the second chip reads the multiple first DSP modes from the first register. In some further embodiments, the SerDes transmitter of the second chip maintains and stores a first mapping table, which is used to indicate the correspondence between multiple first DSP modes and multiple DSP parameters. The SerDes transmitter of the second chip reads the multiple first DSP modes in the first mapping table and sends the multiple first DSP modes to the high-speed serial interface controller of the second chip. Among them, the multiple first DSP modes are, for example, LR, MR, SR, and XSR, etc. The embodiments of the present application do not limit the DSP mode.

[0147] Among them, the high-speed serial interface controller of the second chip generates the first TSB based on the multiple first DSP modes. The TSB identification field of the first TSB indicates that the data packet is a TSB; the payload field of the first TSB is used to carry the multiple first DSP modes supported by the SerDes transmitter of the second chip; the check field of the first TSB is used to carry the check information of the first TSB. For example, taking the first TSB using the TSB instance shown in Table 1 and the multiple first DSP modes including LR, MR, SR and XSR as an example, the value of symbol0 of the first TSB is 0xA0, indicating that the data packet is a TSB; the value of each bit in symbol1 of the first TSB corresponds to a DSP mode, the value of bit0 is 1, indicating that the LR mode is supported, the value of bit1 is 1, indicating that the MR mode is supported, the value of bit2 is 1, indicating that the SR mode is supported, the value of bit3 is 1, indicating that the XSR mode is supported, and the values ​​of the remaining bits are is 0, that is, the value of symbol1 of the first TSB is 11110000; the value of bit0-bit3 in symbol2 of the first TSB is 0000, indicating that there is no command, only declaring the supported DSP mode, and the value of the remaining bits is 0; the value of bit0-bit3 in symbol3 of the first TSB is 1000, indicating that there is no command; symbol4-13 of the first TSB are default values; symbol15 field and symbol15 field are CRC check information of symbol1-symbol3 fields. It should be noted that the above description of the first TSB is exemplary and does not limit the first TSB.

[0148] Among them, the high-speed serial interface controller of the second chip sends the generated first TSB in the form of a parallel signal to the SerDes transmitter of the second chip; the SerDes transmitter of the second chip converts the data packet in the form of the parallel signal into a serial signal, and uses the DSP in the SerDes transmitter of the second chip to equalize the serial signal, and sends the equalized serial signal to the SerDes receiver of the first chip.

[0149] The process shown in step 501 above is illustrated below with reference to FIG6 . FIG6 is a schematic diagram of a first chip and a second chip provided in an embodiment of the present application. As shown in FIG6 , FIG6 includes a first chip 601 and a second chip 602. The first chip 601 includes a high-speed serial interface controller 6011 and a SerDes 6012. The high-speed serial interface controller 6011 includes a TSB analysis module (TSB_CHECK), a bit error rate monitoring module (BER_MONITOR), a DSP mode control module (DSP_CTRL), and a TSB generation module (TSB_GEN). The SerDes 6012 includes a SerDes transmitter (TX_DSP) and a SerDes receiver (RX_DSP). The second chip 602 includes a high-speed serial interface controller 6021 and a SerDes 6022. The structures of the high-speed serial interface controller 6021 and the SerDes 6022 are similar to those of the high-speed serial interface controller 6011 and the SerDes 6012, and are not described in detail. The DSP mode control module in the high-speed serial interface controller 6021 obtains multiple first DSP modes supported by the SerDes transmitter of the second chip from the configuration file of the high-speed serial interface controller 6021, and sends the multiple first DSP modes to the TSB generation module in the high-speed serial interface controller 6021; the TSB generation module in the high-speed serial interface controller 6021 generates the first TSB based on the multiple first DSP modes, and sends the first TSB to the transmitter of SerDes 6022; the transmitter of SerDes 6022 sends the first TSB to the receiver of SerDes 6012. It should be noted that the functional module division method of the high-speed serial interface controllers of the first chip and the second chip in Figure 6 is only exemplary. Those skilled in the art can divide the functional modules in Figure 6 into more or fewer functional modules according to actual needs, and the embodiments of the present application do not limit this.

[0150] 502. The first chip receives the first TSB through a SerDes receiving end of the first chip.

[0151] The SerDes receiver of the first chip receives a serial signal from the SerDes transmitter of the second chip. The SerDes receiver of the first chip performs equalization processing on the received serial signal through the DSP of the SerDes receiver of the first chip, converts the equalized serial signal into a parallel signal, and sends the parallel signal to the high-speed serial interface controller of the first chip. The high-speed serial interface controller of the first chip identifies the parallel signal as a TSB based on the TSB identification field in the parallel signal. The high-speed serial interface controller of the first chip parses the TSB and reads each field of the TSB to obtain the negotiation information carried by the TSB. Exemplarily, continuing with the example of the first TSB in step 501, the high-speed serial interface controller of the first chip reads 11110000 from the symbol1 field of the first TSB, and obtains that the first DSP mode supported by the SerDes transmitter of the second chip is LR, MR, SR and XSR, and reads 0000 from bit0-bit3 of the symbol2 field of the first TSB, and obtains that the first TSB is only used to declare the supported DSP mode, and reads 1000 from bit0-bit3 of the symbol3 field of the first TSB, indicating that there is no DSP mode adjustment command, and reads CRC check information of the symbol1-symbol3 fields of the TSB from the symbol15 field and symbol15 field of the first TSB.

[0152] In some embodiments, the high-speed serial interface controller of the first chip reads a check field in the first TSB to obtain check information for the first TSB, and checks other fields of the first TSB based on the check information of the first TSB. If the check fails, the other fields are restored based on the check information and the restored other fields are read; if the check passes, the other fields are directly read. The process of the high-speed serial interface controller of the first chip checking other fields of the first TSB based on the check information of the first TSB includes: generating check information for other fields of the first TSB; comparing the check information read from the check field of the first TSB with the generated check information; if they are inconsistent, the check fails; if they are consistent, the check passes.

[0153] 6 is used as an example to illustrate the process shown in step 502. SerDes 6012 receives the first TSB, converts the first TSB from a serial signal to a parallel signal, and sends the first TSB in the form of a parallel signal to the TSB parsing module in the high-speed serial interface controller 6011. The TSB parsing module parses the first TSB to obtain the multiple first DSP modes. The TSB parsing module sends the multiple first DSP modes to the DSP mode control module in the high-speed serial interface controller 6011.

[0154] 503. Based on the multiple first DSP modes indicated by the first TSB, the first chip sends a second TSB to the SerDes receiver of the second chip through the SerDes transmitter of the first chip. The second TSB carries the first DSP mode targeted by the first test. The second TSB is used to instruct the second chip to configure the SerDes transmitter of the second chip to the first DSP mode targeted by the first test.

[0155] The high-speed serial interface controller of the first chip determines a first DSP to be tested based on multiple first DSP modes. In some embodiments, all of the multiple first DSP modes are DSP modes to be tested, meaning that all DSP modes supported by the SerDes transmitter of the second chip are tested. In other embodiments, some of the multiple first DSP modes are DSP modes to be tested, meaning that some of the DSP modes supported by the SerDes transmitter of the second chip are tested. For example, if the first chip records a first DSP mode that the second chip refused to test during a previous negotiation, the first chip ignores this first DSP mode in the current negotiation. In other words, the first DSP modes to be tested in the current negotiation do not include the first DSP mode that the second chip refused to test during the previous negotiation, thereby improving the efficiency of the current negotiation. For another example, if the first TSB indicates an unavailable first DSP mode among the multiple first DSP modes, the first chip ignores this unavailable first DSP mode in the current negotiation. In other words, the first DSP modes to be tested in the current negotiation do not include this unavailable first DSP mode. "Unavailable" refers to a hardware failure associated with the first DSP mode or the first DSP mode being disabled. The DSP mode to be tested may also be determined in other ways, which is not limited in the embodiments of the present application.

[0156] Among them, the first chip tests the first DSP mode in the first DSP mode to be tested in sequence. In some embodiments, the first chip tests the first DSP mode to be tested in the order of the performance of the first DSP mode to be tested. For example, the first DSP mode to be tested is tested in the order of the performance of the first DSP mode from high to low; for another example, the first DSP mode to be tested is tested in the order of the performance of the first DSP mode from low to high. In other embodiments, the first chip selects the first DSP mode for the next test according to the test result of the first DSP mode for the previous test, wherein the method of selecting the first DSP mode for the next test based on the test result of the previous test will be introduced later and will not be repeated here. The embodiment of the present application does not limit the test order of the first DSP mode to be tested.

[0157] The high-speed serial interface controller of the first chip generates a second TSB based on the first DSP mode to be tested. The TSB identification field of the second TSB is used to indicate that the data packet is a TSB; the payload field of the second TSB is used to carry control information for the first test, where the control information for the first test includes a request for a DSP mode test and the first DSP mode targeted by the first test; and the checksum field of the second TSB is used to carry checksum information for the second TSB. For example, taking the second TSB using the TSB instance shown in Table 1 and the first DSP mode targeted by the first test as LR, the value of symbol0 of the second TSB is 0xA0, indicating that the data packet is a TSB; the value of each bit in symbol1 of the second TSB is 0; the value of bit0-bit3 in symbol2 of the second TSB is 0001, indicating a request to adjust the DSP mode of the transmitter, and the value of the remaining bits is 0; the value of bit0-bit3 in symbol3 of the second TSB is 0001, indicating that the DSP mode targeted by this adjustment is LR; symbols4-13 of the first TSB are default values; symbol14 and symbol15 are CRC check information of symbol1-symbol3. It should be noted that the above description of the second TSB is exemplary and does not limit the second TSB.

[0158] The process of the first chip sending the second TSB to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip is the same as the process of the second chip sending the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip in step 501, and will not be repeated here.

[0159] 6 is used as an example to illustrate the process shown in step 503. The DSP mode control module in the high-speed serial interface controller 6011 sends the first DSP mode targeted by the first test to the TSB generation module. The TSB generation module generates a second TSB based on the first DSP mode and sends the second TSB to the SerDes transmitter in SerDes 6012. The SerDes transmitter in SerDes 6012 sends the second TSB to the SerDes receiver in SerDes 6012.

[0160] 504. The second chip receives the second TSB through the SerDes receiving end of the second chip.

[0161] The process of the second chip receiving the second TSB through the SerDes receiving end of the second chip is similar to the process of the first chip receiving the first TSB through the SerDes receiving end of the first chip in step 502, and will not be repeated here.

[0162] 505. The second chip configures the SerDes transmitter of the second chip to the first DSP mode targeted by the first test.

[0163] Among them, if the first DSP mode targeted by the first test carried by the second TSB is one of the multiple first DSP modes supported by the SerDes transmitter of the second chip, the second chip configures the SerDes transmitter of the second chip to the first DSP mode targeted by the first test, that is, the high-speed serial interface controller of the second chip accepts the first test.

[0164] The SerDes transmitter of the second chip maintains and stores a first mapping table, where the first mapping table is used to indicate a correspondence between a plurality of first DSP modes and a plurality of DSP parameters. In some embodiments, the first mapping table is stored in a register of the SerDes transmitter of the second chip. The embodiments of the present application do not limit the storage location of the first mapping table.

[0165] Among them, the process of the second chip configuring the SerDes transmitter of the second chip to the first DSP mode targeted by the first test includes: the SerDes transmitter of the second chip determines the DSP parameters corresponding to the first DSP mode targeted by the first test based on the first mapping table; the SerDes transmitter of the second chip completes the configuration of the SerDes transmitter of the second chip based on the DSP parameters corresponding to the first DSP mode targeted by the first test.

[0166] In some embodiments, the SerDes transmitter of the second chip includes multiple filters, each filter has a different order, and filters of different orders correspond to different first DSP modes. The DSP parameter is the filter order, and the first mapping table is used to maintain the mapping relationship between multiple first DSP modes and filter orders. The SerDes transmitter of the second chip determines the first filter order based on the first mapping table. The first filter order is the filter order corresponding to the first DSP mode targeted by the first test, and the filter of the DSP of the SerDes transmitter of the second chip is switched to the first filter. The order of the first filter is the first filter order, so as to complete the configuration of the SerDes transmitter of the second chip as the first DSP mode targeted by the first test. It should be noted that the above description of the DSP parameter as the filter order is only exemplary. In some embodiments, the DSP parameter can also be other parameters related to the DSP mode configuration, and the embodiments of the present application do not limit this.

[0167] 506. The second chip generates a third TSB and sends the third TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. The third TSB carries the first feedback information of the second chip on the second TSB. The first feedback information indicates that the second chip accepts the first test on the SerDes transmitting end of the second chip.

[0168] Among them, the TSB identification field of the third TSB is used to indicate that the data packet is a TSB; the payload field of the third TSB is used to carry the first feedback information; and the check field of the third TSB is used to carry the check information of the third TSB. For example, taking the TSB example shown in Table 1 as an example, the value of symbol0 of the third TSB is 0xA0, indicating that the data packet is a TSB; the value of each bit in symbol1 of the third TSB is 0; the value of bit0-bit3 in symbol2 of the second TSB is 0010, indicating that the DSP mode adjustment of the transmitter is accepted, and the value of the remaining bits is 0; the value of bit0-bit3 in symbol3 of the third TSB is 0001, indicating that the DSP mode for this adjustment is LR; symbols4-13 of the third TSB are default values; symbol14 and symbol15 are CRC check information of symbol1-symbol3. It should be noted that the above description of the third TSB is exemplary and does not limit the third TSB.

[0169] The process of the second chip sending the third TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip is the same as the process of the second chip sending the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip in step 501, and will not be repeated here.

[0170] It should be noted that the above steps 505 and 506 are described using the example of the second chip accepting the first test. In some embodiments, if the first DSP mode targeted by the first test carried by the second TSB is not one of the multiple first DSP modes supported by the SerDes transmitter of the second chip, the second chip does not execute the above steps 505 and 506, but generates a TSB that carries second feedback information. The second feedback information instructs the second chip to refuse to perform the first test on the SerDes transmitter of the second chip, and sends the TSB to the SerDes receiver of the first chip through the SerDes transmitter of the second chip.

[0171] It should be noted that the above steps 505 and 506 are described by taking the example of the high-speed serial interface controller of the second chip deciding whether to accept or reject the test based on whether the DSP mode targeted by the first test belongs to one of multiple first DSP modes. In some embodiments, the high-speed serial interface controller of the second chip can decide whether to accept or reject the test based on other methods. The embodiments of the present application do not limit the decision-making method.

[0172] 6 as an example, the process shown in the above steps 504 to 505 is described with an example. The SerDes receiving end in SerDes 6012 receives the second TSB and sends the second TSB to the TSB parsing module in the high-speed serial interface controller 6021. The TSB parsing module parses the second TSB to obtain the first DSP mode targeted by the first test carried by the second TSB. The TSB parsing module sends the first DSP mode to the DSP mode control module; the DSP mode control module receives the first DSP mode supported by the SerDes transmitting end of the second chip when the first DSP mode belongs to the first DSP mode. In the case of a DSP mode, the first DSP mode is sent to the SerDes transmitter in SerDes6012 to configure the SerDes transmitter to the first DSP mode, and the DSP mode control module sends the first feedback information for the first test to the TSB generation module; the TSB generation module generates a third TSB based on the first feedback information, and sends the third TSB to the SerDes transmitter in SerDes6022, and the SerDes transmitter in SerDes6022 sends the third TSB to the SerDes receiver in SerDes6012.

[0173] 507 . The first chip receives the third TSB through the SerDes receiving end of the first chip.

[0174] The process of the first chip receiving the third TSB through the SerDes receiving end of the first chip is similar to the process of the first chip receiving the first TSB through the SerDes receiving end of the first chip in step 502, and will not be repeated here.

[0175] 508. The first chip determines a first bit error rate of the first test, where the first bit error rate of the first test is a bit error rate of a first data transmission direction on a link between the first chip and the second chip in a first DSP mode targeted by the first test.

[0176] The high-speed serial interface controller of the first chip determines the first bit error rate of the first test when the first feedback information carried by the third TSB instructs the second chip to accept the first test.

[0177] In some embodiments, the first bit error rate is represented by a bit error rate (BER), which is used to indicate the proportion of erroneous bits in the transmitted binary data. The process of the high-speed serial interface controller of the first chip determining the first bit error rate of the first test includes: generating check information based on other fields in the third TSB except the check field; comparing the check information read from the check field of the third TSB with the generated check information to determine the number of erroneous bits in the third TSB; determining the bit error rate based on the number of erroneous bits and the total number of bits in the third TSB, and the bit error rate is also the first bit error rate of the first test. It should be noted that the above description of the method for determining the first bit error rate of the first test is only exemplary, and those skilled in the art can use other methods to determine the first bit error rate according to actual needs, and the embodiments of the present application are not limited to this.

[0178] Among them, the first bit error rate is the bit error rate of the third TSB after DSP processing in the SerDes receiving end of the first chip. The relationship between the first bit error rate and the target bit error rate can reflect whether the DSP performance of the first data transmission direction of the link can meet the requirements. The first bit error rate is greater than the target bit error rate and the larger the gap, the less the DSP performance of the first data transmission direction of the link can meet the requirements. The first bit error rate is less than the target bit error rate and the larger the gap, the more excessive the DSP performance of the first data transmission direction of the link. Among them, the target bit error rate can be a target bit error rate value, such as 1%, 0.5%, etc., or a target bit error rate range, such as 0.5% to 1.5%, etc. It should be noted that the above examples of target bit error rates are only exemplary. The target bit error rate can be set according to the requirements for DSP performance. The embodiments of the present application do not limit the target bit error rate.

[0179] It should be noted that the above step 508 is explained by taking the example of the first chip determining the first bit error rate of the first test when the feedback information carried by the TSB received by the first chip indicates that the second chip accepts the first test. In some embodiments, if the feedback information carried by the TSB received by the first chip indicates that the second chip rejects the first test, the first chip does not execute the above step 508, but executes the following step 509 to realize the next test of the first data transmission direction of the link.

[0180] Continuing with FIG6 as an example, the process shown in steps 507 and 508 will be described below. The SerDes receiving end in SerDes 6012 receives the third TSB and sends the third TSB to the TSB parsing module in the high-speed serial interface controller 6021. The TSB parsing module parses the third TSB to obtain first feedback information carried by the third TSB and sends the first feedback information to the DSP mode control module. When the first feedback information indicates that the second chip accepts the first test, the DSP mode control module determines the bit error rate in the direction from the second chip to the first chip through the bit error rate monitoring module in SerDes 6012 to obtain the first bit error rate of the first test. The DSP mode control module records the first DSP mode and the first bit error rate for the first test.

[0181] 509. Based on the multiple first DSP modes, the first chip performs the second to Nth tests on the first data transmission direction of the link in the same manner as steps 503 to 508 above, and determines the first bit error rate of each test, where N is the number of DSP modes supported by the SerDes transmitter of the second chip, and N is an integer greater than 1.

[0182] It should be noted that the above steps 503 to 509 are an implementation method based on multiple first DSP modes, in which the first data transmission direction of the link between the first chip and the second chip is tested at least once to determine the first bit error rate of each test. In some embodiments, the process is also implemented based on other methods, which is not limited in the embodiments of the present application.

[0183] 510. The first chip determines a first target DSP mode of the second chip based on a first bit error rate obtained in each test.

[0184] Among them, the process of the first chip determining the first target DSP mode includes: the high-speed serial interface controller of the first chip determines the first test based on the first bit error rate obtained in each test, and the first test is a test in which the difference between the obtained first bit error rate and the target bit error rate is the smallest; the high-speed serial interface controller of the first chip determines the first DSP mode targeted by the first test as the first target DSP mode.

[0185] In some embodiments, the register of the high-speed serial interface controller of the first chip records the first DSP mode targeted by each test and the corresponding first bit error rate; the high-speed serial interface controller of the first chip determines the first DSP mode targeted by the first test from the register, and determines the first DSP mode as the first target DSP mode.

[0186] It should be noted that the above steps 503 to 508 are described using an example test strategy in which the first chip first tests the first DSP mode to be tested one by one, and after completing all tests, determines the first target DSP mode based on the first bit error rate obtained in each test. Of course, other test strategies can also be used to determine the first target DSP mode of the second chip. For example, in some embodiments, the target bit error rate is a target bit error rate value. After each test, the first chip determines the difference between the first bit error rate obtained in the test and the target bit error rate. If the difference between the first bit error rate obtained in any test and the target bit error rate is less than a preset value, the test is terminated and the first DSP mode targeted by the test is determined as the first target DSP mode. For another example, in other embodiments, the target bit error rate is a target bit error rate range. After each test, the first chip determines whether the first bit error rate obtained in the test is within the target bit error rate range. If the first bit error rate obtained in any test is within the target bit error rate range, the test is terminated and the first DSP mode targeted by the test is determined as the first target DSP mode. For another example, in some other embodiments, after each test, the first chip determines the relationship between the first bit error rate obtained in this test and the target bit error rate, and based on this relationship, determines the first DSP mode for the next test. For example, if the first bit error rate obtained in this test is greater than the target bit error rate, it means that the DSP performance corresponding to the first DSP mode targeted by this test is insufficient, and the DSP performance corresponding to the first DSP mode selected for the next test should be higher than the performance corresponding to the first DSP mode selected for this test; if the first bit error rate obtained in this test is less than the target bit error rate, it means that the DSP performance corresponding to the first DSP mode targeted by this test is excessive, and the DSP performance corresponding to the first DSP mode selected for the next test should be lower than the performance corresponding to the first DSP mode selected for this test. The test strategy provided by any of the above embodiments can improve the efficiency of DSP mode testing and shorten the time of DSP mode testing. It should be noted that the test strategies provided in the above embodiments are only exemplary. Those skilled in the art can combine the above test strategies according to actual needs, or adopt other test strategies. The embodiments of the present application do not limit this.

[0187] 511. The first chip generates a fourth TSB, and sends the fourth TSB to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip, where the fourth TSB carries the first target DSP mode.

[0188] Among them, the TSB identification field of the fourth TSB is used to indicate that the data packet is a TSB; the payload field of the fourth TSB is used to carry control information, which includes a request for DSP mode configuration and the first target DSP mode; the check field of the fourth TSB is used to carry the check information of the fourth TSB.

[0189] The process of the first chip sending the fourth TSB to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip is the same as the process of the second chip sending the first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip in step 501, and will not be repeated here.

[0190] 512. The second chip receives the fourth TSB through the SerDes receiving end of the second chip, and configures the SerDes transmitting end of the second chip to the first target DSP mode.

[0191] In step 512, the process of the second chip receiving the fourth TSB through the SerDes receiving end of the second chip is similar to the process of the first chip receiving the first TSB through the SerDes receiving end of the first chip in step 502, and is not further described. In step 512, the process of the second chip configuring the SerDes transmitting end of the second chip to the first target DSP mode is similar to the process of the second chip configuring the SerDes transmitting end of the second chip to the first DSP mode targeted by the first test in step 505, and is not further described.

[0192] In the above method, the relationship between the first bit error rate and the target bit error rate can reflect whether the DSP performance of the first data transmission direction of the link can meet the requirements. The first bit error rate is greater than the target bit error rate and the larger the gap is, the less the DSP performance of the first data transmission direction of the link can meet the requirements. The first bit error rate is less than the target bit error rate and the smaller the gap is, the more excessive the DSP performance of the first data transmission direction of the link is. Therefore, the first DSP mode targeted by the test with the smallest difference between the first bit error rate and the target bit error rate is determined as the first target DSP mode. On the premise of meeting the requirements for DSP performance, it can avoid the problem of excessive DSP performance caused by adopting a DSP mode with too high performance, and thus avoid the problem of increased SerDes power consumption and delay caused by the DSP mode with too high performance.

[0193] The following describes a method for configuring a DSP mode for a first chip using only the SerDes receiving end of the first chip as an example. FIG7 is a flow chart illustrating a method for configuring a DSP mode according to an embodiment of the present application. The first chip includes a high-speed serial interface controller and a SerDes. As shown in FIG7 , the method is interactively executed by the high-speed serial interface controller of the first chip and the SerDes receiving end of the first chip as an example. The method includes the following steps 701 to 708.

[0194] 701. A SerDes receiving end of a first chip sends a plurality of second DSP modes supported by the SerDes receiving end of the first chip to a high-speed serial interface controller of the first chip.

[0195] Among them, the SerDes transmitting end of the first chip maintains and stores a second mapping table, which is used to indicate the correspondence between multiple second DSP modes and multiple DSP parameters. The SerDes receiving end of the first chip reads the multiple second DSP modes in the second mapping table and sends the multiple second DSP modes to the high-speed serial interface controller of the first chip.

[0196] It should be noted that step 701 is described using the example of the SerDes receiver of the first chip sending the multiple second DSP modes to the high-speed serial interface controller of the first chip. In some embodiments, the configuration file of the first chip records the multiple second DSP modes supported by the SerDes receiver of the first chip, and the high-speed serial interface controller of the first chip reads the multiple first DSP modes from the configuration file. In other embodiments, the multiple second DSP modes are stored in a second register of the high-speed serial interface controller of the first chip, and the high-speed serial interface controller of the first chip reads the multiple second DSP modes from the second register. This embodiment of the present application is not limited to this.

[0197] 702. The high-speed serial interface controller of the first chip sends the second DSP mode targeted by the first test to the SerDes receiving end of the first chip based on the multiple second DSP modes.

[0198] The high-speed serial interface controller of the first chip determines the second DSP mode to be tested based on the plurality of second DSP modes. The manner in which the high-speed serial interface controller of the first chip determines the second DSP mode to be tested and the order in which the second DSP modes to be tested are similar to those in step 503 above and are not further described.

[0199] 703. The SerDes receiving end of the first chip receives the second DSP mode targeted by the first test, and configures the SerDes receiving end of the first chip to the second DSP mode.

[0200] The SerDes receiving end of the first chip maintains and stores a second mapping table, which is used to indicate the correspondence between multiple second DSP modes and multiple DSP parameters. In some embodiments, the first mapping table is stored in a register of the SerDes transmitting end of the second chip. The embodiments of the present application do not limit the storage location of the first mapping table.

[0201] Among them, the process of the first chip configuring the SerDes receiver of the first chip to the second DSP mode targeted by the first test includes: the SerDes receiver of the first chip determines the DSP parameters corresponding to the second DSP mode targeted by the first test based on the second mapping table; the SerDes receiver of the first chip completes the configuration of the SerDes receiver of the first chip based on the DSP parameters corresponding to the second DSP mode targeted by the first test.

[0202] In some embodiments, the SerDes receiving end of the first chip includes multiple filters, each filter has a different order, and filters of different orders correspond to different second DSP modes. The DSP parameter is the filter order, and the second mapping table is used to maintain the mapping relationship between multiple second DSP modes and filter orders. The SerDes receiving end of the first chip determines the second filter order based on the second mapping table. The second filter order is the filter order corresponding to the second DSP mode targeted by the first test, and the filter of the DSP of the SerDes receiving end of the first chip is switched to the second filter. The order of the second filter is the second filter order, so as to complete the configuration of the SerDes transmitting end of the first chip to the second DSP mode targeted by the first test. It should be noted that the above description of the DSP parameter as the filter order is only exemplary. In some embodiments, the DSP parameter can also be other parameters related to the DSP mode configuration, and the embodiments of the present application do not limit this.

[0203] 704. The high-speed serial interface controller of the first chip determines a second bit error rate of the first test, where the second bit error rate is a bit error rate of the first data transmission direction of the link between the first chip and the second chip in the second DSP mode targeted by the first test.

[0204] The process of the first chip determining the second bit error rate of the first test is similar to the process of the first chip determining the first bit error rate of the first test in step 508, and will not be repeated herein.

[0205] 705. The high-speed serial interface controller of the first chip performs the second to Mth tests on the first data transmission direction of the link based on the multiple second DSP modes in a manner similar to steps 702 to 704 above, and determines the second bit error rate of each test, where M is the number of DSP modes supported by the SerDes receiving end of the first chip, and M is an integer greater than 1.

[0206] It should be noted that the above steps 702 to 705 are an implementation method based on multiple second DSP modes, performing at least one test on the first data transmission direction of the link to determine the second bit error rate of each test. In some embodiments, this process is also implemented based on other methods, which is not limited in the embodiments of the present application.

[0207] 706. The high-speed serial interface controller of the first chip determines a second target DSP mode of the first chip based on the second bit error rate obtained in each test.

[0208] Among them, the process of the first chip determining the second target DSP mode includes: the high-speed serial interface controller of the first chip determines a second test based on the second bit error rate obtained in each test, and the second test is a test in which the difference between the obtained second bit error rate and the target bit error rate is the smallest; the high-speed serial interface controller of the first chip determines the second DSP mode targeted by the second test as the second target DSP mode.

[0209] In some embodiments, the register of the high-speed serial interface controller of the first chip records the second DSP mode targeted by each test and the corresponding second bit error rate; the high-speed serial interface controller of the first chip determines the second DSP mode targeted by the second test from the register, and determines the second DSP mode as the second target DSP mode.

[0210] It should be noted that the above steps 702 to 706 are described using an example test strategy in which the first chip first tests the second DSP mode to be tested one by one, and after completing all tests, determines the second target DSP mode based on the second bit error rate obtained in each test. Of course, other test strategies can also be used to determine the first target DSP mode of the second chip. For example, in some embodiments, the target bit error rate is a target bit error rate value. After each test, the first chip determines the difference between the second bit error rate obtained in the current test and the target bit error rate. If the difference between the second bit error rate obtained in any test and the target bit error rate is less than a preset value, the test is terminated and the second DSP mode targeted by the test is determined as the second target DSP mode. For another example, in other embodiments, the target bit error rate is a target bit error rate range. After each test, the first chip determines whether the second bit error rate obtained in the current test is within the target bit error rate range. If the second bit error rate obtained in any test is within the target bit error rate range, the test is terminated and the second DSP mode targeted by the test is determined as the second target DSP mode. For another example, in some other embodiments, after each test, the first chip determines the relationship between the second bit error rate obtained in this test and the target bit error rate, and based on the relationship, determines the second DSP mode for the next test. For example, if the second bit error rate obtained in this test is greater than the target bit error rate, it means that the DSP performance corresponding to the second DSP mode targeted by this test is insufficient, and the DSP performance corresponding to the second DSP mode selected for the next test is higher than the performance corresponding to the second DSP mode selected for this test; if the second bit error rate obtained in this test is less than the target bit error rate, it means that the DSP performance corresponding to the second DSP mode targeted by this test is excessive, and the DSP performance corresponding to the second DSP mode selected for the next test is lower than the performance corresponding to the second DSP mode selected for this test. The test strategy provided by any of the above embodiments can improve the efficiency of DSP mode testing and shorten the time of DSP mode testing. It should be noted that the test strategies provided in the above embodiments are only exemplary. Those skilled in the art can combine the above test strategies according to actual needs, or adopt other test strategies. The embodiments of the present application do not limit this.

[0211] 707. The high-speed serial interface controller of the first chip sends the second target DSP mode to the SerDes receiving end of the first chip.

[0212] 708. The SerDes receiving end of the first chip configures the SerDes receiving end of the first chip to the second target DSP mode.

[0213] Step 708 is similar to step 703 and will not be described in detail.

[0214] In the above method, whether the DSP performance of the first data transmission direction of the link can meet the requirements is reflected by the relationship between the second bit error rate and the target bit error rate. The second bit error rate is greater than the target bit error rate and the larger the difference is, the less the DSP performance of the first data transmission direction of the link can meet the requirements. The second bit error rate is less than the target bit error rate and the larger the difference is, the more excessive the DSP performance of the first data transmission direction of the link is. Therefore, the second DSP mode for the test with the smallest difference between the second bit error rate and the target bit error rate is determined as the second target DSP mode. On the premise of meeting the requirements for DSP performance, it can avoid the problem of excessive DSP performance caused by adopting a DSP mode with too high performance, and thus avoid the problem of increased SerDes power consumption and delay caused by the DSP mode with too high performance.

[0215] The following describes an example in which a first chip configures both the DSP mode of the second chip's SerDes transmitter and the DSP mode of the first chip's SerDes receiver. FIG8 is a flowchart of a DSP mode configuration method provided by an embodiment of the present application. As shown in FIG8 , the method includes steps 801 to 811, using the method interactively executed by the first and second chips as an example.

[0216] 801. The second chip sends a first TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. The first TSB carries multiple first DSP modes supported by the SerDes transmitting end of the second chip.

[0217] 802. The first chip receives the first TSB through a SerDes receiving end of the first chip.

[0218] 803. Based on the multiple first DSP modes indicated by the first TSB, the first chip sends a second TSB to the SerDes receiver of the second chip through the SerDes transmitter of the first chip. The second TSB carries the first DSP mode targeted by the first test. The second TSB is used to instruct the second chip to configure the SerDes transmitter of the second chip to the first DSP mode targeted by the first test.

[0219] 804 . The second chip receives the second TSB through the SerDes receiving end of the second chip, and configures the SerDes transmitting end of the second chip to the first DSP mode targeted by the first test.

[0220] 805. The second chip generates a third TSB and returns the third TSB to the SerDes receiving end of the first chip through the SerDes transmitting end of the second chip. The third TSB carries the first feedback information of the second chip on the second TSB. The first feedback information indicates that the second chip accepts the first test of the SerDes transmitting end of the second chip.

[0221] The above steps 801 to 805 are similar to the above steps 501 to 506 and are not described in detail.

[0222] 806. The first chip configures the SerDes receiving end of the first chip to the second DSP mode targeted by the first test based on the multiple second DSP modes supported by the SerDes receiving end of the first chip.

[0223] Step 806 is similar to the above steps 702 and 703 and will not be described in detail.

[0224] 807. The first chip receives the third TSB through the SerDes receiving end of the first chip and determines the third bit error rate of the first test. The third bit error rate of the first test is the bit error rate of the first data transmission direction of the link between the first chip and the second chip in the first DSP mode and the second DSP mode targeted by the first test.

[0225] This step 807 is similar to the above steps 508 and 508, and will not be repeated here.

[0226] 808. The first chip performs the 2nd to Kth tests on the first data transmission direction of the link based on the multiple first DSP modes and the multiple second DSP modes in a manner similar to steps 803 to 807 above, and determines the third bit error rate of each test, where K is the number of tests and K is an integer greater than 1.

[0227] 809. The first chip determines a first target DSP mode of the second chip and a second DSP mode of the first chip based on the third bit error rate obtained in each test.

[0228] The high-speed serial interface controller of the first chip records the first DSP mode, the second DSP mode, and the third bit error rate for each test. The process of the first chip determining the first target DSP mode of the second chip and the second DSP mode of the first chip includes: the high-speed serial interface controller of the first chip determines a third test based on the third bit error rate obtained in each test, the third test being the test in which the difference between the obtained third bit error rate and the target bit error rate is minimized; and the high-speed serial interface controller of the first chip determines the first DSP mode for which the third test is conducted as the first target DSP mode, and determines the second DSP mode for which the third test is conducted as the second target DSP mode.

[0229] It should be noted that the above steps 801 to 809 are explained by first configuring the SerDes transmitter of the second chip to the first DSP mode targeted by the first test, and then configuring the SerDes receiver of the first chip to the second DSP mode targeted by the first test. That is, steps 801 to 805 are executed first, and then step 806 is executed. In some embodiments, step 806 is executed first, and then steps 801 to 805 are executed. In other embodiments, steps 806 and steps 801 to 805 are executed synchronously. The embodiments of the present application do not limit this.

[0230] 810. The first chip configures the SerDes receiving end of the first chip to the second target DSP mode, and sends the first target DSP mode to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip.

[0231] The process of configuring the SerDes receiving end of the first chip to the second target DSP mode by the first chip in step 810 is the same as the above step 808. The process of sending the first target DSP mode to the SerDes receiving end of the second chip through the SerDes transmitting end of the first chip in step 810 is the same as the above step 511 and will not be repeated here.

[0232] 811. The second chip configures the SerDes transmitter of the second chip to the first target DSP mode.

[0233] This step 811 is similar to the above step 512 and will not be described in detail.

[0234] In the above method, whether the DSP performance in the first data transmission direction of the link can meet the requirements is reflected by the relationship between the third bit error rate and the target bit error rate. The larger the difference between the third bit error rate and the target bit error rate, the less the DSP performance in the first data transmission direction of the link can meet the requirements. The larger the difference between the second bit error rate and the target bit error rate, the more excessive the DSP performance in the first data transmission direction of the link. Therefore, the second DSP mode targeted by the test with the smallest difference between the third bit error rate and the target bit error rate is determined as the second target DSP mode, and the first DSP mode targeted by the test is determined as the first target DSP mode. This can avoid the problem of excessive DSP performance caused by adopting an overly high-performance DSP mode while meeting the DSP performance requirements, thereby avoiding the problem of increased SerDes power consumption and latency caused by the overly high-performance DSP mode. Furthermore, the receiving end and the transmitting end in the first data transmission direction can be tested simultaneously, and more DSP modes can be tested, with a wider adjustment range for DSP performance, which is conducive to determining the DSP mode that best meets the requirements.

[0235] It should be noted that the embodiments shown in Figures 5, 7, and 8 above are all described using the example of a first chip testing a first data transmission direction of a link between the first chip and the second chip to determine the target DSP mode of the SerDes receiver of the first chip and / or the SerDes transmitter of the second chip. The second data transmission direction of the link, that is, the direction from the first chip to the second chip, is tested by the second chip to determine the target DSP mode of the SerDes transmitter of the first chip and / or the SerDes receiver of the second chip. The process of testing the second chip is the same as that of testing the first chip and will not be repeated here.

[0236] It should be noted that the embodiments shown in Figures 5, 7 and 8 above are all described by taking the first device and the second device as two chips interconnected based on a high-speed serial interface as an example. In some embodiments, the first device and the second device are two communication devices that perform data transmission based on a high-speed serial interface, that is, the first device is a first communication device, the second device is a second communication device, and the first communication device and the second communication device perform data transmission through a high-speed serial interface. The process of the DSP model configuration method in this scenario is the same as the process shown in Figures 5, 7 and 8 above, and will not be repeated.

[0237] FIG9 is a schematic structural diagram of a DSP mode configuration device provided in an embodiment of the present application, which is applied to a first device. The device includes: an acquisition module 901 , a testing module 902 , a determination module 903 and a sending module 904 .

[0238] The acquisition module 901 is configured to acquire a plurality of first DSP modes supported by a SerDes transmitting end of a second device;

[0239] The testing module 902 is configured to perform at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determine a first bit error rate for each test, the first bit error rate being a bit error rate for the first data transmission direction of the link under the first DSP mode targeted by each test, the first data transmission direction being a direction from the second device to the first device;

[0240] The determining module 903 is configured to determine a first target DSP mode of the second device based on a first bit error rate obtained in each test;

[0241] The sending module 904 is configured to send the first target DSP mode to the second device, so that the SerDes sending end of the second device is configured to the first target DSP mode.

[0242] Optionally, the SerDes receiving end of the first device supports multiple second DSP modes, and the testing module 902 is further configured to:

[0243] Based on the multiple second DSP modes, perform at least one test on the first data transmission direction of the link, and determine a second bit error rate for each test, where the second bit error rate is a bit error rate for the first data transmission direction of the link under the second DSP mode targeted by each test;

[0244] determining a second target DSP mode of the first device based on a second bit error rate obtained in each test;

[0245] The SerDes receiving end of the first device is configured to the second target DSP mode.

[0246] Optionally, the first device further includes:

[0247] The receiving module is configured to receive, through the SerDes receiving end of the first device, a first training stream block TSB sent by the second device through the SerDes transmitting end of the second device, where the first TSB carries the multiple first DSP modes.

[0248] Optionally, the sending module is further configured to:

[0249] Sending a second TSB to the SerDes receiving end of the second device through the SerDes transmitting end of the first device, where the second TSB carries the first DSP mode targeted by the current test, to indicate that the SerDes transmitting end of the second device is configured as the first DSP mode targeted by the current test;

[0250] The acquisition module is configured to acquire a third TSB returned by the SerDes transmitting end of the second device to the SerDes receiving end of the first device, where the third TSB carries feedback information of the SerDes transmitting end of the second device on the second TSB;

[0251] The determination module is used to:

[0252] If the feedback information indicates that the SerDes transmitter of the second device accepts the test, determining a bit error rate of the test;

[0253] If the feedback information indicates that the SerDes transmitter of the second device rejects the current test, the next test is performed on the first data transmission direction of the link.

[0254] Optionally, the device further comprises:

[0255] a configuration module, configured to configure the SerDes receiving end of the first device to a second DSP mode targeted by this test;

[0256] The determination module 903 is configured to determine a second bit error rate for each test.

[0257] Optionally, the determining module 903 is configured to:

[0258] Determining a first test based on a first bit error rate obtained in each test, where the first test is a test in which a difference between the obtained first bit error rate and a target bit error rate is minimized;

[0259] The first DSP mode targeted by the first test is determined as the first target DSP mode.

[0260] Optionally, the determining module 903 is configured to:

[0261] Determining a second test based on the second bit error rate obtained in each test, where the second test is a test in which a difference between the obtained second bit error rate and a target bit error rate is minimized;

[0262] The second DSP mode targeted by the second test is determined as the second target DSP mode.

[0263] Optionally, the SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and the plurality of DSP parameters;

[0264] This configuration module is used to:

[0265] Determining, by the SerDes receiving end of the first device based on the second mapping table, DSP parameters corresponding to the second target DSP mode;

[0266] The configuration of the SerDes receiving end of the first device is completed based on the DSP parameters corresponding to the second target DSP mode through the SerDes receiving end of the first device.

[0267] It should be noted that, in other embodiments, the steps that the above modules are responsible for implementing can be specified as needed, and the above modules can respectively implement different steps in the above DSP mode configuration method to achieve all the functions of the above device. That is, the DSP mode configuration device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate when implementing the DSP mode configuration method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the corresponding method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0268] Among them, the acquisition module 901, the test module 902, the determination module 903, and the sending module 904 can all be implemented by software or by hardware. For example, the implementation of the acquisition module 901 will be described below using the acquisition module 901 as an example. Similarly, the implementation of the test module 902, the determination module 903, and the sending module 904 can refer to the implementation of the acquisition module 901.

[0269] As an example of a software functional unit, the acquisition module 901 may include codes running on a network device.

[0270] As an example of a hardware functional unit, the acquisition module 901 can be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0271] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the DSP modes involved in this application were obtained with full authorization.

[0272] An embodiment of the present application provides a computer-readable storage medium, which can be any available medium that can be stored by a computing device or a data storage device such as a data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes a program code, and when the program code is executed by a first device, the first device executes the steps performed by the first device in the DSP mode configuration method provided in the above method embodiment, or when the program code is executed by a second device, the second device executes the steps performed by the second device in the DSP mode configuration method provided in the above method embodiment.

[0273] Those skilled in the art will appreciate that the various method steps and units described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0274] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0275] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0276] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0277] In addition, each unit in each embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software units.

[0278] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computing device (which can be a personal computer, a server, or a computing device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0279] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, the first device can be referred to as the second device, and similarly, the second device can be referred to as the first device. Both the first device and the second device can be network devices, and in some cases, can be separate and different devices.

[0280] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more. The terms "system" and "network" are often used interchangeably in this document.

[0281] It should also be understood that the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined that..." or "if [stated condition or event] is detected" may be interpreted to mean "upon determining that..." or "in response to determining that..." or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0282] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0283] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer program instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0284] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired or wireless method. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., a digital video disc (DVD), or a semiconductor medium (e.g., a solid-state drive)), etc.

[0285] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0286] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A DSP mode configuration method, characterized in that: Applied to a first device, the method includes: Acquire multiple first DSP modes supported by a SerDes transmitter of the second device; performing at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determining a first bit error rate for each test, the first bit error rate being a bit error rate for the first data transmission direction of the link under the first DSP mode for each test, the first data transmission direction being a direction from the second device to the first device; determining a first target DSP mode of the second device based on a first bit error rate obtained in each test; The first target DSP mode is sent to the second device, and the second device configures the SerDes transmitting end of the second device to the first target DSP mode.

2. The method according to claim 1, characterized in that The SerDes receiving end of the first device supports multiple second DSP modes, and the method further includes: Based on the multiple second DSP modes, perform at least one test on the first data transmission direction of the link, and determine a second bit error rate for each test, where the second bit error rate is a bit error rate of the first data transmission direction of the link in the second DSP mode targeted by each test; determining a second target DSP mode of the first device based on a second bit error rate obtained in each test; The SerDes receiving end of the first device is configured to the second target DSP mode.

3. The method according to claim 1, characterized in that The obtaining of multiple first DSP modes supported by the SerDes transmitting end of the second device includes: A first training stream block TSB is received, which is sent by the second device through a SerDes transmitter of the second device, where the first TSB carries the multiple first DSP modes.

4. The method according to claim 1, wherein The step of performing at least one test on a first data transmission direction of a link between the first device and the second device based on the plurality of first DSP modes and determining a first bit error rate for each test includes: Sending a second TSB to the SerDes receiving end of the second device, where the second TSB carries the first DSP mode targeted by this test, and the second TSB is used to instruct the second device to configure the SerDes transmitting end of the second device to the first DSP mode targeted by this test; Obtain a third TSB returned by the SerDes transmitting end of the second device, where the third TSB carries feedback information of the second device to the second TSB; If the feedback information indicates that the second device accepts the test on the SerDes transmitter of the second device, determining a first bit error rate of the test; If the feedback information indicates that the second device refuses to perform the current test on the SerDes transmitter of the second device, the next test is performed on the first data transmission direction of the link.

5. The method according to claim 2, characterized in that The step of performing at least one test on the first data transmission direction of the link based on the multiple second DSP modes and determining a second bit error rate for each test includes: Configuring the SerDes receiving end of the first device to the second DSP mode targeted by this test; Determine the second bit error rate for each test.

6. The method according to claim 1, characterized in that The determining, based on the first bit error rate obtained in each test, a first target DSP mode of the second device, includes: Determining a first test based on a first bit error rate obtained in each test, where the first test is a test in which a difference between the obtained first bit error rate and a target bit error rate is minimized; A first DSP mode targeted by the first test is determined as the first target DSP mode.

7. The method according to claim 2, characterized in that Determining the second target DSP mode of the first device based on the second bit error rate obtained in each test includes: Determining a second test based on the second bit error rate obtained in each test, where the second test is a test in which a difference between the obtained second bit error rate and the target bit error rate is minimized; A second DSP mode targeted by the second test is determined as the second target DSP mode.

8. The method according to claim 1, characterized in that The SerDes transmitting end of the second device maintains a first mapping table, where the first mapping table is used to indicate a correspondence between the plurality of first DSP modes and a plurality of DSP parameters; The process of configuring, by the second device, the SerDes transmitting end of the second device to the first target DSP mode includes: The SerDes transmitting end of the second device determines the DSP parameters corresponding to the first target DSP mode based on the first mapping table; The SerDes transmitting end of the second device completes the configuration of the SerDes transmitting end of the second device based on the DSP parameters corresponding to the first target DSP mode.

9. The method according to claim 2, characterized in that The SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and a plurality of DSP parameters; Configuring the SerDes receiving end of the first device to the second target DSP mode includes: The SerDes receiving end of the first device determines the DSP parameters corresponding to the second target DSP mode based on the second mapping table; The SerDes receiving end of the first device completes the configuration of the SerDes receiving end of the first device based on the DSP parameters corresponding to the second target DSP mode.

10. A DSP mode configuration method, characterized in that: The method comprises: The second device sends a plurality of first DSP modes supported by the SerDes transmitting end of the second device to the first device; The first device obtains the plurality of first DSP modes; The first device performs at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determines a first bit error rate for each test, where the first bit error rate is a bit error rate of the first data transmission direction of the link under the first DSP mode targeted by each test, where the first data transmission direction is from the second device to the first device; The first device determines a first target DSP mode of the second device based on a first bit error rate obtained in each test; The first device sends the first target DSP mode to the second device; The second device configures the SerDes transmitter of the second device to the first target DSP mode.

11. The method according to claim 10, characterized in that The SerDes receiving end of the first device supports multiple second DSP modes, and the method further includes: The first device performs at least one test on the first data transmission direction of the link based on the multiple second DSP modes, and determines a second bit error rate for each test, where the second bit error rate is a bit error rate of the first data transmission direction of the link in the second DSP mode targeted by each test; The first device determines a second target DSP mode of the first device based on a second bit error rate obtained in each test; The first device configures the SerDes receiving end of the first device to the second target DSP mode.

12. The method according to claim 10, characterized in that The first device acquires the plurality of first DSP modes, including: The first device receives a first training stream block TSB sent by the second device through the SerDes transmitting end of the second device through the SerDes receiving end of the first device, where the first TSB carries the multiple first DSP modes.

13. The method according to claim 10, characterized in that The first device performs at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determines a first bit error rate for each test, including: The first device sends a second TSB to the SerDes receiving end of the second device through the SerDes transmitting end of the first device, where the second TSB carries the first DSP mode targeted by this test; The second device configures the SerDes transmitter of the second device to a first DSP mode targeted by the test based on the second TSB; The second device returns a third TSB to the SerDes receiving end of the first device through the SerDes transmitting end of the second device, where the third TSB carries feedback information of the SerDes transmitting end of the second device on the second TSB; The first device obtains the third TSB through the SerDes receiving end of the first device; If the feedback information indicates that the SerDes transmitter of the second device accepts the test, the first device determines a bit error rate of the test; If the feedback information indicates that the SerDes transmitter of the second device rejects the current test, the first device performs a next test on the first data transmission direction of the link.

14. The method according to claim 11, characterized in that The first device performs at least one test on the first data transmission direction of the link based on the multiple second DSP modes, and determines a second bit error rate of each test, including: The first device configures the SerDes receiving end of the first device to a second DSP mode targeted by this test; The first device determines a second bit error rate for each test.

15. The method according to claim 10, characterized in that The first device determines a first target DSP mode of the second device based on a first bit error rate obtained in each test, including: The first device determines a first test based on a first bit error rate obtained in each test, wherein the first test is a test in which a difference between the obtained first bit error rate and a target bit error rate is minimized; The first device determines a first DSP mode targeted by the first test as the first target DSP mode.

16. The method according to claim 11, characterized in that The first device determines a second target DSP mode of the first device based on a second bit error rate obtained in each test, including: The first device determines a second test based on the second bit error rate obtained in each test, wherein the second test is a test in which a difference between the obtained second bit error rate and a target bit error rate is minimized; The first device determines a second DSP mode targeted by the second test as the second target DSP mode.

17. The method according to claim 10, wherein: The SerDes transmitting end of the second device maintains a first mapping table, where the first mapping table is used to indicate a correspondence between the plurality of first DSP modes and a plurality of DSP parameters; The process of configuring, by the second device, the SerDes transmitting end of the second device to the first target DSP mode includes: The SerDes transmitting end of the second device determines the DSP parameters corresponding to the first target DSP mode based on the first mapping table; The SerDes transmitting end of the second device completes the configuration of the SerDes transmitting end of the second device based on the DSP parameters corresponding to the first target DSP mode.

18. The method according to claim 11, characterized in that The SerDes receiving end of the first device maintains a second mapping table, where the second mapping table is used to indicate a correspondence between the plurality of second DSP modes and a plurality of DSP parameters; The first device configures the SerDes receiving end of the first device to the second target DSP mode, including: The SerDes receiving end of the first device determines the DSP parameters corresponding to the second target DSP mode based on the second mapping table; The SerDes receiving end of the first device completes the configuration of the SerDes receiving end of the first device based on the DSP parameters corresponding to the second target DSP mode.

19. A DSP mode configuration device, characterized in that: Applied to a first device, the device includes: An acquisition module, configured to acquire a plurality of first DSP modes supported by a SerDes transmitting end of a second device; a testing module configured to perform at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determine a first bit error rate for each test, the first bit error rate being a bit error rate of the first data transmission direction of the link under the first DSP mode targeted by each test, the first data transmission direction being a direction from the second device to the first device; a determination module, configured to determine a first target DSP mode of the second device based on a first bit error rate obtained in each test; The sending module is used to send the first target DSP mode to the second device, so that the second device configures the SerDes sending end of the second device to the first target DSP mode.

20. A data transmission device, characterized in that: The device includes a SerDes and a high-speed serial interface controller. The SerDes receiving end supports multiple DSP modes, the SerDes transmitting end supports multiple DSP modes, and the high-speed serial interface controller is used to control the DSP modes of the SerDes receiving end and the SerDes transmitting end.

21. A communication system, characterized in that: The communication system includes a first device and a second device, wherein a receiving end of the SerDes of the first device supports multiple second DSP modes, and a transmitting end of the SerDes of the second device supports multiple first DSP modes; The second device is configured to send, to the first device, a plurality of first DSP modes supported by a SerDes transmitting end of the second device; The first device is used to: Acquire multiple first DSP modes supported by a SerDes transmitter of the second device; performing at least one test on a first data transmission direction of a link between the first device and the second device based on the multiple first DSP modes, and determining a first bit error rate for each test, the first bit error rate being a bit error rate for the first data transmission direction of the link under the first DSP mode for each test, the first data transmission direction being a direction from the second device to the first device; determining a first target DSP mode of the second device based on a first bit error rate obtained in each test; sending the first target DSP mode to the second device; The second device is further used for: The SerDes transmitter of the second device is configured to be in the first target DSP mode.

22. A storage medium, characterized in that At least one program code is stored in the storage medium, and the at least one program code is read by the first device to enable the first device to execute the DSP mode configuration method according to any one of claims 1 to 9.

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