Circuit board and display module

Abstract

The present application relates to the technical field of display, and provides a circuit board, a display module, and a display device. The circuit board comprises a first area, a second area and a third area, and the second area is located between the first area and the third area; the first area and the second area each comprise at least two conductive layers, and the third area comprises at least three conductive layers; the first area is provided with a first hollow recess and signal lines, the first area overlaps a wiring area of a display panel, and a circuit in the wiring area is electrically connected to a driving chip by means of the first hollow recess; the second area is provided with a plurality of golden fingers; and the third area is provided with a plurality of functional devices.

Description

Circuit board and display module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on February 27, 2024, with application number 202410217769.2 and titled “A Circuit Board and Display Module,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a circuit board and a display module. Background Art

[0004] With the rapid development of display technology, people's requirements for the performance and aesthetics of display products are becoming increasingly demanding. Thinness and lightness are currently a hot topic in the display product market. This requires a denser layout of components and wiring within display products, as well as greater space utilization. Currently, the design of circuit boards in display products is relatively complex, occupying a significant amount of space.

[0005] Overview

[0006] The embodiments of this application adopt the following technical solutions:

[0007] In the first aspect, an embodiment of the present application provides a circuit board for use in a display panel, wherein the circuit board includes a first area, a second area, and a third area, and the second area is located between the first area and the third area; wherein the first area and the second area include at least two conductive layers, and the third area includes at least three conductive layers; the first area is provided with a first hollow groove and a signal line, the first area overlaps with the wiring area of ​​the display panel, and the circuit in the wiring area is electrically connected to the driving chip through the first hollow groove, the second area is provided with multiple gold fingers, and the third area is provided with multiple functional devices.

[0008] In at least one circuit board provided in an embodiment of the present application, the first area is further provided with a plurality of test terminals, including a power supply test terminal and a shift register test terminal, and the test terminals are configured to detect the circuit of the display panel.

[0009] In at least one circuit board provided in an embodiment of the present application, the signal line includes a power signal line.

[0010] In at least one circuit board provided in an embodiment of the present application, in a direction perpendicular to the plane where the circuit board is located, the portion of the circuit board located in the third area includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer, the portion of the circuit board located in the second area includes the second conductive layer and the third conductive layer, and the portion of the circuit board located in the first area includes the second conductive layer and the third conductive layer; insulating material is arranged between any two adjacent conductive layers; wherein, the first hollow groove passes through the second conductive layer and the third conductive layer, the gold finger is arranged on the third conductive layer, the functional device is arranged on the side of the first conductive layer away from the second conductive layer, and the first area is also provided with a plurality of test terminals, and the test terminals are arranged on the second conductive layer.

[0011] In at least one circuit board provided in an embodiment of the present application, the third conductive layer is arranged to be opposite to the wiring area of ​​the display panel in a direction perpendicular to the plane of the circuit board, and the second conductive layer is located on the side of the third conductive layer away from the display panel; the gold finger is configured to be bound to the wiring area.

[0012] In at least one circuit board provided in an embodiment of the present application, the signal line includes a power signal line, and the power signal line includes a first power line and a second power line. The first power line includes a first end, a first main portion, and a second end. The first main portion of the first power line is disposed on the second conductive layer and located on a side of the first hollow groove away from the second region. The first and second ends of the first power line are disposed on the third conductive layer. The second power line includes a third end, a second main portion, and a fourth end. The second power line is disposed on the third conductive layer, and the second main portion of the second power line overlaps the first main portion of the first power line.

[0013] In at least one circuit board provided in an embodiment of the present application, the portion of the third conductive layer located in the first area includes a plurality of first connecting lines, the portion of the second conductive layer located in the first area includes a plurality of second connecting lines, the first connecting lines are electrically connected to the gold fingers, and the second connecting lines are electrically connected to the first connecting lines and the test terminals, respectively.

[0014] In at least one circuit board provided in an embodiment of the present application, the portion of the second conductive layer located in the second area includes a first conductive pattern, a second conductive pattern and a third conductive pattern arranged in sequence along the first direction; wherein, the orthographic projection of the second conductive pattern on the third conductive layer covers the multiple gold fingers, and the second conductive pattern is a continuous structure; the first conductive pattern and the third conductive pattern are both grid structures, and the orthographic projections of the first conductive pattern and the third conductive pattern on the third conductive layer do not overlap with the multiple gold fingers; the first direction is the direction from the first area to the second area.

[0015] In at least one circuit board provided by an embodiment of the present application, the first conductive pattern, the second conductive pattern, and the third conductive pattern are grounded respectively.

[0016] In at least one circuit board provided in an embodiment of the present application, the portion of the second conductive layer located in the first area is further provided with a first conductive island and a second conductive island, the first hollow groove, the signal line and the test terminal are all arranged in the area between the first conductive island and the second conductive island, and the first conductive island and the second conductive island are grounded.

[0017] In at least one circuit board provided in an embodiment of the present application, the portion of the third conductive layer located in the second area includes an alignment pattern, the second conductive layer also includes a second hollow groove, and the orthographic projection of the alignment pattern on the second conductive layer is located in the second hollow groove.

[0018] In at least one circuit board provided in an embodiment of the present application, in a direction perpendicular to the plane where the circuit board is located, the portion of the circuit board located in the third area includes a first shielding layer, a first covering layer, a first bonding layer, the first conductive layer, a first insulating layer, the second conductive layer, a second covering layer, the third conductive layer, a second insulating layer, the fourth conductive layer, a third covering layer, the fifth conductive layer, a third insulating layer, the sixth conductive layer, a second bonding layer, a fourth covering layer and a second shielding layer arranged in sequence; the multiple functional devices are located on a side of the first covering layer away from the first bonding layer, and the multiple functional devices and the orthographic projection of the first shielding layer on the first conductive layer do not overlap with each other.

[0019] In at least one circuit board provided in an embodiment of the present application, in a direction perpendicular to the plane where the circuit board is located, the portion of the circuit board located in the second area includes the first covering layer, the first adhesive layer, the second conductive layer, the second covering layer, the third conductive layer, the second adhesive layer and the fourth covering layer arranged in sequence, a third hollow groove is provided on the second adhesive layer and the fourth covering layer, and the orthographic projection of the area enclosed by the outer contour of the third hollow groove on the third conductive layer covers the gold finger; the portion of the circuit board located in the first area includes the first shielding layer, the first covering layer, the first adhesive layer, the second conductive layer, the second covering layer, the third conductive layer, the second adhesive layer, the fourth covering layer and the second shielding layer arranged in sequence.

[0020] In a second aspect, an embodiment of the present application provides a display module comprising a display panel and a circuit board as described in any one of the first aspects, wherein the multiple gold fingers in the circuit board are electrically connected to the display panel, and the orthographic projection of the first area of ​​the circuit board on the display panel covers at least a portion of the routing area of ​​the display panel.

[0021] In at least one display module provided in an embodiment of the present application, the display module further includes a driver chip, which is electrically connected to the display panel, and the orthographic projection of the driver chip on the display panel overlaps with the area enclosed by the orthographic projection of the first hollow groove of the circuit board on the display panel.

[0022] In at least one display module provided in an embodiment of the present application, the display panel includes a display surface and a back surface, the first area of ​​the circuit board is configured to be able to be bent to the back surface of the display panel, and a portion of the first area is adhered to the back surface through a conductive cloth.

[0023] In a third aspect, an embodiment of the present application provides a display device comprising a display module as described in any one of the second aspects.

[0024] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] FIG1 is a schematic top view of a circuit board in a related art according to an embodiment of the present application;

[0028] FIG2 is a schematic top view of the structure in which the circuit board and the display panel shown in FIG1 are bound together;

[0029] FIG3 is a schematic top view of the structure in which the circuit board in FIG2 is bent to the back side of the display panel;

[0030] FIG4 is a schematic diagram of a top view of a circuit board provided in an embodiment of the present application;

[0031] FIG5 is a schematic top view of the structure in which the circuit board and the display panel shown in FIG4 are bound together;

[0032] FIG6 is a schematic top view of the structure in which the circuit board in FIG5 is bent to the back side of the display panel;

[0033] FIG7 is a schematic diagram of a cross-sectional structure of a circuit board provided in an embodiment of the present application;

[0034] FIG8 is a schematic top view of a local area of ​​a third conductive layer in a circuit board provided by an embodiment of the present application;

[0035] FIG9 is a schematic top view of the structure of the second conductive layer in the circuit board provided in an embodiment of the present application;

[0036] FIG10 is a schematic top view of the structure of the third conductive layer in the circuit board provided in an embodiment of the present application;

[0037] 11 and 12 are schematic top views of first and third conductive patterns on two types of second conductive layers according to embodiments of the present application;

[0038] FIG13 is a schematic structural diagram of the first area in the circuit board provided in an embodiment of the present application.

[0039] Detailed description

[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0042] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0043] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0044] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0045] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the stated value.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0047] The polygons in this specification are not in a strict sense, and may be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and may have some small deformations due to tolerances.

[0048] Figure 1 provides a structural schematic diagram of the circuit board in the related art, Figure 2 provides a structural schematic diagram of the circuit board and the display panel in the related art when they are bound together, and Figure 3 provides a structural schematic diagram of the circuit board in the display module when it is bent to the back of the display panel.

[0049] As shown in Figure 1, the circuit board is provided with a gold finger area 1, a power signal line EL (such as EL traces 3&4), multiple test terminals 2, a conductive pattern 5, a flexible conductive film 6 and a connector 7; among them, the power signal line (such as EL traces 3&4) on the circuit board occupies more design space due to its relatively large line width; in addition, due to the display module's requirements for electromagnetic shielding performance, a conductive pattern 5 is usually provided in a local area of ​​the circuit board to improve the electromagnetic shielding performance of the display module, and the conductive pattern 5 used for electromagnetic shielding also occupies more design space; therefore, the design space utilization rate of the circuit board (such as the flexible circuit board FPC) in the related art is low and the size is large. As shown in Figure 3, when it is bent to the back of the display panel, the overall space occupied is large, which makes it difficult to use in lightweight display products.

[0050] The related art is provided with a second area A2 (also known as the gold finger area) and a third area A3 (also known as the functional area) as shown in FIG1 , a display area AA as shown in FIG2 , a driver chip DIC (Display IC, also known as a display driver chip) and a flexible circuit board FPC as shown in FIG2 and FIG3 , and a wiring area (PNL wiring area) of the display panel.

[0051] Based on this, an embodiment of the present application provides a circuit board for use in a display panel. As shown in FIG4 , the circuit board includes a first area A1, a second area A2, and a third area A3, with the second area A2 located between the first and third areas A1 and A3. The first and second areas A1 and A2 include at least two conductive layers, and the third area A3 includes at least three conductive layers. The first area A1 is provided with a first hollow groove C1 and a signal line (e.g., including a power signal line EL). As shown in FIG5 , the first area A1 overlaps with the display panel's wiring area (PNL wiring area). The circuit in the wiring area (partial structure of the circuit can be seen in FIG9 and FIG10 ) is electrically connected to a driver chip DIC (Display IC, also known as a display driver chip) via the first hollow groove C1. As shown in FIG7 , the second area A2 is provided with multiple gold fingers GF, and the third area A3 is provided with multiple functional devices Q. FIG7 is a schematic cross-sectional structure diagram along the B1B2 direction of FIG4 .

[0052] The above-mentioned circuit board may include a flexible circuit board (FPC), wherein FPC is also called a soft circuit board or a flexible circuit board, which is popular for its excellent properties such as light weight, thin thickness, and free bending and folding.

[0053] In the embodiment of the present application, the first area A1, the second area A2 and the third area A3 are sequentially arranged in a direction in which the display area AA of the display panel points to the circuit board FPC.

[0054] In an exemplary embodiment, the portion of the circuit board located in the first area A1 includes the same number of conductive layers as the portion of the circuit board located in the second area A2 .

[0055] In an exemplary embodiment, the number of conductive layers included in the portion of the circuit board located in the first area A1 and the number of conductive layers included in the portion of the circuit board located in the second area A2 are respectively smaller than the number of conductive layers included in the portion of the circuit board located in the third area A3.

[0056] For example, the number of conductive layers included in the portion of the circuit board located in the first area A1 and the number of conductive layers included in the portion of the circuit board located in the second area A2 are both two. For example, the number of conductive layers included in the portion of the circuit board located in the third area A3 is six.

[0057] In an exemplary embodiment, the material of the conductive layer in the circuit board includes metal, such as copper (Cu).

[0058] Among them, when the circuit board is bound to the display panel, the space of the first area A1 in the circuit board is saved by setting the first area A1 to overlap with the routing area (PNL routing area) of the display panel. A first hollow groove C1 is set in the first area A1 of the circuit board, and the driver chip (display driver chip DIC) is electrically connected to the routing area on the display panel through the first hollow groove C1, that is, the driver chip and the routing area on the display panel overlap, and the orthographic projection of the driver chip on the display panel and the area enclosed by the outer contour of the first hollow groove C1 overlap on the display panel.

[0059] Illustratively, the signal lines include but are not limited to power signal lines, ground lines, shift register signal lines, and the like.

[0060] Exemplarily, the width of the power signal line EL is approximately in the range of 0.8 mm to 1.2 mm.

[0061] In an exemplary embodiment, the orthographic projection of the driver chip DIC on the display panel overlaps with the orthographic projection of the area enclosed by the outer contour of the first hollow groove C1 on the display panel, including but not limited to the following situations:

[0062] The first is that the orthographic projection of the driver chip DIC on the display panel and the orthographic projection of the area enclosed by the outer contour of the first hollow groove C1 on the display panel partially overlap; at this time, the orthographic projection area of ​​the driver chip DIC on the display panel can be larger than the orthographic projection area of ​​the area enclosed by the outer contour of the first hollow groove C1 on the display panel.

[0063] The second type is that the orthographic projection of the driver chip DIC on the display panel is located within the orthographic projection of the area enclosed by the outer contour of the first hollow groove C1 on the display panel. At this time, the orthographic projection area of ​​the driver chip DIC on the display panel is less than or equal to the orthographic projection area of ​​the area enclosed by the outer contour of the first hollow groove C1 on the display panel.

[0064] In an embodiment of the present application, the third area A3 is provided with a plurality of functional devices, including but not limited to capacitors, resistors, microcontrollers and other electronic components.

[0065] Compared with the circuit boards in the related art, the circuit board provided in the embodiment of the present application has a newly added first area A1. When the circuit board is bound to the display panel and is not bent to the back of the display panel, the newly added first area A1 does not increase the size of the display area AA of the display module pointing in the direction of the circuit board due to the overlap between the first area A1 and the wiring area (PNL wiring area) of the display panel. Furthermore, by providing a first hollow groove C1 in the first area A1, the driver chip DIC is electrically connected to the wiring area of ​​the display panel through the first hollow groove C1, thereby ensuring normal electrical connection between the driver chip DIC and the wiring area of ​​the display panel. In addition, since the signal line originally set in the third area A3 in the related art is set in the first area A1, the design space of the third area A3 can be greatly reduced, and the size of the third area A3 along the direction from the first area A1 to the second area A2 is reduced, thereby reducing the design space of the display module.

[0066] In some embodiments, the size of the third area A3 in the circuit board provided in the embodiments of the present application in the direction along the first area A1 pointing to the second area A2 is smaller than the size of the third area A3 in the circuit board in the related art without the newly added first area A1 in the direction along the first area A1 pointing to the second area A2.

[0067] In at least one circuit board provided in an embodiment of the present application, as shown in FIG4 , the first area A1 is further provided with a plurality of test terminals TP, including power supply test terminals and shift register test terminals, which are configured to detect the circuit of the display panel.

[0068] Exemplarily, the power test terminal can be electrically connected to the power line; for example, the power test terminal can include a first power test terminal and a second power test terminal, the power line can include a first power line and a second power line, the first power test terminal is electrically connected to the first power line, and the second power test terminal can be electrically connected to the second power line.

[0069] Exemplarily, the shift register test terminal can be electrically connected to the shift register signal line; for example, the shift register signal line can include a reset signal line, an initialization signal line, and a light-emitting control signal line, and the shift register test terminal can include a reset test terminal, an initialization test terminal, and a light-emitting control test terminal, wherein the reset signal line and the reset test terminal are electrically connected, the initialization signal line and the initialization test terminal are electrically connected, and the light-emitting control signal line and the light-emitting control signal line are electrically connected.

[0070] In the circuit board provided in the embodiment of the present application, compared with the circuit board in the related art, since the first area A1 overlaps with the routing area (PNL routing area) of the display panel, when the circuit board is not bent to the back, the size of the display area AA of the display module pointing in the direction of the circuit board is not increased; and by setting the test terminal TP originally set in the third area A3 in the first area A1, the size of the third area A3 along the direction pointing to the second area A2 from the first area A1 can be further reduced, thereby reducing the design space of the display module.

[0071] In some embodiments, since the first area A1 and the routing area (PNL routing area) of the display panel at least partially overlap, the size of the third area A3 in the circuit board provided in the embodiments of the present application in the direction along the first area A1 pointing to the second area A2 is smaller than the size of the third area A3 in the circuit board in the related art without the newly added first area A1 in the direction along the first area A1 pointing to the second area A2.

[0072] In at least one circuit board provided in an embodiment of the present application, as shown in FIG4 , the signal line includes a power signal line EL.

[0073] Exemplarily, as shown in FIG4 , one of the two signal lines marked as the power signal line EL is a first power line ELVDD, and the other is a second power line ELVSS.

[0074] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 7, the portion of the circuit board located in the third area A3 includes a first conductive layer L1, a second conductive layer L2, a third conductive layer L3, a fourth conductive layer L4, a fifth conductive layer L5 and a sixth conductive layer L6, the portion of the circuit board located in the second area A2 includes a second conductive layer L2 and a third conductive layer L3, and the portion of the circuit board located in the first area A1 includes a second conductive layer L2 and a third conductive layer L3; and insulating material is provided between any two adjacent conductive layers.

[0075] As shown in Figures 7-10, the first hollow groove C1 passes through the second conductive layer L2 and the third conductive layer L3, the gold finger GF is set on the third conductive layer L3, the functional device Q is set on the side of the first conductive layer L1 away from the second conductive layer L2, and the test terminal TP is set on the second conductive layer L2.

[0076] In an exemplary embodiment, the materials of the first conductive layer L1 , the second conductive layer L2 , the third conductive layer L3 , the fourth conductive layer L4 , the fifth conductive layer L5 and the sixth conductive layer L6 are all the same; for example, the materials thereof include copper (Cu).

[0077] There is no limitation on whether the insulating materials provided between any two adjacent conductive layers are the same, and this can be determined based on the design and requirements.

[0078] The first hollow groove C1 located in the first area A1 penetrates the second conductive layer L2 and the third conductive layer L3 , so that the driving chip DIC can be electrically connected to the wiring area of ​​the display panel through the first hollow groove C1 .

[0079] The functional device Q is arranged on the side of the first conductive layer L1 away from the second conductive layer L2, so that after the circuit board and the display panel are bound, the functional device Q is arranged toward the side away from the display panel, that is, when the circuit board is not bent to the back of the display panel, the direction of the functional device Q is consistent with the direction of the display surface of the display panel.

[0080] The functional devices Q mentioned above include but are not limited to resistors, capacitors, microprocessors and other electronic components.

[0081] In an embodiment of the present application, by setting the first area A1 and the second area A2 to include a second conductive layer L2 and a third conductive layer L3, on the one hand, compared with the area where the gold finger GF is set in the related art, the film thickness difference between the second area A2 (provided with the gold finger GF) and the third area A3 (provided with the functional device Q) in the present application is reduced, that is, the step difference is reduced, thereby reducing the probability of damage between the second area A2 and the third area A3, and improving the reliability of the circuit board; on the other hand, by setting the first area A1 to include at least two conductive layers (for example, including the second conductive layer L2 and the third conductive layer L3), the design space of each device in the first area A1 can be saved.

[0082] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 7, the third conductive layer L3 is arranged to be opposite to the routing area of ​​the display panel in a direction perpendicular to the plane of the circuit board, and the second conductive layer L2 is located on the side of the third conductive layer L3 away from the display panel in a direction perpendicular to the plane of the circuit board; the gold finger GF is configured to be bound to the routing area.

[0083] In an embodiment of the present application, the second conductive layer L2 is arranged to be located on the side of the third conductive layer L3 away from the display panel in a direction perpendicular to the plane where the circuit board is located. In this way, after the circuit board and the display panel are bound, when the circuit board is not bent to the back of the display panel, the test terminal TP arranged on the second conductive layer L2 and the display surface of the display panel are oriented in the same direction, thereby facilitating the use of the test terminal TP to test the circuit in the display panel; in addition, the gold finger GF arranged on the third conductive layer L3 is oriented toward the wiring area of ​​the display panel in a direction perpendicular to the plane where the circuit board is located, thereby facilitating the binding of the gold finger GF to the wiring area of ​​the display panel.

[0084] In at least one circuit board provided by an embodiment of the present application, as shown in FIG. 4 , the signal line includes a power signal line EL, and the power signal line EL includes a first power line ELVDD and a second power line ELVSS.

[0085] Figure 9 provides a schematic top-down view of the various traces and conductive structures on the second conductive layer L2, and Figure 10 provides a schematic top-down view of the various traces and conductive structures on the third conductive layer L3. As shown in Figures 9 and 10 , the first power line ELVDD includes a first end portion ELVDD-2, a first main portion ELVDD-1, and a second end portion ELVDD-3. The first main portion ELVDD-1 of the first power line is disposed in the second conductive layer L2 and is located on a side of the first hollow groove C1 away from the second area A2. The first end portion ELVDD-2 and the second end portion ELVDD-3 of the first power line are disposed on the third conductive layer L3.

[0086] As shown in Figure 10, the second power line ELVSS includes a first end ELVSS-2, a first main part ELVSS-1 and a second end ELVSS-3. The second power line ELVSS is set on the third conductive layer L3, and the first main part of the second power line ELVSS overlaps with the first main part ELVDD-1 of the first power line ELVDD.

[0087] In an embodiment of the present application, by setting the first main part ELVDD-1 of the first power line in the second conductive layer L2, setting the second power line ELVSS in the third conductive layer L3, and making the first main part of the second power line ELVSS and the first main part ELVDD-1 of the first power line ELVDD overlap, the design space of the first area A1 can be saved to a great extent.

[0088] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 10, the portion of the third conductive layer L3 located in the first area A1 includes a plurality of first connecting wires LJ1, and as shown in Figure 9, the portion of the second conductive layer L2 located in the first area A1 includes a plurality of second connecting wires LJ2, the first connecting wires LJ1 are electrically connected to the gold finger GF, and the second connecting wires LJ2 are electrically connected to the first connecting wires LJ1 and the test terminal TP, respectively.

[0089] The first connection line LJ1 is provided on the same layer as the gold finger GF on the third conductive layer L3, and the first connection line LJ1 and the gold finger GF can be manufactured simultaneously in the same manufacturing process. The second connection line LJ2 is provided on the same layer as the test terminal TP on the second conductive layer L2, and the second connection line LJ2 and the test terminal TP can be manufactured simultaneously in the same manufacturing process. In addition, the second connection line LJ2 and the first connection line LJ1 are electrically connected together via a through-hole provided in the insulating material between the second conductive layer L2 and the third conductive layer L3.

[0090] In actual applications, the test terminal TP can be electrically connected to the corresponding signal line through the second connection line LJ2, the first connection line LJ1, and the gold finger GF in sequence, so that the circuit on the display panel can be detected through the test terminal to ensure that there is no abnormality in the circuit of the display panel before it is prepared to form a display module.

[0091] In at least one circuit board provided in an embodiment of the present application, as shown in FIG9 , the portion of the second conductive layer L2 located in the second area A2 includes a first conductive pattern D1, a second conductive pattern D2, and a third conductive pattern D3 sequentially arranged along a first direction (e.g., direction OA). It should be noted that in FIG8 , FIG9 , FIG10 , and FIG11 and FIG12 hereinafter, the black areas represent hollowed-out or cutout regions in the conductive layer. FIG8 is an enlarged schematic diagram of the portion within the dotted elliptical circle in FIG10 .

[0092] As shown in Figures 9 and 10, the orthographic projection of the second conductive pattern D2 on the third conductive layer L3 covers multiple gold fingers GF, and the second conductive pattern D2 is a continuous structure; the first conductive pattern D1 and the third conductive pattern D3 are both grid structures, and the orthographic projections of the first conductive pattern D1 and the third conductive pattern D3 on the third conductive layer L3 do not overlap with the multiple gold fingers GF; the first direction (for example, the OA direction) is the direction from the first area A1 to the second area A2.

[0093] In an exemplary embodiment, orthographic projections of the first conductive pattern D1 and the third conductive pattern D3 on the third conductive layer L3 are respectively located on two opposite sides of a region where the plurality of gold fingers GF are located.

[0094] Here, whether the mesh structure of the first conductive pattern D1 and the mesh structure of the third conductive pattern D3 are the same is not limited. For example, in order to reduce the difficulty of the manufacturing process and reduce the design cost, the mesh structure of the first conductive pattern D1 and the mesh structure of the third conductive pattern D3 can be set to be the same.

[0095] The specific size and structure of the grid structure are not limited here.

[0096] For example, FIG11 and FIG12 provide schematic top views of the mesh structure of two first conductive patterns D1 and the mesh structure of the third conductive pattern D3.

[0097] In at least one circuit board provided by an embodiment of the present application, the first conductive pattern D1 , the second conductive pattern D2 , and the third conductive pattern D3 are grounded respectively.

[0098] In practical applications, when bonding the gold fingers (GF) on a display panel to a circuit board, the heating and pressurizing process can easily cause the film layer to expand or contract. Related circuit boards, due to their poor heat dissipation, can easily reduce the yield rate of bonding the display panel and circuit board, increasing manufacturing costs.

[0099] In an embodiment of the present application, the portion of the second conductive layer L2 located in the second area A2 includes a first conductive pattern D1, a second conductive pattern D2 and a third conductive pattern D3 arranged in sequence along a first direction (for example, an OA direction), and the orthographic projection of the second conductive pattern D2 on the third conductive layer L3 covers a plurality of gold fingers GF. The second conductive pattern D2 is a continuous structure, and the second conductive pattern D2 can simultaneously provide good electromagnetic shielding and heat dissipation performance. In addition, by setting the first conductive pattern D1 and the third conductive pattern D3 as a grid structure, the heat dissipation effect near the area where the gold finger GF is located can be further improved, thereby improving the use characteristics of the circuit board and reducing power consumption.

[0100] In at least one circuit board provided in an embodiment of the present application, as shown in FIG4 , the portion of the second conductive layer L2 located in the first area A1 is further provided with a first conductive island I1 and a second conductive island I2. A first hollow slot C1, a signal line (e.g., a power signal line EL), and a test terminal TP are all provided in the region between the first conductive island I1 and the second conductive island I2. The first conductive island I1 and the second conductive island I2 are grounded. The first conductive island I1 and the second conductive island I2 are used to achieve and enhance electromagnetic shielding performance, thereby improving signal transmission stability between the circuit board and the display module.

[0101] In an exemplary embodiment, as shown in FIG. 4 , the first conductive island I1 and the second conductive island I2 may be independently provided, ie, there is a gap between them.

[0102] In an exemplary embodiment, as shown in FIG. 13 , the first conductive island I1 and the second conductive island I2 may be connected together by a conductive material.

[0103] For example, as shown in Figure 13, a conductive island structure I3 can be set in the redundant space (space without electrical devices and wiring) of the second conductive layer L2 located in the first area A1 to connect the first conductive island I1 and the second conductive island I2 into a whole, thereby further improving the electromagnetic shielding performance and further improving the signal transmission stability of the circuit board and the display module.

[0104] The shapes of the planar graphics of the first conductive island I1, the second conductive island I2 and the conductive island structure I3 are not limited here, and can be specifically determined according to the design space on the second conductive layer L2.

[0105] For example, the planar shapes of the first conductive island I1, the second conductive island I2, and the conductive island structure I3 may include arcs, polygons, and combinations of arcs and polygons. Arcs include circles, ellipses, semicircles, semiellipses, and sectors; polygons include triangles, quadrilaterals, and pentagons; and combinations of arcs and polygons include shapes formed by splicing arcs and polygons, or shapes formed by removing a local area from an arc or polygon.

[0106] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 10, the portion of the third conductive layer L3 located in the second area A2 includes an alignment pattern M. As shown in Figures 9 and 11, the second conductive layer L2 also includes a second hollow groove C2, and the orthographic projection of the alignment pattern M on the second conductive layer L2 is located in the second hollow groove C2.

[0107] In an embodiment of the present application, a second hollow groove C2 is provided in the second conductive layer L2, so that when the circuit board and the display panel are bound, light can pass through the second hollow groove C2 to identify the alignment pattern M, so as to perform precise alignment and improve the binding yield of the circuit board and the display panel.

[0108] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 7, the portion of the circuit board located in the third area A3 includes a first shielding layer EMI1, a first covering layer F1, a first adhesive layer AD1, a first conductive layer L1, a first insulating layer J1, a second conductive layer L2, a second covering layer F2, a third conductive layer L3, a second insulating layer J2, a fourth conductive layer L4, a third covering layer F3, a fifth conductive layer L5, a third insulating layer J3, a sixth conductive layer L6, a second adhesive layer AD2, a fourth covering layer F4 and a second shielding layer EMI2, which are arranged in sequence in a direction perpendicular to the plane of the circuit board; a plurality of functional devices Q are located on a side of the first covering layer F1 away from the first adhesive layer AD1, and the orthographic projections of the plurality of functional devices Q and the first shielding layer EMI1 on the first conductive layer L1 do not overlap with each other.

[0109] The materials of the first shielding layer EMI1 and the second shielding layer EMI2 are not limited here. For example, the materials of both may include metal, polymer composite materials with electromagnetic shielding properties, or organic materials with electromagnetic shielding properties.

[0110] In an exemplary embodiment, the materials of the above-mentioned covering layer and insulating layer both include insulating materials, and the insulating materials may include organic insulating materials and inorganic insulating materials, wherein the organic insulating materials may include resins and plastics, and the inorganic insulating materials may include silicon nitride, silicon oxide or silicon oxynitride.

[0111] Illustratively, the materials of the above-mentioned covering layers may all include organic insulating materials, such as polyimide (PI).

[0112] Illustratively, the materials of the above-mentioned insulating layers may all include organic insulating materials, such as polypropylene (PP).

[0113] Illustratively, the materials of the above-mentioned bonding layers may all include adhesives or glues.

[0114] In at least one circuit board provided in an embodiment of the present application, as shown in Figure 7, the portion of the circuit board located in the second area A2 includes a first covering layer F1, a first adhesive layer AD1, a second conductive layer L2, a second covering layer F2, a third conductive layer L3, a second adhesive layer AD2 and a fourth covering layer F4 arranged in sequence in a direction perpendicular to the plane of the circuit board. A third hollow groove C3 is provided on the second adhesive layer AD2 and the fourth covering layer F4, and the orthographic projection of the area enclosed by the outer contour of the third hollow groove C3 on the third conductive layer L3 covers the gold finger GF.

[0115] The above “covering” means that the area of ​​the region enclosed by the outer contour of the third hollow groove C3 is greater than or equal to the area of ​​the region where the gold finger GF is located, so that the third hollow groove C3 can completely reveal the gold finger GF.

[0116] In the embodiment of the present application, the first shielding layer EMI1 and the second shielding layer EMI2 are not provided in the second area A2. Instead, the electromagnetic shielding and heat dissipation functions are achieved by providing the first conductive pattern D1, the second conductive pattern D2 and the third conductive pattern D3 on the second conductive layer L2.

[0117] In addition, in an embodiment of the present application, a third hollow groove C3 is provided on the second adhesive layer AD2 and the fourth covering layer F4, so that the third hollow groove C3 exposes the gold finger GF provided on the third conductive layer L3, thereby facilitating the binding of multiple gold fingers GF to the wiring area of ​​the display panel.

[0118] As shown in Figure 7, the portion of the circuit board located in the first area A1 includes a first shielding layer EMI1, a first covering layer F1, a first adhesive layer AD1, a second conductive layer L2, a second covering layer F2, a third conductive layer L3, a second adhesive layer AD2, a fourth covering layer F4 and a second shielding layer EMI2 which are arranged in sequence.

[0119] In some embodiments of the present application, the first conductive island I1 and the second conductive island I2 disposed in the first region A1 of the second conductive layer L2 and the shielding layer may have the following positional relationship:

[0120] In the first type, the orthographic projections of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 do not overlap with the orthographic projection of the second shielding layer EMI2 on the third conductive layer L3.

[0121] In the second case, the orthographic projections of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 do not overlap with the orthographic projection of the first shielding layer EMI1 on the third conductive layer L3.

[0122] In the third case, the orthographic projection of at least one of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 overlaps with the orthographic projection of the second shielding layer EMI2 on the third conductive layer L3.

[0123] Fourthly, the orthographic projection of at least one of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 overlaps with the orthographic projection of the first shielding layer EMI1 on the third conductive layer L3.

[0124] It should be noted that, in this specification, “there is overlap” means at least partial overlap, including both partial overlap and complete overlap.

[0125] If the design space permits, it can be set that the orthographic projection of at least one of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 overlaps with the orthographic projection of the second shielding layer EMI2 on the third conductive layer L3, and the orthographic projection of at least one of the first conductive island I1 and the second conductive island I2 on the third conductive layer L3 overlaps with the orthographic projection of the first shielding layer EMI1 on the third conductive layer L3, thereby further improving the electromagnetic shielding performance and further improving the signal transmission stability of the circuit board and the display module.

[0126] Exemplarily, the circuit board may further include a plurality of lead terminals Pin out as shown in FIG8 , which are arranged in the third conductive layer L3 and electrically connected to each gold finger GF, wherein each gold finger GF is electrically connected to the functional device Q or trace in the third area A3 through the lead terminal Pin out.

[0127] Exemplarily, the circuit board may further include a flexible conductive film DDM and a connector CNT (Connecter) as shown in FIG. 4 , wherein the connector CNT may be electrically connected to a SOC chip (System on Chip).

[0128] This specification only introduces the structures and components in the circuit board that are related to the invention. Of course, the circuit board may also include other structures and components. For details, please refer to the introduction in the relevant technology, which will not be repeated here.

[0129] An embodiment of the present application provides a display module, as shown in Figure 5, including a display panel and a circuit board FPC as described above, multiple gold fingers GF in the circuit board FPC are electrically connected to the display panel, and the orthographic projection of the first area A1 of the circuit board on the display panel covers at least part of the routing area (PNL routing area) of the display panel.

[0130] The orthographic projection of the first area A1 of the circuit board on the display panel covers at least a portion of the wiring area (PNL wiring area) of the display panel, including:

[0131] The first case: the orthographic projection of the first area A1 of the circuit board on the display panel covers a portion of the wiring area (PNL wiring area) of the display panel.

[0132] The second situation: the orthographic projection of the first area A1 of the circuit board on the display panel covers the entire wiring area (PNL wiring area) of the display panel.

[0133] In an embodiment of the present application, by setting the orthographic projection of the first area A1 of the circuit board on the display panel to cover at least part of the wiring area (PNL wiring area) of the display panel, when the circuit board FPC is bound to the display panel and is not bent to the back of the display panel, since the first area A1 overlaps with the wiring area (PNL wiring area) of the display panel, the newly added first area A1 does not increase the size of the display area AA of the display module pointing to the direction of the circuit board FPC; and by setting the first hollow groove C1 in the first area A1, the driver chip DIC is electrically connected to the wiring area of ​​the display panel through the first hollow groove C1, ensuring the normal electrical connection between the driver chip DIC and the wiring area of ​​the display panel; in addition, since the signal line originally set in the third area A3 in the related art is set in the first area A1, the design space of the third area A3 can be greatly reduced, and the size of the third area A3 along the direction from the first area A1 to the second area A2 is reduced, thereby reducing the design space of the display module.

[0134] In at least one display module provided in an embodiment of the present application, as shown in Figure 5, the display module also includes a driver chip DIC, the driver chip DIC is electrically connected to the display panel, and the orthographic projection of the driver chip DIC on the display panel overlaps with the area enclosed by the orthographic projection of the first hollow groove C1 of the circuit board FPC on the display panel.

[0135] For example, the overlap between the orthographic projection of the driver chip DIC on the display panel and the area enclosed by the orthographic projection of the first hollow groove C1 of the circuit board FPC on the display panel includes but is not limited to the following situations:

[0136] The first is that the orthographic projection of the driver chip DIC on the display panel and the orthographic projection of the area enclosed by the outer contour of the first hollow groove C1 on the display panel partially overlap; at this time, the orthographic projection area of ​​the driver chip DIC on the display panel can be larger than the orthographic projection area of ​​the area enclosed by the outer contour of the first hollow groove C1 on the display panel.

[0137] The second type is that the orthographic projection of the driver chip DIC on the display panel is located within the orthographic projection of the area enclosed by the outer contour of the first hollow groove C1 on the display panel. At this time, the orthographic projection area of ​​the driver chip DIC on the display panel is less than or equal to the orthographic projection area of ​​the area enclosed by the outer contour of the first hollow groove C1 on the display panel.

[0138] In at least one display module provided in an embodiment of the present application, the display panel includes a display surface and a back surface. As shown in Figure 6 , the first area A1 of the circuit board is configured to bend toward the back surface of the display panel. A portion of the first area A1 is bonded to the back surface via conductive fabric. The "display surface" refers to the side capable of displaying images.

[0139] In an exemplary embodiment, the routing area (PNL routing area) of the display panel and the first area A1 can be bent to the back of the display panel at the same time and attached to the back. At this time, the routing area of ​​the display panel is located between the back and the first area A1 of the circuit board.

[0140] In actual applications, the circuit board FPC is fixed (bound) to the routing area of ​​the display panel. When the routing area (PNL routing area) of the display panel and the first area A1 are bent to the back of the display panel at the same time, the circuit board is fixed to the routing area, and the routing area is adhered to the back of the display panel through the conductive cloth. In this way, the first conductive island I1, the second conductive island I2, the first shielding layer EMI1 and the second shielding layer EMI2 in the circuit board can shield the first area A1 of the circuit board and the line signals in the routing area. In addition, the conductive cloth can shield the line signals on the back of the display panel and the line signals in the routing area of ​​the display panel. In this way, the circuit stability of the display module can be further improved, and the display effect and reliability of the display module can be improved.

[0141] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A circuit board, applied to a display panel, comprising a first area, a second area, and a third area, wherein the second area is located between the first area and the third area; in, The first area and the second area include at least two conductive layers, and the third area includes at least three conductive layers; the first area is provided with a first hollow groove and a signal line, the first area overlaps with the wiring area of ​​the display panel, and the circuit in the wiring area is electrically connected to the driver chip through the first hollow groove, the second area is provided with multiple gold fingers, and the third area is provided with multiple functional devices.

2. The circuit board according to claim 1, wherein The first area is further provided with a plurality of test terminals, including a power supply test terminal and a shift register test terminal, and the test terminals are configured to detect the circuit of the display panel.

3. The circuit board according to claim 1, wherein The signal line includes a power signal line.

4. The circuit board according to claim 1, wherein In a direction perpendicular to the plane of the circuit board, the portion of the circuit board located in the third area includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; the portion of the circuit board located in the second area includes the second conductive layer and the third conductive layer; and the portion of the circuit board located in the first area includes the second conductive layer and the third conductive layer; an insulating material is provided between any two adjacent conductive layers; Among them, the first hollow groove passes through the second conductive layer and the third conductive layer, the gold finger is arranged on the third conductive layer, the functional device is arranged on the side of the first conductive layer away from the second conductive layer, and the first area is also provided with a plurality of test terminals, and the test terminals are arranged on the second conductive layer.

5. The circuit board according to claim 4, wherein the third conductive layer is arranged to be opposite to the wiring area of ​​the display panel in a direction perpendicular to the plane of the circuit board, and the second conductive layer is located on a side of the third conductive layer away from the display panel; and the gold finger is configured to be bound to the wiring area.

6. The circuit board according to claim 4, wherein The signal line includes a power signal line, and the power signal line includes a first power line and a second power line. The first power line includes a first end, a first main part, and a second end. The first main part of the first power line is arranged on the second conductive layer and is located on the side of the first hollow groove away from the second area. The first end and the second end of the first power line are arranged on the third conductive layer; the second power line includes a third end, a second main part, and a fourth end. The second power line is arranged on the third conductive layer, and the second main part of the second power line overlaps with the first main part of the first power line.

7. The circuit board according to claim 6, wherein: The portion of the third conductive layer located in the first area includes a plurality of first connecting lines, and the portion of the second conductive layer located in the first area includes a plurality of second connecting lines, the first connecting lines are electrically connected to the gold fingers, and the second connecting lines are electrically connected to the first connecting lines and the test terminals respectively.

8. The circuit board according to claim 7, wherein: The portion of the second conductive layer located in the second area includes a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially arranged along a first direction, wherein the first direction is a direction from the first area to the second area; Among them, the orthographic projection of the second conductive pattern on the third conductive layer covers the multiple gold fingers, and the second conductive pattern is a continuous structure; the first conductive pattern and the third conductive pattern are both grid structures, and the orthographic projections of the first conductive pattern and the third conductive pattern on the third conductive layer do not overlap with the multiple gold fingers.

9. The circuit board according to claim 8, wherein The first conductive pattern, the second conductive pattern, and the third conductive pattern are grounded, respectively.

10. The circuit board according to claim 4, wherein The portion of the second conductive layer located in the first area is further provided with a first conductive island and a second conductive island, the first hollow groove, the signal line and the test terminal are all arranged in the area between the first conductive island and the second conductive island, and the first conductive island and the second conductive island are grounded.

11. The circuit board according to any one of claims 4 to 10, wherein: The portion of the third conductive layer located in the second area includes an alignment pattern, the second conductive layer further includes a second hollow groove, and an orthographic projection of the alignment pattern on the second conductive layer is located in the second hollow groove.

12. The circuit board according to any one of claims 4 to 10, wherein: In a direction perpendicular to the plane where the circuit board is located, the portion of the circuit board located in the third area includes a first shielding layer, a first covering layer, a first adhesive layer, the first conductive layer, a first insulating layer, the second conductive layer, a second covering layer, the third conductive layer, a second insulating layer, the fourth conductive layer, a third covering layer, the fifth conductive layer, a third insulating layer, the sixth conductive layer, a second adhesive layer, a fourth covering layer and a second shielding layer arranged in sequence; the multiple functional devices are located on a side of the first covering layer away from the first adhesive layer, and the multiple functional devices and the orthographic projection of the first shielding layer on the first conductive layer do not overlap with each other.

13. The circuit board according to claim 12, wherein: In a direction perpendicular to the plane of the circuit board, the portion of the circuit board located in the second area includes the first covering layer, the first adhesive layer, the second conductive layer, the second covering layer, the third conductive layer, the second adhesive layer, and the fourth covering layer, which are arranged in sequence. A third hollow groove is provided on the second adhesive layer and the fourth covering layer, and the orthographic projection of the area enclosed by the outer contour of the third hollow groove on the third conductive layer covers the gold finger; In a direction perpendicular to the plane where the circuit board is located, the portion of the circuit board located in the first area includes the first shielding layer, the first covering layer, the first bonding layer, the second conductive layer, the second covering layer, the third conductive layer, the second adhesive layer, the fourth covering layer and the second shielding layer.

14. A display module, comprising a display panel and a circuit board as described in any one of claims 1 to 13, wherein the multiple gold fingers in the circuit board are electrically connected to the display panel, and the orthographic projection of the first area of ​​the circuit board on the display panel covers at least a portion of the routing area of ​​the display panel.

15. The display module according to claim 14, wherein: The display module further includes a driving chip electrically connected to the display panel, and an orthographic projection of the driving chip on the display panel overlaps with an area enclosed by an orthographic projection of the first hollow groove of the circuit board on the display panel.

16. The display module according to claim 15, wherein: The display panel includes a display surface and a back surface. The first area of ​​the circuit board is configured to be bendable to the back surface of the display panel. A portion of the first area is bonded to the back surface via a conductive cloth.

17. A display device comprising the display module according to any one of claims 14 to 16.

Images