Delay reporting method and apparatus

Abstract

Provided in the embodiments of the present application is a delay reporting method. The method can be applied to a first module. The first module may report a target delay corresponding to data at a plurality of specific positions in a data stream, wherein the plurality of specific positions are at intervals of a fixed length, and a cycle of the plurality of specific positions corresponds to a cycle in which padding sequences are inserted into the data stream. In the embodiments of the present application, if the first module corresponds to a sending end, the target delay corresponding to the data at the specific positions is equivalent to a maximum delay, and if the first module corresponds to a receiving end, the target delay corresponding to the data at the specific positions is equivalent to a minimum delay. It can be seen that by means of the present solution, delay information can be accurately reported.

Description

A method and device for reporting time delay

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 1, 2024, with application number 202410243239.5 and invention name “A method and device for delay reporting”, and the Chinese patent application filed with the State Intellectual Property Office on May 8, 2024, with application number 202410565627.5 and invention name “A method and device for delay reporting”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communications, and in particular to a method and device for reporting time delays. Background Art

[0003] Communication devices can exchange data with each other. A sender can send a message to a receiver, and the sender can add a message sending timestamp to the message sent to the receiver. Correspondingly, after receiving the message sent by the sender, the receiver can record the message receiving timestamp to facilitate subsequent processing measures based on the sending timestamp and receiving timestamp. For example, in a time synchronization scenario, the receiver can perform time synchronization based on the sending timestamp and receiving timestamp. In this case, the sender can be understood as a communication device that acts as a sender, and the receiver can be understood as a communication device that acts as a receiver.

[0004] The accuracy of the aforementioned sending timestamp and receiving timestamp directly affects the accuracy of the results obtained by executing subsequent processing measures. For example, in the scenario of time synchronization, the accuracy of the sending timestamp and receiving timestamp directly affects the accuracy of time synchronization.

[0005] Therefore, how the sending end accurately determines the sending timestamp of the message and how the receiving end accurately determines the receiving timestamp of the message are problems that need to be solved urgently. Summary of the Invention

[0006] The embodiments of the present application provide a method and apparatus for reporting time delay, which can accurately report time delay.

[0007] In the first aspect, the present application provides a delay reporting method, which can be applied to the first module. The first module can report the target delay corresponding to the data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream. In an embodiment of the present application, if the first module corresponds to the transmitting end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay; if the first module corresponds to the receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay. It can be seen that, by using this solution, delay information can be accurately reported.

[0008] In one possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks. Here, 8712 is the period corresponding to after the padding sequence is inserted into the data stream, and 8704 is the period corresponding to before the padding sequence is inserted into the data stream. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position corresponds to 8704, and when the first module corresponds to the receiving end, the period of the specific position corresponds to 8712. Here, the period of the specific position is an integer multiple of 8172 data blocks or an integer multiple of 8704 data blocks, which can be understood as the period corresponding to an integer multiple of the length of 8172 data blocks or an integer multiple of the length of 8704 data blocks. In one possible implementation, the data block includes 128 bits or 120 bits. For example, if the data block is a data block that has been encoded with a forward error correction (FEC) inner code, the data block includes 128 bits. If the data block has not been FEC inner code encoded, or if the data block has been FEC inner code decoded, the data block includes 120 bits. As a specific example, when the first module corresponds to the transmitting end, the data block includes 120 bits, and when the first module corresponds to the receiving end, the data block includes 128 bits.

[0009] In one possible implementation, the periods of the multiple specific positions are integer multiples of any of the following values: 8704*120=1044480 bits; or 8704*128=1114112 bits; or 8712*128=1115136 bits, or 8712*120=1045440 bits. Wherein, if the first module corresponds to the transmitting end, before the first module performs the check sequence (pad) addition and padding sequence addition operations on the data stream, the period of the specific position is an integer multiple of 8704*120=1044480 bits; after the first module performs the check sequence addition operation on the data stream, the period of the specific position is an integer multiple of 8704*128=1114112 bits; after the first module further performs the check sequence addition operation on the data stream, the period of the specific position is an integer multiple of 8712*128=1115136 bits. If the first module corresponds to the receiving end, before the first module performs the check sequence deletion operation and the padding sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8712*128=1115136 bits; after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*128=1114112 bits; after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*120=1044480 bits.

[0010] In one possible implementation, the period of the multiple specific positions may be an integer multiple of 64 data blocks or an integer multiple of 65 data blocks. Here, 65 is the period corresponding to after the padding sequence is inserted into the data stream, and 64 is the period corresponding to before the padding sequence is inserted into the data stream. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position is an integer multiple of 64 data blocks, and when the first module corresponds to the receiving end, the period of the specific position is an integer multiple of 65 data blocks. Here, the period of the specific position being an integer multiple of 64 data blocks or an integer multiple of 65 data blocks can be understood as the period corresponding to an integer multiple of the length of 64 data blocks or an integer multiple of the length of 65 data blocks.

[0011] In a possible implementation, each of the aforementioned 64 data blocks and 65 data blocks may include 4 bits. In this scenario, the padding sequence may be inserted by inserting a 4-bit pilot signal every 64 4-bit data blocks.

[0012] In one possible implementation, the specific position may be the starting position of a data block. The starting position of a data block may be the first byte, the first bit, or the first symbol of the data block. In a scenario where the data block includes 128 bits, the data block mentioned here may be an FEC codeword.

[0013] In a specific example, the FEC codeword may be an FEC inner codeword. In other words, the aforementioned specific position may be the starting position of the FEC inner codeword.

[0014] In a possible implementation, the specific position is the starting position of the next data block after the padding sequence is inserted into the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0015] In one possible implementation, the data stream is a data stream obtained through FEC inner coding. Specifically, if the first module corresponds to the transmitting end, the first module may perform FEC inner coding and padding operations on the data entering the first module. Accordingly, in one example, the data stream referred to herein may be the data stream after the FEC inner coding and padding operations are performed. If the first module corresponds to the receiving end, in one example, the data stream may be the data stream sent by the transmitting end to the first module. In other words, the data stream is the data stream entering the first module and subjected to FEC inner coding and padding operations at the transmitting end. In another example, considering that the receiving end may perform FEC inner coding decoding on the data stream after the transmitting end sends it to the receiving end, the data stream may also be the data stream obtained after the receiving end performs FEC inner coding decoding on the received data stream. In other words, if the first module corresponds to the receiving end, in another example, the data stream may be the data stream obtained after FEC inner coding decoding.

[0016] In one possible implementation, in addition to inserting a padding sequence into the data stream, the transmitter may also insert a check sequence. Specifically, when the transmitter performs FEC inner code encoding on the data stream, an 8-bit check sequence may be inserted for every 128 bits of data. Since the transmitter inserts a 1024-bit pad every 8704 FEC inner code blocks when inserting the pad, the period of inserting the padding sequence into the data stream by the transmitter is an integer multiple of the period of inserting the check sequence into the data stream. Precisely because the period of inserting the padding sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream, the peak position of the large sawtooth wave overlaps with the peak position of the small sawtooth wave, and the trough position of the large sawtooth wave overlaps with the trough position of the small sawtooth wave. Therefore, the period of the aforementioned specific position can be determined based on the period of inserting the padding sequence into the data stream to determine the target delay.

[0017] In one possible implementation, the target latency is the latency of data at the aforementioned multiple specific locations passing through the first module. Alternatively, the target latency is the latency of data at the aforementioned multiple specific locations passing through the inner FEC layer in the first module. If the first module is an optical module, the target latency is the latency of data at the aforementioned multiple specific locations passing through the optical module. Alternatively, the target latency is the latency of data at the aforementioned multiple specific locations passing through the inner FEC layer in the optical module. The inner FEC layer is a layer used to implement the inner FEC function.

[0018] In one possible implementation, among the data at the aforementioned multiple specific locations, the data at each specific location may correspond to a first delay, and therefore, the data at the aforementioned multiple specific locations may correspond to multiple first delays. Considering that the existing Institute of Electrical and Electronics Engineers (IEEE) 802.3cx Chapter 90 defines corresponding maximum delay registers and minimum delay registers for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Chapter 90 mechanism for reporting delays at the physical layer, the maximum value and / or minimum value of the multiple first delays may be reported. In other words, the aforementioned target delay may be the maximum value and / or minimum value of the multiple first delays. In this case, the first module may also measure the first delay corresponding to the data at each specific location in the data at the multiple specific locations to obtain multiple first delays, so as to report the maximum value and / or minimum value of the multiple first delays and realize the reporting of delay information.

[0019] In a possible implementation, a new register may be defined to report the aforementioned maximum value and / or minimum value to the second module.

[0020] As a specific example, a maximum transmit (TX) delay register and / or a minimum transmit delay register for inner code FEC are defined. The TX maximum delay register is used by a module serving as a transmitter to report the maximum value, and the TX minimum delay register is used by a module serving as a transmitter to report the minimum value. In other words, when a first module corresponds to a transmitter, the first module can use the TX maximum delay register for inner code FEC to report the maximum value to the second module, and / or use the TX minimum delay register for inner code FEC to report the minimum value to the second module.

[0021] As another specific example, a maximum receive (RX) delay register and / or a minimum receive (RX) delay register for the inner code FEC are defined. The RX maximum delay register is used by a module serving as a receiving end to report the maximum value, and the RX minimum delay register is used by a module serving as a receiving end to report the minimum value. In other words, when a first module corresponds to a receiving end, the first module can use the RX maximum delay register for the inner code FEC to report the maximum value to the second module, and / or use the RX minimum delay register for the inner code FEC to report the minimum value to the second module.

[0022] In a possible implementation, the first module may use an existing register to report the maximum value and / or minimum value to the second module. In this way, the target delay can be reported by using the existing register.

[0023] As a specific example, if the first module corresponds to the transmitting end, the first module may use the TX maximum latency register of the physical medium attachment (PMA) / physical media dependent (PMD) to report the maximum value to the second module. Similarly, the first module may use the TX minimum latency register of the PMA / PMD to report the minimum value to the second module.

[0024] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum latency register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the RX minimum latency register of the PMA / PMD to report the minimum value to the second module.

[0025] In one possible implementation, the first module may report the target delay to a second module. In one example, the second module may be a media access control (MAC) layer module of the communication device. The MAC layer module may then compensate its own recorded timestamps based on the target delay, thereby making the compensated timestamps more accurate.

[0026] In a possible implementation, the first module may be an optical module or a physical (PHY) layer chip, which can provide an inner code FEC function.

[0027] In one possible implementation, the optical module includes an inner code FEC module, which is used to implement an inner code FEC function. The inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module. The inner code FEC encoding module is used to implement the FEC inner code encoding function, and the inner code FEC decoding module is used to implement the FEC inner code decoding function.

[0028] On the second aspect, the present application provides a delay reporting method, which can be applied to a first module, and the first module can obtain the delay jitter value of the target data passing through the first submodule in the first module. The target data is the data sent by the first module, or the target data is the data received by the first module. There is a submodule with a fixed value of delay jitter in the first submodule. Furthermore, based on the delay jitter value, delay information is reported to the second module. In an embodiment of the present application, considering that the first submodule will introduce delay jitter, thereby causing jitter in the delay of the target data passing through the first module, the first module reports the delay information to the second module based on the delay jitter value introduced by the first submodule, so that the reported delay information is more accurate.

[0029] In one possible implementation, the first module may further determine a first delay for the target data to pass through a second submodule within the first module. As an example, the second submodule may be a submodule that introduces almost no delay jitter. Accordingly, in a specific implementation, when the first module reports delay information to the second module, the delay information may be reported to the second module based on the delay jitter value and the first delay. In other words, the first module may report delay information to the second module based on the delay jitter value and the first delay for the target data to pass through the second submodule that introduces almost no delay jitter, thereby making the delay information reported by the first module to the second module more accurate.

[0030] In a possible implementation, the first module may determine a target delay according to the delay jitter value and the first delay, and report the target delay as the aforementioned delay information to the second module.

[0031] In one possible implementation, if the first module corresponds to a communication device serving as a transmitter, the first communication device may determine the sum of the delay jitter value and the first delay as the target delay. If the first communication device corresponds to a communication device serving as a receiver, the first communication device may determine the target delay as the difference between the first delay and the delay jitter value. This approach ensures that the target delay reported by the first module satisfies the requirement that "for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay."

[0032] In one possible implementation, considering that the existing IEEE 802.3cx Section 90 defines corresponding maximum delay registers and minimum delay registers for each layer of the physical layer, in order to be compatible with the current IEEE 802.3cx Section 90 mechanism for reporting delays at the physical layer, the first delay may include two delays, namely, the maximum delay for the target data to pass through the second submodule, and the minimum delay for the target data to pass through the second submodule. Accordingly, in this case, the target delay includes: a maximum target delay obtained based on the maximum delay and the delay jitter value, and a minimum target delay obtained based on the minimum delay and the delay jitter value.

[0033] In a possible implementation, a new register may be defined to report the aforementioned maximum target delay and / or minimum target delay to the second module.

[0034] As a specific example, a TX maximum delay register and / or a TX minimum delay register for inner code FEC are defined. The TX maximum delay register is used by a module acting as a transmitter to report the maximum target delay, and the TX minimum delay register is used by a module acting as a transmitter to report the minimum target delay. In other words, when a first module corresponds to a transmitter, the first module can use the TX maximum delay register for inner code FEC to report the maximum target delay to the second module, and use the TX minimum delay register for inner code FEC to report the minimum target delay to the second module.

[0035] As another specific example, an RX maximum delay register and / or an RX minimum delay register for inner code FEC are defined. The RX maximum delay register is used by a module serving as a receiving end to report the maximum target delay, and the RX minimum delay register is used by a module serving as a receiving end to report the minimum target delay. In other words, when a first module corresponds to a receiving end, the first module can use the RX maximum delay register for inner code FEC to report the maximum target delay to the second module, and use the RX minimum delay register for inner code FEC to report the minimum target delay to the second module.

[0036] In a possible implementation, the first module may use an existing register to report the maximum target delay and / or the minimum target delay to the second module. In this way, the target delay can be reported by using the existing register.

[0037] As a specific example, if the first module corresponds to the transmitting end, the first module can use the TX maximum latency register of the physical medium attachment (PMA) / physical media dependent (PMD) to report the maximum target latency to the second module. Similarly, the first module can use the TX minimum latency register of the PMA / PMD to report the minimum target latency to the second module.

[0038] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum latency register of the PMA / PMD to report the maximum target latency to the second module. Similarly, the first module can use the RX minimum latency register of the PMA / PMD to report the minimum target latency to the second module.

[0039] In a possible implementation, the second submodule may be a submodule of the first module other than the first submodule.

[0040] In one possible implementation, if the first module corresponds to a transmitting end, the second submodule may be, for example, a submodule in an inner code FEC module that performs operations such as convolution interleaving, distribution, and modulation coding. If the first module corresponds to a receiving end, the second submodule may be, for example, a submodule in an inner code FEC module that performs operations such as inverse convolution deinterleaving, multiplexing, and modulation decoding.

[0041] In one possible implementation, determining the first delay for the target data to pass through the second submodule in the first module may involve obtaining a preset first delay. The first delay may be a value determined during the design phase of the first module, and the value of the first delay is related to the performance of the first module.

[0042] In a possible implementation, when determining the first delay of the target data passing through the second submodule in the first module, the delay of the target data passing through the second submodule may be counted to obtain the first delay.

[0043] In one possible implementation, the time delay of the target data passing through the second submodule can be calculated by calculating the time delay of at least one bit of the target data passing through the second submodule to obtain the first time delay. For example, the target data can be sampled and the time delay of the sampled data passing through the second submodule can be calculated. In another example, the time delay of each bit of the target data passing through the second submodule can be calculated to obtain the first time delay.

[0044] In one possible implementation, the first module further includes a third submodule, and the first module can further determine a second delay for the target data to pass through the third submodule in the first module. In a scenario where the first module determines the second delay, the first module can report the delay information to the second module based on the delay jitter value and the second delay, thereby accurately reporting the delay information to the second module.

[0045] In a possible implementation, the third submodule may be another submodule in the first module that is different from the first submodule and the second submodule. For example, the third submodule may include a PMA submodule and a PMD submodule.

[0046] In one possible implementation, the second module includes: a media access control (MAC) layer module. In one possible implementation, the delay jitter value may be a preset fixed value. For example, when the first module is an optical module, the delay jitter value may include the sum of a first jitter value and a second jitter value. The first jitter value may be a delay jitter value introduced by adding or deleting a check sequence and interleaving or deinterleaving a data stream. The second jitter value may be a delay jitter value introduced by adding or deleting a pad. The fixed value may be, for example, a value between 4.6 ns and 4.8 ns.

[0047] In one possible implementation, the first submodule includes a submodule for detecting delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence. As a specific example, for a transmitting end, the first submodule may include: a submodule for detecting delay jitter caused by adding a check sequence, and a submodule for detecting delay jitter caused by adding a padding sequence. Correspondingly, for a receiving end, the first submodule may include: a submodule for detecting delay jitter caused by deleting a check sequence, and a submodule for detecting delay jitter caused by deleting a padding sequence.

[0048] In one possible implementation, the first submodule includes a submodule for detecting delay jitter caused by interleaving or deinterleaving of data streams. As a specific example, for a transmitting end, the first submodule may include a submodule for detecting delay jitter caused by interleaving of data streams. Correspondingly, for a receiving end, the first submodule may include a submodule for detecting delay jitter caused by deinterleaving of data streams.

[0049] In one possible implementation, the submodule that experiences delay jitter due to adding a check sequence may be a submodule within the inner code FEC module that performs FEC inner code encoding; the submodule that experiences delay jitter due to adding a padding sequence may be a submodule within the inner code FEC module that performs padding sequence addition; and the submodule that experiences delay jitter due to data stream interleaving may be a submodule within the inner code FEC module that performs data stream interleaving. In other words, the first submodule may include: a submodule within the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition.

[0050] In one possible implementation, the submodule experiencing delay jitter due to check sequence deletion may be a submodule within the inner code FEC module that performs FEC inner code decoding; the submodule experiencing delay jitter due to padding sequence deletion may be a submodule within the inner code FEC module that performs padding sequence deletion; and the submodule experiencing delay jitter due to data stream deinterleaving may be a submodule within the inner code FEC module that performs data stream deinterleaving. In other words, the first submodule may include: a submodule within the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence deletion.

[0051] In one possible implementation, both the transmitting end and the receiving end can perform a cyclic shift operation. In one example, if the shift direction corresponding to the cyclic shift operation performed by the receiving end is the same as the shift direction corresponding to the cyclic shift operation performed by the transmitting end, the first submodule may include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the delay jitter value introduced by the cyclic shift submodule may be 4.5 nanoseconds.

[0052] In one possible implementation, when the first submodule further includes a cyclic shift submodule, the aforementioned delay jitter value may be calculated by adding the delay jitter of 4.5 ns introduced by the cyclic shift submodule to the sum of the first jitter value and the second jitter value. Since the sum of the first jitter value and the second jitter value is between 4.6 ns and 4.8 ns, the aforementioned delay jitter value may be between (4.5 ns + 4.6 ns = 9.1 ns) and (4.5 ns + 4.8 ns = 9.3 ns).

[0053] In one possible implementation, the target data may correspond to the data included in one cycle of the specific position described in the first aspect above. For example, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0054] In a possible implementation, the data block includes 128 bits or 120 bits.

[0055] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0056] In a third aspect, an embodiment of the present application provides a delay reporting device, which includes: a sending unit for reporting the target delay corresponding to data at multiple specific positions in a data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream.

[0057] In one possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

[0058] In a possible implementation, the data block includes 128 bits, 120 bits, or 4 bits.

[0059] In a possible implementation, the period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

[0060] In a possible implementation, the specific position is a starting position of an FEC codeword, and the starting position is the first bit, the first symbol, or the first byte of the FEC codeword.

[0061] In a possible implementation, the FEC codeword includes: an FEC inner codeword.

[0062] In a possible implementation, the data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

[0063] In a possible implementation manner, a period for inserting a filling sequence into the data stream is an integer multiple of a period for inserting a check sequence into the data stream.

[0064] In a possible implementation, the target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

[0065] In one possible implementation, the device further includes: a processing unit, configured to measure a first delay corresponding to data at each of the multiple specific locations to obtain multiple first delays; wherein the target delay includes a maximum value and / or a minimum value among the multiple first delays.

[0066] In a possible implementation, the sending unit is configured to: report the maximum value using a TX maximum delay register of the inner code FEC; and / or report the minimum value using a TX minimum delay register of the inner code FEC.

[0067] In one possible implementation, the sending unit is configured to: report the maximum value using a TX maximum delay register of a physical medium attachment (PMA) / physical medium dependent (PMD); and / or report the minimum value using a TX minimum delay register of a PMA / PMD.

[0068] In a possible implementation, the sending unit is configured to: report the maximum value using an RX maximum delay register of the inner code FEC; and / or report the minimum value using an RX minimum delay register of the inner code FEC.

[0069] In a possible implementation, the sending unit is configured to: report the maximum value by using the RX maximum delay register of the PMA / PMD; and / or report the minimum value by using the RX minimum delay register of the PMA / PMD.

[0070] In a possible implementation manner, the sending unit is configured to report the target delay corresponding to the data at the multiple specific positions in the data stream to a media access control (MAC) layer.

[0071] In a possible implementation, the device is applied to an optical module or a physical (PHY) layer chip.

[0072] In a possible implementation, the optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

[0073] In a possible implementation, the specific position is the starting position of the next data block after the padding sequence is inserted into the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0074] In a fourth aspect, an embodiment of the present application provides a delay reporting device, which is applied to a first module, and the device includes: a processing unit, which is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule including a submodule with a delay jitter with a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; a sending unit, which is used to report the delay information to the second module based on the delay jitter value.

[0075] In one possible implementation, the processing unit is further used to determine a first delay of the target data passing through a second submodule in the first module; and the sending unit is used to report the delay information to the second module based on the delay jitter value and the first delay.

[0076] In a possible implementation manner, the sending unit is configured to report to the second module a target delay obtained according to the delay jitter value and the first delay.

[0077] In a possible implementation, the target delay includes: the sum of the delay jitter value and the first delay; or a difference obtained by subtracting the delay jitter value from the first delay.

[0078] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained according to the maximum delay and the delay jitter value, and the minimum target delay obtained according to the minimum delay and the delay jitter value.

[0079] In one possible implementation, if the target data is data sent by the first module, the sending unit is used to: use the TX maximum delay register of the inner code forward error correction FEC to report the maximum target delay to the second module; use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0080] In one possible implementation, if the target data is data sent by the first module, the sending unit is used to: use the TX maximum delay register of the physical medium attachment PMA / physical medium dependent PMD to report the maximum target delay to the second module; and use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0081] In one possible implementation, if the target data is data received by the first module, the sending unit is used to: use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module; and use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0082] In one possible implementation, if the target data is data received by the first module, the sending unit is used to: use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module; use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0083] In a possible implementation, the second submodule includes: a submodule other than the first submodule.

[0084] In one possible implementation, the second submodule includes: a submodule in the inner code FEC module that performs convolution interleaving, distribution, and modulation coding operations; or a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

[0085] In a possible implementation manner, the processing unit is configured to obtain the preset first delay.

[0086] In a possible implementation, the processing unit is configured to: count a first time delay of the target data passing through the second submodule.

[0087] In a possible implementation, counting a delay of the target data passing through the second submodule includes counting a delay of at least one bit of the target data passing through the second submodule to obtain the first delay.

[0088] In one possible implementation, the processing unit is further used to determine the second delay of the target data passing through the third submodule in the first module; and the sending unit is used to report the delay information to the second module based on the delay jitter value and the second delay.

[0089] In a possible implementation, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0090] In a possible implementation, the second module includes: a media access control MAC layer module.

[0091] In a possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0092] In a possible implementation, the first submodule includes: a cyclic shift submodule.

[0093] In a possible implementation, the first submodule includes a submodule for detecting delay jitter caused by addition or deletion of a check sequence, or addition or deletion of a padding sequence.

[0094] In a possible implementation, the first submodule includes a submodule that detects delay jitter caused by interleaving or deinterleaving of data streams.

[0095] In one possible implementation, the first submodule includes: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition operations; or a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence removal operations.

[0096] In a possible implementation, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0097] In a possible implementation, the data block includes 128 bits or 120 bits.

[0098] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0099] In a fifth aspect, an embodiment of the present application provides a device. The device includes a processor configured to execute the method described in the first aspect and any one of the above first aspects; or the processor configured to execute the instructions or computer program in the memory to execute the method described in the second aspect and any one of the above second aspects.

[0100] In one possible implementation, the device also includes a memory, which is used to store instructions or computer programs, and the processor is used to execute the instructions or computer programs in the memory, triggering the method described in the first aspect of the device and any one of the above first aspects; or, the processor is used to execute the instructions or computer programs in the memory, and execute the method described in the second aspect and any one of the above second aspects.

[0101] In a sixth aspect, an embodiment of the present application provides a device comprising an interface circuit and a processing circuit, wherein the interface circuit is used to receive and / or send data, and the processing circuit is used to perform data processing.

[0102] In an example, the device can be used to perform the method described in any one of the first aspects above. In this case:

[0103] The interface circuit is used to report the target delay corresponding to data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a filling sequence in the data stream.

[0104] In one example, the processing circuit is used to measure the first delay corresponding to the data at each specific location among the data at the multiple specific locations to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0105] In yet another example, the device may be used to perform the method described in any one of the second aspects above. In this case:

[0106] The processing circuit is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule includes a submodule with a delay jitter having a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; the interface circuit is used to report the delay information to the second module based on the delay jitter value.

[0107] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, including instructions or a computer program, which, when running on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects, or, when running on a computer, enables the computer to execute the method described in the second aspect and any one of the above second aspects.

[0108] In an eighth aspect, an embodiment of the present application provides a computer program product comprising instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects, or enables the computer to execute the method described in the second aspect and any one of the above second aspects.

[0109] In the ninth aspect, an embodiment of the present application provides a chip, including an interface circuit and a processing circuit, and the chip is used to execute the method described in the first aspect and any one of the above first aspects; or, execute the method described in the second aspect and any one of the above second aspects.

[0110] In the tenth aspect, an embodiment of the present application provides an optical module, comprising an interface circuit and a processing circuit, wherein the optical module is used to execute the method described in the first aspect and any one of the above first aspects; or, to execute the method described in the second aspect and any one of the above second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0112] FIG1a is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0113] FIG1b is a schematic structural diagram of another communication device provided in an embodiment of the present application;

[0114] FIG1c is a schematic diagram of a delay introduced by an FEC function provided in an embodiment of the present application;

[0115] FIG1d is a schematic structural diagram of another communication device provided in an embodiment of the present application;

[0116] FIG1e is a schematic diagram of a delay introduced by an inner code FEC function provided in an embodiment of the present application;

[0117] FIG1f is a schematic diagram of a time delay introduced by another inner code FEC function provided in an embodiment of the present application;

[0118] FIG1g is a schematic diagram of a time delay introduced by another inner code FEC function provided in an embodiment of the present application;

[0119] FIG1h is a schematic diagram of a delay introduced by an inner code FEC function provided in an embodiment of the present application;

[0120] FIG2 is a schematic diagram of a flow chart of a delay reporting method provided in an embodiment of the present application;

[0121] FIG3 is a schematic structural diagram of a first module provided in an embodiment of the present application;

[0122] FIG4 is a flow chart of another delay reporting method provided in an embodiment of the present application;

[0123] FIG5 is a schematic diagram of an inner code FEC processing process provided by an embodiment of the present application;

[0124] FIG6 is a schematic diagram of the structure of a delay reporting device provided in an embodiment of the present application;

[0125] FIG7 is a schematic structural diagram of another delay reporting device provided in an embodiment of the present application;

[0126] FIG8 is a schematic structural diagram of a device provided in an embodiment of the present application;

[0127] FIG9 is a schematic structural diagram of a device provided in an embodiment of the present application;

[0128] FIG10 is a schematic diagram of the structure of a chip or optical module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0129] The embodiments of the present application provide a method and apparatus for reporting time delay, which can accurately report time delay.

[0130] To facilitate understanding, the application scenarios of reporting latency are first introduced.

[0131] In the time synchronization scenario, time synchronization can be performed between communication devices by means of interactive messages. The communication device mentioned in the embodiment of the present application can be a network device such as a switch, a router, a slicing packet network (SPN) device or an optical transmission network (OTN) device, or a component of a network device, such as a single board or line card or interface on a network device, or a functional module on a network device, or a chip, or a pluggable optical module on a network device, or a server, a network card on a server, or a network card of other devices, etc., which is not specifically limited in the embodiment of the present application. The communication devices can be directly connected, for example, but not limited to, via an Ethernet line or an optical cable.

[0132] The 1588 protocol is a high-precision time synchronization protocol. The 1588 protocol can provide nanosecond (ns) level time synchronization accuracy. Currently, the International Telecommunication Union (ITU-T) G.8273.2 defines four classes of time synchronization accuracy requirements, namely class A, class B, class C, and class D. Among them, the time accuracy corresponding to class A is ±100ns; the time accuracy corresponding to class B is ±70ns; the time accuracy corresponding to class C is ±30ns; and the time accuracy corresponding to class D is ±5ns. Therefore, in one example, communication devices can synchronize time by exchanging 1588 messages. The 1588 messages mentioned here can be understood as messages that comply with the 1588 protocol.

[0133] When communication devices exchange 1588 messages to perform time synchronization, in a specific implementation, the communication device that sends the 1588 message can add a sending timestamp in the 1588 message, and the sending timestamp indicates the time when the 1588 message was sent. Correspondingly, the communication device that receives the 1588 message will record the receiving timestamp of the 1588 message, and the receiving timestamp indicates the time when the 1588 message was received. Furthermore, the communication device that receives the 1588 message can perform time synchronization based on the aforementioned sending timestamp and receiving timestamp. Since the sending timestamp and receiving timestamp are input parameters for time synchronization, the accuracy of the sending timestamp and receiving timestamp directly affects the accuracy of time synchronization. In other words, it is particularly important to ensure the accuracy of the aforementioned sending timestamp and receiving timestamp.

[0134] Currently, a communication device records a timestamp in the following manner: a MAC layer of the communication device records the timestamp. In a specific scenario, for a communication device including an Ethernet interface, the MAC layer of the communication device may record the timestamp.

[0135] Next, the method of recording timestamps by the communication device is introduced in conjunction with the structure of the communication device.

[0136] Refer to Figure 1a, which is a schematic structural diagram of a communication device provided in an embodiment of the present application, including the structure of a transmitting end communication device and the structure of a receiving end communication device.

[0137] As shown in Figure 1a, both a transmitting and receiving communication device may include a MAC layer and a physical layer. The physical layer may include a PCS, a PMA, and a PMD. Furthermore, the application layer may correspond to upper-layer services, for example.

[0138] As the transmitter, its MAC layer generates MAC frames and sends them to the physical layer. For example, the MAC layer can receive data from upstream devices or upper-layer services and encapsulate the data into MAC frames. Alternatively, if the MAC layer does not receive data from upstream devices or upper-layer services, it generates a corresponding MAC frame based on the idle stream.

[0139] The MAC layer of the transmitting end sends the MAC frame to the physical layer of the transmitting end. The physical layer may include the PCS, PMA, and PMD. The MAC layer of the transmitting end may record the timestamp of when it sends the MAC frame to the physical layer as the aforementioned sending timestamp.

[0140] The PCS may process the received data stream and send the processed data to the PMA. The data stream mentioned here may be a bit stream including multiple bits, which may be obtained by processing the MAC frame.

[0141] The PMA can modulate the data from the PCS into a signal that the channel supports transmission.

[0142] The PMD is a signal transmitter used to transmit the signal modulated by the PMA through a transmission medium.

[0143] The physical layer of the receiving end receives the signal transmitted on the aforementioned transmission medium, processes the signal, and then passes it to the MAC layer of the receiving end. As mentioned above, the physical layer of the receiving end also includes PMD, PMA and PCS.

[0144] The PMD at the receiving end first receives the signal transmitted on the transmission medium. Then, the PMA demodulates the signal. The data obtained after PMA demodulation is passed to the PCS, and the PCS performs the corresponding operation on the received data, wherein the operation performed by the PCS at the receiving end is the inverse operation performed by the PCS at the transmitting end. Furthermore, the PCS can send the processed data stream to the MAC layer. At this point, after the MAC layer at the receiving end receives the data stream sent by the PCS, it can obtain the MAC frame sent by the transmitting end and further process the MAC frame, for example, parsing the MAC frame and sending it to the upstream device or upper-layer service. Among them, when the MAC layer at the receiving end receives the data stream processed by the PCS, the MAC layer at the receiving end can record the timestamp of its receipt of the data stream as the reception timestamp.

[0145] In order to support the high-precision time synchronization feature of 1588, the physical layer of the communication device can report the delay of the data stream passing through the physical layer to the MAC layer, so that when the MAC records the timestamp, it can compensate the recorded timestamp based on the delay of the data stream passing through the physical layer, thereby making the timestamp more accurate after the MAC layer compensates. Specifically:

[0146] For the sender, the MAC layer can add the delay of the data stream passing through the physical layer to the timestamp recorded by itself to obtain the sending timestamp. It is easy to understand that the sending timestamp can be considered as the timestamp of the physical layer of the sender actually sending the data stream.

[0147] For the receiving end, the MAC layer can subtract the delay of the data stream passing through the physical layer from the timestamp recorded by itself to obtain the receiving timestamp. It is not difficult to understand that the receiving timestamp can be considered as the timestamp when the physical layer of the receiving end actually receives the data stream.

[0148] As described above, the data stream transmitted at the physical layer is a bit stream consisting of multiple bits. The physical layer cannot identify which parts of the bit stream correspond to 1588 messages. Therefore, the physical layer cannot accurately calculate the latency of 1588 messages. To solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer latency. That is, the latency of the data stream passing through the physical layer is stable near a fixed value. In this way, the physical layer can report this fixed value to the MAC layer, and the MAC layer can compensate the timestamp based on this fixed value.

[0149] However, for some communication devices, such as those with 100GE Ethernet interfaces, the PCS of their physical layer includes an FEC function. The FEC function of the PCS performs operations such as adding and deleting parity bits and interleaving and deinterleaving data streams. These operations introduce latency jitter, resulting in unstable latency for data streams passing through the physical layer. In the embodiments of the present application, parity bits may also be referred to as parity sequences, and the two terms may be used interchangeably.

[0150] It should be noted that any communication device can serve as both a transmitter and a receiver. In other words, the roles of the transmitter and receiver shown in Figure 1a can be interchanged. If the roles of the transmitter and receiver shown in Figure 1a are interchanged, the direction of the data flow will also change accordingly, that is, the direction of the data flow can flow from the transmitter after the role swap to the receiver after the role swap.

[0151] Referring to Figure 1b, which is a schematic diagram of the structure of another communication device provided in an embodiment of the present application, the structure of the communication device shown in Figure 1b is substantially the same as that of the communication device shown in Figure 1a, except that the PCS of the communication device shown in Figure 1b includes an FEC function.

[0152] For the communication device shown in Figure 1b, the sum of the delays introduced by the FEC function of the transmitter and the FEC function of the receiver is fixed. For example, the PCS of the transmitter will perform FEC encoding, and the encoding process includes adding check bits, which will introduce corresponding delay jitter. In addition, the transmitter will also perform data stream interleaving operations, and data stream interleaving operations will also introduce certain delay jitter. Similarly, the PCS of the receiver will perform FEC decoding, and the decoding process includes deleting check bits, which will introduce corresponding delay jitter. In addition, the transmitter will also perform deinterleaving operations on the data stream, and performing deinterleaving operations on the data stream will also introduce certain delay jitter. For the convenience of description, the delay generated by the implementation of the FEC function at the transmitter is called FEC_TX delay, and the delay generated by the implementation of the FEC function at the receiver is called FEC_RX delay. The FEC_TX delay and FEC_RX delay can be shown in Figure 1c. Figure 1c is a schematic diagram of the delay introduced by an FEC function provided in an embodiment of the present application. The abscissa shown in FIG1c represents the bit stream passing through the PCS module, and the ordinate represents the delay.

[0153] In an example, the FEC function of the PCS may also be referred to as an outer code FEC function, and the FEC codeword obtained by the PCS at the transmitting end performing FEC encoding may be referred to as an FEC outer codeword.

[0154] Furthermore, the current IEEE 802.3dj Task Force (B400G standard) defines support for concatenated coding at the physical layer. Specifically, an inner FEC is inserted between the PMA and PMD for FEC inner coding and decoding. For example, the FEC codeword generated by the inner FEC encoding at the transmitter is referred to as the inner FEC codeword.

[0155] For further understanding, please refer to Figure 1d, which is a schematic diagram of the structure of another communication device provided in an embodiment of the present application. As shown in Figure 1d, the physical layer of the communication device supporting concatenated coding includes: a PCS supporting FEC function, PMA 101, PMA 102, inner code FEC, and PMD. PMA 101 and PMA 102 interact with each other via an attachment unit interface (AUI). Here,

[0156] The PCS and PMA 101 may belong to the first chip, and the PMA 102 , inner code FEC, and PMD may belong to the optical module.

[0157] Because inner code FEC requires inner code-related operations, which also introduce delay jitter, compared to outer code FEC, inner code FEC also includes pad addition and deletion operations.

[0158] In one example, for the transmitting end, the operations performed by the inner code FEC include: encoding, interleaving and padding sequence (pad) addition. For the receiving end, the operations performed by the inner code FEC include: pad deletion, deinterleaving and decoding. In one example, the encoding can be, for example, inserting 8 bits of check bits for every 120 bits of information bits (message bits), and the interleaving can be, for example, 8:1 codeword interleaving. The padding can be, for example, filling 1024 bits of data every 8704 inner code blocks (each inner code block is 128 bits). That is, a pad with a length corresponding to 8 inner code blocks is inserted every 8704 inner code blocks. In addition, after the transmitting end performs the pad addition operation, the obtained data stream can be encoded by four-level pulse amplitude modulation 4 (PAM4), that is, two bits in the data stream can be used as symbols obtained after PAM4 encoding.

[0159] In another example, for the transmitter, the inner code FEC operations include: convolution interleaving, Bose Chaudhuri Hocquenghem (BCH) encoding, and padding. For the receiver, the inner code FEC operations performed by it are the inverse operations of the inner code FEC operations performed by the transmitter, specifically including: pad removal, BCH decoding, and deconvolution interleaving.

[0160] The convolution interleaving operation may, for example, be to send every 40 bits of data to N delay channels (lines) in a polling manner. For example, taking the number of delay channels as 3 as an example, the three delay lines are the 0th delay line, the 1st delay line, and the 2nd delay line. Among them, the 0th delay line will not perform a delay operation on the data, the 1st delay line will delay every 40 bits of data by the time corresponding to 6*40 bits, and the 2nd delay line will delay every 40 bits of data by the time corresponding to 12*40 bits. Deconvolution interleaving is the inverse process of convolution interleaving. During the deconvolution interleaving process, the 2nd delay line will not perform a delay operation on the data, the 1st delay line will delay every 40 bits of data by the time corresponding to 6*40 bits, and the 0th delay line will delay every 40 bits of data by the time corresponding to 12*40 bits.

[0161] BCH encoding, for example, inserts 16 check bits into every 110 bits of information. Correspondingly, BCH decoding removes the 16 check bits from every 126 bits of encoded information, resulting in 110 bits of information.

[0162] Pad addition can be achieved by inserting a 4-bit pilot into every 64 4-bit data blocks. In other words, in this scenario, the pad can be a pilot. Correspondingly, pad deletion involves deleting the 4-bit pilot included in every 65 4-bit data blocks (i.e., deleting one of the data blocks used as a pilot), resulting in 64 4-bit data blocks.

[0163] For the transmitting end, the two sub-functions of adding check bits and interleaving included in the encoding process will introduce delay jitter. Correspondingly, for the receiving end, the two sub-functions of deleting check bits and deinterleaving included in the decoding process will also introduce delay jitter. This causes the FEC_TX delay and FEC_RX delay to introduce delay jitter in the shape of a sawtooth wave. The sawtooth wave period is about 4.5ns (1024 / 113.4375G / 2), and the sawtooth wave amplitude is about 0.28125ns (64 / 113.4375G / 2). For understanding, refer to Figure 1e, which is a schematic diagram of the delay introduced by an inner code FEC function provided in an embodiment of the present application. In an example, one period of the sawtooth wave shown in Figure 1e can include 8 FEC inner code codewords. Among them:

[0164] In the formula 1024 / 113.4375G / 2:

[0165] 1024 corresponds to the number of bits contained in 8 FEC inner code words. One FEC inner code word contains 128 bits.

[0166] 113.4375G corresponds to the baud rate of a single physical channel (lane);

[0167] 2 means that when PAM4 encoding is performed on the data stream, one symbol consists of 2 bits;

[0168] In the formula 64 / 113.4375G / 2:

[0169] 64 means that in 8:1 codeword interleaving, the first bit of the ninth virtual lane is located at the 65th bit in the interleaved data and needs to wait until the first 64 bits are sent before it can be sent;

[0170] 113.4375G corresponds to the baud rate of a single physical channel;

[0171] 2 means that one symbol consists of 2 bits.

[0172] In addition, for the transmitting end, adding this sub-function of pad will introduce delay jitter, and correspondingly, for the receiving end, deleting this sub-function of pad will also introduce delay jitter. This causes the FEC_TX delay and FEC_RX delay to also introduce delay jitter in the shape of a sawtooth wave. The sawtooth wave period mentioned here is about 4910ns (8704*128 / 113.4375G / 2), and the sawtooth wave amplitude is about 4.5ns (1024 / 113.4375G / 2). Compared with the sawtooth wave introduced by the above-mentioned encoding process or decoding process, the sawtooth wave period introduced by adding or deleting pad is larger, which can be simply called a large sawtooth. Correspondingly, the sawtooth wave introduced by the encoding process or decoding process is called a small sawtooth. Please refer to Figure 1f for understanding. Figure 1f is a schematic diagram of the delay introduced by an inner code FEC function provided in an embodiment of the present application. Figure 1f shows the delay introduced by the filling operation of the transmitting end and the delay introduced by the defilling operation of the receiving end. That is to say, in the scenario of cascade coding, there is delay jitter in the aforementioned optical module due to the addition and deletion of check bits, interleaving and deinterleaving, and addition and deletion of pads. Among them, the period of the sawtooth wave shown in Figure 1f is an integer multiple of the period of the sawtooth wave shown in Figure 1e. Therefore, the delay after the delay introduced by the addition and deletion of check bits and interleaving and deinterleaving (as shown in the previous Figure 1e) and the delay caused by the addition and deletion of pads (as shown in the previous Figure 1f) are superimposed can be understood with reference to Figure 1g. Figure 1g is a schematic diagram of the delay introduced by another inner code FEC function provided in an embodiment of the present application.

[0173] In the formula 8704*128 / 113.4375G / 2:

[0174] 8704*128 indicates the number of bits included in the 8704 FEC inner code words;

[0175] 113.4375G corresponds to the baud rate of a single physical channel;

[0176] 2 means that one symbol consists of 2 bits.

[0177] In the formula 1024 / 113.4375G / 2:

[0178] 1024 means that every 8704 inner code blocks are filled with 1024 bits of padding data;

[0179] 113.4375G corresponds to the baud rate of a single physical channel;

[0180] 2 means that one symbol consists of 2 bits.

[0181] Regarding the sawtooth wave shown in Figure 1g, it should be noted that:

[0182] The small sawtooth corresponding to the FEC_TX delay and the small sawtooth corresponding to the FEC_RX delay have the same period. In other words, the peak position of the small sawtooth corresponding to the FEC_TX delay overlaps with the peak position of the small sawtooth corresponding to the FEC_RX delay, and the trough position of the small sawtooth corresponding to the FEC_TX delay overlaps with the trough position of the small sawtooth corresponding to the FEC_RX delay. However, the amount of data (e.g., the number of bits) included in one period of the small sawtooth corresponding to the FEC_TX delay may be the same as or different from the amount of data included in one period of the small sawtooth corresponding to the FEC_RX delay.

[0183] Similarly, the large sawtooth corresponding to the FEC_TX delay and the large sawtooth corresponding to the FEC_RX delay have the same period. In other words, the peak position of the large sawtooth corresponding to the FEC_TX delay overlaps with the peak position of the large sawtooth corresponding to the FEC_RX delay, and the trough position of the large sawtooth corresponding to the FEC_TX delay overlaps with the trough position of the large sawtooth corresponding to the FEC_RX delay. However, the amount of data (e.g., the number of bits) included in one period of the large sawtooth corresponding to the FEC_TX delay may be the same as or different from the amount of data included in one period of the large sawtooth corresponding to the FEC_RX delay.

[0184] In addition, for the sender:

[0185] In one example, a single cycle of a large sawtooth wave can include 8704 data blocks corresponding to FEC inner codewords, with each data block containing 120 information bits. After the transmitter performs FEC inner code encoding, an 8-bit parity check sequence is added to each data block. Therefore, a single cycle can be considered to include 8704 data blocks, with each data block containing 128 bits. Furthermore, after the transmitter performs a padding operation, a pad corresponding to the length of 8 FEC codewords is inserted within a single cycle, meaning that a single cycle can be considered to include 8712 data blocks, with each data block containing 128 bits. In other words, the data contained in a single cycle can be considered to consist of the following three scenarios: 8704 * 120 = 1,044,480 bits; 8704 * 128 = 1,114,112 bits; or 8712 * 128 = 1,115,136 bits.

[0186] In another example, the data included in one cycle may also include: 8712*120=1045440 bits.

[0187] Those skilled in the art will readily understand that the above four lengths can all be considered as periods corresponding to a large sawtooth wave.

[0188] After the sending end performs the pad adding operation on the data stream, the data stream with the added pad can be sent to the receiving end.

[0189] For the receiving end:

[0190] One cycle of the large sawtooth wave can include 8712 data blocks corresponding to FEC inner codewords, each containing 128 bits. The receiving end can perform a pad removal operation on the data blocks corresponding to these 8712 FEC inner codewords, removing the pads inserted by the transmitting end. After the receiving end performs the pad removal operation, one cycle includes 8704 data blocks corresponding to the FEC inner codewords, each containing 128 bits. Furthermore, the receiving end can perform FEC inner code decoding on the data blocks corresponding to these 8704 FEC inner codewords, removing the 8-bit check sequence in each data block. Therefore, after the receiving end performs FEC inner code decoding, one cycle includes 8704 data blocks, each containing 120 bits. Therefore, for the receiving end, the data included in one cycle can be the following three cases: 8712*128=1115136 bits; or 8704*128=1114112 bits; or 8704*120=1044480 bits.

[0191] In another example, the data included in one cycle may also include: 8712*120=1045440 bits.

[0192] Regarding the aforementioned delay jitter introduced by FEC or inner code FEC, the IEEE 802.3cx standard stipulates that the delay reported by the transmitter is equivalent to the maximum delay, and the delay reported by the receiver is equivalent to the minimum delay. For example, in the scenario shown in Figure 1c, the delay reported by the transmitter is X+N, and the delay reported by the receiver is YN.

[0193] However, the IEEE 802.3cx standard does not specify a specific implementation method for the transmitter to report the maximum delay and a specific implementation method for the receiver to report the minimum delay in a scenario where the physical layer supports the concatenated coding function.

[0194] For the inner code FEC function, the factors that introduce delay jitter include the addition and deletion of check bits, interleaving and deinterleaving, and the addition and deletion of pads. For the transmitting end, the delay corresponding to the data at the starting position of a specific data block, and its corresponding FEC_TX delay is equivalent to the maximum delay. Similarly, for the receiving end, the delay corresponding to the data at the starting position of a specific data block, and its corresponding FEC_RX delay is equivalent to the minimum delay. For understanding, please refer to Figure 1h, which is a schematic diagram of the delay introduced by an inner code FEC function provided in an embodiment of the present application. In Figure 1h:

[0195] The data corresponding to the locations circled by hollow circles has a latency equivalent to the maximum latency. This is because the areas circled by hollow circles correspond to the maximum latency introduced by check sequence additions and deletions, interleaving and deinterleaving, and padding sequence additions and deletions. Check sequence additions and deletions here refer to the addition or deletion of check sequences, while padding additions and deletions refer to the addition or deletion of padding sequences.

[0196] The data corresponding to the locations circled by solid circles have a delay equivalent to the minimum delay. The areas circled by hollow circles correspond to the minimum delay introduced by parity sequence additions and deletions, interleaving and deinterleaving, and the minimum delay introduced by padding sequence additions and deletions.

[0197] The data at the position circled by the hollow circle is the data at the starting position of the specific data block. Correspondingly, the data at the position circled by the solid circle is also the data at the starting position of the specific data block.

[0198] As mentioned above, the period of the large sawtooth is an integer multiple of the period of the small sawtooth. Therefore, the period of the hollow circle shown in FIG1h corresponds to the period of the large sawtooth.

[0199] As described above for FIG1g, in the scenario shown in FIG1h:

[0200] In one example, one period of the hollow circle includes 8704 data blocks, and one data block includes 120 bits. In another example, one period of the hollow circle includes 8704 data blocks, and one data block includes 128 bits. In another example, one period of the hollow circle includes 8712 data blocks, and one data block includes 128 bits.

[0201] In one example, one period of the solid circle includes 8712 data blocks, and one data block includes 128 bits. In another example, one period of the solid circle includes 8704 data blocks, and one data block includes 128 bits. In another example, one period of the solid circle includes 8704 data blocks, and one data block includes 120 bits.

[0202] The data blocks can be numbered sequentially, and if there are m data blocks between two adjacent circles, the difference between the data block numbers corresponding to the two adjacent circles can be m. In this case, the period of the positions corresponding to the aforementioned circles is also m. For example, if there are 8712 data blocks between the data blocks corresponding to two hollow circles, the difference between the data block numbers corresponding to the two hollow circles can be 8712. Accordingly, the period of the positions marked by the hollow circles is 8712.

[0203] In addition, the existing IEEE 802.3cx Section 90 requires that when the physical layer of a communication device reports delay, each layer thereof reports the maximum delay and minimum delay respectively. Specifically, IEEE 802.3cx Section 90 defines registers for each layer to report the maximum delay and minimum delay. For example, IEEE 802.3cx Section 90 defines the PMA / PMD TX maximum delay register, the PMA / PMD TX minimum delay register, the PMA / PMD RX maximum delay register, and the PMA / PMD RX minimum delay register, where:

[0204] The TX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device acts as a transmitter;

[0205] The TX minimum delay register of PMA / PMD is used to report the minimum delay of PMA / PMD when the communication device is used as a transmitter;

[0206] The RX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device acts as a receiving end;

[0207] The RX minimum delay register of the PMA / PMD is used to report the minimum delay of the PMA / PMD when the communication device acts as a receiving end.

[0208] In view of this, an embodiment of the present application provides a delay reporting method, which can accurately report the delay in a scenario where the physical layer supports the cascade coding function, while complying with the IEEE 802.3cx standard that "for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay."

[0209] Next, the delay reporting method provided in the embodiment of the present application is introduced with reference to the accompanying drawings.

[0210] Before introducing the latency reporting method provided in the embodiments of the present application, it is necessary to explain that:

[0211] For a communication device, it may include a physical layer module, which is used to implement the functions implemented by the aforementioned physical layer. For the physical layer, it may include multiple sub-modules, each of which is used to implement a specific physical layer function. For example, the physical layer module includes a PCS sub-module, a PMA sub-module, and a PMD sub-module. The PCS sub-module is used to implement the functions implemented by the aforementioned PCS, the PMA sub-module is used to implement the functions implemented by the aforementioned PMA, and the PMD sub-module is used to implement the functions implemented by the aforementioned PMD.

[0212] In addition, the communication device may further include an optical module, which may also include corresponding submodules for implementing corresponding functions. For example, for a communication device having the structure shown in FIG1d , the optical module may include a PMA submodule, an inner code FEC module, and a PMD submodule.

[0213] Furthermore, time synchronization is only one application scenario provided by the embodiments of this application. The solutions of the embodiments of this application can also be applied to other scenarios. For example, in a flow detection scenario, a communication device can also use the solutions of the embodiments of this application to determine the sending timestamp or receiving timestamp of a message. The application scenarios of the embodiments of this application are not listed here one by one.

[0214] See Figure 2, which is a flowchart of a delay reporting method provided in an embodiment of the present application.

[0215] The delay reporting method shown in Figure 2 can be applied to the first module, which can be a module in a communication device. The communication device mentioned here can be a communication device as a transmitting end or a communication device as a receiving end, and the embodiment of the present application does not make specific limitations. The structure of the first module can be shown in Figure 3, which is a structural schematic diagram of a first module provided in an embodiment of the present application. As shown in Figure 3, the first module includes a bit stream processing module, a delay determination module and a delay reporting module. The bit stream processing module may include an FEC module and other modules that interact with the FEC module. The delay determination module is used to determine the delay, and the delay reporting module is used to report the determined delay to the second module.

[0216] In one example, the first module may be a PHY module or an optical module. As a specific example, the structure of the communication device including the first module is as shown in Figure 1d. In this case, the FEC module shown in Figure 3 may be a module that implements the inner code FEC function. The module that implements the inner code FEC function may also be referred to as an "inner code FEC module."

[0217] The PHY module mentioned in the embodiments of the present application may be, for example, a PHY chip for implementing PHY functions.

[0218] The method shown in FIG. 2 may include the following steps S101 - S102 .

[0219] S101: Determine target delays corresponding to data at multiple specific locations in a data stream, where the multiple specific locations are spaced at fixed lengths, and periods of the multiple specific locations correspond to periods of inserting padding sequences into the data stream.

[0220] In the embodiment of the present application, the data stream is a bit stream sent from a transmitting end to a receiving end.

[0221] In an embodiment of the present application, the first module may report the target latency to the second module. In one example, the second module may be a MAC layer module of the communication device. In this way, the MAC layer module may compensate its own recorded timestamps based on the target latency, thereby making the compensated timestamps more accurate.

[0222] In an embodiment of the present application, if the first module is a module corresponding to the transmitting end, such as the module corresponding to the inner code FEC shown in Figure 1d, or the optical module including PMA102, inner code FEC and PMD shown in Figure 1d, then the first module can perform FEC inner code encoding and pad addition operations on the data entering the first module. Accordingly, in one example, the data stream mentioned here can be the data stream after the FEC inner code encoding and pad addition operations are performed. If the first module is a module corresponding to the receiving end, then in one example, the data stream can be the data stream sent by the transmitting end to the first module. In other words, the data stream is the data stream entering the first module, and the data stream has been subjected to FEC inner code encoding and pad addition operations at the transmitting end.

[0223] In another example, considering that after the transmitting end sends the data stream to the receiving end, the receiving end may perform FEC inner code decoding on the data stream, the data stream may also be the data stream obtained after the receiving end performs FEC inner code decoding on the received data stream. In other words, if the first module is the module corresponding to the receiving end, in another example, the data stream may be the data stream obtained after FEC inner code decoding.

[0224] The first module is a module corresponding to the transmitting end, which can be understood as the first module being a module in the communication device serving as the transmitting end; the first module is a module corresponding to the receiving end, which can be understood as the first module being a module in the communication device serving as the receiving end. The first module is a module corresponding to the receiving end, which can also be understood as the first module corresponding to the receiving end; the first module is a module corresponding to the transmitting end, which can also be understood as the first module corresponding to the transmitting end.

[0225] In an embodiment of the present application, the target delay is the delay of the data at the aforementioned multiple specific locations passing through the first module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific locations passing through the inner code FEC layer in the first module. In the case where the first module is an optical module, the target delay is the delay of the data at the aforementioned multiple specific locations passing through the optical module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific locations passing through the inner code FEC layer in the optical module. The inner code FEC layer is a layer for implementing the inner code FEC function. In the scenario where the first module is a PHY module, the target delay is the delay of the data at the aforementioned multiple specific locations passing through the inner code FEC layer in the PHY module.

[0226] In a specific example, the optical module may include an inner code FEC module corresponding to the inner code FEC layer. Therefore, in one example, the target delay may be the delay of data at the aforementioned multiple specific locations passing through the inner code FEC module in the optical module. The inner code FEC module is used to implement the inner code FEC function. In a specific example, the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module. The inner code FEC encoding module is used to implement the FEC inner code encoding function, and the inner code FEC decoding module is used to implement the FEC inner code decoding function. As an example, when the communication device acts as a transmitter, the inner code FEC module includes an inner code FEC encoding module. As another example, when the communication device acts as a receiver, the inner code FEC module includes an inner code FEC decoding module. As another example, considering that a communication device can act as both a transmitter and a receiver, the inner code FEC module may include an inner code FEC encoding module and an inner code FEC decoding module.

[0227] In an embodiment of the present application, if the first module corresponds to the transmitting end, the target delay corresponding to the data at the multiple specific positions is equivalent to the maximum delay. If the first module corresponds to the receiving end, the target delay corresponding to the data at the multiple specific positions is equivalent to the minimum delay. As can be seen from the previous description of Figure 1h, the multiple specific positions can be the positions circled in Figure 1h, that is, the starting positions of specific data blocks. With reference to Figure 1h, it can be understood that for the transmitting end, the multiple specific positions can be the positions circled by the hollow circles in Figure 1h. For the receiving end, the multiple specific positions can be the positions circled by the solid circles in Figure 1h. The multiple specific positions are spaced at fixed lengths. In addition, the period of the multiple specific positions corresponds to the period of inserting the padding sequence in the data stream.

[0228] As previously described with respect to FIG. 1h , the period of the multiple specific positions can be 8712 data blocks or 8704 data blocks, where 8712 is the period corresponding to the insertion of the padding sequence into the data stream, and 8704 is the period corresponding to the insertion of the padding sequence into the data stream. Of course, the period of the multiple specific positions can also be an integer multiple of 8712 data blocks or an integer multiple of 8704 data blocks. For example, if the period of the specific positions is K times 8712 data blocks or 8704 data blocks, then the larger the value of K, the fewer specific positions need to be used for delay statistics, and accordingly, the fewer computing resources consumed for calculating the target delay.

[0229] In one example, a data block may include 128 bits or 120 bits. For example, if the data block is a data block that has been FEC inner-coded, the data block includes 128 bits. If the data block has not been FEC inner-coded, or if the data block has been FEC inner-coded, the data block includes 120 bits. If a data block includes 128 bits, the data block may also be referred to as an FEC inner-code codeword.

[0230] As can be seen from the above description of FIG. 1h , the periods of the multiple specific positions may include the following situations:

[0231] 8704*120=1044480 bits; or, 8712*120=1045440 bits; or, 8704*128=1114112 bits; or, 8712*128=1115136 bits.

[0232] Therefore, in one example, the period of the multiple specific positions may be an integer multiple of 1044480 bits, an integer multiple of 1114112 bits, or an integer multiple of 1115136 bits.

[0233] In the scenario where convolution interleaving, BCH encoding, and pad insertion are performed at the transmitting end, a data block may include 4 bits, and the period of the multiple specific positions may be 65 data blocks or 64 data blocks, where 65 is the period corresponding to after the padding sequence is inserted into the data stream, and 64 is the period corresponding to before the padding sequence is inserted into the data stream.

[0234] In the embodiment of the present application, the specific position may be the starting position of a data block. The starting position of a data block may be the first byte, the first bit, or the first symbol of the data block. In the scenario where the data block comprises 128 bits, the specific data block mentioned here may be a specific FEC codeword, for example, an FEC inner codeword.

[0235] For example, in the embodiment of the present application, the specific position may be the starting position of the next data block after the padding sequence is inserted into the data stream, that is, the starting position of the first data block in the payload.

[0236] In one example, the data stream may include multiple target data, each target data may include N data blocks. Accordingly, the aforementioned specific position may be the starting position of the N data blocks. In other words, the data stream may include multiple data blocks, and the multiple data blocks may be divided into multiple groups, with N data blocks as a group, and each group corresponds to one target data. In a scenario where a data block includes 128 bits, the target data may include N FEC inner codewords.

[0237] In an embodiment of the present application, in addition to inserting a padding sequence into the data stream, the transmitting end may also insert a check sequence. Specifically, when performing FEC inner coding on the data stream, the transmitting end may insert an 8-bit check sequence for every 120 bits of data. In an embodiment of the present application, the period at which the transmitting end inserts the padding sequence into the data stream is an integer multiple of the period at which the check sequence is inserted into the data stream. For example, this can be understood in conjunction with Figure 1h. In Figure 1h, the period of the small sawtooth wave corresponds to the period at which the check sequence is inserted into the data stream, and the period of the large sawtooth wave corresponds to the period at which the padding sequence is inserted into the data stream. The period of the large sawtooth wave is an integer multiple of the period of the small sawtooth wave. In one example, the period of the large sawtooth wave may be 8704 times the period of the small sawtooth wave. Because the period of inserting the padding sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream, the peak position of the large sawtooth wave overlaps with the peak position of the small sawtooth wave, and the trough position of the large sawtooth wave overlaps with the trough position of the small sawtooth wave. Therefore, the period of the aforementioned specific position can be determined based on the period of inserting the padding sequence into the data stream to determine the target delay.

[0238] In an example, among the data at the aforementioned multiple specific locations, the data at each specific location may correspond to a first time delay. Therefore, the data at the aforementioned multiple specific locations may correspond to multiple first time delays.

[0239] In the embodiment of the present application, the multiple first time delays may be the same, or may not be completely the same, or may be completely different, and the embodiment of the present application does not make any specific limitation.

[0240] As previously mentioned, the existing IEEE 802.3cx Section 90 defines corresponding maximum and minimum delay registers for each physical layer. Therefore, to maintain compatibility with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays, the maximum and / or minimum values ​​among the multiple first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the multiple first delays.

[0241] As described above, the multiple first time delays may be the same, or may be skewed or completely different. When the multiple first time delays are the same, the maximum value and the minimum value are the same. When the multiple first time delays are skewed or completely different, the maximum value is smaller than the minimum value.

[0242] In one example, when S101 is specifically implemented, the first module can measure the first delay corresponding to the data at each specific location in the data at the multiple specific locations to obtain multiple first delays.

[0243] If the first module corresponds to the transmitting end, then for the data stream entering the first module, 8704 data blocks (each data block includes 120 bits) can be taken as a group, and the first delay of the data at the starting position of each group of data blocks in the first module can be measured to obtain multiple first delays.

[0244] If the first module corresponds to the receiving end, then for the data stream entering the first module, 8712 data blocks (each data block includes 128 bits) can be taken as a group, and the first delay of the data at the starting position of each group of data blocks in the first module can be measured to obtain multiple first delays.

[0245] The embodiment of the present application does not specifically limit the specific implementation method of determining the first delay.

[0246] In one example, the first module can record the delay for data at a specific position in the target data, thereby determining the first delay. In another example, the first module can determine the delay for data at multiple positions in the target data to pass through the first module, thereby obtaining multiple delays corresponding to each target data. The multiple positions mentioned here may include the specific position, for example, the multiple positions may be various positions in the target data. Accordingly, for any target data, the first delay can be determined from the multiple delays corresponding to the target data. That is: from the multiple delays, the delay corresponding to the specific position is extracted to obtain the first delay. For example: for the target data, the first module can determine the delay for each bit of data in the target data to pass through the first module, and extract the delay for the data at the starting position in the target data to pass through the first module, thereby obtaining the first delay.

[0247] The embodiment of the present application does not specifically limit the method for determining the time delay of data at any position in the target data passing through the first module. Two possible implementation methods are introduced below.

[0248] In one implementation, the first module can record the first moment when it receives the data of the location, and record the second moment when it sends the data of the location, and subtract the difference between the second moment and the first moment to determine it as the delay of the data of the location passing through the first module.

[0249] In another example, after receiving the data at the location, the first module can cache the data at the location. Accordingly, the first module can send the cached data in order based on the data already cached in the cache. Therefore, the position of the data at the location in the cache can represent the length of time the data at the location needs to wait in the cache, and the length of the wait can represent the delay of the data at the location passing through the first module. Therefore, the first module can determine the delay of the data at the location passing through the first module based on the position of the data at the location in the cache.

[0250] S102: Report target delays corresponding to data at multiple specific locations in the data stream.

[0251] The first module can use a corresponding register to report the target latency to the second module. In a scenario where the target latency includes the aforementioned maximum and / or minimum values, in one example, the first module can use a corresponding register to report the maximum and / or minimum values ​​to the second module. The following describes several specific implementations of how the first module uses the corresponding register to report the maximum and / or minimum values ​​to the second module.

[0252] In one example, if the first module corresponds to a transmitting end, then:

[0253] As a specific example, a new register can be defined to report the maximum value and / or minimum value to the second module. For example, a TX maximum delay register and / or a TX minimum delay register for the inner code FEC can be defined, with the TX maximum delay register being used to report the maximum value, and the TX minimum delay register being used to report the minimum value. In other words, the first module can use the TX maximum delay register for the inner code FEC to report the maximum value to the second module, and / or use the TX minimum delay register for the inner code FEC to report the minimum value to the second module.

[0254] As another specific example, the first module can use the TX maximum latency register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the TX minimum latency register of the PMA / PMD to report the minimum value to the second module. In this way, the target latency can be reported by reusing existing registers.

[0255] In one example, if the first module corresponds to a receiving end, then:

[0256] As another specific example, a new register can be defined to report the maximum value and / or minimum value to the second module. For example, a RX maximum delay register and / or RX minimum delay register for the inner code FEC can be defined, with the RX maximum delay register used to report the maximum value, and the RX minimum delay register used to report the minimum value. In other words, the first module can use the RX maximum delay register for the inner code FEC to report the maximum value to the second module, and / or use the RX minimum delay register for the inner code FEC to report the minimum value to the second module.

[0257] As another specific example, the first module may use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module may use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0258] From the above description, it can be seen that by using the solution of the embodiment of the present application, the first module can follow the principle that "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay" and accurately report the delay to the second module.

[0259] The above describes the delay reporting method provided in the embodiment of the present application. Next, the solution provided in the embodiment of the present application will be introduced in combination with specific scenarios.

[0260] Example 1: Specific implementation of the delay reporting method shown in FIG2 .

[0261] In this scenario, the structure of the communication device may adopt the structure shown in FIG. 1 d , and the first module may be an optical module of the communication device, which includes a PMA 102 , an inner code FEC, and a PMD.

[0262] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0263] S1: Record the delay of the starting position of the i-th data block in the data stream it sends through the optical module to obtain DelayTX(1, i), where:

[0264] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0265] The value of i can be 8704, 8704*2, 8704*3, ... 8704*k.

[0266] S2: Determine the maximum value DelayTX_max of DelayTX(1, i) and the minimum value DelayTX_min of DelayTX(1, i).

[0267] S3: Report DelayTX_max and DelayTX_min to the MAC layer module.

[0268] In an example, DelayTX_max can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0269] In yet another example, DelayTX_max may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and DelayTX_min may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0270] For a communication device serving as a receiving end, its optical module can perform the following operations:

[0271] S1': records the time delay of the starting position of the j-th FEC inner code block in the received data stream passing through the optical module to obtain DelayRX(1, j).

[0272] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0273] The value of j can be 8712, 8712*2, 8712*3, ... 8712*k.

[0274] S2 ′: Determine the maximum value DelayRX_max of DelayRX(1, j) and the minimum value DelayRX_min of DelayRX(1, j).

[0275] S3': Report DelayRX_max and DelayRX_min to the MAC layer module.

[0276] In an example, DelayRX_max may be reported to the MAC layer module via the RX maximum delay register of the inner code FEC, and DelayRX_min may be reported to the MAC layer module via the RX minimum delay register of the inner code FEC.

[0277] In yet another example, DelayRX_max may be reported to the MAC layer module via the RX maximum delay register of the PMA / PMD, and DelayRX_min may be reported to the MAC layer module via the RX minimum delay register of the PMA / PMD.

[0278] The inventors of the present application also discovered that if the submodules included in the first module include a submodule capable of introducing delay jitter, then if the first module can report delay information to the second module based on the delay jitter value, then the first module can also accurately report delay information to the second module while complying with the IEEE 802.3cx standard that "for the transmitting end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay."

[0279] In view of this, the embodiment of the present application further provides another delay reporting method in parallel with the delay reporting method shown in Figure 2. Next, the delay reporting method is introduced in conjunction with Figure 4. Figure 4 is a flow chart of another delay reporting method provided by the embodiment of the present application.

[0280] The method shown in FIG4 can be applied to the first module. Regarding the first module, please refer to the above description of the first module, and no repetitive description will be given here.

[0281] The method shown in FIG4 may include the following S201 - S202 .

[0282] S201: Obtain a delay jitter value of target data passing through a first submodule in a first module, wherein the first submodule includes a submodule having a delay jitter with a fixed value, and the target data is data sent by the first module, or the target data is data received by the first module, wherein the delay jitter value is the preset fixed value.

[0283] Regarding the target data, the description of the target data in the method shown in FIG2 may be referred to above, and will not be repeated here.

[0284] In this embodiment of the present application, the first submodule has a fixed value of delay jitter. As previously described regarding the inner code FEC function, the implementation of the inner code FEC function, including the addition or deletion of check sequences, data interleaving or deinterleaving, and the addition or deletion of padding sequences, all result in delay jitter. For the transmitter, the delay jitter introduced by adding check sequences, data interleaving, and adding padding sequences is the aforementioned fixed value. For the receiver, the delay jitter introduced by deleting check sequences, data deinterleaving, and deleting padding sequences is also the aforementioned fixed value.

[0285] Therefore, in one example, the first submodule may include: a submodule for detecting delay jitter caused by adding or deleting a check sequence, a submodule for detecting delay jitter caused by adding or deleting a padding sequence, and a submodule for detecting delay jitter caused by interleaving or deinterleaving a data stream. Alternatively, the first submodule may further include a cyclic shift submodule.

[0286] As a specific example, for the transmitting end, the first submodule may include: a submodule for delay jitter caused by adding a check sequence, a submodule for delay jitter caused by adding a padding sequence, and a submodule for delay jitter caused by interleaving of data streams. Correspondingly, for the receiving end, the first submodule may include: a submodule for delay jitter caused by deleting a check sequence, a submodule for delay jitter caused by deleting a padding sequence, and a submodule for delay jitter caused by deinterleaving of data streams.

[0287] In one example, the submodule described above, which experiences delay jitter due to the addition of a check sequence, may be a submodule within the inner code FEC module that performs FEC inner code encoding; the submodule described above, which experiences delay jitter due to the addition of a padding sequence, may be a submodule within the inner code FEC module that performs padding sequence addition; and the submodule described above, which experiences delay jitter due to data stream interleaving, may be a submodule within the inner code FEC module that performs data stream interleaving. In other words, the first submodule may include: a submodule within the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition.

[0288] In another example, the aforementioned submodule that experiences delay jitter due to check sequence deletion may be a submodule within the inner code FEC module that performs FEC inner code decoding; the aforementioned submodule that experiences delay jitter due to padding sequence deletion may be a submodule within the inner code FEC module that performs padding sequence deletion; and the aforementioned submodule that experiences delay jitter due to data stream deinterleaving may be a submodule within the inner code FEC module that performs data stream deinterleaving. In other words, the first submodule may include: a submodule within the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence deletion.

[0289] In another example, the aforementioned first submodule may be a cyclic shift submodule. The cyclic shift submodule is configured to perform a cyclic shift operation. As an example, the transmitting end may further perform a cyclic shift operation before performing encoding processing (e.g., inner code FEC processing). Accordingly, the receiving end may further perform a cyclic shift operation after performing decoding processing. As another example, the transmitting end may further perform a cyclic shift operation after performing BCH encoding and before performing pilot insertion. Accordingly, the receiving end may further perform a cyclic shift operation after performing pilot deletion and before performing BCH decoding.

[0290] In one example, if the shift direction corresponding to the cyclic shift operation performed by the receiving end is the same as the shift direction corresponding to the cyclic shift operation performed by the transmitting end, the first submodule may include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the delay jitter value introduced by the cyclic shift submodule may be 4.5 nanoseconds.

[0291] In an embodiment of the present application, the delay jitter value may be a preset fixed value. For example, when the first module is an optical module, the delay jitter value may include the sum of a first jitter value and a second jitter value, and the first jitter value may be the delay jitter value introduced by adding or deleting the check sequence, and interleaving or deinterleaving the data stream. The second jitter value may be the delay jitter value introduced by adding or deleting the pad. The fixed value may be, for example, a value between 4.6ns and 4.8ns. As a specific example, according to the above description of Figures 1e, 1f, and 1g, the delay jitter value introduced by adding or deleting the check sequence, and interleaving or deinterleaving the data stream is 0.28125ns, and the delay jitter value introduced by adding or deleting the pad is 4.5ns. Therefore, the delay jitter value may be 4.78125ns. When the first submodule further includes a cyclic shift submodule, the delay jitter value can be calculated by adding the delay jitter of 4.5 ns introduced by the cyclic shift submodule to the sum of the first jitter value and the second jitter value. In other words, the delay jitter value can be between (4.5 ns + 4.6 ns = 9.1 ns) and (4.5 ns + 4.8 ns = 9.3 ns).

[0292] In some examples, the delay jitter value may also be referred to as a delay variation value.

[0293] S202: Report delay information to the second module according to the delay jitter value.

[0294] After determining the delay jitter value, delay information may be reported to the second module according to the delay jitter value.

[0295] Regarding the second module, the description of the second module in the above embodiments can be referred to and will not be repeated here.

[0296] In an example, the first module may report the delay jitter value to the second module.

[0297] In another example, the first module may further determine a first delay for the target data to pass through a second submodule within the first module. In an embodiment of the present application, the second submodule may be a submodule that introduces little delay jitter. The submodule that introduces little delay jitter mentioned herein may also be understood as a submodule that introduces less delay jitter. In a specific example, the second submodule may be a submodule within the first module other than the first submodule.

[0298] In one example, if the first module corresponds to the transmitting end, the second submodule may be, for example, a submodule in the inner code FEC module that performs operations such as convolution interleaving, distribution, and modulation coding. The modulation coding mentioned here may be, for example, PAM4 encoding. If the first module corresponds to the receiving end, the second submodule may be, for example, a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations. The modulation coding mentioned here may be, for example, PAM4 decoding. In embodiments of the present application, determining the first delay may be implemented in a variety of ways. Two possible implementations are described below.

[0299] In an example, the first module may obtain a preset first delay, where the first delay may be a value determined by the first module during a design phase, and the value of the first delay is related to the performance of the first module.

[0300] In another example, the first module can calculate the first delay of the target data passing through the second submodule. In a specific implementation, calculating the first delay of the target data passing through the second submodule can be performed by calculating the delay of at least one bit of the target data passing through the second submodule, thereby obtaining the first delay. For example, the target data can be sampled and the delay of the sampled data passing through the second submodule can be calculated. In another example, the first delay can be calculated by calculating the delay of each bit of the target data passing through the second submodule.

[0301] For any bit of data, the delay of passing through the second sub-module can be the difference between the time when the second sub-module sends the data and the time when the second sub-module receives the data, or it can be determined based on the position of the data in the cache. The embodiments of the present application do not make specific limitations.

[0302] In a scenario where the first module determines the first delay, S202 may, during specific implementation, report delay information to the second module based on the delay jitter value and the first delay.

[0303] As a specific example, the first module may determine the aforementioned delay jitter value and the first delay as the delay information, and report the determined delay information to the second module.

[0304] As another specific example, the first module may determine a target delay according to the delay jitter value and the first delay, and report the target delay as the aforementioned delay information to the second module.

[0305] The embodiment of the present application does not specifically limit the method for determining the target delay based on the delay jitter value and the first delay. The first module can calculate the delay jitter value and the first delay to obtain the target delay.

[0306] In one example, in order to make the data reported by the first module satisfy "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay", the first communication device determines the specific implementation method of determining the target delay based on the delay jitter value and the first delay, which may be related to the role of the first communication device.

[0307] In a specific example, if the first module corresponds to a communication device serving as a transmitter, the first communication device may determine the target delay as the sum of the delay jitter value and the first delay. If the first communication device corresponds to a communication device serving as a receiver, the first communication device may determine the target delay as the difference obtained by subtracting the delay jitter value from the first delay.

[0308] In one example, the first delay may include one delay.

[0309] In another example, considering that existing IEEE 802.3cx Section 90 defines corresponding maximum and minimum delay registers for each physical layer, to be compatible with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays, the first delay may include two delays: the maximum delay for target data to pass through the second submodule, and the minimum delay for the target data to pass through the second submodule. In one example, the maximum delay and the minimum delay are the same. In another example, the maximum delay is greater than the minimum delay.

[0310] As mentioned above, the first delay may include a maximum delay and a minimum delay. In this case, the target delay determined based on the delay jitter value and the first delay may include a maximum target delay and a minimum target delay.

[0311] The maximum target delay can be determined based on the maximum delay and the delay jitter value. Specifically, if the first module corresponds to a communication device as a transmitting end, the first communication device can determine the sum of the delay jitter value and the maximum delay as the maximum target delay, and determine the sum of the delay jitter value and the minimum delay as the minimum target delay. If the first communication device corresponds to a communication device as a receiving end, the first communication device can determine the difference obtained by subtracting the delay jitter value from the maximum delay as the maximum target delay, and determine the difference obtained by subtracting the delay jitter value from the minimum delay as the minimum target delay.

[0312] Next, a method in which the first module reports the maximum target delay and the minimum target delay to the second module is introduced.

[0313] In one example, if the first module corresponds to a transmitting end, then:

[0314] As another specific example, new registers can be defined to report the maximum target delay and minimum target delay to the second module. For example, a TX maximum delay register and a TX minimum delay register for inner code FEC can be defined, with the TX maximum delay register used to report the maximum target delay, and the TX minimum delay register used to report the minimum target delay. In other words, the first module can use the TX maximum delay register for inner code FEC to report the maximum target delay to the second module, and / or use the TX minimum delay register for inner code FEC to report the minimum target delay to the second module.

[0315] As another specific example, the first module may use the TX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module may use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0316] In one example, if the first module corresponds to a receiving end, then:

[0317] As another specific example, new registers can be defined to report the maximum target delay and minimum target delay to the second module. For example, an RX maximum delay register and an RX minimum delay register for inner code FEC can be defined. The RX maximum delay register is used to report the maximum target delay, and the RX minimum delay register is used to report the minimum target delay. In other words, the first module can use the RX maximum delay register for inner code FEC to report the maximum target delay to the second module, and / or use the RX minimum delay register for inner code FEC to report the minimum target delay to the second module.

[0318] As another specific example, the first module may use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module may use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0319] In one example, the first module further includes a third submodule, and the first module can further determine a second delay of the target data passing through the third submodule in the first module. The third submodule mentioned herein can be a submodule in the first module that is different from the first and second submodules. For example, the third submodule can include a PMA submodule and a PMD submodule.

[0320] The implementation principle of the first module determining the second delay of the target data passing through the third sub-module is the same as the implementation principle of the first module determining the first delay of the target data passing through the second sub-module. Therefore, for the specific implementation of "the first module determining the second delay of the target data passing through the third sub-module", please refer to the description of the first module determining the first delay in the previous text, and will not be repeated here.

[0321] In a scenario where the first module determines the second delay, S202 may, during specific implementation, report delay information to the second module based on the delay jitter value and the second delay.

[0322] As a specific example, the first module may determine the aforementioned delay jitter value and the second delay as the delay information, and report the determined delay information to the second module.

[0323] As another specific example, the first module may calculate the delay jitter value and the second delay, and report the calculation result as the delay information to the second module. In a specific example, if the first module corresponds to a communication device acting as a transmitter, the first communication device may determine the sum of the delay jitter value and the second delay as the delay information. If the first communication device corresponds to a communication device acting as a receiver, the first communication device may determine the difference between the second delay and the delay jitter value as the delay information.

[0324] In this scenario, the first communication device can use the relevant registers of the PMA / PMD to report the delay information to the second module. As an example, the second delay can also include a maximum delay and a minimum delay. Accordingly, the delay information can include a maximum delay value obtained based on the delay jitter value and the maximum delay of the second delay, and a minimum delay value obtained based on the delay jitter value and the minimum delay of the second delay. Furthermore, the first communication device can use the relevant registers of the PMA / PMD to report the maximum delay value and the minimum delay value to the second module.

[0325] Specifically, if the first module corresponds to the transmitting end, that is, the target data is data sent by the first module, then the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with an inner code FEC function (such as an optical module), the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0326] If the first module corresponds to the receiving end, that is, the target data is data received by the first module, then the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with an inner code FEC function (such as an optical module), the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0327] The above describes the delay reporting method provided in the embodiment of the present application. Next, the solution provided in the embodiment of the present application will be introduced in combination with specific scenarios.

[0328] Example 2: Specific implementation of the delay reporting method shown in FIG4 .

[0329] In this scenario, the first module may be an optical module of a communication device, where the optical module includes the PMA 102 , an inner code FEC, and a PMD.

[0330] In this case, the operations performed by the inner code FEC may be as shown in FIG5 , which is a schematic diagram of an inner code FEC processing process provided by an embodiment of the present application. As shown in FIG5 :

[0331] At the transmitter, inner code FEC can perform the following operations: convolutional interleaving, distribution, inner code FEC processing, interleaving, padding, and other processing. The other processing mentioned here may include, for example, PAM4 encoding. Inner code FEC processing may, for example, perform a parity check sequence addition operation. The submodule that performs parity check sequence addition, interleaving, and padding is the first submodule, while the submodule that performs convolutional interleaving, distribution, and other processing is the second submodule.

[0332] At the receiving end, the inner code FEC performs the inverse of the operations performed by the transmitting end. For example, the receiving end's inner code FEC can perform the following operations: other processing (such as PAM4 decoding), pad removal, deinterleaving, inner code FEC processing, multiplexing, and inverse convolutional deinterleaving. Inner code FEC processing can, for example, perform parity check sequence removal. The submodule that performs parity check sequence removal, deinterleaving, and pad removal is the first submodule, and the submodule that performs inverse convolutional deinterleaving, combining, and other processing is the second submodule.

[0333] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0334] S4: Obtain the delay jitter value of 4.78125.

[0335] S5: Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax1 and a minimum delay Xmin1.

[0336] S6: Report the maximum target delay Xmax1+4.78125 and the minimum target delay Xmin1+4.78125 to the MAC layer module.

[0337] In one example, Xmax1+4.78125 may be reported to the MAC layer module via the TX maximum delay register of the inner code FEC, and Xmin1+4.78125 may be reported to the MAC layer module via the TX minimum delay register of the inner code FEC.

[0338] In yet another example, Xmax1+4.78125 may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and Xmin1+4.78125 may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0339] For a communication device serving as a receiving end, its optical module can perform the following operations:

[0340] S4': Obtain the delay jitter value of 4.78125.

[0341] S5': Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax2 and a minimum delay Xmin2.

[0342] S6′: Report the maximum target delay Xmax2-4.78125 and the minimum target delay Xmin2-4.78125 to the MAC layer module.

[0343] In one example, Xmax2-4.78125 can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and Xmin2-4.78125 can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0344] In yet another example, Xmax2-4.78125 may be reported to the MAC layer module via the RX maximum delay register of the PMA / PMD, and Xmin2-4.78125 may be reported to the MAC layer module via the RX minimum delay register of the PMA / PMD.

[0345] It should be noted that Figure 5 is only used to facilitate understanding of the inner code FEC processing process shown in this solution. In addition to the content shown in Figure 5, the inner code FEC processing process may also include other content. For example, the transmitter may perform a cyclic shift operation after performing the distribution operation and before performing the inner code FEC processing. Correspondingly, the receiver may also perform a cyclic shift operation after performing the inner code FEC processing and before performing the multiplexing operation. In this case:

[0346] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0347] S7: Obtain the delay jitter value: 4.78125+4.5=9.28125.

[0348] S8: Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax3 and a minimum delay Xmin3.

[0349] S9: Report the maximum target delay Xmax3+9.28125 and the minimum target delay Xmin3+9.28125 to the MAC layer module.

[0350] In one example, Xmax3+9.28125 may be reported to the MAC layer module via the TX maximum delay register of the inner code FEC, and Xmin3+9.28125 may be reported to the MAC layer module via the TX minimum delay register of the inner code FEC.

[0351] In yet another example, Xmin3+9.28125 may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and Xmin3+9.28125 may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0352] For a communication device serving as a receiving end, its optical module can perform the following operations:

[0353] S7': Obtain the delay jitter value of 9.28125.

[0354] S8': Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax4 and a minimum delay Xmin4.

[0355] S9': Report the maximum target delay Xmax4-9.28125 and the minimum target delay Xmin4-9.28125 to the MAC layer module.

[0356] In one example, Xmax4-9.28125 can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and Xmin4-9.28125 can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0357] In yet another example, Xmin4-9.28125 may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and Xmin4-9.28125 may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0358] Based on the delay reporting method provided in the above embodiment, the embodiment of the present application also provides a corresponding device, which is described below with reference to the accompanying drawings.

[0359] See Figure 6, which is a schematic diagram of the structure of a delay reporting device provided in an embodiment of the present application. The delay reporting device shown in Figure 6 can be used to execute the delay reporting method shown in Figure 2 provided in the above method embodiment.

[0360] As shown in FIG6 , the delay reporting apparatus 600 includes a sending unit 601 .

[0361] The sending unit 601 is used to report the target delay corresponding to data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream.

[0362] In one possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

[0363] In a possible implementation, the data block includes 128 bits, 120 bits, or 4 bits.

[0364] In a possible implementation, the period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

[0365] In a possible implementation, the specific position is a starting position of an FEC codeword, and the starting position is the first bit, the first symbol, or the first byte of the FEC codeword.

[0366] In a possible implementation, the FEC codeword includes: an FEC inner codeword.

[0367] In a possible implementation, the data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

[0368] In a possible implementation manner, a period for inserting a filling sequence into the data stream is an integer multiple of a period for inserting a check sequence into the data stream.

[0369] In a possible implementation, the target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

[0370] In a possible implementation, the apparatus further includes: a processing unit 602 .

[0371] The processing unit 602 is configured to measure a first delay corresponding to data at each specific location among the data at the multiple specific locations to obtain multiple first delays; wherein the target delay includes a maximum value and / or a minimum value among the multiple first delays.

[0372] In a possible implementation, the sending unit 601 is configured to: report the maximum value using the TX maximum delay register of the inner code FEC; and / or report the minimum value using the TX minimum delay register of the inner code FEC.

[0373] In one possible implementation, the sending unit 602 is configured to: report the maximum value using a TX maximum delay register of a physical medium attachment (PMA) / physical medium dependent (PMD); and / or report the minimum value using a TX minimum delay register of a PMA / PMD.

[0374] In a possible implementation, the sending unit 603 is configured to: report the maximum value using the RX maximum delay register of the inner code FEC; and / or report the minimum value using the RX minimum delay register of the inner code FEC.

[0375] In a possible implementation, the sending unit 604 is configured to: report the maximum value by using the RX maximum delay register of the PMA / PMD; and / or report the minimum value by using the RX minimum delay register of the PMA / PMD.

[0376] In a possible implementation, the sending unit 605 is configured to report the target delay corresponding to the data at the multiple specific positions in the data stream to a media access control (MAC) layer.

[0377] In a possible implementation, the device is applied to an optical module or a physical (PHY) layer chip.

[0378] In a possible implementation, the optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

[0379] In a possible implementation, the specific position is the starting position of the next data block after the padding sequence is inserted into the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0380] Referring to Figure 7, which is a schematic diagram of the structure of another delay reporting device provided in an embodiment of the present application, the delay reporting device shown in Figure 7 can be used to execute the delay reporting method shown in Figure 4 provided in the above method embodiment.

[0381] As shown in FIG7 , the delay reporting apparatus 700 includes a processing unit 701 and a sending unit 702 .

[0382] A processing unit 701 is configured to obtain a delay jitter value of target data passing through a first submodule in the first module, where the first submodule includes a submodule for delay jitter having a fixed value, and the target data is data sent by the first module, or the target data is data received by the first module, where the delay jitter value is the preset fixed value.

[0383] The sending unit 702 is configured to report the delay information to the second module according to the delay jitter value.

[0384] In one possible implementation, the processing unit 701 is further used to determine the first delay of the target data passing through the second submodule in the first module; and the sending unit 702 is used to report the delay information to the second module based on the delay jitter value and the first delay.

[0385] In a possible implementation, the sending unit 702 is configured to report to the second module a target delay obtained according to the delay jitter value and the first delay.

[0386] In a possible implementation, the target delay includes: the sum of the delay jitter value and the first delay; or a difference obtained by subtracting the delay jitter value from the first delay.

[0387] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained according to the maximum delay and the delay jitter value, and the minimum target delay obtained according to the minimum delay and the delay jitter value.

[0388] In one possible implementation, if the target data is data sent by the first module, the sending unit 702 is used to: use the TX maximum delay register of the inner code forward error correction FEC to report the maximum target delay to the second module; use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0389] In one possible implementation, if the target data is data sent by the first module, the sending unit 702 is used to: use the TX maximum delay register of the physical medium attachment PMA / physical medium related PMD to report the maximum target delay to the second module; and use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0390] In one possible implementation, if the target data is data received by the first module, the sending unit 702 is used to: use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module; use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0391] In one possible implementation, if the target data is data received by the first module, the sending unit 702 is used to: use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module; use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0392] In a possible implementation, the second submodule includes: a submodule other than the first submodule.

[0393] In one possible implementation, the second submodule includes: a submodule in the inner code FEC module that performs convolution interleaving, distribution, and modulation coding operations; or a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

[0394] In a possible implementation, the processing unit 701 is configured to obtain the preset first delay.

[0395] In a possible implementation, the processing unit 701 is configured to: count a first time delay of the target data passing through the second submodule.

[0396] In a possible implementation, the counting of the first delay of the target data passing through the second submodule includes: counting the delay of at least one bit of the target data passing through the second submodule to obtain the first delay.

[0397] In one possible implementation, the processing unit 701 is further used to determine the second delay of the target data passing through the third submodule in the first module; and the sending unit 702 is used to report the delay information to the second module based on the delay jitter value and the second delay.

[0398] In a possible implementation, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0399] In a possible implementation, the second module includes: a media access control MAC layer module.

[0400] In a possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0401] In a possible implementation, the first submodule includes: a cyclic shift submodule.

[0402] In a possible implementation, the first submodule includes a submodule for detecting delay jitter caused by addition or deletion of a check sequence, or addition or deletion of a padding sequence.

[0403] In a possible implementation, the first submodule includes a submodule that detects delay jitter caused by interleaving or deinterleaving of data streams.

[0404] In one possible implementation, the first submodule includes: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition operations; or a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence removal operations.

[0405] In a possible implementation, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0406] In a possible implementation, the data block includes 128 bits or 120 bits.

[0407] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0408] Referring to Figure 8, which is a schematic diagram of the structure of a device provided in an embodiment of the present application, the device 800 shown in Figure 8 includes an interface circuit 801 and a processing circuit 802. The interface circuit 801 is used to receive and / or send data, and the processing circuit 802 is used to process data.

[0409] In one example, the device 800 may be used to execute the delay reporting method corresponding to FIG2 provided in the above method embodiment.

[0410] The interface circuit 801 is used to report the target delay corresponding to data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream; in one example, the processing circuit 802 is used to measure the first delay corresponding to the data at each specific position in the data at the multiple specific positions to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0411] In yet another example, the device 800 may be used to execute the latency reporting method corresponding to FIG. 4 provided in the above method embodiment. In this case:

[0412] The processing circuit 802 is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule includes a submodule with a delay jitter having a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; the interface circuit 801 is used to report delay information to the second module based on the delay jitter value.

[0413] See Figure 9, which is a structural diagram of a device provided in an embodiment of the present application.

[0414] In one example, the device 900 shown in FIG9 can be used to execute the delay reporting method corresponding to FIG2 provided in the above method embodiment.

[0415] In yet another example, the device 900 shown in FIG9 may be used to execute the delay reporting method corresponding to FIG4 provided in the above method embodiment.

[0416] As shown in FIG9 , device 900 includes a processor 910. Device 900 may include one or more processors 910, with FIG9 illustrating a single processor as an example. Processor 910 is configured to execute the latency reporting method corresponding to FIG2 provided in the above method embodiment, or the latency reporting method corresponding to FIG4 provided in the above method embodiment.

[0417] Processor 910 may be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. Processor 910 may include a digital signal processor (DSP). Processor 910 may further include a hardware chip. The hardware chip may be an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0418] In one example, the device 900 further includes a memory 930. The memory 930 may include a volatile memory (English: volatile memory), such as a random-access memory (RAM); the memory 930 may also include a non-volatile memory (English: non-volatile memory), such as a flash memory (English: flash memory), a hard disk drive (HDD), or a solid-state drive (SSD); and the memory 930 may also include a combination of the aforementioned types of memory. When the device 900 is used to execute the latency reporting method corresponding to FIG. 2 provided in the above method embodiment, the memory 930 may, for example, store the aforementioned target latency. When the device is used to execute the latency reporting method corresponding to FIG. 4 provided in the above method embodiment, the memory may, for example, store the aforementioned fixed value.

[0419] Optionally, the memory 930 stores an operating system and programs, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the programs may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 910 can read the programs in the memory 930 to implement the methods provided in the embodiments of the present application.

[0420] In one example, the device 900 also includes a communication interface 920. In the embodiment of the present application, the processor 910, the communication interface 920 and the memory 930 can be connected through a bus system or other means, where Figure 9 takes the connection through the bus system 940 as an example.

[0421] The communication interface 920 is used to receive and / or send data. For example, when the device 900 is used to perform the delay reporting method corresponding to FIG. 2 provided in the above method embodiment, the communication interface 910 is used to report the target delay corresponding to data at multiple specific locations in the data stream. When the device 900 is used to perform the delay reporting method corresponding to FIG. 4 provided in the above method embodiment, the communication interface 910 is used to report delay information to the second module based on the delay jitter value.

[0422] Bus system 940 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Bus system 940 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG9 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0423] The present application also provides a chip or optical module, the structure of which may be as shown in Figure 10. Referring to Figure 10, this figure is a schematic diagram of the structure of a chip or optical module provided in an embodiment of the present application. The chip or optical module 1000 shown in Figure 10 includes an interface circuit 1001 and a processing circuit 1002. The interface circuit 1001 is used to receive and / or transmit data, and the processing circuit 1002 is used to process data.

[0424] In one example, the chip or optical module 1000 can be used to execute the delay reporting method corresponding to FIG2 provided in the above method embodiment.

[0425] The interface circuit 1001 is configured to report target delays corresponding to data at multiple specific locations in a data stream, where the multiple specific locations are spaced at fixed lengths, and a period of the multiple specific locations corresponds to a period of inserting a padding sequence into the data stream. As an example, the processing circuit 1002 is configured to measure a first delay corresponding to data at each of the multiple specific locations to obtain multiple first delays; wherein the target delay includes a maximum value and / or a minimum value among the multiple first delays.

[0426] In another example, the chip or optical module 1000 can be used to execute the delay reporting method corresponding to FIG4 provided in the above method embodiment.

[0427] The processing circuit 1002 is configured to obtain a delay jitter value of target data passing through a first submodule in the first module, the first submodule including a submodule with a fixed delay jitter value, the target data being data sent by the first module or data received by the first module, wherein the delay jitter value is a preset fixed value. The interface circuit 1001 is configured to report delay information to the second module based on the delay jitter value.

[0428] The present application provides a computer-readable storage medium comprising instructions or a computer program that, when executed on a computer, causes the computer to execute the method described in the above method embodiments. For example, the computer may execute the latency reporting method corresponding to FIG. 2 provided in the above method embodiments; or, for another example, the computer may execute the latency reporting method corresponding to FIG. 4 provided in the above method embodiments.

[0429] The present application provides a computer program product comprising instructions or a computer program that, when executed on a computer, causes the computer to perform the methods described in the above method embodiments. For example, the computer may perform the latency reporting method corresponding to FIG. 2 provided in the above method embodiments; or, in another example, the computer may perform the latency reporting method corresponding to FIG. 4 provided in the above method embodiments.

[0430] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0431] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0432] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical business division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0433] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0434] In addition, each business unit in each embodiment of the present application can be integrated into a processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or software business units.

[0435] If the integrated unit is implemented in the form of a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0436] Those skilled in the art will appreciate that, in one or more of the above examples, the services described herein can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these services can be stored on a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transmission of computer programs from one location to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0437] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention.

[0438] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A delay reporting method, characterized in that: The method comprises: Report target delays corresponding to data at multiple specific locations in a data stream, where the multiple specific locations are spaced at fixed lengths, and a period of the multiple specific locations corresponds to a period of inserting a padding sequence in the data stream.

2. The method according to claim 1, characterized in that The period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

3. The method according to claim 2, characterized in that The data block includes 128 bits, 120 bits, or 4 bits.

4. The method according to claim 1, wherein The period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

5. The method according to any one of claims 1 to 4, characterized in that The specific position is the starting position of the FEC codeword, and the starting position is the first bit, the first symbol, or the first byte of the FEC codeword.

6. The method according to claim 4 or 5, characterized in that The FEC codeword includes: an FEC inner codeword.

7. The method according to any one of claims 1 to 6, characterized in that The data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

8. The method according to any one of claims 1 to 7, characterized in that The period of inserting the filling sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream.

9. The method according to any one of claims 1 to 8, characterized in that The target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

10. The method according to any one of claims 1 to 9, characterized in that The method further comprises: Measuring a first time delay corresponding to data at each specific location among the data at the multiple specific locations to obtain multiple first time delays; The target delay includes the maximum value and / or the minimum value of the multiple first delays.

11. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in the data stream, including: Using the TX maximum delay register of the inner code FEC, reporting the maximum value; and / or, The minimum value is reported using the TX minimum delay register for inner code FEC.

12. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in the data stream, including: using the TX Maximum Latency register of the Physical Medium Attachment PMA / Physical Medium Dependent PMD to report the maximum value; and / or, The minimum value is reported using the TX minimum delay register of the PMA / PMD.

13. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in the data stream, including: Using the RX maximum delay register of the inner code FEC, reporting the maximum value; and / or, The minimum value is reported using the RX minimum delay register for inner code FEC.

14. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in the data stream, including: Using the RX maximum delay register of the PMA / PMD to report the maximum value; and / or, The minimum value is reported using the RX minimum latency register of the PMA / PMD.

15. The method according to any one of claims 1 to 14, characterized in that: Reports the target latency for data at multiple specific locations in the data stream, including: The target delay corresponding to the data at the multiple specific positions in the data stream is reported to a media access control (MAC) layer.

16. The method according to any one of claims 1 to 15, characterized in that The method is applied to an optical module or a physical (PHY) layer chip.

17. The method according to claim 16, characterized in that The optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

18. The method according to any one of claims 1 to 17, characterized in that: The specific position is the starting position of the next data block after the filling sequence is inserted into the data stream, and the starting position is the first bit, the first symbol, or the first byte of the data block.

19. A delay reporting method, characterized in that: Applied to the first module, the method includes: Obtaining a delay jitter value of target data passing through a first submodule in the first module, where the first submodule includes a submodule for delay jitter having a fixed value, the target data being data sent by the first module, or the target data being data received by the first module, wherein the delay jitter value is the preset fixed value; Report the delay information to the second module according to the delay jitter value.

20. The method according to claim 19, characterized in that The method further comprises: Determining a first time delay for the target data to pass through the second submodule in the first module; The reporting delay information to the second module according to the delay jitter value includes: Report the delay information to the second module according to the delay jitter value and the first delay.

21. The method according to claim 20, characterized in that The reporting the delay information to the second module according to the delay jitter value and the first delay includes: Reporting a target delay obtained according to the delay jitter value and the first delay to the second module.

22. The method according to claim 21, characterized in that The target delay includes: the sum of the delay jitter value and the first delay; or A difference obtained by subtracting the delay jitter value from the first delay.

23. The method according to claim 21 or 22, characterized in that The first delay includes: The maximum delay and minimum delay of the target data passing through the second submodule; Accordingly, the target delay includes: A maximum target delay is obtained according to the maximum delay and the delay jitter value, and a minimum target delay is obtained according to the minimum delay and the delay jitter value.

24. The method according to claim 23, wherein If the target data is data sent by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Using the TX maximum delay register of the inner code forward error correction FEC, the maximum target delay is reported to the second module; The minimum target delay is reported to the second module using the TX minimum delay register of the inner code FEC.

25. The method according to claim 23, characterized in that If the target data is data sent by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: reporting the maximum target delay to the second module using a TX maximum delay register of a physical medium attachment (PMA) / physical medium dependent (PMD); The minimum target delay is reported to the second module using the TX minimum delay register of the PMA / PMD.

26. The method according to claim 23, wherein If the target data is data received by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Using the RX maximum delay register of the inner code FEC, reporting the maximum target delay to the second module; The minimum target delay is reported to the second module using the RX minimum delay register of the inner code FEC.

27. The method according to claim 23, characterized in that If the target data is data received by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Utilize the RX maximum delay register of PMA / PMD to report the maximum target delay to the second module; The minimum target delay is reported to the second module using the RX minimum delay register of the PMA / PMD.

28. The method according to any one of claims 20 to 27, characterized in that: The second submodule includes: Submodules other than the first submodule.

29. The method according to any one of claims 20 to 27, wherein: The second submodule includes: The submodule in the inner code FEC module performs convolution interleaving, distribution and modulation coding operations; Alternatively, the submodule in the inner code FEC module performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

30. The method according to any one of claims 20 to 29, characterized in that: Determining a first time delay for the target data to pass through the second submodule in the first module includes: Obtain the preset first delay.

31. The method according to any one of claims 20 to 29, wherein: Determining a first time delay for the target data to pass through the second submodule in the first module includes: A first time delay of the target data passing through the second submodule is counted.

32. The method according to claim 31, characterized in that The counting of a first time delay of the target data passing through the second submodule includes: The time delay of at least one bit data in the target data passing through the second submodule is counted to obtain the first time delay.

33. The method according to claim 19, wherein The method further comprises: Determining a second time delay for the target data to pass through the third submodule in the first module; The reporting delay information to the second module according to the delay jitter value includes: Report the delay information to the second module according to the delay jitter value and the second delay.

34. The method according to claim 33, wherein The third submodule includes: a PMA submodule and / or a PMD submodule.

35. The method according to any one of claims 19 to 34, characterized in that The second module includes: Media Access Control MAC layer module.

36. The method according to any one of claims 19 to 35, wherein: The fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

37. The method according to claims 19-36, characterized in that The first submodule includes a submodule for detecting delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence.

38. The method according to claims 19-37, characterized in that The first submodule includes a submodule for detecting delay jitter caused by interleaving or deinterleaving of data streams.

39. The method according to claims 19-38, characterized in that The first submodule includes: A submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition operations; Alternatively, a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence removal operations.

40. The method according to any one of claims 19 to 39, wherein: The first submodule includes: Circular shift submodule.

41. The method according to any one of claims 19-40, characterized in that The target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

42. The method according to claim 41, wherein The data block includes 128 bits or 120 bits.

43. The method according to any one of claims 19 to 40, wherein: The target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440*N bits, where N is a positive integer.

44. A time delay reporting device, characterized in that: The device comprises: A sending unit is used to report target delays corresponding to data at multiple specific positions in a data stream, where the multiple specific positions are spaced at fixed lengths, and the periods of the multiple specific positions correspond to the periods of inserting padding sequences in the data stream.

45. A time delay reporting device, characterized in that: Applied to the first module, the device includes: a processing unit, configured to obtain a delay jitter value of target data passing through a first submodule in the first module, the first submodule including a submodule for delay jitter having a fixed value, the target data being data sent by the first module, or the target data being data received by the first module, wherein the delay jitter value is the preset fixed value; The sending unit is configured to report the delay information to the second module according to the delay jitter value.

46. ​​A time delay reporting device, characterized in that: The device is used to perform the method according to any one of claims 1 to 18, or the device is used to perform the method according to any one of claims 19 to 43.

47. A time delay reporting device, characterized in that: The device includes an interface circuit and a processing circuit; The interface circuit is used to perform the data sending and / or receiving operation in the method according to any one of claims 1 to 18, and the interface circuit is used to perform the data processing operation in the method according to any one of claims 1 to 18; or The interface circuit is used to perform the data sending and / or receiving operations in any one of the methods described in claims 19 to 43, and the interface circuit is used to perform the data processing operations in any one of the methods described in claims 19 to 43.

48. The device according to claim 47, wherein the device is: Optical module, or chip.

49. A device, characterized in that include: processor and memory; The memory is used to store instructions or computer programs; The processor is configured to execute the instructions or computer program and perform the method according to any one of claims 1 to 43.

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