Array substrate, display panel, display device and driving method

Abstract

An array substrate, a display panel, a display device and a driving method. The array substrate comprises: a substrate (1); a plurality of gate lines (2); a plurality of data lines (3), wherein at least one data line (3) among the data lines (3) comprises first data portions (31) and second data portions (32) alternately distributed in a second direction, and extension lines of two first data portions (31) on two sides of each second data portion (32) do not coincide in the second direction; a plurality of pixel electrodes, wherein the maximum length of each pixel electrode (4) in a first direction is greater than the maximum length thereof in the second direction, and the orthographic projections of the plurality of pixel electrodes (4) on the substrate (1) at least partially overlap the orthographic projections of the gate lines (2) on the substrate (1); and a plurality of first common electrodes (65) extending in the second direction and disconnected at positions intersecting with the gate lines (2), wherein the orthographic projections of the first common electrodes (65) on the substrate (1) at least partially cover gaps between the data lines (3) and the pixel electrodes (4).

Description

Array substrate, display panel, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to an international application filed with the State Intellectual Property Office of China on February 27, 2024, with application number PCT / CN2024 / 078797 and application name “Array Substrate, Display Panel, Display Device and Driving Method,” all or part of which is incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, a display device, and a driving method. Background Art

[0004] Compared to the conventional pixel drive structure of one gate line and one data line (1G1D), special pixel drive structures are sometimes used to reduce the number of data lines and increase the number of scan lines. These special pixel drive structures are the dual-gate pixel drive structure (Dual Gate) and the triple-gate pixel drive structure (Triple Gate). In a display panel of the same size, compared to the 1G1D pixel drive structure, the triple-gate pixel drive structure increases the number of scan lines by two times, while the number of data lines is reduced to one-third of the original. If a drive structure in which the gate drive circuit is integrated into the display panel (Gate on Array, GOA) is used, the increase in the number of scan lines does not require additional driver circuit costs, while the reduction in the number of data lines can reduce the number of driver ICs, thus having a cost advantage. Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, a display device, and a driving method. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction;

[0008] a plurality of data lines located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction, at least one of the plurality of data lines comprising: first data portions and second data portions alternately distributed along the second direction; in the second direction, extensions of two first data portions on either side of the second data portion do not overlap;

[0009] a plurality of pixel electrodes, wherein a maximum length of the pixel electrodes in the first direction is greater than a maximum length in the second direction; and an orthographic projection of the plurality of pixel electrodes on the substrate overlaps at least partially with an orthographic projection of the gate line on the substrate;

[0010] A plurality of first common electrodes extend along the second direction and are disconnected at positions intersecting the gate lines. The orthographic projections of the first common electrodes on the substrate at least partially cover the gaps between the data lines and the pixel electrodes.

[0011] In a possible implementation, the array substrate further includes: a first common line extending along the first direction; an orthographic projection of the first common line on the substrate passes through a central area of ​​the orthographic projection of the pixel electrode on the substrate;

[0012] The first common electrode is connected to the first common wiring.

[0013] In one possible embodiment, the array substrate includes: a second common routing group extending along the second direction; the second common routing group is disconnected at a position intersecting the gate line; the second common routing group includes: a first sub-common routing group and a second sub-common routing group arranged along the first direction, wherein a length of the first sub-common routing group in the second direction is less than a length of the second sub-common routing group in the second direction, and in the second direction, the first sub-common routing group and the second sub-common routing group are alternately arranged;

[0014] The array substrate further includes: a common compensation portion connected to a side of the first sub-common wiring away from the second sub-common wiring; and the first common electrode includes the first sub-common wiring and the common compensation portion.

[0015] In a possible implementation, the first common electrode has a fifth outer edge extending along the second direction on a side facing the second sub-common wiring; and the extension lines of the fifth outer edges of two adjacent first common electrodes in the second direction do not overlap.

[0016] In a possible implementation, the first common electrode includes: a wiring body, and a wiring protrusion extending from at least one side of the wiring body along the second direction;

[0017] The orthographic projection of the routing protrusion on the substrate does not overlap with the orthographic projection of the data line on the substrate.

[0018] In a possible implementation, the orthographic projection of the first common electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode on the substrate.

[0019] In a possible implementation manner, the maximum length of the first common electrode in the second direction is smaller than the minimum distance between two adjacent gate lines in the second direction;

[0020] A width of the first common electrode in the first direction is greater than a width of the second sub-common wiring in the first direction.

[0021] In a possible embodiment, at least one gate line among the plurality of gate lines includes a plurality of gate line groups sequentially distributed along a first direction; the gate line group includes: a first gate line portion extending along the first direction and sequentially distributed, a second gate line portion, and a third gate line portion located between the first gate line portion and the second gate line portion and connecting the first gate line portion and the second gate line portion; an extension line of the first gate line portion does not overlap with an extension line of the second gate line portion, and an extension direction of the third gate line portion intersects the first direction;

[0022] The orthographic projections of the plurality of pixel electrodes on the substrate at least partially overlap with the orthographic projections of the first gate line portion and the second gate line portion on the substrate.

[0023] In a possible implementation, the third gate line portion extends along the third direction, and the third direction intersects the first direction and the second direction.

[0024] In a possible implementation manner, a length of the gate line group in the first direction is substantially equal to a length of the pixel electrode in the first direction.

[0025] In a possible implementation manner, a length of the first gate line portion in the first direction is less than or equal to a maximum length of the second gate line portion in the first direction.

[0026] In a possible embodiment, the gate line further includes: a gate line connecting portion located between adjacent gate line groups and connecting adjacent gate line groups; the gate line connecting portion extends along the first direction, and an extension line is located between the first gate line portion and the second gate line portion.

[0027] In a possible embodiment, in the same gate line group, the orthographic projection of the first gate line portion on the substrate is covered by the orthographic projection of one pixel electrode on the substrate, and the orthographic projection of the second gate line portion on the substrate is covered by the orthographic projection of another adjacent pixel electrode in the second direction on the substrate.

[0028] In a possible implementation manner, the orthographic projection of the gate line on the substrate is a straight line.

[0029] In a possible implementation, the second data portion includes: a first sub-data portion, a second sub-data portion, and a third sub-data portion; the first sub-data portion extends along the first direction; the second sub-data portion and the third sub-data portion extend along the second direction and are located on the same side of the first sub-data portion;

[0030] One end of the first sub-data portion is connected to one end of the second sub-data portion, and the other end is connected to one end of the third sub-data portion and one of the first data portions; the other end of the second sub-data portion is connected to another of the first data portions.

[0031] In a possible implementation manner, the first sub-data portion of two adjacent second data portions and the first data portion between the two adjacent second data portions form a groove;

[0032] At least a portion of the first common electrode, in the orthographic projection of the substrate, is located within the orthographic projection of the groove.

[0033] In a possible implementation manner, the orthographic projection of the first data portion on the substrate is located in a region between the orthographic projections of two adjacent pixel electrodes on the substrate in the first direction;

[0034] An orthographic projection of the second data portion on the substrate has an overlapping area with an orthographic projection of the gate line on the substrate.

[0035] In one possible embodiment, the array substrate further includes: a plurality of transistors; at least one of the plurality of transistors includes: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the control electrode on the substrate; and orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the active pattern on the substrate;

[0036] The first stage multiplexes the second sub-data portion; the third stage multiplexes the third sub-data portion;

[0037] The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the part of the second pole first portion on the orthographic projection of the substrate is located between the second sub-data portion and the third sub-data portion on the orthographic projection of the substrate.

[0038] In a possible implementation manner, a length of the second pole overlapping portion in the second direction is substantially equal to a length of the first data portion in the second direction.

[0039] In a possible implementation, a width of the second pole overlapping portion in the first direction is greater than a width of the second pole first portion in the first direction.

[0040] In a possible implementation, the array substrate further includes: a third common line extending along the first direction; the third common line is disconnected at a position where it intersects with the data line.

[0041] In a possible embodiment, the array substrate further includes: a fourth common routing line extending along the second direction; the fourth common routing line is an orthographic projection of the substrate, passing through the central area of ​​the orthographic projection of the pixel electrode on the substrate; and the plurality of third common routing lines between two adjacent data lines are all connected to the fourth common routing line.

[0042] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0043] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0044] The present disclosure further provides a method for driving the display panel provided in the embodiment of the present disclosure, which includes:

[0045] Controlling a plurality of gate lines to load scanning signals row by row, and controlling the gate lines to load the scanning signals for a duration greater than 1H;

[0046] During at least a portion of a period in which the gate line is loaded with a scan signal, the data line is controlled to be loaded with a data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1A is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0048] FIG1B is a schematic diagram of a single film layer where the gate lines are located in FIG1A;

[0049] FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0050] FIG1D is a schematic diagram of a single film layer where the data line is located in FIG1A;

[0051] FIG1E is a schematic diagram of a single film layer where the pixel electrode is located in FIG1A ;

[0052] FIG1F is an enlarged schematic diagram of the transistor T in FIG1A ;

[0053] FIG2A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0054] FIG2B is a schematic diagram of a single film layer where the gate lines are located in FIG2A;

[0055] FIG2C is a schematic diagram of a single film layer of the active layer in FIG2A ;

[0056] FIG2D is a schematic diagram of a single film layer where the data line is located in FIG2A;

[0057] FIG2E is a schematic diagram of a single film layer where the pixel electrode is located in FIG2A ;

[0058] FIG3 is a schematic cross-sectional view of FIG2A taken along the dotted line AA′;

[0059] FIG4 is a schematic cross-sectional view of FIG2A taken along the dotted line BB′;

[0060] FIG5 is a schematic diagram of a pixel driving architecture provided by an embodiment of the present disclosure;

[0061] FIG6 is a schematic diagram of a color resist layer provided by an embodiment of the present disclosure;

[0062] FIG7 is a schematic diagram of a method for driving a display panel according to an embodiment of the present disclosure;

[0063] FIG8A is a schematic diagram of a driving process according to an embodiment of the present disclosure;

[0064] FIG8B is a driving timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation method can be implemented in a variety of different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0067] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "approximately the same" may refer to values ​​that are within 10% of each other.

[0068] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0069] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0070] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0071] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0072] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0073] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0074] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0076] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0077] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0078] Low cost has become a must for LCD panel development. The triple-gate pixel driver structure can effectively reduce the number of COF ICs, but the pixel aperture ratio will be seriously affected by the change from vertical to horizontal pixel arrangement.

[0079] 1A to 1F, 2A to 2E, 3 and 4, wherein FIG1A is one schematic diagram of an array substrate provided in an embodiment of the present disclosure, FIG1B is a schematic diagram of a single film layer in a layer where the gate line is located in FIG1A, FIG1C is a schematic diagram of a single film layer in a layer where the active layer is located in FIG1A, FIG1D is a schematic diagram of a single film layer in a layer where the data line is located in FIG1A, and FIG1E is a schematic diagram of a single film layer in a layer where the pixel electrode is located in FIG1A, FIG2A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure, FIG2B is a schematic diagram of a single film layer in a layer where the gate line is located in FIG2A, FIG2C is a schematic diagram of a single film layer in a layer where the active layer is located in FIG2A, FIG2D is a schematic diagram of a single film layer in a layer where the data line is located in FIG2A, and FIG2E is a schematic diagram of a single film layer in a layer where the pixel electrode is located in FIG2A, FIG3 is a schematic cross-sectional view taken along the dotted line AA' in FIG2A, and FIG4 is a schematic cross-sectional view taken along the dotted line BB' in FIG2A. An embodiment of the present disclosure provides an array substrate, which includes:

[0080] Substrate 1;

[0081] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0082] Multiple data lines 3 are located on the same side of the substrate 1 as the multiple gate lines 2, and the multiple data lines 3 extend along the second direction Y. At least one of the multiple data lines 3 includes: first data portions 31 and second data portions 32 alternately distributed along the second direction Y. In the second direction Y, the extension lines of the two first data portions 31 on both sides of the second data portion 32 do not overlap, that is, the data lines 3 are distributed in a zigzag shape.

[0083] Multiple pixel electrodes 4, a maximum length a1 of the pixel electrodes 4 in the first direction X is greater than a maximum length a2 in the second direction Y, that is, the long side direction of the pixel electrodes 4 is the same as the extension direction of the gate lines 2; and the orthographic projections of the multiple pixel electrodes 4 on the substrate 1 overlap at least partially with the orthographic projections of the gate lines 2 on the substrate 1; optionally, at least a portion of the orthographic projection of at least one pixel electrode 4 among the multiple pixel electrodes 4 on the substrate 1 may be located in an area formed by the intersection of adjacent gate lines 2 and adjacent data lines 3; that is, the intersection of the multiple gate lines 2 and the multiple data lines 3 may form multiple grid areas, and at least a portion of the orthographic projection of the pixel electrodes 4 on the substrate 1 may be located in the grid area formed by the intersection;

[0084] A plurality of first common electrodes 65 extend along the second direction Y and are disconnected at positions intersecting the gate lines 2 ; the orthographic projection of the first common electrodes 65 on the substrate 1 covers at least a portion of the orthographic projection of the gap between the data lines 3 and the pixel electrodes 4 on the substrate 1 .

[0085] In the embodiment of the present disclosure, the maximum length a1 of the pixel electrode 4 in the first direction X is greater than the maximum length a2 in the second direction Y, which is a triple gate pixel drive (Triple Gate) structure, and the orthographic projections of multiple pixel electrodes 4 on the substrate 1 and the orthographic projections of the gate lines 2 on the substrate 1 at least partially overlap, so that the pixel electrodes 4 can shield the electric field on the gate lines 2, thereby avoiding light leakage at the gate lines 2 of the array substrate. The width of the black matrix directly above the gate lines 2 can be reduced to a certain extent or no longer required, thereby improving the aperture ratio; in addition, the array substrate also includes a first common electrode 65; the orthographic projection of the first common electrode 65 on the substrate 1 covers at least part of the orthographic projection of the gap between the data line 3 and the pixel electrode 4 on the substrate 1, which can shield or reduce the lateral parasitic capacitance between the data line 3 and the pixel electrode 4, and improve a series of image quality problems such as crosstalk caused by the lateral parasitic capacitance between the data line 3 and the pixel electrode 4, vertical lines caused by COF polarity reversal, and mixed color vertical lines.

[0086] In one possible embodiment, referring to Figures 1A-1F and 2A-2E, the array substrate further includes: a first common trace 61 extending along a first direction X; the orthographic projection of the first common trace 61 on the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 4 on the substrate 1, and the first common electrode 65 is connected to the first common trace 61. In one possible embodiment, referring to Figures 1A and 1B, the orthographic projection of the first common trace 61 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a first storage capacitor is formed by the first common trace 61 and the pixel electrode 1.

[0087] In one possible embodiment, referring to Figures 1A-1F , the array substrate further includes: a second common routing group 620 extending along a second direction Y; the second common routing group 620 is disconnected at a location intersecting with the gate line 2, and the second common routing group 620 includes two second common routing lines 62 extending along the second direction Y. Referring to Figure 1A , the two second common routing lines 62 are disposed on both sides of the data line and can be used to shield the coupling capacitance between the data line and the pixel electrode.

[0088] In one possible embodiment, as shown in Figures 1A-1F , the two second common routing lines 62 of the same second common routing group 620 can be a first sub-common routing line 621 and a second sub-common routing line, respectively. The length of the first sub-common routing line 621 in the second direction Y can be shorter than the length of the second sub-common routing line 622 in the second direction Y. The first sub-common routing lines 621 and the second sub-common routing lines 622 are arranged alternately in the second direction Y. That is, of the two second common routing lines 62 in the second common routing group 620, the shorter one in the second direction Y can be used as the first sub-common routing line 621, and the longer one can be used as the second sub-common routing line 622. Furthermore, the second sub-common routing lines 622 of two adjacent second common routing groups 620 in the second direction Y are located on different sides of the data line 3. Optionally, the width e5 of the first sub-common routing line 621 in the first direction X can be substantially the same as the width e4 of the second sub-common routing line 622 in the first direction X.

[0089] In one possible embodiment, as shown in conjunction with Figures 1A-1E , the array substrate further includes a common compensation portion 650 connected to a side of the first sub-common trace 621 away from the second sub-common trace 622. The first common electrode 65 includes the first sub-common trace 621 and the common compensation portion 650. The portion of the common compensation portion 650 close to the data line 3 can serve as the first sub-common trace 621.

[0090] In one possible embodiment, as shown in FIG1B , adjacent first common electrodes 65 are staggered along the second direction Y. Specifically, the first common electrodes 65 have a fifth outer edge w5 extending along the second direction Y. Extensions of the fifth outer edges w5 of two adjacent first common electrodes 65 in the second direction Y do not overlap. This adapts to the bend of the data line 3 and avoids overlapping with the data line 3.

[0091] In one possible embodiment, referring to Figures 1A, 1B, and 1F, the first common electrode 65 includes: a wiring body 651, and a wiring protrusion 652 extending from at least one side of the wiring body 651 along the second direction Y; the array substrate also includes: a transistor; the transistor includes: a first electrode TC1, a second electrode TC2, and a third electrode TC3; the orthographic projection of the wiring protrusion 652 on the substrate 1 overlaps with the orthographic projection of the second electrode TC2 on the substrate 1.

[0092] In a possible embodiment, referring to Figures 1A and 1B, in the second direction Y, the number of routing protrusions 652 of two adjacent first common electrodes 65 may be different. For example, in Figure 1B, the first first common electrode 65 on the right side from top to bottom has one routing protrusion 652 facing upward and one routing protrusion 652 facing downward; while the second first common electrode 65 on the right side from top to bottom has one routing protrusion 652 facing upward and two routing protrusions 652 facing downward to adapt to other structures at different positions (for example, the first first common electrode 65 on the right side from top to bottom has one routing protrusion 652 facing downward to adapt to the shape of the gate line 2 at that position to avoid overlapping with the gate line 2).

[0093] In the embodiment of the present disclosure, the driving architecture is a Z architecture, and one data line 3 drives the pixel electrodes 4 on the left and right sides of the data line 3. The number of routing protrusions 652 of different first common electrodes 65 can be different, so that the first common electrode 65 can match the structure between the first data portion 31, the second data portion 32 and the gate line 2, and the area of ​​the first common electrode 65 can be maximized as much as possible without affecting the functions of other structures.

[0094] In a possible embodiment, referring to FIG. 1A to FIG. 1E , the orthographic projection of the first common electrode 65 on the substrate 1 does not overlap with the orthographic projection of the data line 3 on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode 4 on the substrate 1 .

[0095] In one possible embodiment, referring to FIG1A , the orthographic projection of the first common electrode 65 on the substrate 1 has an overlapping area with the orthographic projection of the second electrode lap portion TC2D of the second electrode TC2 of the transistor on the substrate 1; optionally, the orthographic projection of the first common electrode 65 on the substrate 1 covers the orthographic projection of the second electrode lap portion TC2D on the substrate 1.

[0096] In a possible embodiment, referring to FIG1B , the maximum length e1 of the first common electrode 65 in the second direction Y is less than the minimum distance e2 between two adjacent gate lines 2 in the second direction Y; in this way, cross-connection with the gate lines 2 is avoided; the width e3 of the first common electrode 65 in the first direction X is greater than the width e4 of the second sub-common line 621 in the first direction X; in a possible embodiment, the width e3 of the first common electrode 65 in the first direction X may be 2 to 10 times the width e4 of the second sub-common line 621 in the first direction X; in a possible embodiment, the width e3 of the first common electrode 65 in the first direction X may be 3 to 5 times the width e4 of the second sub-common line 621 in the first direction X.

[0097] In one possible embodiment, as shown in Figures 1A-1F and 2A-2E, the orthographic projection of the second common signal line 62 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a second storage capacitor is formed by the second common signal line 62 and the pixel electrode 4.

[0098] In a possible embodiment, referring to Figures 1A to 1F and Figures 2A to 2E, at least one gate line 2 among the plurality of gate lines 2 includes a plurality of gate line groups 20 distributed in sequence along the first direction X; the gate line group 20 includes: a first gate line portion 21 extending along the first direction X and distributed in sequence, a second gate line portion 22, and a third gate line portion 23 located between the first gate line portion 21 and the second gate line portion 22 and connecting the first gate line portion 21 and the second gate line portion 22; an extension line of the first gate line portion 21 does not coincide with an extension line of the second gate line portion 22, and an extension direction of the third gate line portion 23 intersects the first direction X; specifically, the first gate line portion 21 and the second gate line portion 22 may not be located on the same straight line, and the overall gate line in the unconventional technology is a horizontal straight line; the first gate line portion 21, the third gate line portion 23, and the second gate line portion 22 may form a "Z"-shaped pattern;

[0099] The orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 at least partially overlap with the orthographic projections of the first gate line portion 21 and the second gate line portion 22 on the substrate 1. Specifically, the orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 may cover the orthographic projections of the first gate line portion 21 and the second gate line portion 22 on the substrate 1.

[0100] In the embodiment of the present disclosure, the gate line group 20 includes: a first gate line portion 21 and a second gate line portion 22 extending and sequentially distributed along the first direction X; the extension line of the first gate line portion 21 does not overlap with the extension line of the second gate line portion 22, and the orthographic projection of the plurality of pixel electrodes 4 on the substrate 1 at least partially overlaps with the orthographic projection of the first gate line portion 21 and the second gate line portion 22 on the substrate 1, and can overlap with the UV2A edge. The pixel electrode 4 can shield the electric field on the gate line 2 to avoid light leakage at the gate line 2 of the array substrate. The width of the black matrix directly above the gate line 2 can be reduced to a certain extent or no longer needs to be set, which greatly improves the aperture ratio. Moreover, the position of the gate line 2 can overlap with the part of the UV2A dark pattern, which can further improve the transmittance.

[0101] It should be noted that, in the embodiment of the present disclosure, the pixel electrode 4 may be designed as a whole piece; in another possible implementation manner, the pixel electrode 4 may also be a structure including slits and strip electrodes, which is not limited here.

[0102] In addition, in the embodiment of the present disclosure, there can be no light-shielding pattern between the two pixel electrodes 4 in the second direction Y, and no other conductive wires are required to shield the electric field (such as the conductive wire extending along the first direction X on the same layer as the pixel electrode 4, Gate BM Less, GBS line), thereby reducing the gap between the two pixel electrodes 4 (it is expected to be reduced from about 20μm (depending on the line width of the gate line 2) to about 5μm (depending on the process capability of preventing connection when the pixel electrode 4 layer is patterned), and the aperture ratio is almost unaffected by the line width of the gate line 2, thereby improving the transmittance of the product; the gate line 2 and UV2A The dark patterns of the characters overlap, and the transmittance loss of the metal opaqueness can be minimized, thereby improving the product transmittance. The width of the gate line 2 can be changed freely for transmittance, and the width of the gate line 2 can be adjusted for display panels of different product specifications without losing transmittance. Compared with the traditional gate line 2, the width increases and the transmittance decreases proportionally, which has a great advantage. The gate line 2 does not require a black matrix design, avoiding the problem of light leakage at the edge of the black matrix caused by unstable liquid crystal alignment at the black matrix corner (Taper corner).

[0103] It should be noted that, in the embodiment of the present disclosure, the gate line 2 extends along the first direction X, which can be understood as the overall extension direction of the gate line 2 extending along the first direction X, but there may be bends at specific local positions; similarly, the data line 3 extends along the second direction Y, which can be understood as the overall extension direction of the data line 3 extending along the second direction Y, but there may be bends at specific local positions; specifically, when the data line 3 is a straight line, the data line 3 extends along the second direction Y, which can also be understood as the data line 3 extending along the second direction Y at all positions.

[0104] In one possible embodiment, the third gate line portion 23 may also form an angle of 30° to 60° with the second direction Y. In another possible embodiment, the third gate line portion 23 may also form an angle of 45° with the second direction Y. In another possible embodiment, the third gate line portion 23 may also be in the shape of an S-shaped curve, an arc, or a broken line.

[0105] In one possible embodiment, as shown in FIG1A , a length a3 of the gate line group 20 in the first direction X is less than or equal to a maximum length a1 of the pixel electrode 4 in the first direction X. That is, the gate line 2 can be arranged in a Z-shaped structure having a first gate line portion 21 , a third gate line portion 23 , and a second gate line portion 22 in the region corresponding to the pixel electrode 4 .

[0106] In a possible implementation, as shown in FIG. 1B , a length a4 of the first gate line portion 21 in the first direction X is substantially equal to a length a5 of the second gate line portion 22 in the first direction X.

[0107] In a possible embodiment, referring to Figures 1A-1F, the gate line 2 further includes: a gate line connecting portion 24 located between adjacent gate line groups 20 and connecting adjacent gate line groups 20; the gate line connecting portion 24 extends along the first direction X, and the extension line is located between the first gate line portion 21 and the second gate line portion 22.

[0108] In a possible embodiment, referring to Figures 1A to 1F, the gate line connection portion 24 may include: a first connection portion 241, a second connection portion 242, and a third connection portion 243 arranged in sequence along the first direction X; wherein the first connection portion 241 may extend along the second direction Y, with one end connected to the second gate line portion 22 in the gate line group 20 on one side, and the other end connected to one end of the second connection portion 242; the second connection portion 242 may extend along the first direction X; the third connection portion 243 may extend along the second direction Y, with one end connected to the other end of the second connection portion 242, and the other end connected to the first gate line portion 21 in the gate line group 20 on the other side.

[0109] In a possible implementation, referring to FIG. 1A to FIG. 1F and FIG. 2A to FIG. 2E , the gate line connection portion 24 may be reused as the control electrode TA (ie, the gate) of the transistor T.

[0110] In one possible embodiment, referring to Figures 1A to 1F and Figures 2A to 2E, in the same gate line group 20, the orthographic projection of the first gate line portion 21 on the substrate 1 is covered by the orthographic projection of a pixel electrode 4 on the substrate 1, and the orthographic projection of the second gate line portion 22 on the substrate 1 is covered by the orthographic projection of another adjacent pixel electrode 4 on the substrate 1 in the second direction Y. For example, as shown in Figure 1A, the orthographic projection of the first gate line portion 21 of the second gate line 2 in the top-to-bottom direction on the substrate 1 is covered by the orthographic projection of the first pixel electrode 4 in the top-to-bottom direction on the substrate 1, and the orthographic projection of the second gate line portion 22 of the second gate line 2 in the top-to-bottom direction on the substrate 1 is covered by the orthographic projection of the second pixel electrode 4 in the top-to-bottom direction on the substrate 1.

[0111] In one possible embodiment, as shown in Figures 2A to 2E, the orthographic projection of the gate line 2 on the substrate 1 can also be a straight line. In the disclosed embodiment, in the Triple Gate pixel architecture, the gate line 2 is designed to be flattened, the pixel electrode 4 covers the portion of the gate line 2, the black matrix design at the position of the gate line 2 is removed, and no GBS design is required; the gate line 2 and the pixel electrode 4 do not need to be completely covered, the pixel electrode 4 only needs to cover 2μm to 2.5μm (for example, 2.25μm) of the gate line 2 (determined by the factory process capability); the aperture ratio is greatly improved, and while improving the aperture ratio, the parasitic capacitance generated between the gate line 2 and the pixel electrode 4 can be effectively reduced. This design is not only applicable to COA design, but also applicable to conventional products with ORG (that is, a thicker organic film layer provided to reduce parasitic capacitance, for example, the flat layer 93 in Figure 4), and even non-ORG products can use the array substrate structure shown in Figure 2A.

[0112] In a possible implementation, referring to FIG. 2A to FIG. 2E , the orthographic projection of the linear gate line 2 on the substrate 1 may overlap with the orthographic projections of two adjacent pixel electrodes 4 in the second direction Y on the substrate 1 .

[0113] In a possible embodiment, referring to FIG. 1A to FIG. 1E , the second data portion 32 includes: a first sub-data portion 301, a second sub-data portion 302, and a third sub-data portion 303; the first sub-data portion 301 extends along a first direction X; the second sub-data portion 302 and the third sub-data portion 303 extend along a second direction Y and are located on the same side of the first sub-data portion 301; one end of the first sub-data portion 301 is connected to one end of the second sub-data portion 302, and the other end is connected to one end of the third sub-data portion 303 and the first data portion 31; the second sub-data portion 302 is connected to one end of the third sub-data portion 303 and the first data portion 31; One end is connected to another first data part 31. Specifically, taking the second second data part 32 from top to bottom in Figure 1D as an example, the right end of the first sub-data part 301 is connected to the lower end of the second sub-data line 302, the left end is connected to the lower end of the third sub-data part 303 and the first data part 31 below, the upper end of the second sub-data part 302 is connected to the first data part 31 above, and the other end of the third sub-data part 303 is in an open state and is not connected to other structures; the first sub-data part 301, the second sub-data part 302, and the third sub-data part 303 form a U-shaped pattern as a whole.

[0114] In the embodiment of the present disclosure, the second data portion 32 includes: a first sub-data portion 301, a second sub-data portion 302, and a third sub-data portion 303, which form a U-shaped pattern. Among them, the second sub-data portion 302 and the third sub-data portion 303 can reuse the first electrode TC1 and the third electrode TC3 of the transistor, so that the transistor has a dual-source design. Under the condition that the width (W value) of the same transistor T is constant, the source of the transistor T and the structure electrically connected to the source (such as the pixel electrode 4, the active pattern 5), and the coupling capacitance Cgs formed with the gate line 2 can be reduced, thereby improving the charging rate.

[0115] In a possible embodiment, referring to Figures 1A-1E and 2A-2E, the first sub-data portion 301 of two adjacent second data portions 32 forms a groove Q with the first data portion 31 between the two adjacent second data portions 32; at least a portion of the positive projection of the first common electrode 65 on the substrate 1 is located within the positive projection of the groove Q on the substrate 1.

[0116] In one possible embodiment, referring to Figures 1A-1E , the orthographic projection of the first data portion 31 on the substrate 1 is located between the orthographic projections of two adjacent pixel electrodes 4 on the substrate 1 in the first direction Y. The orthographic projection of the second data portion 32 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1. Optionally, the orthographic projection of the first data portion 31 on the substrate 1 does not overlap with the orthographic projection of the gate line 2 on the substrate 1.

[0117] Optionally, the data line 3 at a position corresponding to the pixel electrode 4 may be used as the first data portion 31 , and the data line 3 at a position corresponding to the gap between two adjacent rows of pixel electrodes 4 may be used as the second data portion 32 .

[0118] In one possible embodiment, as shown in Figures 1A and 1D, the orthographic projection of the first data part 31 and / or the second data part 32 on the substrate 1 does not overlap with the orthographic projection of the pixel electrode 4 on the substrate 1, which can reduce the coupling capacitance between the data line 3 and the pixel electrode 4, effectively improving the crosstalk caused by the coupling capacitance between the data line 3 and the pixel electrode 4; at the same time, it reduces the overall load of the data line 3, effectively improving the charging bottleneck problem of the three-gate pixel driving structure.

[0119] In a possible implementation, referring to FIG. 1A to FIG. 1E , a length f1 of the first data portion 31 in the second direction Y is less than or equal to a maximum length f2 of the pixel electrode 4 in the second direction Y.

[0120] In one possible embodiment, referring to FIG. 1A to FIG. 1E and FIG. 1F , FIG. 1F is an enlarged schematic diagram of the transistor T in FIG. 1A , the array substrate further includes: a plurality of transistors T; at least one of the plurality of transistors T includes: a control electrode TA, an active pattern 50, and a first electrode TC1, a second electrode TC2, and a third electrode TC3 sequentially distributed along a first direction X; orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the control electrode TA on the substrate 1; and orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the active pattern 50 on the substrate 1.

[0121] The first stage TC1 multiplexes the second sub-data portion 302; the third stage TC3 multiplexes the third sub-data portion 303;

[0122] The second pole TC2 includes: a second pole first portion TC21 extending along the second direction Y, and a second pole overlapping portion TC2D connected to one end of the second pole first portion TC21; the part of the orthographic projection of the second pole first portion TC21 on the substrate 1 is located between the orthographic projections of the second sub-data portion 302 and the third sub-data portion 303 on the substrate 1.

[0123] In the embodiment of the present disclosure, the transistor T includes: a first electrode TC1, a second electrode TC2, and a third electrode TC3. The dual-source design can reduce the second electrode TC of the transistor T and the structure electrically connected to the second electrode TC (such as the pixel electrode 4, the active pattern 50), and the coupling capacitance Cgs formed with the gate line 2 under the condition that the width (W value) of the same transistor T is constant, thereby improving the charging rate.

[0124] In a possible embodiment, referring to FIG1A to FIG1E , the length f3 of the second electrode overlap portion TC2D in the second direction Y is substantially equal to the length f1 of the first data portion 31 in the second direction Y. In the embodiment of the present disclosure, by setting the second overlap portion TC2D longer in the second direction Y, the storage capacitance Cst formed between the pixel electrode 4 and the common electrode layer of the opposing substrate can be increased (because the second overlap portion TC2D is electrically connected to the pixel electrode 4 through a transistor, the second overlap portion TC2D can be used as a structure integrated with the pixel electrode 4). Without affecting the aperture ratio, increasing the storage capacitance Cst formed between the pixel electrode 4 and the common electrode layer of the opposing substrate can effectively improve crosstalk, afterimages, leakage caused by frequency conversion (leakage is more serious at low frequencies), vertical lines caused by the polarity reversal of the chip on flex (COF), and other display defects.

[0125] In a possible implementation, referring to FIG. 1A to FIG. 1E , a width f4 of the second pole overlapping portion TC2D in the first direction X is greater than a width f5 of the second pole first portion TC21 in the first direction X.

[0126] In a possible implementation, as shown in FIG. 1A , the orthographic projection of the second electrode overlapping portion TC2D on the substrate 1 may overlap with the orthographic projection of the pixel electrode 4 on the substrate 1 .

[0127] In one possible embodiment, as shown in conjunction with FIG. 1A and FIG. 1E , the pixel electrode 4 includes: a pixel electrode body PA; and a pixel electrode lap portion PB extending from one side of the pixel electrode body PA along a first direction X. The orthographic projection of the pixel electrode lap portion PB on the substrate 1 overlaps with the orthographic projection of the second electrode lap portion TC2D on the substrate 1. In this way, the pixel electrode lap portion PB and the second electrode lap portion TC2D can be connected by drilling at the overlapping portion, further achieving electrical connection between the transistor T and the pixel electrode 4.

[0128] In one possible embodiment, as shown in Figures 1A to 1E and Figures 2A to 2E, the pixel electrode overlap portion PB and the second electrode overlap portion TC2D may be electrically connected at their intersection via a first via K1. The two first vias K1 corresponding to two adjacent pixel electrodes 4 connected to the same data line 3 via the transistor T are located on different sides of the data line 3. For example, as shown in Figure 1A, the first via K1 corresponding to the pixel electrode 4 in the second column and first row connected to the left data line 3 is located on the right side of the data line 3, and the first via K1 corresponding to the pixel electrode 4 in the first column and second row connected to the left data line 3 (only a portion of the pixel electrode 4 is shown in Figure 1A) is located on the left side of the data line 3. In the embodiment of the present disclosure, the pixel electrode 4 is provided with a pixel electrode overlap portion PB, the data line 3 is provided with a first data portion 31 and a U-shaped second data line portion 32, and the transistor T reuses the U-shaped second data line portion 32, so that the various structural patterns of the display panel are closely matched, and the transistor has a dual-source design, which improves the charging rate while also enabling the display panel to have a high transmittance.

[0129] In a possible implementation, as shown in FIG. 1E , the orthographic projection of the second electrode overlapping portion TC2D on the substrate 1 may cover the orthographic projection of the pixel electrode overlapping portion PB on the substrate 1 .

[0130] In one possible embodiment, in combination with Figures 1A to 1E and Figures 2A to 2E, at least a portion of the orthographic projection of the pixel electrode overlapping portion PB on the substrate 1 may be located within the orthographic projection of the first groove Q on the substrate 1. In one possible embodiment, in combination with Figures 1A to 1E and Figures 2A to 2E, the orthographic projection of the first common electrode 65 on the substrate 1 may cover the orthographic projection of the pixel electrode overlapping portion PB on the substrate 1. In one possible embodiment, in combination with Figures 1A to 1E and Figures 2A to 2E, the minimum length e6 of the first common electrode 65 in the second direction Y may be greater than the maximum length e7 of the pixel electrode overlapping portion PB in the second direction Y; in one possible embodiment, in combination with Figures 1A to 1E and Figures 2A to 2E, the minimum length e3 of the first common electrode 65 in the first direction X may be greater than the maximum length e8 of the pixel electrode overlapping portion PB in the first direction X.

[0131] 1A and 1F , the control electrode TA of the transistor T can reuse the gate line 2. Specifically, the first electrode TC1 and the third electrode TC3 can serve as the source of the transistor T, and the second electrode TC2 can serve as the drain of the transistor T.

[0132] In a possible embodiment, referring to Figures 1A to 1F and Figures 2A to 2E, the array substrate further includes: a third common trace 63 extending along the first direction X; the third common trace 63 is disconnected at the position where it intersects with the data line 3; and the third common trace 63 passes through the center of the third gate line portion 33. In the embodiment of the present disclosure, the array substrate further includes: a third common trace 63 extending along the first direction X, which can prevent cross-color between sub-pixels of different colors in the second direction Y. Moreover, when the gate line 2 crosses two pixel electrodes 4 in the second direction Y and passes through the gap between the two pixel electrodes 4, the signal electric field of the gate line 2 may affect the steering of the liquid crystal because there is no driving electric field of the pixel electrode 4. At this time, the third common trace 63 can be used for light shielding, without the need for black matrix light shielding, thereby greatly improving the aperture ratio and transmittance.

[0133] In a possible implementation, in order to prevent the signal electric field of the gate line 2 from affecting the direction of the liquid crystal, a metal layer other than the layer where the floating data line 3 is located may be used for light shielding.

[0134] In one possible embodiment, as shown in Figures 1A and 1B , the orthographic projection of the third common line 63 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a third storage capacitor is formed by the third common line 63 and the pixel electrode 4.

[0135] In a possible implementation, referring to FIG. 1A to FIG. 1F and FIG. 2A to FIG. 2E , the third common trace 63 may be made of the same layer and material as the data line 3 .

[0136] In one possible embodiment, as shown in Figures 1A-1F and 2A-2E, the array substrate further includes: a fourth common routing line 64 extending along the second direction Y; the orthographic projection of the fourth common routing line 64 on the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 4 on the substrate 1; and multiple third common routing lines 63 between two adjacent data lines 3 are all connected to the fourth common routing line 64. The third common routing lines 63 and the fourth common routing lines 64 can form a mesh structure as a whole, thereby improving the uniformity of the common signal of the display panel.

[0137] In a possible implementation, the fourth common line 64 may be made of the same layer and material as the data line 3 .

[0138] In one possible implementation, the third common trace 63 and / or the fourth common trace 64 can be electrically connected to the first common trace 61 in a peripheral area outside the display area. Specifically, the two can be electrically connected by punching holes. In this way, the first common trace 61, the second common trace 62, the third common trace 63, and the fourth common trace 64 can form an integrated connection structure, all of which transmit common signals.

[0139] Specifically, as shown in Figure 7, the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, which is used to drive the deflection of the liquid crystal; the second electrode TC of the transistor T and the structure electrically connected to the second electrode TC (such as the pixel electrode 4, the active pattern 50) and the gate line 2 can form a coupling capacitor Cgs, and Clc can be the capacitance generated by the liquid crystal between the array substrate and the opposite substrate, which is used to drive the deflection of the liquid crystal.

[0140] In a possible implementation, as shown in FIG5 , the plurality of pixel electrodes 4 include: pixel electrode rows 410 extending along a first direction X, and pixel electrode columns 420 extending along a second direction;

[0141] The pixel electrodes 4 of the same pixel electrode row 410 emit light with the same wavelength range;

[0142] The pixel electrode array 420 includes a plurality of pixel electrode groups 400 sequentially distributed along the second direction Y. The pixel electrode groups 400 include a first pixel electrode 41, a second pixel electrode 42, and a third pixel electrode 43 sequentially distributed along the second direction Y. The first pixel electrode 41 emits a greater wavelength range of light than the second pixel electrode 42, and the second pixel electrode 42 emits a greater wavelength range of light than the third pixel electrode 43. Specifically, the first pixel electrode 41 may emit red light, the second pixel electrode 42 may emit green light, and the third pixel electrode 43 may emit blue light.

[0143] In a possible implementation, as shown in FIG. 5 , in a pixel electrode column 420 , two adjacent pixel electrodes 4 are electrically connected to different data lines 3 ; in a pixel electrode row 410 , all pixel electrodes 4 are electrically connected to the same gate line 2 .

[0144] In one possible embodiment, as shown in FIG6 , the array substrate further includes: a color resist layer 7; the color resist layer 7 includes: a first color resist strip 71, a second color resist strip 72, and a third color resist strip 73 extending along a first direction X and sequentially distributed along a second direction Y; the orthographic projection of the first color resist strip 71 on the substrate 1 covers the orthographic projection of the first pixel electrode 41 on the substrate 1; the orthographic projection of the second color resist strip 72 on the substrate 1 covers the orthographic projection of the second pixel electrode 42 on the substrate 1; and the orthographic projection of the third color resist strip 73 on the substrate 1 covers the orthographic projection of the third pixel electrode 43 on the substrate 1. In the embodiment of the present disclosure, the array substrate further includes the color resist layer 7. On the one hand, because the color resist layer is thicker, the distance between the data line 3 and the layer where the pixel electrode 4 is located can be increased, thereby reducing the parasitic capacitance between the data line 3 and the pixel electrode 4; on the other hand, for curved products, when the color resist layer 7 is provided on the array substrate, when the array substrate is bent, the pixel electrode 4 and the color resist layer 7 move simultaneously, thereby avoiding color mixing problems.

[0145] In a possible embodiment, as shown in FIG6 , the color resist layer 7 further has a plurality of color resist openings 70; the orthographic projection of the color resist opening 70 on the substrate 1 at least partially overlaps with the orthographic projection of the intersection area of ​​the gate line 2 and the data line 3 on the substrate 1. The intersection area of ​​the gate line 2 and the data line 3 may also be the area where the transistor T is located. Optionally, the orthographic projection of the color resist opening 70 on the substrate 1 at least partially overlaps with the orthographic projection of the transistor T on the substrate 1. In the embodiment of the present disclosure, the color resist layer 7 at the position of the transistor T is dug up. On the one hand, the color layer width can be directly monitored through the color resist opening 70 here; on the other hand, the conventional array substrate structure (i.e., non-COA structure, i.e., conventional array substrate structure in which the color filter is provided on the opposite substrate) can be reduced. When the cell gap is reduced, the conductive layer on the opposite substrate side is close to the device (such as transistor T) on the array substrate side, causing a similar top gate drive risk.

[0146] In addition, in the embodiment of the present disclosure, the gate line 2 passes through the first parasitic capacitor C of the two pixel electrodes 4. gp 自 and the second parasitic capacitance C gp他 , the first parasitic capacitance C gp自 The effect is on the feed-through voltage of the self-pixel (i.e. the current sub-pixel), and the second parasitic capacitance C gp他 That is, when the signal voltage acting on the gate line 2 changes, the pulling effect on the potential of other pixels (that is, the sub-pixels adjacent to the current sub-pixel) can be effectively reduced by using the color resist layer 7 to be set on the array substrate (COA technology). gp自 and the second parasitic capacitance C gp他 .

[0147] In a possible implementation, the first color resist 71 may be a red color resist, the second color resist 72 may be a green color resist, and the third color resist 73 may be a blue color resist.

[0148] In one possible embodiment, as shown in conjunction with Figures 3 and 4 , a color resist overlapping portion 74 may be provided between adjacent first color resists 71 and second color groups 72, a color resist overlapping portion 74 may be provided between adjacent second color resists 72 and third color groups 73, and a color resist overlapping portion 74 may be provided between adjacent third color resists 73 and first color groups 71. In one possible embodiment, as shown in conjunction with Figure 4 , at least a portion of the orthographic projection of the color resist overlapping portion 74 on the substrate 1 may overlap with at least a portion of the orthographic projection of the gate line 2 on the substrate 1.

[0149] In a possible embodiment, in combination with Figures 3 and 4, the layer where the data line 3 is located can be located on the side of the layer where the gate line 2 is located away from the substrate 1, the layer where the pixel electrode 4 is located can be located on the side of the layer where the data line 3 is located away from the layer where the gate line 2 is located, the active pattern 50 can be located between the layer where the data line 3 is located and the layer where the gate line 2 is located, a gate insulating layer 91 can also be provided between the layer where the gate line 2 is located and the layer where the active pattern 50 is located, a passivation layer 92 can also be provided between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, and a flat layer 93 can also be provided between the passivation layer 92 and the layer where the pixel electrode 4 is located.

[0150] In one possible implementation, the planarization layer 93 may be an organic film layer; in one possible implementation, the passivation layer 92 may be a PVX layer, for example, including a silicon nitride material layer.

[0151] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, the opposite substrate being provided with a common electrode layer.

[0152] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0153] Based on the same inventive concept, referring to FIG8A , an embodiment of the present disclosure further provides a method for driving a display panel, which includes:

[0154] Step S100, controlling the plurality of gate lines to load scanning signals row by row, and controlling the duration of the gate lines loading the scanning signals to be greater than 1H;

[0155] Step S200 : controlling the data lines to load data signals during at least a portion of a period in which the gate lines are loaded with scan signals.

[0156] Since the number of row scan lines in the three-gate pixel driving structure has doubled, and the number of data lines has become one-third of the original number, if a GOA (Gate on Array) driving structure is adopted, the increase in the number of scan lines does not require additional cost of the driving circuit, and the reduction in the number of data lines can reduce the number of driving ICs, thus having a cost advantage; however, compared with the 1G1D structure, the row write time in the three-gate pixel driving structure is reduced to one-third of the original time, which will directly affect the performance of the entire display panel. In the embodiment of the present disclosure, by controlling the duration of the gate line loading the scan signal to be greater than 1H and pre-charging the gate line, the problem of the reduced row write time in the three-gate pixel driving structure affecting the performance of the entire display panel can be improved.

[0157] In a possible implementation, step S100, controlling the gate line to load the scanning signal for a duration greater than 1H, includes:

[0158] The duration of the control gate line loading scan signal is 4H.

[0159] Specifically, as shown in FIG8B , the scan signal may include a first period T1 and a second period T2, wherein the second period T2 is delayed from the first period T1. Specifically, the first period T1 may be a precharge period, which may be 3 hours, and the second period T2 may be 1 hour. Specifically, the data line may be controlled to load a data signal during the second period T2.

[0160] Specifically, H may represent the charging time of one row, which is calculated based on the resolution and refresh rate of the display panel.

[0161] In the disclosed embodiment, the "Z"-shaped routing shape of the gate line 2 will span two sub-pixels, the self-pixel and the other-pixel. When the other-pixel is a pixel in the previous row of the self-pixel, when the signal of the gate line 2 is turned off, there will be a pull-down signal to the other-pixel. At this time, the signal waveform of the gate line 2 is required to be 1H without pre-charge, so that the rising edge and falling edge of the signal of the gate line 2 will act on the other-pixel at the same time, and finally the effects of the pull-up and pull-down will cancel each other out; when the other-pixel is a pixel in the next row of the self-pixel, the signal waveform of the gate line 2 can be an nH signal with pre-charge, for example, referring to Figure 8B, pre-charged for 3H, when the signal of the gate line 2 is turned off, the other-pixel will continue to charge and will not be affected by the change in the signal waveform of the gate line 2. Therefore, the "Z"-shaped routing shape of the signal of the gate line 2 of this structure that spans other pixels is the best for driving pixels in the next row.

[0162] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0163] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction; a plurality of data lines located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction, at least one of the plurality of data lines comprising: first data portions and second data portions alternately distributed along the second direction; in the second direction, extensions of two first data portions on either side of the second data portion do not overlap; a plurality of pixel electrodes, wherein a maximum length of the pixel electrodes in the first direction is greater than a maximum length in the second direction; and an orthographic projection of the plurality of pixel electrodes on the substrate overlaps at least partially with an orthographic projection of the gate line on the substrate; A plurality of first common electrodes extend along the second direction and are disconnected at positions intersecting the gate lines. The orthographic projections of the first common electrodes on the substrate at least partially cover the gaps between the data lines and the pixel electrodes.

2. The array substrate according to claim 1, wherein: The array substrate further includes: a first common line extending along the first direction; the orthographic projection of the first common line on the substrate passes through a central area of ​​the orthographic projection of the pixel electrode on the substrate; The first common electrode is connected to the first common wiring.

3. The array substrate according to claim 1 or 2, wherein: The array substrate includes: a second common routing group extending along the second direction; the second common routing group is disconnected at a position intersecting the gate line; the second common routing group includes: a first sub-common routing group and a second sub-common routing group arranged along the first direction, wherein the length of the first sub-common routing group in the second direction is less than the length of the second sub-common routing group in the second direction, and the first sub-common routing group and the second sub-common routing group are alternately arranged in the second direction; The array substrate further includes: a common compensation portion connected to a side of the first sub-common wiring away from the second sub-common wiring; and the first common electrode includes the first sub-common wiring and the common compensation portion.

4. The array substrate according to claim 3, wherein: A side of the first common electrode facing the second sub-common wiring has a fifth outer edge extending along the second direction; and extension lines of the fifth outer edges of two adjacent first common electrodes in the second direction do not overlap.

5. The array substrate according to any one of claims 1 to 4, wherein: The first common electrode includes: a wiring body, and a wiring protrusion extending from at least one side of the wiring body along the second direction; The orthographic projection of the routing protrusion on the substrate does not overlap with the orthographic projection of the data line on the substrate.

6. The array substrate according to any one of claims 1 to 5, wherein: The orthographic projection of the first common electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode on the substrate.

7. The array substrate according to any one of claims 1 to 5, wherein: The maximum length of the first common electrode in the second direction is smaller than the minimum distance between two adjacent gate lines in the second direction; A width of the first common electrode in the first direction is greater than a width of the second sub-common wiring in the first direction.

8. The array substrate according to any one of claims 1 to 7, wherein: At least one of the plurality of gate lines includes a plurality of gate line groups sequentially distributed along a first direction; the gate line group includes: a first gate line portion extending along the first direction and sequentially distributed, a second gate line portion, and a third gate line portion located between the first gate line portion and the second gate line portion and connecting the first gate line portion and the second gate line portion; an extension line of the first gate line portion does not overlap with an extension line of the second gate line portion, and an extension direction of the third gate line portion intersects the first direction; The orthographic projections of the plurality of pixel electrodes on the substrate at least partially overlap with the orthographic projections of the first gate line portion and the second gate line portion on the substrate.

9. The array substrate according to claim 8, wherein: The third gate line portion extends along the third direction, and the third direction intersects the first direction and the second direction.

10. The array substrate according to claim 8 or 9, wherein: The length of the gate line group in the first direction is substantially equal to the length of the pixel electrode in the first direction.

11. The array substrate according to claim 10, wherein: A length of the first gate line portion in the first direction is less than or equal to a maximum length of the second gate line portion in the first direction.

12. The array substrate according to any one of claims 1 to 11, wherein: The gate line further includes a gate line connecting portion located between adjacent gate line groups and connecting adjacent gate line groups; the gate line connecting portion extends along the first direction, and an extension line is located between the first gate line portion and the second gate line portion.

13. The array substrate according to any one of claims 1 to 12, wherein: In the same gate line group, the orthographic projection of the first gate line portion on the substrate is covered by the orthographic projection of a pixel electrode on the substrate, and the orthographic projection of the second gate line portion on the substrate is covered by the orthographic projection of another adjacent pixel electrode in the second direction on the substrate.

14. The array substrate according to any one of claims 1 to 7, wherein: The orthographic projection of the gate line on the substrate is a straight line.

15. The array substrate according to any one of claims 1 to 14, wherein: The second data portion includes: a first sub-data portion, a second sub-data portion, and a third sub-data portion; the first sub-data portion extends along the first direction; the second sub-data portion and the third sub-data portion extend along the second direction and are located on the same side of the first sub-data portion; One end of the first sub-data portion is connected to one end of the second sub-data portion, and the other end is connected to one end of the third sub-data portion and one of the first data portions; the other end of the second sub-data portion is connected to another of the first data portions.

16. The array substrate according to claim 15, wherein: The first sub-data portion of two adjacent second data portions and the first data portion between the two adjacent second data portions form a groove; At least a portion of the first common electrode, in the orthographic projection of the substrate, is located within the orthographic projection of the groove.

17. The array substrate according to claim 15 or 16, wherein: The orthographic projection of the first data portion on the substrate is located in a region between orthographic projections of two adjacent pixel electrodes on the substrate in the first direction; An orthographic projection of the second data portion on the substrate has an overlapping area with an orthographic projection of the gate line on the substrate.

18. The array substrate according to any one of claims 15 to 17, wherein: The array substrate further includes: a plurality of transistors; at least one of the plurality of transistors includes: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the control electrode on the substrate; and orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the active pattern on the substrate; The first stage multiplexes the second sub-data portion; the third stage multiplexes the third sub-data portion; The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the part of the second pole first portion on the orthographic projection of the substrate is located between the second sub-data portion and the third sub-data portion on the orthographic projection of the substrate.

19. The array substrate according to claim 18, wherein: The length of the second pole overlapping portion in the second direction is substantially equal to the length of the first data portion in the second direction.

20. The array substrate according to claim 18 or 19, wherein: The width of the second pole overlapping portion in the first direction is greater than the width of the second pole first portion in the first direction.

21. The array substrate according to any one of claims 1 to 20, wherein: The array substrate further includes: a third common line extending along the first direction; the third common line is disconnected at a position where it intersects with the data line.

22. The array substrate according to claim 21, wherein: The array substrate also includes: a fourth common routing line extending along the second direction; the fourth common routing line is an orthographic projection of the substrate, passing through the central area of ​​the orthographic projection of the pixel electrode on the substrate; and multiple third common routing lines between two adjacent data lines are all connected to the fourth common routing line.

23. A display panel, wherein: The array substrate comprises the array substrate according to any one of claims 1 to 22, further comprising: an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

24. A display device, wherein: Comprising the display panel as claimed in claim 23.

25. A method for driving a display panel as claimed in claim 23, wherein: include: Controlling a plurality of gate lines to load scanning signals row by row, and controlling the gate lines to load the scanning signals for a duration greater than 1H; During at least a portion of a period in which the gate line is loaded with a scan signal, the data line is controlled to be loaded with a data signal.

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