Semiconductor device

Abstract

Provided is a novel semiconductor device. A vertical transistor is provided so as to overlap a capacitive element. The vertical transistor is provided so as to overlap an opening penetrating an insulating layer. A semiconductor layer of the vertical transistor includes a channel formation region extending along a side surface of the insulating layer in the opening. In a plan view, the length of the opening in a first direction is different from the length of the opening in a second direction orthogonal to the first direction.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include DRAM, SRAM, and flash memory.

[0004] Furthermore, as the amount of data handled increases, there is a demand for memory devices with larger storage capacities. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors. In addition, there is a demand for memory devices with improved data write and read speeds.

[0005] International Publication No. 2021 / 053473

[0006] M. Oota et. al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0007] An object of one embodiment of the present invention is to provide a storage device with a large storage capacity. Another object is to provide a storage device with a small occupation area. Another object is to provide a storage device with high storage density. Another object is to provide a storage device with high operation speed. Another object is to provide a storage device with high reliability. Another object is to provide a storage device with low power consumption. Another object is to provide a novel storage device.

[0008] Note that the description of the above-mentioned problems does not preclude the existence of other problems. Those skilled in the art will naturally find other problems from the description in the specification, drawings, claims, etc., and other problems can be extracted from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problems and other problems).

[0009] (1) One aspect of the present invention is a semiconductor device having a first capacitor and a first transistor, the semiconductor device including: a first insulating layer provided on a first conductive layer; a first opening penetrating the first insulating layer and reaching the first conductive layer; a second conductive layer having a region overlapping with the first conductive layer and a region overlapping with a side surface of the first insulating layer in the first opening; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping with the second conductive layer via a portion of the second insulating layer and a region overlapping with a side surface of the first insulating layer via another portion of the second insulating layer; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on an edge layer; a second opening that penetrates the third insulating layer and reaches the third conductive layer; a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, and a channel formation region along a side surface of the third insulating layer in the second opening; a fourth insulating layer provided on the semiconductor layer; and a fifth conductive layer having a region that overlaps with the channel formation region of the transistor via a portion of the fourth insulating layer, wherein the first opening and the second opening have different lengths in a first direction and a second direction perpendicular to the first direction when viewed in a plan view.

[0010] Also, in (1), for example, the second conductive layer functions as one electrode of the first capacitance element, the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of the source electrode or drain electrode of the first transistor, and the fourth conductive layer functions as the other of the source electrode or drain electrode of the first transistor.

[0011] In addition, in (1), the length in the second direction is preferably two to five times the length in the first direction. The first capacitance element and the first transistor preferably have an overlapping region in a plan view.

[0012] (2) Another aspect of the present invention is a semiconductor device including a first capacitor, a first transistor, and a second transistor, the semiconductor device including: a first insulating layer provided on the first conductive layer; a second conductive layer having a region overlapping with the first conductive layer and a region overlapping with a side surface of the first insulating layer; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping with the second conductive layer via a portion of the second insulating layer; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, a channel formation region of the first transistor, and a channel formation region of the second transistor; a fourth insulating layer provided on the semiconductor layer; and a fifth conductive layer having a region overlapping with the channel formation region of the first transistor via a portion of the fourth insulating layer and a channel formation region of the second transistor via another portion of the fourth insulating layer.

[0013] Also, in (2), for example, the second conductive layer functions as one electrode of the first capacitance element, the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of the source electrodes or drain electrodes of each of the first transistor and the second transistor, and the fourth conductive layer functions as the other of the source electrodes or drain electrodes of each of the first transistor and the second transistor.

[0014] In addition, in (2), the first capacitive element preferably has a first region overlapping with the first transistor in a plan view, and a second region overlapping with the second transistor in a plan view.

[0015] In addition, in (1) or (2), the semiconductor layer preferably contains an oxide semiconductor.

[0016] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. Alternatively, a storage device with a small occupation area can be provided. Alternatively, a storage device with a high storage density can be provided. Alternatively, a storage device with a high operating speed can be provided. Alternatively, a storage device with high reliability can be provided. Alternatively, a storage device with low power consumption can be provided. Alternatively, a novel storage device can be provided.

[0017] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art will naturally find the other effects from the description in the specification, drawings, claims, etc., and it is possible to extract the other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0018] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a perspective view showing an example of a semiconductor device. FIGS. 1C and 1D are cross-sectional views showing an example of a semiconductor device. FIG. 1E is an equivalent circuit diagram of a semiconductor device. FIG. 2A is a plan view showing an example of a semiconductor device. FIG. 2B is a perspective view showing an example of a semiconductor device. FIGS. 2C and 2D are cross-sectional views showing an example of a semiconductor device. FIG. 2E is an equivalent circuit diagram of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIG. 3B is a perspective view showing an example of a semiconductor device. FIGS. 3C and 3D are cross-sectional views showing an example of a semiconductor device. FIG. 3E is an equivalent circuit diagram of a semiconductor device. FIG. 4A is a plan view showing an example of a semiconductor device. FIG. 4B is a perspective view showing an example of a semiconductor device. FIGS. 4C and 4D are cross-sectional views showing an example of a semiconductor device. FIG. 4E is an equivalent circuit diagram of a semiconductor device. FIGS. 5A1, 5B1, and 5C1 are plan views showing an example of a semiconductor device. FIGS. 5A2, 5B2, and 5C2 are perspective views showing an example of a semiconductor device. FIG. 6A is a plan view showing an example of a semiconductor device. FIG. 6B is a cross-sectional view showing an example of a semiconductor device. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIG. 8A is a plan view showing an example of a semiconductor device. FIG. 8B is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10F are views showing examples of planar shapes of openings. FIG. 11 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 12A and 12B are views showing an example of a configuration of a memory cell. FIGS. 13A and 13B are views showing an example of a configuration of a memory cell. FIGS. 14A to 14G are views showing an example of a circuit configuration of a memory cell. FIGS. 15A and 15B are perspective views showing an example of a configuration of a semiconductor device. FIG. 16 is a block diagram illustrating a CPU. FIGS. 17A and 17B are perspective views of a semiconductor device. FIGS. 18A and 18B are perspective views of a semiconductor device. FIG. 19 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 20A and 20B are views showing an example of a configuration of an electronic component. FIGS. 21A to 21C are views showing an example of a configuration of a mainframe computer. Fig. 22A is a diagram illustrating an example of the configuration of a space equipment, and Fig. 22B is a diagram illustrating an example of the configuration of a storage system.

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0020] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0021] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0022] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in plan views, perspective views, etc.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0024] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0025] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0026] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0027] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0029] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0030] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0031] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0032] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0033] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0034] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0035] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0036] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0037] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0038] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0039] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) n-type transistors.

[0040] In addition, in drawings and the like, to clearly show the potential of wirings, electrodes, etc., "H" indicating a potential H or "L" indicating a potential L may be added adjacent to the wirings, electrodes, etc. Furthermore, "H" or "L" may be enclosed in a box next to wirings, electrodes, etc. where a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0041] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0042] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0043] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. Furthermore, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element," and the other electrode may be referred to as a "second terminal of the capacitance element."

[0044] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0045] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0046] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0047] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0048] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0049] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to one embodiment of the present invention can be used for, for example, a memory cell.

[0050] <Configuration Example of Semiconductor Device> FIG. 1A is a plan view of a semiconductor device 10A according to one embodiment of the present invention. FIG. 1B is a perspective view of the semiconductor device 10A. FIG. 1C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 1A. FIG. 1D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 1A. FIG. 1E is an equivalent circuit diagram of the semiconductor device 10A. Note that in order to facilitate understanding of the configuration of the semiconductor device 10A, some components are omitted from perspective views, plan views, and the like.

[0051] As shown in the circuit diagram of FIG. 1E, the semiconductor device 10A includes a capacitor 110 and a transistor 120. One electrode of the capacitor 110 is connected to a wiring PL, and the other electrode of the capacitor 110 is connected to one of the source and drain of the transistor 120. The other of the source and drain of the transistor 120 is connected to a wiring BL. The gate of the transistor 120 is connected to a wiring WL. The wiring PL functions as a power supply line and has a function of supplying a fixed potential to one electrode of the capacitor 110. The wiring BL functions as a bit line. The wiring WL functions as a word line.

[0052] A specific configuration example of the semiconductor device 10A will be described. The semiconductor device 10A has a conductive layer 102 on an insulating layer 101. The conductive layer 102 functions as wiring PL. An insulating layer 103 is also provided on the conductive layer 102. An opening 104 that penetrates the insulating layer 103 and reaches the conductive layer 102 is provided in a region overlapping with the conductive layer 102. Note that in the semiconductor device 10A shown in this embodiment, the planar shape of the opening 104 (the shape as viewed from the Z direction) is an oval shape including straight and curved portions, but it is also possible for the opening 104 to have an oval shape (ellipse) that does not include straight portions. Furthermore, the shape of the opening 104 can be other than an oval. For example, it can be a polygon.

[0053] A conductive layer 105 is provided to cover the inner wall of the opening 104. The conductive layer 105 has a region that connects to the conductive layer 102 in the opening 104. The conductive layer 105 also has a region that overlaps with a side surface of the insulating layer 103 in the opening 104. The conductive layer 105 also has a region that extends on the insulating layer 103 in a direction perpendicular to the Z direction (e.g., the Y direction).

[0054] The semiconductor device 10A also has an insulating layer 106 on the insulating layer 103 and the conductive layer 105. The semiconductor device 10A also has a conductive layer 107 on the insulating layer 106, including a region that overlaps with the opening 104. The conductive layer 107 has a region that overlaps with the conductive layer 105 inside the opening 104, with the insulating layer 106 interposed therebetween. The conductive layer 107 also has a region that overlaps with a side surface of the insulating layer 103, with the insulating layer 106 and the conductive layer 105 interposed therebetween. The conductive layer 107 also has a region that overlaps with the conductive layer 102, with the insulating layer 106 and the conductive layer 105 interposed therebetween.

[0055] A region where the conductive layer 105 and the conductive layer 107 overlap with each other with the insulating layer 106 interposed therebetween functions as a capacitor 110. The conductive layer 105 functions as one electrode of the capacitor 110. The conductive layer 107 functions as the other electrode of the capacitor 110. The capacitor 110 included in the semiconductor device 10A according to one embodiment of the present invention has a region that extends along the side surface of the insulating layer 103 in the opening 104. Therefore, the capacitance per unit occupied area of ​​the capacitor 110 is large. Furthermore, the capacitance of the capacitor 110 can be increased or decreased by adjusting the thickness of the insulating layer 103. That is, the capacitance per unit occupied area can be easily adjusted.

[0056] A capacitor whose capacitance can be adjusted mainly by the thickness of the insulating layer 103, such as the capacitor 110 included in the semiconductor device 10A according to one embodiment of the present invention, is also called a "vertical capacitor" or "VC (Vertical Capacitor)."

[0057] The semiconductor device 10A also has conductive layers 109a and 109b on the insulating layer 106 and the conductive layer 107. In this specification and the like, the conductive layers 109a and 109b may be collectively referred to as the conductive layer 109. The semiconductor device 10A also has an opening 111 that penetrates the insulating layer 108 and reaches the conductive layer 107 in a region overlapping the conductive layer 107. As shown in FIG. 1C , in the cross-sectional structure viewed from the Y direction, the opening 111 can be said to penetrate not only the insulating layer 108 but also the conductive layer 109. In the semiconductor device 10A shown in this embodiment, the shape of the opening 111 viewed from the Z direction is oval, but the shape of the opening 111 can also be other than oval.

[0058] A semiconductor layer 112 is provided to cover the inner wall of the opening 111. The semiconductor layer 112 has a region that runs along the inside of the opening 111. The semiconductor layer 112 also has a region that connects to the conductive layer 107 in the opening 111. The semiconductor layer 112 also has a region that overlaps with the side surface of the insulating layer 108 in the opening 111. The semiconductor layer 112 also has a region that contacts the side surface of the conductive layer 109 in the opening 111. The semiconductor layer 112 also has a region that extends in the X direction on the conductive layer 109 and a region that extends in the Y direction on the insulating layer 108.

[0059] The semiconductor device 10A also has an insulating layer 113 on the insulating layer 108 and the conductive layer 109. The semiconductor device 10A also has a conductive layer 114 on the insulating layer 113, including a region overlapping with the opening 111. The conductive layer 114 has a region inside the opening 111 that overlaps with the semiconductor layer 112 via the insulating layer 113. The conductive layer 114 also has a region that overlaps with a side surface of the insulating layer 108 via the insulating layer 113 and the semiconductor layer 112. The conductive layer 114 also has a region that overlaps with the conductive layer 107 via the insulating layer 113 and the semiconductor layer 112.

[0060] In addition, an insulating layer 115 is provided over the conductive layer 114 and the insulating layer 113 .

[0061] The conductive layer 107 functions as one of a source electrode and a drain electrode of the transistor 120. The conductive layer 109 functions as the other of the source electrode and the drain electrode of the transistor 120. The insulating layer 113 functions as a gate insulating layer of the transistor 120. The conductive layer 114 functions as a gate electrode of the transistor 120.

[0062] An OS transistor (a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed) is preferably used as the transistor 120. An oxide semiconductor has a band gap of 2 eV or more and therefore has an extremely small off-state current.

[0063] The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1yA (1 x 10 −２４Note that the off-state current value of a Si transistor (a transistor including silicon in a semiconductor layer in which a channel is formed) per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) More than 1pA (1×10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0064] By using an OS transistor as the transistor 120, charge written to the capacitor 110 can be held for a long period of time. By using an OS transistor as the transistor 120, an operation of rewriting data at a predetermined cycle (refresh operation) is unnecessary. Alternatively, the frequency of the refresh operation can be significantly reduced. Therefore, the power consumption of the semiconductor device 10A functioning as a memory cell can be reduced.

[0065] In this specification and the like, a memory cell using an OS transistor or a storage device using an OS transistor is also referred to as an "OS memory".

[0066] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A semiconductor device including an OS transistor has stable operation and high reliability even in a high-temperature environment.

[0067] In addition, an OS transistor has a high withstand voltage between the source and the drain. By using an OS transistor as a transistor included in a semiconductor device, the operation is stable even when the transistor size is reduced, and a highly reliable semiconductor device can be realized.

[0068] The transistor 120 included in the semiconductor device 10A according to one embodiment of the present invention is a transistor in which a source electrode and a drain electrode are spaced apart in the Z direction. That is, the source and drain of the transistor 120 are located at different heights. Such a transistor is also referred to as a "vertical channel transistor," a "vertical channel transistor," a "vertical transistor," or a "Vertical Field Effect Transistor (VFET)."

[0069] Here, a configuration example of the transistor 120 which is a vertical transistor and a configuration example of the capacitor 110 which is a vertical capacitor will be described in more detail.

[0070] <Vertical Transistor> Fig. 6A is a plan view of a transistor 120 that can be used in a semiconductor device 10A according to one embodiment of the present invention. Fig. 6B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 6A. Note that Fig. 6A illustrates a case in which the shape of the opening 111 is circular when viewed from the Z direction.

[0071] As described above, the conductive layer 107 functions as one of the source electrode and the drain electrode of the transistor 120, and the conductive layer 109 functions as the other of the source electrode and the drain electrode of the transistor 120. A region of the semiconductor layer 112 in contact with the conductive layer 107 functions as one of the source region and the drain region of the transistor 120, and a region of the semiconductor layer 112 in contact with the conductive layer 109 functions as the other of the source region and the drain region of the transistor 120.

[0072] Furthermore, a region of the semiconductor layer 112 along the side surface of the insulating layer 108 functions as a channel formation region. Therefore, the length from the conductive layer 107 to the conductive layer 109 on the side surface of the insulating layer 108 is the channel length L of the transistor 120 (see FIG. 6B ). That is, the channel length L of the transistor 120, which is a vertical transistor, is determined by the thickness ta of the insulating layer 108. Note that in this specification, the insulating layer 108 may be referred to as a spacer layer.

[0073] Furthermore, the channel formation region of the semiconductor layer 112 is formed in a cylindrical shape along the side surface of the insulating layer 108 within the opening 111. Therefore, the perimeter of the opening 111 as viewed from the Z direction corresponds to the channel width W of the transistor 120 (see FIG. 6A ). If necessary, the perimeter of any position of the opening 111 can be set to the channel width W. For example, the perimeter of the bottom of the opening can be set to the channel width W, or the perimeter of the top of the opening 111 can be set to the channel width W. Furthermore, for example, the perimeter of the opening 111 can be set to a position halfway through the thickness ta of the insulating layer 108. Although the planar shape of the opening 111 is shown as a circle in FIG. 6A , this is not limiting. For example, the planar shape of the opening 111 as viewed from the Z direction can be an oval, a polygon, or the like.

[0074] 7A , the side surface of the opening 111 preferably has a slope. The slope of the side surface of the opening 111 can improve the coverage of the semiconductor layer 112, the insulating layer 113, and the conductive layer 114, including the region formed inside the opening 111. Specifically, the side surfaces of the insulating layer 108 and the conductive layer 109 exposed by the formation of the opening 111 preferably have a slope. In this specification, the angle between the bottom surface and the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) is referred to as the "taper angle θ."

[0075] By reducing the taper angle θ of each of the insulating layer 108 and the conductive layer 109, the coverage of the semiconductor layer 112, the insulating layer 113, and the conductive layer 114 to be formed later can be improved. That is, the semiconductor layer 112, the insulating layer 113, and the conductive layer 114 can be easily formed on the inner wall of the opening 111. On the other hand, the smaller the taper angle θ, the larger the area occupied by the opening 111. Therefore, the area occupied by the transistor 120 increases, making it difficult to miniaturize and highly integrate the transistor 120. Furthermore, the larger the taper angle θ of each of the insulating layer 108 and the conductive layer 109, the lower the coverage of the semiconductor layer 112, the insulating layer 113, and the conductive layer 114, resulting in a decrease in the manufacturing yield and reliability of the transistor 120. For these reasons, the taper angle θ of each of the side surfaces of the insulating layer 108 and the conductive layer 109 is preferably 45° or greater and less than 90°, and more preferably 50° or greater and 75° or less. The taper angles θ of the side surfaces of the insulating layer 108 and the conductive layer 109 can be the same or different.

[0076] 7B , during the formation of the opening 111, a portion of the conductive layer 107 may be removed depending on the etching conditions for the conductive layer 107 and the insulating layer 108. The bottom of the opening 111 may include a curved portion. When the bottom of the opening 111 has a curved portion, the semiconductor layer 112, the insulating layer 113, and the like provided on the curved portion may also have a curved portion. This reduces electric field concentration on the insulating layer 113 near the curved portion when a voltage is applied to the conductive layer 114, thereby improving the withstand voltage of the transistor 120 and suppressing electrostatic breakdown of the transistor 120. Therefore, the reliability of the semiconductor device can be improved. Furthermore, when viewed in a direction perpendicular to the Z direction (e.g., the Y direction), the conductive layer 114, which functions as the gate electrode of the transistor 120, and the conductive layer 107, which functions as one of the source and drain electrodes of the transistor 120, preferably have a region where they overlap with each other. In this manner, an electric field can be applied from the conductive layer 114 to the entire semiconductor layer 112 that overlaps with the insulating layer 108, which can improve the electrical characteristics of the transistor 120. For example, the on-state current of the transistor 120 can be increased.

[0077] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0078] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 108. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0079] <Vertical Capacitor> Fig. 8A is a plan view of a capacitor 110 that can be used in a semiconductor device 10A according to one embodiment of the present invention. Fig. 8B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 8A. Note that Fig. 8A illustrates a case in which the shape of the opening 104 is circular when viewed from the Z direction.

[0080] As described above, the conductive layer 105 functions as one electrode of the capacitor 110, and the conductive layer 107 functions as the other of the source electrode and the drain electrode of the capacitor 110. A region where the conductive layer 105 and the conductive layer 107 overlap with each other with the insulating layer 106 interposed therebetween functions as the capacitor 110.

[0081] The capacitance of the capacitance element 110 is determined by the relative dielectric constant of the insulating layer 106, the area where the conductive layers 105 and 107 overlap, and the distance over which the conductive layers 105 and 107 face each other. That is, in this embodiment, the capacitance is determined by the sum of the area where the conductive layers 105 and 107 overlap at the bottom of the opening 104, the area where the conductive layers 105 and 107 overlap on the insulating layer 103, and the area where the conductive layers 105 and 107 overlap along the side surfaces of the insulating layer 103.

[0082] Furthermore, the capacitance of the capacitive element 110, which is a vertical capacitive element, can be determined mainly by the area where the conductive layers 105 and 107 overlap along the side surface of the insulating layer 103. In other words, it can be determined by the product of the thickness tb of the insulating layer 103 and the perimeter (length Wc) of the opening 104 when viewed from the Z direction.

[0083] If necessary, the perimeter of any position of the opening 111 can be set to length Wc. For example, the perimeter of the bottom of the opening 104 can be set to length Wc, or the perimeter of the top of the opening 104 can be set to length Wc. Furthermore, for example, the perimeter of the opening 104 can be set to a position halfway through the thickness tb of the insulating layer 103. Although the planar shape of the opening 104 is shown as a circle in FIG. 8A , this is not limiting. For example, the planar shape of the opening 104 can be an oval, a polygon, or the like.

[0084] Furthermore, similar to the opening 111, in order to improve the coverage of the conductive layer 105 and the insulating layer 106, it is preferable that the taper angle θ (not shown) of the side surface of the opening 104 be 45° or more and 90° or less, and more preferably 50° or more and 75° or less.

[0085] 9A , when the opening 104 is formed, a portion of the conductive layer 102 may be removed depending on the etching conditions for the insulating layer 103. The bottom of the opening 104 may include a curved portion. Removing a portion of the conductive layer 102 increases the area of ​​the region of the capacitor 110 corresponding to the bottom of the opening 104, thereby increasing the capacitance of the capacitor 110. Including a curved portion in the bottom of the opening 104 increases the area of ​​the region of the capacitor 110 corresponding to the bottom of the opening 104, thereby increasing the capacitance of the capacitor 110.

[0086] 9B , the capacitor element 110 can be configured as shown in FIG. 9B . In FIG. 9B , the end 121 of the conductive layer 105 is located lower than the upper surface of the insulating layer 103. This makes it possible to suppress electric field concentration in the insulating layer 106 near the end 121, compared to when the end 121 is located on the insulating layer 103. By suppressing the electric field concentration in the insulating layer 106, dielectric breakdown of the insulating layer 106 can be suppressed, and a highly reliable semiconductor device can be provided.

[0087] 9B shows an example in which region 122 between the upper surface of insulating layer 103 and the side surface of opening 104 has a curved portion. Region 122 having a curved portion can suppress electric field concentration in insulating layer 106 near region 122. Suppressing electric field concentration in insulating layer 106 suppresses dielectric breakdown of insulating layer 106, making it possible to provide a highly reliable semiconductor device.

[0088] <Planar Shape of Openings and Number of Openings> As described above, increasing the circumferential length of the opening 111 can increase the on-current of the transistor 120. Furthermore, increasing the circumferential length of the opening 104 can increase the capacitance of the capacitor 110. For example, if the planar shape of the opening 111 or the opening 104 viewed from the Z direction is circular and its diameter is 60 nm, the circumference is 188.5 nm. As shown in FIG. 1A , making the opening 111 an oval that is elongated in the Y direction can increase the on-current of the transistor 120. Furthermore, making the opening 104 an oval that is elongated in the Y direction can increase the capacitance of the capacitor 110.

[0089] Increasing the on-state current of the transistor 120 can increase the operating speed of the semiconductor device 10A. Increasing the capacitance of the capacitor 110 can improve the data retention capability of the semiconductor device 10A. Increasing the capacitance of the capacitor 110 can also reduce the influence of parasitic capacitance of the bit line, thereby improving the accuracy of reading retained data. This can improve the reliability of the semiconductor device 10A.

[0090] For example, as shown in FIG. 10A , if the width of an oval is 60 nm and the length is 140 nm, the circumference is 349 nm. Therefore, the circumference can be approximately 1.9 times that of a circle with a diameter of 60 nm. Therefore, the on-state current of the transistor 120 can be increased by approximately 1.9 times. Furthermore, the capacitance of the capacitor 110 can be increased by approximately 1.9 times.

[0091] That is, when the opening 111 is viewed in a plan view (when viewed from the Z direction), the on-current of the transistor 120 can be increased by making the length 151 of the opening 111 in a first direction different from the length 152 of the opening 111 in a second direction perpendicular to the first direction. Here, for example, if the first direction is the X direction, the second direction corresponds to the Y direction. Furthermore, when the shape of the opening 111 viewed in a plan view, i.e., the planar shape of the opening 111, is oval, the length in the first direction corresponds to the length in the direction of the minor axis, and the length in the second direction corresponds to the length in the direction of the major axis. Furthermore, when the planar shape of the opening 111 is rectangular, the length in the first direction corresponds to the direction in which the distance between opposing sides is shorter, and the length in the second direction corresponds to the direction in which the distance is longer.

[0092] Furthermore, by making the length 151 in the first direction and the length 152 in the second direction perpendicular to the first direction different when the opening 104 is seen in a plan view, the capacitance of the capacitive element 110 can be increased. As with the opening 111, when the shape of the opening 104 when seen in a plan view, i.e., the planar shape of the opening 104, is oval, the first direction corresponds to the direction of the minor axis, and the second direction corresponds to the direction of the major axis. Furthermore, when the planar shape of the opening 104 is rectangular, the length in the first direction corresponds to the direction in which the distance between opposing sides is shorter, and the second direction corresponds to the direction in which the distance is longer.

[0093] Even when the planar shapes of the openings 111 and 104 are other than oval and other than rectangular, the lengths in the first direction and the second direction can be determined based on the above concept.

[0094] The length 151 in the first direction and the length 152 in the second direction of the opening 111 can be the length at the top of the opening 111, the length at the bottom of the opening 111, or the length from the top to the bottom of the opening 111. Similarly, the length 151 in the first direction and the length 152 in the second direction of the opening 104 can be the length at the top of the opening 104, the length at the bottom of the opening 104, or the length from the top to the bottom of the opening 104.

[0095] Furthermore, when the length 151 in the first direction is shorter than the length 152 in the second direction, the length 152 in the second direction is preferably 1.5 to 10 times, and more preferably 2 to 5 times, the length 151 in the first direction. By setting the relationship between the length 152 in the second direction and the length 151 in the first direction within the above range, a significant increase in the area occupied by the transistor 120 can be suppressed and the on-current of the transistor 120 can be increased. Furthermore, a significant increase in the area occupied by the capacitor 110 can be suppressed and the capacitance of the capacitor 110 can be increased.

[0096] Next, consider a case where the area occupied by the opening 111 or the opening 104 is fixed at 60 nm × 140 nm. For example, as shown in FIG. 10B , if two openings 111 each having a diameter of 60 nm are provided in a rectangular region of 60 nm × 140 nm, the total perimeter of the two openings is 379 nm, which is longer than that of an ellipse. This further increases the on-state current of the transistor 120. Similarly, if two openings 104 each having a diameter of 60 nm are provided in a rectangular region of 60 nm × 140 nm, the capacitance of the capacitor 110 can be increased compared to that of an ellipse.

[0097] 10C , when ten openings 111 each having a diameter of 24 nm are provided in a rectangular region of 60 nm × 140 nm, the total perimeter of the ten openings is 751 nm. This further increases the on-state current of the transistor 120. Similarly, when ten openings 104 each having a diameter of 24 nm are provided in a rectangular region of 60 nm × 140 nm, the capacitance of the capacitor 110 can be further increased.

[0098] 10D to 10F show the relationship between the number of openings and the total perimeter when the planar shape of openings 111 or openings 104 is a square.

[0099] As shown in Figure 10D, when the opening 111 or opening 104 is a rectangle of 60 nm x 140 nm, the perimeter is 400 nm. Also, as shown in Figure 10E, when two square openings 111 or openings 104 with sides of 60 nm are provided in a rectangular region of 60 nm x 140 nm, the total perimeter of the two openings is 480 nm. Also, as shown in Figure 10F, when ten square openings 111 or openings 104 with sides of 24 nm are provided in a rectangular region of 60 nm x 140 nm, the total perimeter of the ten openings is 960 nm.

[0100] In this way, by dividing the opening 104 into multiple parts, the total perimeter can be increased even with the same occupied area. Therefore, the on-state current of the transistor 120 per unit occupied area can be increased. Similarly, by dividing the opening 104 into multiple parts, the total perimeter can be increased even with the same occupied area. Therefore, the capacitance of the capacitor 110 per unit occupied area can be increased. Therefore, the operating speed, reliability, and the like of the semiconductor device 10A can be improved without increasing the occupied area. Furthermore, the occupied area of ​​the transistor 120 can be reduced without reducing the on-state current of the transistor 120. Furthermore, the occupied area of ​​the capacitor 110 can be reduced without reducing the capacitance of the capacitor 110. Therefore, the memory density of a memory device using the semiconductor device 10A as a memory cell can be increased. Furthermore, the memory capacity of a memory device using the semiconductor device 10A as a memory cell can be increased.

[0101] <Modification 1> A configuration example of a semiconductor device 10B, which is a modification of the semiconductor device 10A, will be described with reference to FIGS. 2A to 2E. FIG. 2A is a plan view of the semiconductor device 10B according to one embodiment of the present invention. FIG. 2B is a perspective view of the semiconductor device 10B. FIG. 2C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 2A. FIG. 2D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 2A. FIG. 2E is an equivalent circuit diagram of the semiconductor device 10B. Note that in order to facilitate understanding of the configuration of the semiconductor device 10B, some components are omitted from perspective views, plan views, and the like.

[0102] The semiconductor device 10B differs from the semiconductor device 10A in that it has two openings 111 and two transistors 120. To reduce repetition of the explanation, the following mainly describes the differences between the semiconductor device 10B and the semiconductor device 10A.

[0103] The semiconductor device 10B has an opening 111[1] that overlaps with a part of the conductive layer 107 and an opening 111[2] that overlaps with another part of the conductive layer 107. The semiconductor device 10B also has a transistor 120[1] and a transistor 120[2].

[0104] In the semiconductor device 10B, the semiconductor layer 112 is provided to cover the opening 111[1] and the opening 111[2]. The semiconductor layer 112 has a region along the inside of the opening 111[1] and a region along the inside of the opening 111[2]. The channel formation region of the transistor 120[1] is formed in the semiconductor layer 112 along the side surface of the insulating layer 108 in the opening 111[1]. The channel formation region of the transistor 120[2] is formed in the semiconductor layer 112 along the side surface of the insulating layer 108 in the opening 111[2].

[0105] The insulating layer 113 is provided to cover the semiconductor layer 112. In the semiconductor device 10B, the insulating layer 113 has a region along the inner side of the opening 111[1] and a region along the inner side of the opening 111[2]. Therefore, a part of the insulating layer 113 functions as a gate insulating layer for the transistor 120[1], and another part functions as a gate insulating layer for the transistor 120[2]. The conductive layer 114 has a region along the inner side of the opening 111[1] and a region along the inner side of the opening 111[2].

[0106] In the semiconductor device 10B, the conductive layer 107 functions as one of the source and drain electrodes of the transistor 120[1] and one of the source and drain electrodes of the transistor 120[2]. In the semiconductor device 10B, the conductive layer 109 functions as the other of the source and drain electrodes of the transistor 120[1] and the other of the source and drain electrodes of the transistor 120[2]. In the semiconductor device 10B, the conductive layer 114 functions as the gate electrode of the transistor 120[1] and the gate electrode of the transistor 120[2].

[0107] 2E, the semiconductor device 10B has a configuration in which the transistor 120[1] and the transistor 120[2] are connected in parallel, and the transistors 120[1] and 120[2] connected in parallel function essentially as a single transistor.

[0108] Vertical transistors are easier to form in parallel than horizontal transistors, and the parallel connection of multiple vertical transistors can be achieved in a smaller area than horizontal transistors.

[0109] As described above, the on-state current of the transistor can be increased without increasing the occupied area by increasing the number of openings 111. The semiconductor device 10B according to one embodiment of the present invention can achieve a higher operating speed than the semiconductor device 10A without increasing the occupied area.

[0110] Note that although this embodiment shows a configuration example of the semiconductor device 10B having two openings 111 on the conductive layer 107, the semiconductor device 10B according to one embodiment of the present invention can have three or more openings 111.

[0111] <Modification 2> A configuration example of a semiconductor device 10C, which is a modification of the semiconductor device 10A, will be described with reference to FIGS. 3A to 3E . FIG. 3A is a plan view of the semiconductor device 10C according to one embodiment of the present invention. FIG. 3B is a perspective view of the semiconductor device 10C. FIG. 3C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 3A . FIG. 3D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 3A . FIG. 3E is an equivalent circuit diagram of the semiconductor device 10C. Note that to facilitate understanding of the configuration of the semiconductor device 10C, some components are omitted from perspective views, plan views, and the like.

[0112] The semiconductor device 10C differs from the semiconductor device 10A in that it has two openings 104. To reduce repetition of the explanation, the following mainly describes the differences between the semiconductor device 10C and the semiconductor device 10A.

[0113] The semiconductor device 10C has an opening 104[1] that overlaps a portion of the conductive layer 102 and an opening 104[2] that overlaps another portion of the conductive layer 102. In the semiconductor device 10C, the conductive layer 105 is provided to cover the openings 104[1] and 104[2]. The conductive layer 105 also has a region along the inside of the opening 104[1] and a region along the inside of the opening 104[2].

[0114] Furthermore, an insulating layer 106 is provided to cover the conductive layer 105. In the semiconductor device 10C, the insulating layer 106 has a region along the inside of the opening 104[1] and a region along the inside of the opening 104[2]. Furthermore, the conductive layer 107 is provided on the insulating layer 106. Furthermore, the conductive layer 107 has a region along the inside of the opening 104[1] and a region along the inside of the opening 104[2].

[0115] In the semiconductor device 10C, if the region inside the opening 104[1] where the conductive layer 105 and the conductive layer 107 overlap each other with the insulating layer 106 interposed therebetween is defined as the capacitance element 110[1], and the region inside the opening 104[2] where the conductive layer 105 and the conductive layer 107 overlap each other with the insulating layer 106 interposed therebetween is defined as the capacitance element 110[2], then the semiconductor device 10C can be said to have a configuration in which the capacitance elements 110[1] and 110[2] are connected in parallel (see FIG. 3E). The capacitance elements 110[1] and 110[2] connected in parallel essentially function as a single capacitance element 110.

[0116] The vertical capacitor element can easily be formed by connecting multiple capacitor elements in parallel. In addition, by increasing the number of openings 104, the area of ​​the region where the conductive layers 105 and 107 overlap can be increased without increasing the occupied area. Therefore, by increasing the number of openings 104, the capacitance of the capacitor element can be increased without increasing the occupied area.

[0117] The semiconductor device 10C according to one embodiment of the present invention can have a higher data retention capability than the semiconductor device 10A without increasing the area occupied by the semiconductor device 10C. Furthermore, the semiconductor device 10C can have a higher data read accuracy than the semiconductor device 10A. Therefore, the semiconductor device 10C can have a higher reliability than the semiconductor device 10A.

[0118] Note that although this embodiment shows a configuration example of the semiconductor device 10C having two openings 104 on the conductive layer 102, the semiconductor device 10C according to one embodiment of the present invention can have three or more openings 104.

[0119] 4A to 4E , a configuration example of a semiconductor device 10D, which is a modification of the semiconductor device 10A, will be described. The semiconductor device 10D has a configuration that combines the semiconductor device 10B and the semiconductor device 10C. Therefore, the semiconductor device 10D is a modification of both the semiconductor device 10B and the semiconductor device 10C.

[0120] Fig. 4A is a plan view of a semiconductor device 10D according to one embodiment of the present invention. Fig. 4B is a perspective view of the semiconductor device 10D. Fig. 4C shows an example of a cross-sectional structure between A1-A2 indicated by a dashed line in Fig. 4A. Fig. 4D shows an example of a cross-sectional structure between A3-A4 indicated by a dashed line in Fig. 4A. Fig. 4E is an equivalent circuit diagram of the semiconductor device 10D. Note that in order to make the configuration of the semiconductor device 10D easier to understand, some components are omitted from perspective views, plan views, etc.

[0121] The semiconductor device 10D differs from the semiconductor devices 10A, 10B, and 10C in that it has two openings 111 and two openings 104. Increasing the number of both the openings 104 and the openings 111 can increase both the on-state current of the transistor 120 and the capacitance of the capacitor 110. The configuration of the semiconductor device 10D can improve the operating speed and reliability without increasing the occupied area.

[0122] As described above, the planar shapes of the openings 104 and 111 are not limited to circular or elliptical. For example, the planar shapes of the openings 104 and 111 may be rectangular (see FIGS. 10D to 10F).

[0123] 5A1 shows a plan view of the semiconductor device 10Ar, and FIG. 5A2 shows a perspective view of the semiconductor device 10Ar. The semiconductor device 10Ar has a configuration in which the planar shapes of the openings 104 and 111 of the semiconductor device 10A are rectangular.

[0124] Fig. 5B1 shows a plan view of the semiconductor device 10Br. Fig. 5B2 shows a perspective view of the semiconductor device 10Br. The semiconductor device 10Br has a configuration in which the planar shapes of the openings 104 and 111 of the semiconductor device 10B are rectangular.

[0125] 5C1 shows a plan view of the semiconductor device 10Dr, and FIG. 5C2 shows a perspective view of the semiconductor device 10Dr. The semiconductor device 10Dr has a configuration in which the planar shapes of the openings 104 and 111 of the semiconductor device 10D are rectangular.

[0126] By making the planar shapes of the openings 104 and 111 rectangular, the on-state current of the transistor 120 and the capacitance of the capacitor 110 can be increased.

[0127] <Constituent Materials of Semiconductor Device> Next, constituent materials that can be used for the semiconductor device 10 according to one embodiment of the present invention (semiconductor device 10A, semiconductor device 10B, semiconductor device 10C, semiconductor device 10D, semiconductor device 10Ar, semiconductor device 10Br, and semiconductor device 10Dr) will be described.

[0128] [Substrate] When the semiconductor device according to one embodiment of the present invention is provided over a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light-transmitting properties and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0129] Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide (also called zinc oxide), or gallium oxide. Furthermore, there is also a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

[0130] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0131] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0132] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, these substrates can be used with elements provided thereon. Elements provided on the substrate include capacitor elements, resistor elements, switch elements, light-emitting elements, memory elements, and the like.

[0133] [Insulating Layer] The insulating layers (insulating layer 101, insulating layer 103, insulating layer 106, insulating layer 108, insulating layer 113, insulating layer 115, etc.) can each use an inorganic insulating film. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film can also be used for the insulating layer of the semiconductor device.

[0134] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0135] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for an insulating layer that functions as a gate insulating layer, such as insulating layer 113, allows for lower voltage during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0136] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0137] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0138] A material capable of exhibiting ferroelectricity can be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include materials obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include materials obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ (X is a real number greater than 0), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, or other piezoelectric ceramics having a perovskite structure can be used.

[0139] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al １−ａ Sc ａ N ｂ(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1. Hereinafter, this may be referred to simply as "AlScN"), Al-Ga-Sc nitride, Ga-Sc nitride, etc. may be used. Ferroelectric materials include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Metal oxides containing element M1 and nitrogen may also be ferroelectric even without element M2. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Since the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitrides may be referred to as Group 13-15 ferroelectrics, Group 13 nitride ferroelectrics, etc.

[0140] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0141] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, etc. may be used.

[0142] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. For example, the insulating layer 106 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0143] Metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Representative examples of metal oxides containing hafnium and zirconium include HfZrO Ｘ Also, HfZrO Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. Ｘ By adding Y (yttrium) to the above, the ferroelectricity can be enhanced.

[0144] In this specification and the like, a material that can have ferroelectricity may be referred to as a "ferroelectric material." A layer of a ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. A device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification and the like.

[0145] It is believed that ferroelectricity is exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. It is also believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals having an orthorhombic crystal structure, as this will exhibit ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0146] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0147] As described above, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even when it is a thin film of a few nanometers, and is therefore preferable for the insulating layer 106. The film thickness of the insulating layer 106 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).

[0148] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 106. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ Even if the area is 1000 nm or less, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the semiconductor device can be reduced.

[0149] A ferroelectric is an insulator that is polarized internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a ferroelectric material can be used as a dielectric to form a nonvolatile memory element. A nonvolatile memory element using a ferroelectric material is sometimes called a "ferroelectric memory."

[0150] The method for forming the insulating layer is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used.

[0151] [Conductive Layer] For the conductive layers (conductive layer 102, conductive layer 105, conductive layer 107, conductive layer 114, etc.), it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy can be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, it is possible to use a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

[0152] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide (also referred to as indium oxide), indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide doped with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0153] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0154] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. Also, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. Also, a stacked structure can be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0155] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112 of the transistor 120, a conductive layer functioning as a gate electrode, such as the conductive layer 114, may have a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the semiconductor layer 112 side. By providing the conductive material containing oxygen on the semiconductor layer 112 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 112.

[0156] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112, the conductive layers 107 and 109 are conductive layers in contact with the semiconductor layer 112. Therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion may be used for the conductive layers 107 and 109. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 107 and 109.

[0157] By using a conductive material containing oxygen for the conductive layers 107 and 109, the conductive layers 107 and 109 can maintain their conductivity even when they absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 107 and 109, this is preferable because the conductive layers 107 and 109 can maintain their conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used for the conductive layers 107 and 109, respectively.

[0158] The method for forming the conductive layer is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0159] [Semiconductor Layer] As the semiconductor layer 112, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Organic materials having semiconductor properties can also be used as compound semiconductors. Metal oxides (also referred to as oxide semiconductors) having semiconductor properties can also be used as compound semiconductors. Impurities can also be added to these semiconductor materials as dopants.

[0160] The semiconductor layer can be made of a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that it is also possible to include impurities as dopants in these semiconductor materials.

[0161] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0162] For example, by using silicon for the semiconductor layer 112 of the transistor 120 and adding phosphorus or arsenic as an n-type dopant to the source and drain regions of the semiconductor layer 112, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to the source and drain regions of the semiconductor layer 112, the transistor can function as a p-type transistor. When the source and drain regions of the semiconductor layer 112 contain both an n-type dopant and a p-type dopant, the conductivity type with a higher dopant concentration is more likely to be realized.

[0163] A two-dimensional material that functions as a semiconductor can be used as the semiconductor layer 112. A two-dimensional material is also called a layered material, and is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0164] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0165] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112, the band gap of the metal oxide is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide that functions as a semiconductor layer and has a band gap larger than that of silicon, the off-state current of the transistor can be significantly reduced. Since an OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced. Note that the metal oxide used for the semiconductor layer will be described in detail in Embodiment 2.

[0166] The method for forming the semiconductor layer is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0167] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0168] In this embodiment, a metal oxide that can be used for a semiconductor layer of a transistor will be described. As the semiconductor layer of a transistor, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in a metal oxide having a stacked structure, the boundaries between stacked layers may be unclear, as will be described later.

[0169] [Metal Oxide] The metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide contains indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0170] Examples of metal oxides include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO). Examples of usable metal oxides include indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide. Gallium oxide, zinc oxide, and the like can also be used.

[0171] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0172] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0173] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0174] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0175] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0176] A structural example of a metal oxide that can increase the field-effect mobility of a transistor will be described. For example, it is preferable to use a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the metal oxide has indium oxide and IGZO on the indium oxide. It is also preferable to use IGZO containing nitrogen as the metal oxide. For example, it is preferable to use IGZO containing nitrogen during or after film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. Furthermore, it is preferable to use at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO as the metal oxide.

[0177] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0178] The metal oxide preferably has crystallinity. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for a semiconductor layer, the density of defect states in the semiconductor layer can be reduced. Therefore, the reliability of a transistor using a metal oxide for a semiconductor layer can be improved. Furthermore, the reliability of a semiconductor device including the transistor can be improved.

[0179] The crystallinity of the metal oxide used in the semiconductor layer is not particularly limited. For example, the semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0180] The crystallinity of the semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques can be used for analysis.

[0181] The metal oxide used in the semiconductor layer preferably has a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation, and the plurality of microcrystals are connected without being oriented in the a-b plane. Furthermore, when a cross section of a metal oxide having a CAAC structure is observed using a high-resolution TEM image (also called a multi-wave interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Therefore, a metal oxide having a CAAC structure can also be said to have a structure having a layered crystal part.

[0182] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface or surface of the metal oxide on which the metal oxide is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal oxide is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal oxide is formed.

[0183] When a metal oxide has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the metal oxide observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the metal oxide is formed.

[0184] When electron diffraction is performed on a metal oxide having a CAAC structure, spots (bright spots) that indicate c-axis orientation are observed in the electron diffraction pattern.

[0185] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0186] A cross-sectional TEM image of a metal oxide having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots that are high in brightness and approximately equal distances from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions where the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90° ± 20°) relative to the surface to be formed, more preferably 75° to 105° (within 90° ± 15°), more preferably 80° to 100° (within 90° ± 10°), and even more preferably 85° to 95° (within 90° ± 5°) can be considered to have a CAAC structure.

[0187] When a metal oxide having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the metal oxide has crystallinity.

[0188] [Composition of Metal Oxide] The metal oxide preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the semiconductor layer, the on-state current of the transistor can be increased, and the frequency characteristics can be improved. For example, it is preferable to use indium oxide for the semiconductor layer.

[0189] The metal oxide may also contain zinc. When the metal oxide contains zinc, it becomes a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used as the semiconductor layer. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn = 2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn = 4:1 [atomic ratio] or a composition close thereto can be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0190] The metal oxide may contain the element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Therefore, the reliability of a transistor using a metal oxide as a semiconductor layer can be improved.

[0191] For example, an In-Zn oxide containing a trace amount of element M can be used as the semiconductor layer. Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof can be used. Also, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used.

[0192] Furthermore, the semiconductor layer can be made of an In—Zn oxide containing element M. Specifically, metal oxides having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:1.2 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:0.5 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:2 (atomic ratio) or a composition close thereto, In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=1:3:2 (atomic ratio) or a composition close thereto, or In:M:Zn=1:3:4 (atomic ratio) or a composition close thereto can be used.

[0193] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0194] Furthermore, when forming a metal oxide containing multiple metal elements, such as In—Ga—Zn oxide, by atomic layer deposition (ALD), the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element may not match the atomic ratio of each metal element in the formed metal oxide.

[0195] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0196] The metal oxide can also have a stacked structure of two or more layers. When the metal oxide used as the semiconductor layer has a two-layer structure of a first layer and a second layer on the first layer, it is preferable that the second layer has a different composition from the first layer. Furthermore, when the metal oxide used as the semiconductor layer has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, it is preferable that the second layer has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0197] The first to third layers may each be made of the metal oxides described above.

[0198] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout can be used. For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereabout can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0199] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0200] By sandwiching the second layer between the first layer and the third layer, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0201] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0202] Furthermore, by increasing the Ga content in the first layer and the third layer, the barrier properties against hydrogen of the first layer and the third layer can be improved. Therefore, it is possible to suppress the diffusion of hydrogen from below the first layer or above the third layer to the second layer. Furthermore, by increasing the Ga content in the first layer and the third layer, it is possible to reduce impurities such as hydrogen or water contained in the metal oxide due to heat or the like applied after the formation of the metal oxide used as the semiconductor layer. Note that the same effect may be achieved by using a metal oxide with a lower In content than the second layer for the first layer and the third layer.

[0203] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, in which the third layer contains indium and gallium.

[0204] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0205] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0206] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0207] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, or one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0208] The first layer, the second layer, and the third layer can each be a stack of layers having the composition described above. For example, the first layer can be configured by stacking a metal oxide having a high In content on a metal oxide having a high Ga content. For example, the third layer can be configured by stacking a metal oxide having a high Ga content on a metal oxide having a high In content.

[0209] [Method for Producing Metal Oxide] The metal oxide can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0210] The metal oxide used as the semiconductor layer can be formed by two types of film formation methods. For example, the metal oxide used as the semiconductor layer can be formed by a first film formation method and a second film formation method.

[0211] The metal oxide used as the semiconductor layer can have a two-layer structure of a first layer and a second layer on the first layer. When the metal oxide has a two-layer structure, the metal oxide can be produced by forming the first layer on a surface to be formed using a first film formation method, and then forming the second layer thereon using a second film formation method.

[0212] The first film formation method preferably uses a film formation method that causes less damage to the surface to be formed than the second film formation method. This can suppress the formation of a mixed layer at the interface between the metal oxide and the layer on which the metal oxide is formed. Furthermore, since it can suppress the incorporation of impurities such as silicon into the second layer formed on the first layer, the crystallinity of the metal oxide layer may be increased.

[0213] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0214] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0215] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0216] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed using the second film formation method on a silicon-containing insulating layer, such as a silicon oxide film, as the formation surface, silicon may be mixed into the metal oxide. The inclusion of impurities such as silicon in the metal oxide may hinder the crystallization of the metal oxide. Furthermore, the use of a metal oxide layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when the heat treatment described below is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0217] Therefore, as described above, by forming a metal oxide layer using the first film formation method before forming a metal oxide layer using the second film formation method, it is possible to suppress the incorporation of impurities into the metal oxide layer. Furthermore, it is possible to suppress alloying with the layer on which the metal oxide layer is to be formed. Therefore, it is possible to improve the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the metal oxide used as the semiconductor layer.

[0218] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0219] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with superior coverage compared to the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the metal oxide can be improved. Therefore, the metal oxide can be well coated on steps, openings, etc. with high aspect ratios.

[0220] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. By forming a second layer having high crystallinity on the first layer having low crystallinity, or by applying a heat treatment after forming the second layer, the crystallinity of the first layer may be increased, with the second layer acting as a nucleus. This may increase the crystallinity of the entire metal oxide layer, including the vicinity of the interface with the surface on which it is formed.

[0221] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to have crystallinity. Note that, when the layer has crystallinity, it preferably has a crystal structure with low lattice matching with the metal oxide of the metal oxide layer.

[0222] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0223] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0224] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0225] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0226] By repeating the above-described method, an In-M-Zn oxide can be formed as a metal oxide on the layer that is the surface to be formed by the ALD method.

[0227] When forming a metal oxide using the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) as an oxidizing agent, the amount of hydrogen mixed into the metal oxide can be reduced.

[0228] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge the excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge the excess reactant, reaction products, etc. from the reaction chamber.

[0229] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0230] The second layer is preferably formed by sputtering.

[0231] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0232] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0233] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0234] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0235] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer to be formed and the metal oxide can be reduced to such an extent that it is difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0236] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0237] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0238] When observing the thickness of the alloyed region of a metal oxide by EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0239] Furthermore, for example, when SIMS analysis is performed on a metal oxide formed on a silicon oxide film, which is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0240] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0241] By reducing the alloyed region, it becomes possible to form a CAAC structure near the surface to be formed. Here, "near the surface to be formed" refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, generally perpendicular to the surface to be formed of the metal oxide.

[0242] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of a metal oxide using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0243] The metal oxide used as the semiconductor layer may have a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer.

[0244] When the metal oxide has a three-layer structure, the metal oxide can be produced by forming a first layer on a surface to be formed using a first film formation method, then forming a second layer using a second film formation method, and then forming a third layer using the first film formation method.

[0245] Even when the metal oxide has a composition that makes it difficult to form a CAAC structure when the first and third layers are formed as a single layer, crystal growth occurs with the second layer as a nucleus, so that the entire metal oxide including the first and third layers can have a CAAC structure. Alternatively, the region including at least a portion of each of the first and third layers and the second layer can have a CAAC structure.

[0246] In particular, even when the first layer and the third layer have a high In content, the metal oxide used as the semiconductor layer can have suitable crystallinity for the semiconductor layer of a transistor. Increasing the In content of the metal oxide used as the semiconductor layer can improve the on-state characteristics of the transistor, while providing a highly crystalline CAAC structure can improve reliability.

[0247] Furthermore, it is preferable that the first layer and the third layer use a metal oxide having the same composition as that of the second layer, since using the same composition may make it easier for CAAC to occur after heat treatment.

[0248] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the metal oxide can have both high crystallinity and high coverage throughout the entire layer.

[0249] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, also has excellent crystallinity.

[0250] When a metal oxide is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the metal oxide, may be in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0251] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0252] In this way, in the method for producing a metal oxide, the second layer having a highly crystalline metal oxide (i.e., CAAC) can be used as a nucleus or seed to increase the crystallinity of the upper and lower metal oxides (here, the first layer and the third layer). This can increase the crystallinity of the entire metal oxide. In other words, the second layer can be used as a nucleus or seed to cause solid-phase growth of the upper and lower metal oxides, thereby forming a highly crystalline metal oxide. A metal oxide formed using such a film formation method, here a CAAC film, can be referred to as an axial growth CAAC (AG CAAC).

[0253] In a metal oxide used as a semiconductor layer, it is preferable that a region having a CAAC structure is widely present throughout the layer. The region having a CAAC structure in the first layer is crystalline connected to the region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystalline connected to the region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. Therefore, a metal oxide composed of the first layer to the third layer may be expressed as a single layer with no clearly observed interface. The metal oxide may be expressed as a single layer.

[0254] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or approximately parallel to the surface on which the metal oxide is formed are confirmed in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axis of the CAAC structure in each of the first to third layers is parallel or approximately parallel to the normal direction of the surface on which the metal oxide is formed.

[0255] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0256] Furthermore, when the metal oxide has a three-layer structure, the metal oxide can also be produced by forming a first layer on a surface to be formed using a first film formation method, then forming a second layer using the first film formation method, and then forming a third layer using a second film formation method.

[0257] As described above, using a metal oxide with a high In content for the semiconductor layer of a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content for the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0258] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, when a cross-section of the metal oxide is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface on which the metal oxide is formed are observed in the second layer.

[0259] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0260] In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0261] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be increased. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0262] One or more of the first to third layers may be formed by stacking layers having different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide having a high Ga content by the first deposition method, and then forming a layer containing a metal oxide having a higher In content than the first layer by the first deposition method.

[0263] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0264] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0265] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the metal oxide can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere, the present invention is not limited to this. For example, by performing microwave plasma treatment on an insulating film, more specifically, a silicon oxide film, provided near a metal oxide used as a semiconductor layer in an oxygen-containing atmosphere, the impurity concentration in the metal oxide can be reduced. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the metal oxide layer.

[0266] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0267] When microwave plasma treatment is performed, it is preferable to heat the substrate. The heating temperature of the substrate is preferably from room temperature (25°C) to 750°C, more preferably from 300°C to 500°C, and even more preferably from 400°C to 450°C. By heating the substrate and performing microwave plasma treatment, it is possible to further promote the reduction of the impurity concentration in the metal oxide. Furthermore, by setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be extremely reduced even when microwave plasma treatment is performed while the substrate is heated.

[0268] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋ ) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in metal oxides by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the metal oxide may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0269] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer, etc. can be suppressed, and the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0270] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the metal oxide. The action of plasma, microwaves, oxygen radicals, etc., can form defects in which hydrogen has entered oxygen vacancies in the metal oxide (hereinafter referred to as V Ｏ This splits the V (sometimes referred to as H) into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the metal oxide. Ｏ In this case, the amount of H can be reduced. In addition, carbon bonded to oxygen or hydrogen can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to the metal oxide, oxygen vacancies in the metal oxide layer can be further reduced.

[0271] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle by which microwave plasma treatment improves the crystallinity of a metal oxide will be explained. First, active species such as oxygen radicals excited by microwaves arrive at the metal oxide surface, and a substitution reaction occurs between the active species and oxygen in the metal oxide. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable for the active species excited by microwaves to contain oxygen (typically oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this promotes the lateral growth. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, improving the crystallinity of the metal oxide.

[0272] On the other hand, a reaction occurs between some of the oxygen in the metal oxide that existed before the microwave plasma treatment and the hydrogen in the metal oxide, in other words, "2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２Since O is one of the factors that hinder the improvement of crystallinity, it is preferable to remove it from the metal oxide. ２ The hydrogen concentration in the metal oxide can be reduced by removing the hydrogen as O, thereby promoting improvement in crystallinity. Note that the hydrogen concentration in the metal oxide can be further reduced by increasing the temperature during microwave plasma treatment.

[0273] It is preferable to perform a heat treatment immediately after the microwave plasma treatment without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be significantly reduced even when the heat treatment is performed.

[0274] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0275] The crystallinity of the layer formed by the first deposition method can be improved, and the crystallinity of the layer formed thereon can be further improved, thereby increasing the crystallinity of the metal oxide as a whole.

[0276] Oxygen supplied to the metal oxide can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). The oxygen injected into the metal oxide is preferably in one or more of the above forms, and is particularly preferably in the form of an oxygen radical.

[0277] Furthermore, it is preferable to perform heat treatment after forming the metal oxide. The heat treatment can enhance the crystallinity of the metal oxide. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process can be replaced with the heat treatment described above.

[0278] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

[0279] The heating device used for the heat treatment is not particularly limited, and any device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element can be used. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0280] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after the ALD film formation, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0281] Furthermore, it is preferable that at least a portion of the first layer or the second layer formed using the first film formation method is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method serves as a nucleus or seed. It is preferable that the region in the first layer or the second layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0282] Furthermore, because the CAAC is formed from the top to the bottom of the first or second layer, the CAAC can be formed up to the vicinity of the layer, regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be increased. Therefore, the method for manufacturing a metal oxide used as a semiconductor layer is particularly suitable when the layer on which the CAAC is formed has an amorphous structure.

[0283] As described above, by performing one or both of microwave plasma treatment and heat treatment, the crystallinity of the entire metal oxide can be increased. Furthermore, impurities in the metal oxide can be reduced. By performing crystal growth in a state where the impurity concentration in the metal oxide is reduced, the crystallinity can be further improved.

[0284] By increasing the crystallinity of the metal oxide, an increase in the electrical resistance of a transistor using the metal oxide as a semiconductor layer can be suppressed, or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby realizing a transistor suitable for high-speed operation.Furthermore, the reliability of the transistor can be improved, and the on-state current can be increased.

[0285] One or both of the microwave plasma treatment and the heat treatment can be performed directly on the formed metal oxide, or can be performed after forming an insulating film or the like on the metal oxide.

[0286] It is preferable to perform a treatment for supplying oxygen to the first layer or the second layer before forming the first layer or after forming the first layer or the second layer by the first film formation method, so that oxygen can be supplied to the metal oxide by heat or the like applied after the treatment.

[0287] Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the first layer or the second layer formed by the first film formation method by forming a metal oxide film in an oxygen-containing atmosphere by sputtering. The formed metal oxide film can be removed immediately after deposition, or can be left as it is. When the formed metal oxide film is left as it is, the metal oxide can be used as a layer (second layer or third layer) provided on the first layer or the second layer. Note that the oxygen-containing atmosphere can be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0288] The metal oxide formed by the above-described manufacturing method has high crystallinity throughout the entire layer. Therefore, in the metal oxide, the boundaries between the stacked films of the first to third layers may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM (scanning transmission electron microscope), etc.

[0289] Furthermore, a metal oxide having a CAAC structure formed using the two types of film formation methods described above may have one or more of a higher dielectric constant, a higher film density, and a higher film hardness than a metal oxide having a CAAC structure formed using one type of film formation method.

[0290] By using a metal oxide having a CAAC structure formed by using the above-described two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0291] Furthermore, metal oxides can sometimes be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, metal oxides can sometimes be formed without using the second film formation method. For example, after forming a first layer using the first film formation method, the crystallinity of the first layer can be increased by performing one or both of microwave plasma treatment and heat treatment. Therefore, the crystallinity of a second layer formed on the first layer using the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, after forming the second layer, the crystallinity of the metal oxide can be increased by performing one or both of microwave plasma treatment and heat treatment. Therefore, a CAAC structure can be formed in the metal oxide.

[0292] As described above, even in a manufacturing method that does not use the second film formation method, a metal oxide having high crystallinity can be formed by solid-phase growth of the upper metal oxide using the first layer formed by the first film formation method as a nucleus or seed. Metal oxides formed by such film formation methods can also be called AG CAAC.

[0293] When the metal oxide has a stacked structure of two or more layers, it can be formed by forming the metal oxide using a single film formation method. When the metal oxide has a two-layer structure of a first layer and a second layer on the first layer, the metal oxide can be formed, for example, by forming the first layer and the second layer in this order using a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. Furthermore, when the metal oxide has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can also be formed using a sputtering method. Furthermore, a portion of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer can be formed by ALD.

[0294] [Metal Oxide Layer of Transistor] The metal oxide of this embodiment can be used as a semiconductor layer of a transistor, for example, the semiconductor layer 112 of the transistor 120.

[0295] A metal oxide used for a semiconductor layer of a transistor preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or approximately parallel to a surface on which the metal oxide is formed in a crystal portion.

[0296] It is believed that metal oxides having a CAAC structure exhibit current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. In other words, it is believed that in metal oxides having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0297] In a semiconductor device according to one embodiment of the present invention, when a metal oxide having a CAAC structure is used for the semiconductor layer 112, metal atoms are arranged in a layered manner in a direction parallel to or substantially parallel to a surface where the metal oxide is to be formed (for example, a side surface of the insulating layer 108). It can also be expressed that the a-b plane of the CAAC structure is provided in a direction parallel to or substantially parallel to the surface where the metal oxide is to be formed. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0298] When a metal oxide is used as a semiconductor layer of a transistor, the thickness of the metal oxide is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 5 nm to 100 nm, still more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, and even more preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the thickness of the metal oxide used as a semiconductor layer is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, even more preferably 5 nm to 12 nm, and even more preferably 5 nm to 10 nm. Furthermore, the average thickness of the metal oxide in the channel formation region of the transistor is particularly preferably 2 nm to 15 nm.

[0299] The first layer preferably has a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0300] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0301] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0302] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0303] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0304] [Impurities in Metal Oxide] Here, the influence of each impurity in the metal oxide layer will be described.

[0305] The metal oxide used as the semiconductor layer of the transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics of the transistor are likely to fluctuate, which may result in poor reliability. Therefore, in order to stabilize the electrical characteristics of an OS transistor, it is effective to reduce the impurity concentration in the metal oxide used as the semiconductor layer. Furthermore, in order to reduce the impurity concentration in the metal oxide used as the semiconductor layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities in the metal oxide used as the semiconductor layer include hydrogen, carbon, and nitrogen. Note that the impurities in the metal oxide refer to, for example, elements other than the main component constituting the metal oxide. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0306] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0307] Furthermore, when nitrogen is contained in a metal oxide, electrons serving as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0308] Furthermore, hydrogen contained in metal oxide reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0309] Furthermore, when a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal as a semiconductor layer is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0310] By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0311] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0312] Embodiment 3 In this embodiment, a configuration example of a semiconductor device 900 using the semiconductor device 10 as a memory cell will be described. The semiconductor device 900 can function as a memory device.

[0313] FIG. 11 is a block diagram showing an example of the configuration of a semiconductor device 900. The semiconductor device 900 shown in FIG. 11 includes a driver circuit 910 and a memory array 920. The memory array 920 includes a plurality of semiconductor devices 10 that function as memory cells. FIG. 11 shows an example in which the memory array 920 includes a plurality of semiconductor devices 10 arranged in a matrix of p rows and q columns (each of p and q is an integer of 2 or greater). By arranging a plurality of semiconductor devices 10 in a matrix, a memory device with a large storage capacity can be realized.

[0314] In Figure 11, the semiconductor device 10 in the first row and first column is shown as semiconductor device 10[1,1], the semiconductor device 10 in the pth row and qth column is shown as semiconductor device 10[p,q], the semiconductor device 10 in the pth row and first column is shown as semiconductor device 10[p,1], the semiconductor device 10 in the first row and qth column is shown as semiconductor device 10[1,q], and the semiconductor device 10 in the rth row and sth column (r is an integer of 1 to p inclusive indicating an arbitrary row, and s is an integer of 1 to q inclusive indicating an arbitrary column) is shown as semiconductor device 10[r,s].

[0315] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as a "row" and the Y direction (direction along the Y axis) is referred to as a "column," but it is also possible to refer to the X direction as a "column" and the Y direction as a "row."

[0316] 12A and 13A are block diagrams showing a portion of the memory array 920. FIGS. 12B and 13B are schematic perspective views showing a portion of the memory array 920. As shown in FIGS. 12A and 12B, a plurality of semiconductor devices 10 functioning as memory cells can be aligned in the row and column directions within the memory array 920. Also, as shown in FIGS. 13A and 13B, a plurality of semiconductor devices 10 functioning as memory cells can be staggered within the memory array 920.

[0317] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0318] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0319] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0320] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0321] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0322] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory array 920. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0323] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory array 920, reading data from the memory array 920, and holding the read data.

[0324] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory array 920. The data (Dout) read from the memory array 920 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0325] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply potential of the semiconductor device 900 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 11 , the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0326] 14A to 14G, an example of a circuit configuration that can be applied to the memory cell of the semiconductor device 900 will be described.

[0327] 14A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).

[0328] The memory cell 951 has the same circuit configuration as the semiconductor device 10. Therefore, the semiconductor device 10 functions as a DRAM or a DOSRAM.

[0329] The memory cell 951 includes a transistor M1 and a capacitor CA. Note that a transistor having a front gate (sometimes simply referred to as a gate) and a back gate can be used as the transistor M1. In this case, the back gate can be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate can be connected to each other.

[0330] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BL, and a gate of the transistor M1 is connected to the wiring WL. A second terminal of the capacitor CA is connected to the wiring CAL.

[0331] The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0332] Data is written and read by applying a high-level potential to the wiring WL, turning on the transistor M1, and bringing the wiring BL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0333] Furthermore, the circuit configuration that can be applied to the memory cell of the semiconductor device 900 is not limited to the circuit configuration shown as the memory cell 951 .

[0334] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951.

[0335] 14B shows an example circuit configuration of a two-transistor, one-capacitor gain cell memory cell. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell memory cell in which an OS transistor is used as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0336] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, and a gate of transistor M2 is connected to wiring WL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to the first terminal of capacitor CB.

[0337] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0338] Data is written by applying a high-level potential to the wiring WL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0339] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0340] Furthermore, for example, the wiring WBL and the wiring RBL can be combined into a single wiring BL. An example circuit configuration of such a memory cell is shown in FIG. 14C . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BL.

[0341] 14D is an example in which the capacitance CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 14E is an example in which the capacitance CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0342] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0343] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, each of the memory cells 953, 954, 955, and 956 can hold multilevel data or analog data.

[0344] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 in which an OS transistor is used as the transistor M2 are one embodiment of an NOSRAM.

[0345] Note that a Si transistor can be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0346] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0347] 14F shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC. The memory cell 957 is also one aspect of NOSRAM.

[0348] A first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BL, and a gate of the transistor M4 is connected to the wiring WL. A second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BL, and a gate of the transistor M6 is connected to the wiring RWL.

[0349] The wiring BL functions as a bit line, the wiring WL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0350] Data is written by applying a high-level potential to the wiring WL, turning on the transistor M4, and establishing electrical continuity between the wiring BL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0351] Data is read by precharging the wiring BL to a predetermined potential, then electrically floating the wiring BL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0352] Note that at least the transistor M4 is preferably an OS transistor.

[0353] Note that Si transistors can be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0354] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0355] 14G shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 14G is a memory cell of an SRAM capable of backing up data.

[0356] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0357] A first terminal of transistor M7 is connected to wiring BL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. A gate of transistor M7 is connected to wiring WL. A first terminal of transistor M8 is connected to wiring BLB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. A gate of transistor M8 is connected to wiring WL.

[0358] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0359] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0360] A second terminal of the capacitor CD1 is connected to the wiring GNDL, and a second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0361] The wirings BL and BLB function as bit lines, the wiring WL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0362] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0363] Data is written by applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BL, and the potential is written to the second terminal of the transistor M10.

[0364] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BL, i.e., the inverted signal of the signal input to the wiring BL, is output to the wiring BLB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0365] Data is read by precharging the wiring BL and the wiring BLB to a predetermined potential in advance, and then applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BLB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BL. The potentials of the wiring BL and the wiring BLB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BL or the wiring BLB.

[0366] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells or eliminates the need for refreshing the memory cells.

[0367] Note that Si transistors can be used as the transistors MS1 to MS4.

[0368] The drive circuit 910 and memory array 920 of the semiconductor device 900 can be provided on the same plane. Furthermore, as shown in FIG. 15A, it is preferable to provide the drive circuit 910 and memory array 920 so that they overlap. By providing the drive circuit 910 and memory array 920 so that they overlap, the signal propagation distance can be shortened. Furthermore, as shown in FIG. 15B, it is also possible to provide multiple memory arrays 920 stacked on top of the drive circuit 910.

[0369] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0370] 16 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 16 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0371] The arithmetic device 960 shown in FIG. 16 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0372] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0373] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0374] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0375] The arithmetic device 960 shown in FIG. 16 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 16 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0376] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0377] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0378] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0379] 16, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or capacitors. If holding data using flip-flops is selected, power is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the power supply to the memory cells in the register 996 can be stopped.

[0380] The memory array 920 and the arithmetic device 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 17A and 17B. The semiconductor device 970A includes an element layer 930 on which a memory array is provided, on an arithmetic device 960. The element layer 930 includes a memory array 920L1, a memory array 920L2, and a memory array 920L3. The arithmetic device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the element layer 930 are shown separately in FIG. 17B.

[0381] By overlapping the element layer 930 having the memory array and the arithmetic device 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0382] As a method for stacking the element layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the element layer 930 having a memory array is stacked directly on the arithmetic device 960 can be used, or a method in which the arithmetic device 960 and the element layer 930 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) can be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0383] Here, the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the element layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0384] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the element layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0385] 17B, ​​a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0386] Although the number of memory arrays functioning as caches is three in this example, the number of memory arrays may be one or two, or may be four or more.

[0387] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can function as part of the cache interface 989. It is also possible to configure the driver circuit 910L1 to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also function as part of the cache interface 989 or be configured to be connected thereto.

[0388] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause a part of the memory array 920 included in the semiconductor device 900 to function as a RAM based on a signal supplied from the arithmetic device 960.

[0389] The semiconductor device 900 can cause a part of the memory array 920 to function as a cache and another part to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0390] It is also possible to provide an element layer 930 having one memory array 920 overlaid on the arithmetic device 960. Fig. 18A shows a perspective view of a semiconductor device 970B.

[0391] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 18A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0392] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0393] It is also possible to stack multiple memory arrays. Figure 18B shows a perspective view of a semiconductor device 970C.

[0394] The semiconductor device 970C includes an element layer 930L1 having a memory array 920L1, an element layer 930L2 having a memory array 920L2 on top of that, and an element layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0395] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0396] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0397] Embodiment 4 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0398] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 19 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices such as computers. In Figure 19, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0399] In FIG. 19 , from the top layer of the triangle, memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAM, and storage memories such as 3D NAND and hard disks (also called HDDs: hard disk drives) are shown.

[0400] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0401] Cache memory has the function of duplicating and storing a portion of data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the access speed to the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. Furthermore, data rewritten in cache memory is duplicated and supplied to DRAM. Note that, although only the L3 cache is illustrated in FIG. 19 , the cache memory is not limited to this. For example, an OS memory according to one aspect of the present invention is also suitable for the lowest-level cache, LLC (Last Level cache) or FLC (Final Level cache).

[0402] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0403] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0404] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0405] The OS memory according to one embodiment of the present invention can retain data for a long period of time. Therefore, it is suitable for the area of ​​Target 1 shown in FIG. 19 . Note that, as indicated by the diagonal hatching in FIG. 19 , Target 1 also includes a portion of the cache (L1, L2, L3) and a portion of the 3D NAND. In other words, Target 1 includes the boundary area between the DRAM and the 3D NAND, and the boundary area between the DRAM and the cache (L1, L2, L3). Furthermore, the OS memory according to one embodiment of the present invention has a high operating speed, enabling excellent write and read operations. Therefore, it can also be used for the area of ​​Target 2 shown in FIG. 19 .

[0406] For example, it is preferable to replace the DRAM shown in FIG. 19 with an OS memory according to one embodiment of the present invention. Here, the DRAM requires a refresh operation and is a destructive readout storage device, so it consumes more power than other storage devices. Therefore, a configuration without a DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or one-thousandth or less of that of a configuration using a DRAM. Therefore, global warming can be mitigated by deploying information processing devices, including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied worldwide.

[0407] In this way, the OS memory according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories in the boundary area between DRAMs and 3D NANDs.

[0408] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0409] Embodiment 5 In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0410] [Electronic Component] FIG. 20A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 20A has semiconductor device 710 inside mold 711. FIG. 20A omits some parts in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0411] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0412] The semiconductor device 900 according to one embodiment of the present invention or the like can be used as the semiconductor device 710. Therefore, the driver circuit 910 can be used as the driver circuit layer 715. The memory array 920 can be used as the memory layer 716. The semiconductor device 710 can be a semiconductor device 970A, a semiconductor device 970B, a semiconductor device 970C, or the like.

[0413] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0414] Furthermore, it is preferable that the plurality of memory cell arrays included in the memory layer 716 be formed using OS transistors and that the plurality of memory cell arrays be monolithically stacked. By forming the plurality of memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0415] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0416] 20B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0417] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0418] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0419] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, a TSV can also be used as the through electrode.

[0420] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0421] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0422] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. It is also possible to create a composite structure that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0423] It is also possible to provide a heat sink (heat dissipation plate) overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0424] In order to mount the electronic component 730 on another substrate, electrodes 733 can also be provided on the bottom of the package substrate 732. FIG. 20B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0425] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0426] 21A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 is sometimes called a supercomputer.

[0427] 21B shows a perspective view of an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0428] Fig. 21C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629, etc., which are mounted on the board 5622. Note that Fig. 21C illustrates components other than electronic components 5626, 5627, and 5628.

[0429] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0430] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0431] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0432] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0433] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0434] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0435] A semiconductor device according to one embodiment of the present invention for space equipment preferably includes an OS transistor. The OS transistor exhibits small variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for environments where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0436] Fig. 22A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 22A shows a planet 6804 in space as an example.

[0437] 22A , a battery management system (also referred to as a BMS) or a battery control circuit can be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0438] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0439] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0440] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0441] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is highly reliable and suitable even in an environment where radiation may be incident.

[0442] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0443] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0444] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0445] [Data Center] A semiconductor device according to one aspect of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power source for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0446] By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. This leads to a reduction in the size of the storage system, the size of the power supply for storing data, the size of the cooling equipment, and the like. This leads to a reduction in the space required for the data center.

[0447] Furthermore, the semiconductor device according to one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device according to one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0448] Fig. 22B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 22B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0449] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can be connected to each other via a network.

[0450] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0451] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0452] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0453] Note that by applying a semiconductor device according to one embodiment of the present invention to one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device according to one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0454] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0455] 10: semiconductor device, 101: insulating layer, 102: conductive layer, 103: insulating layer, 104: opening, 105: conductive layer, 106: insulating layer, 107: conductive layer, 108: insulating layer, 109: conductive layer, 110: capacitance element, 111: opening, 112: semiconductor layer, 113: insulating layer, 114: conductive layer, 115: insulating layer, 120: transistor, 121: end, 122: region, 151: length, 152: length, 700: electronic part 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit , 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Element layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 951: Memory cell, 953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 958: Memory cell, 960: Arithmetic unit, 989: Cache interface, 990: Substrate, 991: ALU, 992: ALU controller, 993: Instruction decoder, 994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register controller, 998: Bus interface, 999: Cache

Claims

A semiconductor device having a first capacitance element and a first transistor, a first insulating layer provided on the first conductive layer; a first opening that penetrates the first insulating layer and reaches the first conductive layer; a second conductive layer having a region overlapping the first conductive layer and a region overlapping a side surface of the first insulating layer in the first opening; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping the second conductive layer via a portion of the second insulating layer and a region overlapping a side surface of the first insulating layer via another portion of the second insulating layer; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; a second opening that penetrates the third insulating layer and reaches the third conductive layer; a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, and a channel formation region along a side surface of the third insulating layer in the second opening; a fourth insulating layer provided on the semiconductor layer; a fifth conductive layer having a region overlapping with a channel formation region of the first transistor via a part of the fourth insulating layer; The semiconductor device has a length in a first direction different from a length in a second direction perpendicular to the first direction when viewed from above. 　 In claim 1, the second conductive layer functions as one electrode of the first capacitance element; the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of a source electrode or a drain electrode of the first transistor; The fourth conductive layer functions as the other of the source electrode and the drain electrode of the first transistor. 　 In claim 1 or claim 2, The length in the second direction is between two and five times the length in the first direction. 　 In claim 1 or claim 2, The semiconductor device has a region where the first capacitive element and the first transistor overlap each other in a plan view. 　 In claim 1 or claim 2, The semiconductor device, wherein the semiconductor layer includes an oxide semiconductor. 　 A semiconductor device having a first capacitance element, a first transistor, and a second transistor, a first insulating layer provided on the first conductive layer; a second conductive layer having a region overlapping the first conductive layer and a region overlapping a side surface of the first insulating layer; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping the second conductive layer via a portion of the second insulating layer; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, a channel formation region of the first transistor, and a channel formation region of the second transistor; a fourth insulating layer provided on the semiconductor layer; a fifth conductive layer having a region overlapping with a channel formation region of the first transistor via a portion of the fourth insulating layer and a channel formation region of the second transistor via another portion of the fourth insulating layer; A semiconductor device having: 　 In claim 6, the second conductive layer functions as one electrode of the first capacitance element; the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of a source electrode and a drain electrode of each of the first transistor and the second transistor; The fourth conductive layer functions as the other of the source electrode and the drain electrode of each of the first transistor and the second transistor. 　 In claim 6 or claim 7, The first capacitive element has a first region that overlaps with the first transistor in a plan view and a second region that overlaps with the second transistor in a plan view. 　 In claim 6 or claim 7, The semiconductor device, wherein the semiconductor layer includes an oxide semiconductor.

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