Task scheduler device and program

Abstract

A task scheduler (100, 100A) according to the present invention includes: a plurality of arithmetic units (51-54) having a power saving mode for reducing power consumption by stopping or reducing arithmetic capability; a arithmetic unit allocation instruction unit (160) for allocating a task to one of the plurality of arithmetic units (51-54); a pre-processing unit (140) in which an arithmetic unit that executes pre-processing of parallel processing issues a wake-up instruction to an other arithmetic unit before the pre-processing is completed; and an arithmetic unit advance wake-up instruction unit (130) that instructs arithmetic units other than the selected other arithmetic unit to return from the power saving mode.

Description

Task scheduler device and program

[0001] The present invention relates to a task scheduler device and a program.

[0002] An overview of the wireless access system will now be described. Fig. 16 is a diagram illustrating the overview of the wireless access system. As shown in Fig. 16, the wireless access system includes a user terminal (UE: User Equipment) (not shown), an antenna (base station antenna) 20, a base station (BBU: Base Band Unit) 30, and a core network 40.

[0003] The antenna 20 is an antenna and a transceiver unit that wirelessly communicates with the UE 10 (hereinafter, the term "antenna" refers collectively to the antenna, the transceiver unit, and its power supply unit). Data transmitted and received is connected to the base station 30 via, for example, a dedicated cable.

[0004] The base station 30 is a stationary radio station established on land that communicates with the UE 10. The base station (BBU: Broad Band Unit) 30 that performs radio signal processing is dedicated hardware (dedicated device) for performing radio signal processing. Alternatively, the base station 30 is a virtual radio access network (vRAN) that performs radio signal processing in a signal processing aggregation system for LTE (Long Term Evolution) or 5G (five generation) using a general-purpose server. In a vRAN, inexpensive, mass-available general-purpose servers can be used as the hardware for the base station 30. The base station 30 includes hardware (HW) 31, a central processing unit (CPU) 32 on the hardware, an OS 33, L1, L2, and L3 protocol radio signal processing applications 1-1, 1-2, and 1-3 (collectively referred to as APL1), and a task scheduler device 34.

[0005] The core network 40 is an EPC (Evolved Packet Core) / (in the following description, " / " indicates "or") 5GC (5G Core Network) or the like.

[0006] A base station block (BBU) in a RAN is an example of a system that requires real-time performance. In a BBU that performs calculations using a CPU 32, a task scheduler device 34 often allocates wireless signal processing tasks to the CPU core to perform the calculations (see Non-Patent Document 1).

[0007] Figure 17 is a diagram illustrating an example of task management for wireless access processing in a base station. Components that are the same as those in Figure 16 are assigned the same reference numerals. The base station (BBU) 30 includes a task scheduler device 34. The task scheduler device 34 manages tasks, assigns priorities, and allocates tasks. The task scheduler device 34 allocates the wireless signal processing task of APL1 to a task queue 37, and assigns it from the task queue 37 to the CPUs (CPU core #0, CPU core #1, ...) 32.

[0008] [LPI (Low Power Idle) Hardware Control] The CPU 32 has a function for controlling the idle state of the CPU 32 through hardware control, which is called LPI. LPI is often referred to as CPU idle or C-state, and hereinafter, LPI will be described as C-state. C-state attempts to save power by turning off the power to part of the CPU 32 circuit when the CPU load decreases (Non-Patent Document 2).

[0009] FIG. 18 is a table showing an example of the C-state. Note that state definitions vary depending on the CPU hardware, so FIG. 18 is merely a reference example. As shown in FIG. 18, the CPU idle state has grades C0 to C6, and as the time without load on the CPU 32 increases, it transitions to a deeper sleep state. A deeper sleep state reduces CPU power consumption, but on the other hand, it takes longer to return from the CPU, which can be an issue from the perspective of low latency.

[0010] The definition of C-states varies depending on the CPU hardware. For example, there are models that do not have C4 or C5, and models where the state after C1 is C1E. The deeper the state, the greater the power saving effect, but the longer it takes to return from idle state.

[0011] Furthermore, the depth to which the CPU idle state transitions is controlled by the CPU hardware and is dependent on the CPU product (it is often not possible to control this from software such as the kernel).

[0012] 19 is a table showing an example of the maximum value of the time required to transition to a state (RESIDENCY) and the time required to return (WAKE-UP LATENCY). Figure 19 shows C-state information for an Intel Xeon CPU E5-26X0 v4 (registered trademark).

[0013] [CPU Idle State Governor] Linux kernel 4 (registered trademark) provides two types of governors to manage the CPU idle state (C-state).

[0014] FIG. 20 is a diagram explaining the CPU idle governor types. As shown in FIG. 20, ladder is used for ticking systems, and menu is used for tickless systems. For example, menu, used in tickless systems, is a method that estimates the appropriate idle state depth for the next idle period based on the performance of the most recent idle period. menu is effective for workloads with regular idle times, but its effectiveness is limited for irregular workloads.

[0015] FIG. 21 is a diagram outlining the logic of menu. As shown in step S201 of FIG. 21, menu records the most recent idle time. Then, as shown in step S202 of FIG. 21, it estimates the next idle time. For example, based on the idle time recorded in step S201 of FIG. 21, if the deviation is small, it adopts the average value T_avr as the next idle time. As shown in step S203 of FIG. 21, menu estimates an appropriate idle state depth based on the estimate of the next idle time. For example, if the estimated next idle time value T_avr is equal to the exit latency (return time) from the idle state (Cx), it is determined that the state is too deep and transitions to the idle state Cx-1.

[0016] Returning to Figure 20, neither of the two types of governor ladders and menus has a mechanism to pre-wake up the CPU from idle state and return it to preparation when a new task arrives. This causes a problem of a delay due to the return time when a task is assigned while in a state transitioning to a deeper state.

[0017] New API (NAPI), [online], [Retrieved February 1, 2024], Internet <URL: https: / / www.kernel.org / doc / html / latest / admin-guide / pm / cpuidle.html> Daniel Molka & Michael Werner, Wake-up latencies for processor idle states on current x86 processors Robert Schone, [online], [Retrieved February 1, 2024], Internet <URL: https: / / link.springer.com / article / 10.1007 / s00450-014-0270-z#citeas>

[0018] As shown in Figure 18, there are different grades of CPU idle state, and as the time without CPU load increases, the state transitions to a deeper sleep state. A deeper sleep state reduces CPU power consumption, but on the other hand, it takes longer to return to normal operation, which can be an issue from the perspective of low latency.

[0019] Figures 22 and 23 are C-state transition diagrams of a computing unit (CPU core) used for calculations. Figure 22 shows a case where the task-free time is short, while Figure 23 shows a case where the task-free time is long. Periods P21 and P24 indicate periods during which the CPU processes tasks. Period P22 indicates a task-free period. Period P23 indicates a delay period until recovery. Time T1 indicates the time when a task occurs. As shown in Figure 22, when the task-free time in period P22 is short, the computing unit is in a shallow sleep state, and the delay period until recovery after a task occurs is short. However, as shown in Figure 23, when the task-free period is long, the computing unit is in a deep sleep state (CPU idle state: grade C6), and the delay period until recovery after a task occurs is extended. In other words, if the computing unit falls into a deep CPU idle state, it takes a long time to recover, resulting in a loss of real-time performance.

[0020] The above problem cannot be overlooked in a system where real-time performance is given top priority, such as the base station (BBU) 30 shown in Figures 16 and 17. For this reason, the base station (BBU) takes measures such as disabling the C-state or setting the idle state transition to a limited depth, such as C1. In other words, tuning aimed at real-time performance may be performed at the expense of power saving.

[0021] In conventional base stations (BBUs), once a device falls into a deep C-state, there is no option but to wait until it recovers. For this reason, measures were taken to prevent the device from falling into a deep C-state, at the expense of power saving.

[0022] Figure 24 is a diagram explaining the gap when applied to parallel processing tasks. In a computer system, there is a configuration in which tasks are processed using multiple computing units on a computer (hereafter referred to as a server). The configuration and assumptions are as follows: Server The server is equipped with multiple computing units. For example, a CPU is equipped with multiple computing cores (computing units). Each computing unit has a "power saving mode" that reduces power consumption by stopping or reducing its computing power, and it takes a certain amount of time to return from power saving mode. Task A task has multiple processing steps, and each task requires a different number of computing units for processing. Requirements Requirement #1: (Processing completion time) The time from the start to completion of processing for each task should not be extended (no overhead should occur) Requirement #2: (Power saving) Each computing unit should be in power saving mode to the maximum extent possible

[0023] For example, in FIG. 24, the server has a CPU equipped with three arithmetic units #0 to #2, and assigns parallel processing tasks to each of the arithmetic units #0 to #2. The parallel processing task may be, for example, UL (Uplink) processing in the PHY (HIGH) processing unit of a vDU (virtual distributed unit) having a MIMO (multiple input multiple output) configuration in a vRAN. The parallel processing tasks are assigned to each of the arithmetic units #0 to #2, and the arithmetic unit #1 sequentially executes one of the parallel processing tasks, pre-processing 11, which has a low degree of parallelism, followed by a multithreading instruction 12 and a post-processing 14-1. Meanwhile, the arithmetic units #0 and #2 are not assigned tasks such as pre-processing and multithreading instructions, which have a low degree of parallelism, as assigned to the arithmetic unit #1. Therefore, both the arithmetic units #0 and #2 are in a sleep state. Then, a post-processing task is assigned to the arithmetic units #0 and #2, and the arithmetic unit #0 executes the post-processing 14-0. The computing unit #2 executes post-processing 14-2.

[0024] However, if the number of arithmetic units in use is increased while both arithmetic units #0 and #2 are in a deep state, a delay occurs in the return processes 13-0 and 13-2 from the power saving mode. The delay in the return processes 13-0 and 13-2 delays the completion of the processing (by about 100 μs), which poses a problem that the above requirement #1: (processing completion time) is not met.

[0025] The present invention has been made in view of the above background, and an object of the present invention is to process tasks executed on a server without extending the processing completion time and with reduced power consumption.

[0026] In order to solve the above-mentioned problems, a task scheduler device is provided which comprises: a plurality of arithmetic units having a power saving mode which reduces power consumption by stopping or reducing the computing power; an arithmetic unit allocation instruction unit which assigns a task to one of the plurality of arithmetic units; a front-stage processing unit in which an arithmetic unit which executes a front-stage process of parallel processing issues a wake-up instruction to other arithmetic units before the front-stage process is completed; and an arithmetic unit advance wake-up instruction unit which issues an instruction to a selected one of the other arithmetic units to return the other arithmetic units from the power saving mode based on the wake-up instruction.

[0027] According to the present invention, tasks executed on a server can be processed without extending the processing completion time and with reduced power consumption.

[0028] FIG. 1 is a schematic configuration diagram of a computing system according to an embodiment of the present invention. FIG. 1 is a schematic configuration diagram of a task scheduler device in which some functions of the computing system according to an embodiment of the present invention are arranged in a middleware layer. FIG. 2 is a diagram showing a management table of the number of computing units required for subsequent processing, which holds the number of computing units required for the next processing, with the name of the previous processing of the task scheduler device of the computing system according to an embodiment of the present invention as a key. FIG. 3 is a diagram showing a management table of the number of computing units required for subsequent processing, which holds the ratio of the number of computing units required for the next processing, with the name of the previous processing of the task scheduler device of the computing system according to an embodiment of the present invention as a key. FIG. 4 is a diagram showing an actual management table of the number of computing units required for subsequent processing, which holds the actual number of computing units required for processing in the past, with the name of the previous processing of the task scheduler device of the computing system according to an embodiment of the present invention as a key. FIG. 5 is a diagram showing a processing time management table, which holds the time required for processing, with the name of the previous processing of the task scheduler device of the computing system according to an embodiment of the present invention as a key. FIG. 6 is a diagram showing a recovery time prediction table according to power saving stages recorded by a wake-up delay time prediction unit of the task scheduler device of the computing system according to an embodiment of the present invention. FIG. 7 is a diagram explaining hardware of a server constituting the computing system according to an embodiment of the present invention. FIG. 8 is a diagram explaining tasks (software) processed by the computing system according to an embodiment of the present invention. FIG. 1 is a diagram showing the flow of each processing step of PHY-HIGH processing (UL) in a MIMO configuration of a computing system according to an embodiment of the present invention. FIG. 2 is a diagram showing the flow of each processing step of AI inference using CNN in a computing system according to an embodiment of the present invention. FIG. 3 is a diagram explaining the basic concept of a task scheduling method of a task scheduler device of a computing system according to an embodiment of the present invention. FIG. 4 is a flowchart showing the task scheduling process of a task scheduler device of a computing system according to an embodiment of the present invention. FIG. 5 is a flowchart showing an operation sequence when a task scheduling method is applied to a radio signal processing application in a RAN of a task scheduler device of a computing system according to an embodiment of the present invention. FIG. 6 is a hardware configuration diagram showing an example of a computer that realizes the functions of a task scheduler device of a computing system according to an embodiment of the present invention. FIG. 7 is a diagram explaining an overview of a wireless access system.1 is a diagram explaining an example of task management for wireless access processing in a base station. FIG. 2 is a diagram showing an example of C-state states in a table. FIG. 3 is a diagram showing an example of the maximum value of the time it takes to transition to a state (RESIDENCY) and the time required for recovery (WAKE-UP LATENCY) in a table. FIG. 4 is a diagram explaining CPU idle Governor types. FIG. 5 is a diagram explaining an overview of the logic of menu. FIG. 6 is a C-state transition image diagram of a computing unit (CPU core) used for calculation. FIG. 7 is a diagram explaining the gap when applied to a parallel processing task.

[0029] Hereinafter, a computing system and the like in an embodiment for carrying out the present invention (hereinafter referred to as "the present embodiment") will be described with reference to the drawings. [Overview] Fig. 1 is a schematic configuration diagram of a computing system according to an embodiment of the present invention. This embodiment is an example in which the computing system is applied to a CPU. In addition to CPUs, the present invention can also be applied to processors such as GPUs (Graphic Processing Units), FPGAs (Field Programmable Gate Arrays), and ASICs (Application Specific Integrated Circuits) if they have an idle state function.

[0030] As shown in FIG. 1, the computing system 1000 includes a server 101, hardware (HW) 50, an operating system (OS) 60, and a task scheduler 100 on a user application 70. The task scheduler 100 is not limited to being implemented on the user application 70, but may also be implemented in the OS kernel, for example. The hardware 50 includes multiple computing units 51, 52, 53, and 54. The computing units 51 to 54 are configured as the cores of a multi-core CPU or the computing units of an accelerator. The computing units 51 to 54 have a power-saving mode, and it takes a certain amount of time to return to a normal state. The power-saving mode is, for example, the CPU idle governor type shown in FIG. 20.

[0031] The OS 60 has drivers (inter-processor interrupt IPI, eventfd, signal, etc.) for waking up the computing units. The computing system 1000 is a task scheduler device and includes computing units 51 to 54 that have a power-saving mode that reduces power consumption by stopping or reducing computing capabilities. The computing system 1000 includes a task scheduler 100 that assigns tasks to the computing units 51 to 54.

[0032] [Task scheduler 100] The task scheduler 100 includes a unit 110 for estimating the number of operators required for subsequent processing, a unit 120 for selecting operators to be woken up, a unit pre-wake-up instruction unit 130, a pre-processing unit 140, a post-processing unit 150, an operator allocation instruction unit 160, and a wake-up delay time prediction unit 170.

[0033] [Layout of Task Scheduler Device] Figure 2 is a schematic configuration diagram of a task scheduler 100A in which some of the functions of the task scheduler 100 in Figure 1 are located in the middleware layer 80. The computing system 1000 shown in Figure 2 includes the task scheduler 100A, which includes, in the middleware layer 80, a unit 110 for estimating the number of computing units required for post-processing, a unit 120 for selecting computing units to be woken up, a unit advance wake-up instruction unit 130, a computing unit allocation instruction unit 160, and a pre-processing unit library function unit 180. In the task scheduler 100A, the pre-processing unit 140 and the post-processing unit 150 remain on the user application 70. Furthermore, the wake-up delay time prediction unit 170 of the task scheduler 100 in Figure 1 is replaced with the pre-processing unit library function unit 180.

[0034] The task scheduler 100A shown in FIG. 2 has a configuration in which commonly used functions (a post-processing required number of computing units estimation unit 110, a computing unit to be woken up selection unit 120, a computing unit pre-wake-up instruction unit 130, a computing unit allocation instruction unit 160, and a pre-processing unit library function unit 180) are provided on the middleware / library layer side. For example, the task scheduler 100A shown in FIG. 2 can be implemented using an AI (Artificial Intelligence) inference library (e.g., adding pre-wake-up logic to a portion of Tensorflow processing) as the pre-processing unit library function unit 180. The task scheduler 100A shown in FIG. 2 can achieve pre-wake-up without modifying the application. Each functional unit of the task schedulers 100 and 100A will be described below.

[0035] <Unit 110 for estimating the number of computing units required for subsequent processing> The unit 110 for estimating the number of computing units required for subsequent processing estimates the number of computing units required for subsequent parallel processing based on information from the pre-processing unit 140. The unit 110 for estimating the number of computing units required for subsequent processing calculates the number of computing units required for subsequent processing by referring to the actual number of computing units required for subsequent processing management table 230, the ratio management table 220 for the number of computing units required for subsequent processing, and the management table 210 for the number of computing units required for subsequent processing. The unit 110 for estimating the number of computing units required for subsequent processing can take each of the following patterns.

[0036] Pattern #1: The unit 110 for estimating the number of arithmetic units required for post-stage processing has a table (FIG. 3) for each function of the pre-stage processing, and sets a fixed number of arithmetic units for the post-stage processing.

[0037] FIG. 3 illustrates a management table 210 for the number of computing units required for subsequent processing, which stores the number of computing units required for the next processing, using the name of the previous processing as a key. The management table 210 for the number of computing units required for subsequent processing is a basic table that stores the name of the previous processing (process name) and the number of computing units required for the next processing. Examples of the name of the previous processing (process name) are re-demapping, equalizer_channel_estimation, mimo_detection, and demodulation. The management table 210 for the number of computing units required for subsequent processing associates the name of the previous processing with the number of computing units required for the next processing. The unit 110 for estimating the number of computing units required for subsequent processing can refer to the management table 210 for the number of computing units required for subsequent processing to determine the number of computing units required for the next processing from the name of the previous processing (process name). In this case, if a process with the name of the previous processing "re-demapping" is specified in the user application, it is determined that the number of computing units required for the next processing is "3."

[0038] Pattern 2: The unit 110 for estimating the number of arithmetic units required for subsequent processing calculates the number of arithmetic units required for subsequent processing by using the ratio (Figure 4) of the number of arithmetic units required for subsequent processing to the number of arithmetic units required for the previous processing.

[0039] 4 is a diagram showing a post-processing required number of arithmetic units ratio management table 220 that holds the ratio of the number of arithmetic units required for the next process, using the name of the previous process as a key. The post-processing required number of arithmetic units ratio management table 220 is a table that stores the name of the previous process (process name) and the ratio of the number of arithmetic units required for the next process. Examples of the name of the previous process (process name) are re-demapping, equalizer_channel_estimation, mimo_detection, and demodulation. The post-processing required number of arithmetic units ratio management table 220 stores the ratio of the number of arithmetic units required for the next process corresponding to the name of the previous process. Since the ratio of the number of arithmetic units required for the next process is stored, the actual number of arithmetic units required is determined by calculation.

[0040] The post-stage processing required number of arithmetic units estimation unit 110 references this post-stage processing required arithmetic unit number ratio management table 220, obtains the ratio of the number of arithmetic units required for the next process from the name of the previous stage process (process name), and performs calculation processing for the number of arithmetic units required for the next process by multiplying the load (processing time) of the previous stage process by the ratio of the number of corresponding arithmetic units. For example, if a process named "re-demapping" for the previous stage process is specified in the user application, the number of arithmetic units required for the next process is calculated based on the ratio of the load (processing time) of the previous stage process to the number of corresponding arithmetic units. Here, if the previous stage process "re-demapping" requires two arithmetic units, the number of arithmetic units required for the post-stage process is calculated as six by multiplying 2 by 3.

[0041] The method of calculating the number of operators in pattern 2 using the ratio management table 220 for the number of operators required for subsequent processing is expected to be more accurate than the method of calculating the number of operators in pattern #1 using the management table 210 for the number of operators required for subsequent processing, because the load (processing time) of the previous processing is reflected in the determination of the number of operators for the subsequent processing.

[0042] Pattern #3: The downstream processing required number of arithmetic units estimation unit 110 calculates the number of arithmetic units required for downstream processing by storing the actual number of arithmetic units used in downstream processing, linked to each upstream processing unit.

[0043] 5 is a diagram showing the post-stage processing required number of arithmetic units actual management table 230, which stores the actual number of cores required for processing in the past, using the name of the pre-stage processing as a key. The post-stage processing required number of arithmetic units actual management table 230 holds the average number of arithmetic units previously required corresponding to the name of the pre-stage processing. The post-stage processing required number of arithmetic units estimation unit 110 references this post-stage processing required number of arithmetic units actual management table 230, and rounds up the decimal points of the actual number of arithmetic units previously required for processing corresponding to the name of the pre-stage processing, and uses the result as the number of arithmetic units required for the post-stage processing. For example, in the case of the pre-stage processing "re-demapping," the actual number of arithmetic units in the post-stage processing required number of arithmetic units actual management table 230 is rounded up to the nearest whole number, and it is determined that the post-stage processing requires three arithmetic units.

[0044] <Wake-up target computing unit selection unit 120> The wake-up target computing unit selection unit 120 selects a computing unit to be woken up based on the number of computing units required calculated by the unit 110 for estimating the number of computing units required for subsequent processing. One selection method is a simple method of issuing wake-up instructions in ascending order of computing unit numbers. Another method is to obtain the allocation status of computing units for the application from the OS, identify computing units that can execute subsequent processing, and then issue a wake-up instruction. In addition, by preferentially selecting computing units in which the pre-processing unit 140 is operating, the code to be newly woken up is minimized.

[0045] <Computer unit advance wake-up instruction unit 130> The processor advance wake-up instruction unit 130 issues a wake-up instruction to the processor selected by the wake-up target processor selection unit 120 to return from a power saving mode, based on a wake-up instruction from the pre-processing unit 140. Examples of realizing this function include notifications by inter-processor interrupts (IPI), eventfd, and signal.

[0046] <Pre-processing unit 140> The pre-processing unit 140, like the post-processing unit 150, is a processing unit implemented on the user application 70 of the task scheduler 100 in Fig. 1 and the task scheduler 100A in Fig. 2. The pre-processing unit 140 and the post-processing unit 150 are not affected by changes in the computing unit used because they are arranged in the user application 70. In other words, the pre-processing unit 140 is a processing unit that occurs before the computing unit used changes.

[0047] The pre-processing unit 140, which executes the first stage of parallel processing, issues a wake-up instruction to the other arithmetic units before the completion of the first stage of processing. The pre-processing unit 140 issues a wake-up instruction to the other arithmetic units at a timing that is earlier than the timing at which an increase in the number of used arithmetic units is expected by a delay time required for the arithmetic units to return from a power saving mode.

[0048] The pre-processing method of the pre-processing unit 140 includes the following processing pattern A and processing pattern B. Processing pattern A: The timing of issuing a pre-wake-up instruction is embedded when the program code of the pre-processing unit 140 is created. For example, in the example of RAN signal processing shown in the sequence of Figure 14 described later, the calculator pre-wake-up instruction unit 130 for the post-processing is embedded at the start of processing of each program for each process (FH reception process, resource element demapping process, equalization / channel estimation process, MIMO identification process, demodulation process, de-scrambling process, and de-rate matching process).

[0049] Processing pattern B: In cases where the timing of processing completion is determined, the timing of expected processing completion is calculated from the "time required for processing" stored in the processing time management table 240 by referring to the processing time management table 240 shown in FIG.

[0050] 6 is a diagram showing a processing time management table 240 that stores the time required for processing, using the name of the pre-stage process as a key. The pre-stage processing unit 140 refers to the processing time management table 240 shown in FIG. 6 and calculates the expected timing for processing completion from the "time required for processing" stored in the processing time management table 240. The pre-stage processing unit 140 then issues a pre-wake-up instruction by subtracting the maximum time required for returning from the power saving mode, obtained by querying the wake-up delay time prediction unit 170, from the calculated expected timing for processing completion.

[0051] As an example, we will outline the behavior of a processor of model number A when it executes the resource element demapping process in the sequence of FIG. 14 described below. At the start of the process, it is confirmed from the processing time management table 240 of FIG. 6 that the redmapping process will take 500 us. Furthermore, for the processor of model number A, 40 us, which is the "maximum time required to return from power saving mode", is subtracted from the wake-up delay time prediction unit 170, and a wake-up instruction is issued 460 us from the start of the previous processing. To summarize the above, the wake-up instruction in this case is expressed by the following equation (1): 460 us = 500 us - 40 us ... (1)

[0052] <Post-Processing Unit 150> Similar to the pre-processing unit 140, the post-processing unit 150 is a processing unit implemented on the user application 70 of the task scheduler 100 in Fig. 1 and the task scheduler 100A in Fig. 2. The post-processing unit 150 calls the computing unit allocation instruction unit 160, which changes and increases the number of computing units to be used.

[0053] 1, the computing unit allocation instruction unit 160 instructs the increase of the number of computing units to be used and the allocation of computing units to tasks by increasing the number of computing units to be used and allocating tasks to computing units, in response to a call from the post-stage processing unit 150. Specifically, the computing unit allocation instruction unit 160 is realized as the execution of a fork() command in Linux (registered trademark) or the increase of threads by pthread().

[0054] <Wake-up delay time prediction unit 170> The wake-up delay time prediction unit 170 acquires the model number of the processor on which the software runs and responds with the time it will take for the processor to return from a power-saving state. Here, the response to the caller (pre-processing unit) is called a wake-up delay time prediction.

[0055] 7 is a diagram showing a recovery time prediction table 250 corresponding to the power saving level recorded by the wake-up delay time prediction unit 170. The recovery time prediction table 250 records the time required for recovery from each power saving level for each processor type. For example, for processor model number A, it is recorded that the time required for recovery from power saving level 1 is 10 us, the time required for recovery from power saving level 2 is 20 us, and the time required for recovery from power saving level 3 is 40 us.

[0056] The wake-up delay time prediction unit 170 obtains the time required to return from the power saving state based on the identifier of the processor type obtained by acquiring the processor model number on which it operates, and based on the record held within the function (Figure 7: return time prediction table 250), and responds to the caller (pre-processing unit).

[0057] The operation of the computing system 1000 configured as described above will be described below. [Configuration and Premise of the Computing System] The computing system 1000 has a configuration in which tasks are processed using multiple computing units on a computer (hereinafter referred to as a server). This embodiment relates to an improvement of the state transition method of this computing system 1000.

[0058] FIG. 8 is a diagram illustrating the hardware of a server constituting the computing system 1000. FIG. 8 is a re-explanation of the hardware 50 of the server 101 of the computing system 1000 of FIG. 1. The hardware 50 includes a plurality of computing units 51 (computing unit #1), 52 (computing unit #2), 53 (computing unit #3), and 54 (computing unit #4). The computing units 51 to 54 have a "power saving mode" that reduces power consumption by stopping or reducing the computing power, and it takes a certain amount of time to return from the power saving mode.

[0059] FIG. 9 is a diagram illustrating tasks (software) processed by the computing system 1000. As shown in FIG. 9, the computing system 1000 (FIG. 1) has tasks executed on the server 101 (FIG. 1), and each task has multiple processing steps 301 to 303, each of which requires a different number of computing units for processing. In the following explanation, the number of computing units required for processing is indicated by an illustration of the computing unit 311 required for the processing. For processing step 301 (process #1), the computing unit 311 required for the processing is "1", for processing step 302 (process #2), the computing unit 311 required for the processing is "3", and for processing step 303 (process #3), the computing unit 311 required for the processing is "2". In this case, for processing step 301 (process #1), the computing unit 311 required for the processing is "1", for processing step 302 (process #2), the computing unit 311 required for the processing is "3", and for processing step 303 (process #3), the computing unit 311 required for the processing is "2". <1> In step 301 (process #1), the processing requires only one arithmetic unit 311, but in the subsequent processing step 302 (process #2), the processing requires three arithmetic units 311. In this way, a task has multiple processing steps, and the number of arithmetic units required for each processing step differs.

[0060] The task schedulers 100 and 100A (FIGS. 1 and 2) of this embodiment realize processing of tasks executed on the server 101 (FIG. 1) without extending the processing completion time and with reduced power consumption.

[0061] [Requirements] Requirement #1: (Processing completion time) The time from the start to the completion of each task's processing must not be extended (no overhead occurs). Requirement #2: (Power saving) Each computing unit must be in the maximum power saving mode.

[0062] [Application Examples and Use Cases] Use cases to which the task schedulers 100 and 100A (FIGS. 1 and 2) of this embodiment are applied will be described.

[0063] <Use Case #1> Use Case #1 is an example of application to a MIMO (multiple input multiple output) configuration in a vRAN (virtual radio access network).

[0064] FIG. 10 is a diagram showing the flow of each processing step of PHY-HIGH processing (UL) in a MIMO configuration. Components identical to those in FIG. 9 are assigned the same reference numerals. FIG. 10 shows an example of application of the task (software) of FIG. 9. The PHY-HIGH processing (UL) sequentially executes FH reception processing (processing step 401; the number of calculators 311 required for the processing (hereinafter simply referred to as the number of calculators) is "1"), resource element demapping (processing step 402; the number of calculators is "1"), equalization processing channel estimation (processing step 403; the number of calculators is "3"), MIMO identification (processing step 404; the number of calculators is "2"), demodulation (processing step 405; the number of calculators is "3"), De-Scram (processing step 406; the number of calculators is "1"), De-RateMatch (processing step 407; the number of calculators is "1"), and LDPCDecode (processing step 408; the number of calculators is "1").

[0065] Of the PHY-HIGH processing (UL) described above, equalization processing channel estimation (processing step 403), MIMO identification (processing step 404), and demodulation (processing step 405) are processes 409 that require high parallelism for calculation, and each task requires three arithmetic units.

[0066] In the present embodiment, when a process requiring a high degree of parallelism for such calculations (a task requiring a large number of required arithmetic units) is known (anticipated) in advance, the task scheduler 100, 100A (FIGS. 1 and 2) issues a wake-up instruction before executing the process requiring a high degree of parallelism for calculations, i.e., during or before the preceding process. In the example of FIG. 10 , a wake-up instruction is issued at the timing of resource element demapping (processing step 402; number of arithmetic units: "1"), which precedes equalization channel estimation (processing step 403), thereby enabling multithreading without delay. This allows the task scheduler 100, 100A to increase the degree of parallelism in PHY-HIGH processing (UL) without wake-up latency.

[0067] <Use Case #2> Use Case #2 is an example of application to AI inference using a CNN (Convolutional Neural Network).

[0068] FIG. 11 is a diagram showing the flow of each processing step of AI inference using CNN. The same components as in FIG. 9 are assigned the same reference numerals. FIG. 11 shows an example of application of the task (software) in FIG. 9. In AI inference, image input (processing step 501; number of processors: 1), convolution processing (processing step 502; number of processors: 3), activation processing (processing step 503; number of processors: 2), pooling processing (processing step 504; number of processors: 2), full connection (processing step 505; number of processors: 2), and output (processing step 506; number of processors: 1) are executed in sequence.

[0069] Of the AI ​​inference processes described above, the convolution process (processing step 502) is a process that requires a high degree of parallelism in calculations, and requires three arithmetic units to execute the task.

[0070] 11, advance wake-up c is instructed at the timing of image input (processing step 501; number of arithmetic units "1"), and multithreading is performed without delay. This enables the task schedulers 100 and 100A to increase the degree of parallelism in AI inference without wake-up latency.

[0071] [Basic Concept] Fig. 12 is a diagram illustrating the basic concept of the task scheduling method of the task schedulers 100, 100A (Figs. 1 and 2) of this embodiment. Fig. 12 is contrasted with the existing technology of Fig. 24. In Fig. 12, the server 101 (Fig. 1) is equipped with multiple computing units #0 to #2, and parallel processing tasks are assigned to each of the computing units #0 to #2. The parallel processing tasks are assigned to each of the computing units #0 to #2, and computing unit #1 sequentially executes one of the parallel processing tasks, a pre-processing 21 with a low degree of parallelism, followed by a post-processing start instruction 24 and a post-processing 26-1.

[0072] In this embodiment, a pre-processing task with low parallelism, pre-processing 21, issues a pre-wake-up instruction 22 to computing units #0 and #2, which are used in the post-processing. That is, the pre-processing task with low parallelism, pre-processing 21, executes computing unit #1, which executes post-processing 26-1 through a post-processing start instruction 24. Meanwhile, the other computing units #0 and #2 issue a pre-wake-up instruction 22 at the pre-processing task with low parallelism to execute post-processing 26-0 and 26-2, which are post-processing tasks. This wakes up computing units #0 and #2 in advance from the sleep state. Computing unit #0 is woken up from the sleep state by wake-up processing 25-0. Computing unit #2 is woken up from the sleep state by wake-up processing 25-2.

[0073] Here, in order for computing unit #1 to execute advance wake-up instruction d in pre-processing 21 with a low degree of parallelism, an existing application must be modified or it must be transparently implemented using middleware. In an example of modifying an application, a task scheduler 100 is provided in a user application 70 shown in FIG. 1. In an example of transparent implementation using middleware, the functions of task scheduler 100A (a unit 110 for estimating the number of computing units required for post-processing, a unit 120 for selecting computing units to be woken up, a computing unit advance wake-up instruction unit 130, a computing unit allocation instruction unit 160, and a pre-processing unit library function unit 180) are arranged in a middleware layer 80 of user application 70 shown in FIG.

[0074] As shown in FIG. 12 , the task scheduler 100, 100A (FIGS. 1 and 2) issues a pre-wake-up instruction from the pre-processing task to the computing unit that executes the post-processing. By issuing a pre-wake-up instruction to the computing unit that executes the post-processing task in the pre-processing task, delay time reduction and power saving are both achieved. As can be seen by comparing the present embodiment in FIG. 12 with the existing technology in FIG. 24 , by pre-wake-up the computing unit that executes the post-processing task, it is possible to achieve both no delay in processing completion (the period of wake-up processing f in FIG. 12 is shortened) and sleep of the computing unit (computing units #0 and #2 remain in a sleep state until the pre-wake-up instruction d in FIG. 12 is executed).

[0075] [Operation Flow of Task Scheduler 100, 100A] Figure 13 is a flowchart showing the task scheduling process of task scheduler 100, 100A. In step S11, pre-processing unit 140 issues a pre-wake-up instruction, which is a call to pre-wake-up processing from the processing corresponding to the pre-stage of parallel processing. Furthermore, pre-processing unit 140 issues the pre-wake-up instruction at a timing that is earlier than the timing at which the number of arithmetic units used is expected to increase, by the delay time required for the arithmetic units to return from power-saving mode. For example, pre-processing unit 140 may embed the timing of issuing the pre-wake-up instruction into its program code when it is created (processing pattern A). Furthermore, pre-processing unit 140 may refer to processing time management table 240 shown in Figure 6 and calculate the expected timing of processing completion from the "time required for processing" stored in processing time management table 240 (processing pattern B).

[0076] In step S12, the unit 110 for estimating the number of computing units required for subsequent processing calculates the number of computing units required for subsequent processing. For example, the unit 110 for estimating the number of computing units required for subsequent processing references the management table 210 for the number of computing units required for subsequent processing (FIG. 3) to set a fixed number of computing units for subsequent processing for each function of the previous processing (Pattern #1). The unit 110 for estimating the number of computing units required for subsequent processing calculates the number of computing units required for subsequent processing by calculation using the management table 220 for the number of computing units required for subsequent processing (FIG. 4), which stores the ratio of the number of computing units required for subsequent processing to the number of computing units required for subsequent processing (Pattern #2). The unit 110 for estimating the number of computing units required for subsequent processing references the management table 230 for the number of computing units required for subsequent processing (FIG. 4), which stores the actual number of computing units used in subsequent processing linked to each previous processing unit, to calculate the number of computing units required for subsequent processing (Pattern #3).

[0077] In step S13 , the wake-up target computing unit selection unit 120 selects a computing unit to be woken up based on the number of required cores calculated by the unit 110 for estimating the number of computing units required for subsequent processing.

[0078] In step S14, the arithmetic unit advance wake-up instruction unit 130 issues a wake-up instruction to the arithmetic unit selected by the wake-up target arithmetic unit selection unit 120.

[0079] In step S15, the post-processing unit 150 calls the computing unit allocation instruction unit 160, which changes and increases the number of computing units to be used.

[0080] In step S16, the computing unit allocation instruction unit 160 receives a call from the post-processing unit 150, increases the number of computing units to be used and instructs the task allocation to the computing units, thereby completing the processing of this flow.

[0081] [Example of application to a radio signal processing application] Figure 14 is a flowchart showing an operation sequence when this task scheduling method is applied to a radio signal processing application in a RAN. This is an example of application to PHY-HIGH processing (UL) in the MIMO configuration of Figure 10. In step S101, the computer executes the PHY-HIGH processing (UL) application and executes FH reception processing using the corresponding arithmetic unit.

[0082] In step S102, the computer executes resource element demapping for the PHY-HIGH processing (UL) application. This resource element demapping process has one arithmetic unit, as shown in FIG. 10 . The subsequent equalization channel estimation process has three arithmetic units, and it is known in advance that this process requires high parallelism for calculation. For this reason, the task scheduler 100, 100A introduces this resource element demapping process as pre-processing and the equalization channel estimation process as post-processing into the pre-processing resource element demapping process. Specifically, in the resource element demapping process of step S102, the task scheduler 100, 100A shown in FIG. 13 executes task scheduling. In FIG. 13 , a pre-wake-up is instructed at the timing of resource element demapping, which precedes equalization channel estimation, to achieve multithreading without delay.

[0083] Thereafter, in step S103, the computer executes equalization processing channel estimation processing (number of calculators: "3"). In step S104, the computer executes MIMO identification processing (number of calculators: "2"). In step S105, the computer executes demodulation processing (number of calculators: "3"). In step S106, the computer executes De-Scram processing (number of calculators: "1"). In step S107, the computer executes De-RateMatch processing (number of calculators: "1").

[0084] Of the PHY-HIGH processing (UL), equalization processing channel estimation (processing step 403), MIMO identification (processing step 404), and demodulation (processing step 405) are processes that require a high degree of parallelism for calculation, and each task requires three computing units.

[0085] In the present embodiment, when a process requiring a high degree of parallelism for such calculations (a task requiring a large number of required arithmetic units) is known (anticipated) in advance, the task scheduler 100, 100A (FIGS. 1 and 2) issues a wake-up instruction before executing the process requiring a high degree of parallelism for calculations, i.e., during or before the preceding process. In the example of FIG. 10 , a wake-up instruction is issued at the timing of resource element demapping (processing step 402; number of arithmetic units: "1"), which precedes equalization channel estimation (processing step 403), thereby enabling multithreading without delay. This allows the task scheduler 100, 100A to increase the degree of parallelism in PHY-HIGH processing (UL) without wake-up latency.

[0086] [Hardware Configuration] The task schedulers 100, 100A (FIGS. 1 and 2) according to the above embodiments are realized by a computer 900 having a configuration such as that shown in FIG. 15. FIG. 15 is a hardware configuration diagram showing an example of the computer 900 that realizes the functions of the task schedulers 100, 100A (FIGS. 1 and 2). The computer 900 has a CPU 901, a ROM 902, a RAM 903, a HDD 904, a communication interface (I / F) 906, an input / output interface (I / F) 905, and a media interface (I / F) 907.

[0087] The CPU 901 operates based on programs stored in the ROM 902 or the HDD 904, and controls each part of the task scheduler 100, 100A (FIGS. 1 and 2). The ROM 902 stores a boot program executed by the CPU 901 when the computer 900 starts up, programs that depend on the hardware of the computer 900, and the like.

[0088] The CPU 901 controls an input device 910 such as a mouse or keyboard, and an output device 911 such as a display, via an input / output I / F 905. The CPU 901 acquires data from the input device 910 via the input / output I / F 905, and outputs generated data to the output device 911. Note that a GPU (Graphics Processing Unit) or the like may be used as a processor together with the CPU 901.

[0089] The HDD 904 stores programs executed by the CPU 901 and data used by the programs. The communication I / F 906 receives data from other devices via a communication network (e.g., NW (Network) 920) and outputs the data to the CPU 901, and also transmits data generated by the CPU 901 to other devices via the communication network.

[0090] The media I / F 907 reads a program or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903. The CPU 901 loads a program related to a target process from the recording medium 912 onto the RAM 903 via the media I / F 907, and executes the loaded program. The recording medium 912 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phase Change Rewritable Disc), a magneto-optical recording medium such as an MO (Magneto Optical Disc), a magnetic recording medium, a conductive memory tape medium, a semiconductor memory, or the like.

[0091] For example, when the computer 900 functions as the task scheduler 100, 100A (FIGS. 1 and 2) configured as one device according to this embodiment, the CPU 901 of the computer 900 realizes the functions of the task scheduler 100, 100A by executing a program loaded onto the RAM 903. The HDD 904 also stores data in the RAM 903. The CPU 901 reads and executes a program related to a target process from a recording medium 912. Alternatively, the CPU 901 may read a program related to a target process from another device via a communication network (NW 920).

[0092] [Effects] As described above, the task scheduler 100, 100A (FIGS. 1 and 2) includes a plurality of arithmetic units 51 to 54 having a power saving mode that reduces power consumption by stopping or reducing the computing capability, an arithmetic unit allocation instruction unit 160 that assigns a task to one of the plurality of arithmetic units 51 to 54, a pre-stage processing unit 140 in which an arithmetic unit that executes a pre-stage process of parallel processing issues a wake-up instruction to the other arithmetic units before the completion of the pre-stage process, and an arithmetic unit advance wake-up instruction unit 130 that issues an instruction to the selected other arithmetic units to return the other arithmetic units from the power saving mode based on the wake-up instruction.

[0093] In this way, the task scheduler 100, 100A issues a pre-wake-up instruction from the pre-processing task to the computing unit used in the post-processing. By waking up from the pre-processing stage, it is possible to eliminate delays when parallel processing starts and set the power-saving mode as the default state. This allows the return from the power-saving mode to be completed when parallel processing starts, thereby suppressing delays while transitioning to the power-saving mode when there is no processing. It is possible to satisfy the requirement #1 "processing completion time" while satisfying the requirement #2 "power saving." As a result, tasks executed on the server can be processed in a power-saving manner without extending the processing completion time.

[0094] In the task scheduler 100, 100A (Figures 1 and 2), the pre-processing unit 140 issues a pre-wake-up instruction at a timing that is earlier than the timing at which an increase in the number of used arithmetic units is expected, by the delay time required for the arithmetic units to return from power saving mode.

[0095] In tasks that use multiple arithmetic units, there are cases where tasks have different arithmetic unit arrangements and numbers of arithmetic units that are used in a fixed order. In these cases, there may be no signs of an increase in CPU usage or no temporal periodicity. The task scheduler 100, 100A can achieve both delay time reduction and power saving by issuing a pre-wake-up instruction from the pre-processing task to the arithmetic units used in the post-processing at a timing when an increase in the number of operators used is expected.

[0096] The task scheduler 100, 100A (FIGS. 1 and 2) includes a unit 110 for estimating the number of operators required for subsequent processing in parallel, based on information from the unit 140 for estimating the number of operators required for subsequent processing in parallel, and a unit 120 for selecting operators to be woken up, based on the number of operators required calculated by the unit 110 for estimating the number of operators required for subsequent processing.

[0097] In this way, the task scheduler 100, 100A can minimize the number of arithmetic units to be pre-wakeup and enhance the power saving effect by estimating the number of arithmetic units required for the subsequent parallel processing based on information from the pre-processing unit 140. In other words, it is possible to minimize the number of arithmetic units to be pre-wakeup.

[0098] Also, a computing system 1000 (Figures 1 and 2) includes computing units 51 to 54 having a power saving mode that reduces power consumption by stopping or reducing their computing capabilities, and includes a task scheduler 100, 100A (Figures 1 and 2) that assigns tasks to the computing units 51 to 54, and the task scheduler 100, 100A includes a plurality of computing units 51 to 54 having a power saving mode that reduces power consumption by stopping or reducing their computing capabilities, a computing unit assignment instruction unit 160 that assigns a task to one of the plurality of computing units 51 to 54, a front-end processing unit 140 in which a computing unit that executes a front-end process of parallel processing issues a wake-up instruction to other computing units before the front-end process is completed, and a computing unit advance wake-up instruction unit 130 that issues an instruction to the selected other computing units to return the other computing units from the power saving mode based on the wake-up instruction.

[0099] In this way, the computing system 1000, which includes the task schedulers 100 and 100A (FIGS. 1 and 2), can process tasks executed on a server during state transitions without extending the processing completion time and with reduced power consumption. The computing system 1000 can also be applied to processors other than CPUs, such as GPUs, FPGAs, and ASICs, if they have an idle state function.

[0100] In this embodiment, the task schedulers 100 and 100A (FIGS. 1 and 2) are implemented in the user application 70, but they may be implemented in the OS kernel.

[0101] Furthermore, among the processes described in the above embodiments, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically using known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings can be changed as desired unless otherwise specified. Furthermore, the components of each device shown in the drawings are functionally conceptual and do not necessarily have to be physically configured as shown. In other words, the specific form of distribution and integration of each device is not limited to that shown in the drawings, and all or part of the devices can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0102] Furthermore, the above-described configurations, functions, processing units, processing means, etc. may be partially or entirely implemented in hardware, for example, by designing them as integrated circuits. The above-described configurations, functions, etc. may also be implemented by software that causes a processor to interpret and execute programs that implement the respective functions. Information such as programs, tables, and files that implement the respective functions may be stored in a memory, a recording device such as a hard disk or a solid-state drive (SSD), or a recording medium such as an integrated circuit (IC) card, a secure digital (SD) card, or an optical disk.

[0103] 50 Hardware 51 to 54 Calculating units 70 User application 80 Middleware layer 100, 100A Task scheduler (task scheduler device) 110 Estimation unit for number of calculating units required for subsequent processing 120 Wake-up target calculating unit selection unit 130 Calculating unit advance wake-up instruction unit 140 Pre-processing unit 150 Post-processing unit 160 Calculating unit allocation instruction unit 170 Wake-up delay time prediction unit 180 Pre-processing unit library function unit 210 Management table for number of calculating units required for subsequent processing 220 Management table for ratio of number of calculating units required for subsequent processing 230 Management table for number of calculating units required for subsequent processing actual result 240 Processing time management table 250 Recovery time prediction table 1000 Computing system

Claims

1. A task scheduler device comprising: a plurality of arithmetic units having a power saving mode that reduces power consumption by stopping or reducing computing capabilities; an arithmetic unit allocation instruction unit that assigns a task to one of the plurality of arithmetic units; a front-end processing unit in which an arithmetic unit that executes a front-end process of parallel processing issues a wake-up instruction to other arithmetic units before the front-end process is completed; and an arithmetic unit advance wake-up instruction unit that issues an instruction to a selected one of the other arithmetic units to return the other arithmetic units from the power saving mode based on the wake-up instruction.

2. The task scheduler device according to claim 1, characterized in that the pre-processing unit issues an advance wake-up instruction to cause the other arithmetic units to return from power-saving mode at a timing that is earlier than the timing at which an increase in the number of arithmetic units is expected, by a delay time required for the other arithmetic units to return from power-saving mode.

3. The task scheduler device according to claim 1, further comprising: a post-processing required number of arithmetic units estimation unit that estimates the number of arithmetic units required for subsequent parallel processing based on information from the pre-processing unit; and a wake-up target arithmetic unit selection unit that selects other arithmetic units to be woken up based on the number of required arithmetic units calculated by the post-processing required number of arithmetic units estimation unit.

4. A program for causing a computer to function as the task scheduler device according to any one of claims 1 to 3.

Images