Solid-state imaging device

Abstract

[Problem] The present invention addresses the problem of enabling switching between a blooming suppression mode and a high saturation charge mode to be performed more appropriately even during pipeline driving. [Solution] A solid-state imaging device according to the present invention includes: a photoelectric conversion unit that generates an electric charge that corresponds to a received light amount by photoelectric conversion; a plurality of transistors that are connected between the photoelectric conversion unit and a first reference voltage node and are connected in series; a first transfer transistor that has one end electrically connected to the photoelectric conversion unit and transfers the electric charge accumulated in the photoelectric conversion unit; a charge-holding unit that holds the electric charge transferred by the first transfer transistor; a second transfer transistor that transfers the electric charge held by the charge-holding unit; and a charge accumulation unit that accumulates the electric charges transferred by the second transfer transistor. The electric charges between the plurality of transistors connected in series are transferred to the charge accumulation unit via the charge-holding unit.

Description

solid-state imaging device

[0001] An embodiment of the present disclosure relates to a solid-state imaging device.

[0002] In a global shutter sensor, a technology is known that suppresses blooming from the photoelectric conversion unit to the charge storage unit by turning on an anti-blooming gate while the charge storage unit is storing signal charge (see Patent Document 1). By using this technology, it is possible to dynamically change the potential barrier of the photoelectric conversion unit, thereby ensuring the saturation charge amount (saturation signal amount) of the photoelectric conversion unit and suppressing blooming at the same time.

[0003] Also known is a configuration in which a second charge holding section is provided at the overflow destination of the charge from the photoelectric conversion section, thereby suppressing blooming and ensuring a saturated charge amount (see Patent Document 2).

[0004] JP 2004-111590 A JP 2017-108275 A

[0005] However, in Patent Document 1, when attempting to control the blooming suppression ratio using the anti-blooming gate voltage under the constraint of maintaining good dark characteristics during pipeline driving of exposure and readout of the charge storage unit MEM, it is difficult to switch between the blooming suppression mode and the high saturation charge mode. Also, in Patent Document 2, in pipeline driving, if charge overflows from the photoelectric conversion unit before AD (analog-to-digital) conversion, the overflowed charge is superimposed on the signal charge of the previous frame stored in the second charge storage unit, making pipeline driving impossible.

[0006] Therefore, the present disclosure provides a semiconductor device that can more appropriately switch between the blooming suppression mode and the high saturation charge amount mode even during pipeline driving.

[0007] In order to solve the above problem, according to the present disclosure, there is provided a solid-state imaging device comprising: a photoelectric conversion unit that generates charges according to the amount of received light through photoelectric conversion; a plurality of transistors that are connected in series between the photoelectric conversion unit and a first reference voltage node; a first transfer transistor that has one end electrically connected to the photoelectric conversion unit and transfers charges accumulated in the photoelectric conversion unit; a charge holding unit that holds the charges transferred by the first transfer transistor; a second transfer transistor that transfers the charges held by the charge holding unit; and a charge accumulation unit that accumulates the charges transferred by the second transfer transistor, wherein the charges between the plurality of series-connected transistors are transferred to the charge accumulation unit via the charge holding unit.

[0008] The plurality of series-connected transistors may include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, wherein a channel potential of the first transistor when off is lower than a channel potential of the first transfer transistor when off, and a channel potential of the second transistor when off is higher than a channel potential of the first transistor when off.

[0009] A channel potential of the second transistor when it is off may be substantially the same as a channel potential of the first transfer transistor when it is off.

[0010] The plurality of series-connected transistors may further include one or more third transistors connected between the first transistor and the second transistor, and the channel potential of the third transistor when off may be between the channel potential of the first transistor when off and the channel potential of the second transistor when off.

[0011] The plurality of series-connected transistors may include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, and an active region between the first transistor and the second transistor may be electrically connected to a channel portion of the first transfer transistor.

[0012] The plurality of serially connected transistors may include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, wherein the second transistor may be in an on state at the start of an exposure period and may be turned off during the exposure period after completion of reading out of the charge storage units of all pixel rows.

[0013] The plurality of serially connected transistors may include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, and the second transistor may be driven at an intermediate voltage between an on voltage and an off voltage during an exposure period.

[0014] The plurality of series-connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node; the pixel may further include a first pixel and a second pixel each having the photoelectric conversion unit, the first transistor, the first transfer transistor, the charge holding unit, and the second transfer transistor; the second transistor may be shared by the first pixel and the second pixel; and a node between the first transistor and the second transistor may be short-circuited between the first pixel and the second pixel.

[0015] Charges overflowing from the photoelectric conversion unit of one of the first pixel and the second pixel may be accumulated in the photoelectric conversion unit of the other.

[0016] The device may further include a first chip and a second chip stacked on the first chip, wherein the photoelectric conversion unit, the plurality of transistors connected in series, the first transfer transistor, the charge holding unit, and the second transfer transistor are arranged on the first chip, and the charge storage unit is arranged on the second chip.

[0017] It may also be a back-illuminated MOS imaging device.

[0018] 1 is a diagram showing an example of the configuration of a CMOS image sensor to which the present technology is applied; FIG. 1 is a circuit diagram showing an example of the configuration of a unit pixel according to a first embodiment; FIG. 2 is a timing chart showing an example of the operation of a unit pixel according to the first embodiment; FIG. 3 is a schematic diagram showing an example of a potential state of a unit pixel according to the first embodiment; FIG. 4 is a timing chart showing an example of the operation of a unit pixel according to the first embodiment; FIG. 5 is a schematic diagram showing an example of a potential state of a unit pixel according to the first embodiment; FIG. 6 is a circuit diagram showing an example of the configuration of a unit pixel according to a second embodiment; FIG. 7 is a timing chart showing an example of the operation of a unit pixel according to the second embodiment; FIG. 8 is a schematic diagram showing an example of a potential state of a unit pixel according to the second embodiment; FIG. 9 is a timing chart showing an example of the operation of a unit pixel according to the third embodiment; FIG. 10 is a timing chart showing an example of the operation of a unit pixel according to a fourth embodiment; FIG. 11 is a schematic diagram showing an example of a potential state of a unit pixel according to the fourth embodiment; FIG. 12 is a circuit diagram showing an example of the configuration of a unit pixel according to a fifth embodiment; FIG. 13 is a plan view showing an example of the layout of a unit pixel according to the fifth embodiment; FIG. 14 is a circuit diagram showing an example of the configuration of a unit pixel according to a sixth embodiment; FIG. 15 is a schematic diagram showing an example of a potential state of a unit pixel according to the sixth embodiment; FIG. 16 is a schematic diagram showing an example of a potential state of a unit pixel according to the sixth embodiment; FIG. 10 is a circuit diagram showing a configuration example of a unit pixel according to a seventh embodiment. FIG. 11 is a cross-sectional view showing a configuration example of a unit pixel according to an eighth embodiment. FIG. 12 is a cross-sectional view showing a configuration example of a unit pixel according to a ninth embodiment. FIG. 13 is a circuit diagram showing a configuration example of a unit pixel according to a tenth embodiment. FIG. 14 is a schematic view showing an example of a potential state of a unit pixel according to a tenth embodiment. FIG. 15 is a schematic view showing an example of a potential state of a unit pixel according to a tenth embodiment. FIG. 16 is a block diagram showing an example of the general configuration of a vehicle control system. FIG. 17 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0019] Hereinafter, an embodiment of a solid-state imaging device will be described with reference to the drawings. The following description will focus on the main components of the solid-state imaging device, but the solid-state imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0020] First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a CMOS (Complementary Metal Oxide Semiconductor) image sensor as a solid-state imaging device to which the present technology is applied.

[0021] The CMOS image sensor 10 includes a pixel array section 11, a vertical drive section 12, a column processing section 13, a horizontal drive section 14, and a system control section 15. The pixel array section 11, the vertical drive section 12, the column processing section 13, the horizontal drive section 14, and the system control section 15 are formed on a semiconductor substrate (chip) not shown.

[0022] Unit pixels (unit pixels 50 in FIG. 2 ) each having a photoelectric conversion element that generates and internally accumulates photocharges whose amount corresponds to the amount of incident light are arranged two-dimensionally in a matrix in the pixel array section 11. Hereinafter, the photocharges whose amount corresponds to the amount of incident light may be simply referred to as “charges,” and unit pixels may be simply referred to as “pixels.”

[0023] The pixel array unit 11 further includes pixel drive lines 16 formed for each row of the matrix-like pixel arrangement in the left-right direction of the drawing (the direction in which the pixels in the pixel rows are arranged), and vertical signal lines 17 formed for each column in the up-down direction of the drawing (the direction in which the pixels in the pixel columns are arranged). One end of each pixel drive line 16 is connected to an output terminal of the vertical drive unit 12 corresponding to each row.

[0024] The CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19. The signal processing unit 18 and the data storage unit 19 may be external signal processing units provided on a board separate from the CMOS image sensor 10, such as a DSP (Digital Signal Processor) or software-based processing, or may be mounted on the same board as the CMOS image sensor 10.

[0025] The vertical drive unit 12 is a pixel drive unit that is configured with a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 11 all at once or in units of rows, etc. Although the specific configuration of this vertical drive unit 12 is not shown in the figure, it is configured to have a readout scanning system and a sweep-out scanning system or a batch sweep-out and batch transfer system.

[0026] The readout scanning system sequentially selects and scans the unit pixels of the pixel array section 11 row by row to read out signals from the unit pixels. In the case of row driving (rolling shutter operation), sweep-out scanning is performed for the readout row to be read out by the readout scanning system, the sweep-out scanning is performed a time period equal to the shutter speed before the readout scanning. In the case of global exposure (global shutter operation), batch sweep-out is performed a time period equal to the shutter speed before the batch transfer.

[0027] This sweeping sweeps out (resets) unnecessary charges from the photoelectric conversion elements of the unit pixels in the readout row. The sweeping out (resetting) of unnecessary charges then performs a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charges in the photoelectric conversion elements and starting a new exposure (starting the accumulation of photoelectric charges).

[0028] The signal read by the readout operation by the readout scanning system corresponds to the amount of light that has entered since the previous readout operation or electronic shutter operation. In the case of row driving, the period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation period (exposure period) of the photocharge in the unit pixel. In the case of global exposure, the period from the batch sweep to the batch transfer is the accumulation period (exposure period).

[0029] The pixel signals output from each unit pixel in a pixel row selected and scanned by the vertical drive unit 12 are supplied to the column processing unit 13 through each vertical signal line 17. The column processing unit 13 performs predetermined signal processing on the pixel signals output from each unit pixel in the selected row through the vertical signal line 17 for each pixel column in the pixel array unit 11, and temporarily holds the pixel signals after signal processing.

[0030] Specifically, the column processing unit 13 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing, as signal processing. This correlated double sampling by the column processing unit 13 removes pixel-specific fixed pattern noise such as reset noise and threshold voltage variations of the amplification transistor. In addition to the noise removal processing, the column processing unit 13 can also be provided with, for example, an AD (analog-digital) conversion function, so as to output the signal level as a digital signal.

[0031] The horizontal driving unit 14 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 13. By selective scanning by this horizontal driving unit 14, pixel signals that have been signal-processed by the column processing unit 13 are sequentially output to the signal processing unit 18.

[0032] The system control unit 15 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 12, column processing unit 13, horizontal driving unit 14, etc. based on the various timing signals generated by the timing generator.

[0033] The signal processing unit 18 has at least an addition processing function and performs various signal processing such as addition processing on the pixel signals output from the column processing unit 13. The data storage unit 19 temporarily stores data necessary for signal processing in the signal processing unit 18.

[0034] Next, a specific structure of the unit pixels 50 arranged in a matrix in the pixel array section 11 of FIG. 1 will be described.

[0035] FIG. 2 is a circuit diagram showing an example of the configuration of the unit pixel 50 according to the first embodiment.

[0036] 2, the unit pixel 50 includes a photoelectric conversion unit 51, two transfer transistors TRX and TRG, two discharge transistors OG1 and OG2, a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. These transistors are, for example, N-type MOS transistors.

[0037] The following mainly describes an example in which a photodiode PD is used as the photoelectric conversion unit 51. The charge (pixel signal) photoelectrically converted by the photodiode PD is transferred and read out.

[0038] A charge holding unit MEM is connected to the transfer transistor TRX. The potential of the charge holding unit MEM is controlled by a control signal applied to the gate electrode of the transfer transistor TRX. For example, when the transfer transistor TRX is turned on, the potential of the charge holding unit MEM deepens, and when the transfer transistor TRX is turned off, the potential of the charge holding unit MEM shallows. Then, for example, when the transfer transistor TRX is turned on, the charge stored in the photodiode PD is transferred to the charge holding unit MEM via the transfer transistor TRX. The drain of the transfer transistor TRX is electrically connected to the source of the transfer transistor TRG, and the gate of the transfer transistor TRX is connected to a pixel drive line.

[0039] The charge holding unit MEM is an area that temporarily holds the charge accumulated in the photodiode PD in order to realize a global shutter function. The charge holding unit MEM holds the charge transferred from the photodiode PD.

[0040] The transfer transistor TRG is connected between the transfer transistor TRX and the floating diffusion FD, and transfers the charges held in the charge holding unit MEM to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor TRX is turned off and the transfer transistor TRG is turned on, the charges held in the charge holding unit MEM are transferred to the floating diffusion FD. The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TRG is connected to a pixel drive line.

[0041] The floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor TRG. The floating diffusion FD is connected to, for example, a reset transistor RST and also to a vertical signal line 17 via an amplification transistor AMP and a selection transistor SEL.

[0042] The drain transistors OG1 and OG2 initialize (reset) the photodiode PD in response to a control signal applied to the gate electrode. The drain transistors OG1 and OG2 are connected in series between the photodiode PD and the overflow drain (Drain). The overflow drain is a fixed power supply. The overflow drain is, for example, the power supply line VDD, but may also be a power supply of the same level as the power supply line VDD. The drain of the drain transistor OG2 is connected to the power supply line VDD, and the source is connected to the drain of the drain transistor OG1. The drain of the drain transistor OG1 is connected to the source of the drain transistor OG2, and the source is connected to the photodiode PD.

[0043] For example, when the drain transistors OG1 and OG2 are turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. That is, the photodiode PD is initialized. Furthermore, the drain transistors OG1 and OG2 form an overflow path between the photodiode PD and the power supply line VDD, and discharge the charge overflowing from the photodiode PD to the power supply line VDD.

[0044] The reset transistor RST initializes (resets) each region from the charge holding unit MEM to the floating diffusion FD in response to a control signal applied to the gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD, and the source is connected to the floating diffusion FD. For example, when the transfer transistor TRG and the reset transistor RST are turned on, the potentials of the charge holding unit MEM and the floating diffusion FD are reset to the potential level of the power supply line VDD. In other words, turning on the reset transistor RST initializes the charge holding unit MEM and the floating diffusion FD.

[0045] The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as an input part of a source follower circuit that reads out charges obtained by photoelectric conversion in the photodiode PD. That is, the amplifier transistor AMP has a source connected to the vertical signal line 17 via the selection transistor SEL, and thereby forms a source follower circuit together with a constant current source connected to one end of the vertical signal line 17.

[0046] The selection transistor SEL is connected between the source of the amplification transistor AMP and the vertical signal line 17, and a control signal is supplied as a selection signal to the gate electrode of the selection transistor SEL. When the control signal is turned on, the selection transistor SEL becomes conductive, and the unit pixel 50 connected to the selection transistor SEL becomes selected. When the unit pixel 50 becomes selected, a pixel signal output from the amplification transistor AMP is read out to the column processing unit 13 via the vertical signal line 17.

[0047] Next, the operation of the drain transistors OG1 and OG2 will be described. Depending on whether the drain transistor OG2 is turned on or off during the exposure period, the unit pixel 50 operates in either the high saturation charge amount mode or the blooming suppression mode.

[0048] Fig. 3 is a timing chart showing an example of the operation of the unit pixel 50 according to the first embodiment. Fig. 4 is a schematic diagram showing an example of the potential state of the unit pixel 50 according to the first embodiment. In the example shown in Fig. 3, the transistor is turned on by a high control voltage (on voltage) and turned off by a low control voltage (off voltage).

[0049] 3 and 4 are diagrams for explaining the high saturation charge mode.

[0050] In the initial state, the drain transistors OG1 and OG2 are in the on state, and therefore the photodiode PD is initialized.

[0051] First, at time t1, the drain transistor OG1 is turned off, thereby starting an exposure period. The exposure period is the period from when the drain transistor OG1 is turned on until the transfer transistor TRX is turned on and then off again.

[0052] Next, at time t2, the drain transistor OG2 is turned off. As a result, as shown in FIG. 4, the potential barrier of the photodiode PD becomes even higher than when the drain transistor OG2 is on. As a result, blooming tends to worsen, but the saturation charge amount can be increased. This state is called the high saturation charge amount mode.

[0053] The channel potential of the drain transistor OG2 when it is off is higher than the channel potential of the drain transistor OG1 when it is off, and is approximately the same as the channel potential of the transfer transistor TRX when it is off.

[0054] Next, at time t3, the transfer transistor TRG and the reset transistor RST are turned on, thereby initializing the floating diffusion FD and the charge holding unit MEM.

[0055] Next, at time t4, the transfer transistor TRG is turned off.

[0056] Next, at time t5, the reset transistor RST is turned off.

[0057] Next, at time t6, the transfer transistor TRX is turned on, whereby the charge stored in the photodiode PD is transferred to the charge holding unit MEM.

[0058] Next, at time t7, the transfer transistor TRX is turned off, thereby ending the exposure period.

[0059] Next, at time t8, the drain transistors OG1 and OG2 are turned on, thereby initializing the photodiode PD.

[0060] 5 and 6 are diagrams illustrating the blooming suppression mode.

[0061] Fig. 5 is a timing chart showing an example of the operation of the unit pixel 50 according to the first embodiment. Fig. 6 is a schematic diagram showing an example of the potential state of the unit pixel 50 according to the first embodiment.

[0062] As shown in FIG. 5, the drain transistor OG2 remains on during the exposure period.

[0063] When the drain transistor OG1 is turned off at time t1, the potential barrier opens more than the potential barrier in the high saturation charge mode, as shown in FIG. 6 . Charges overflowing from the photodiode PD are selectively drained to the overflow drain. This makes it possible to further suppress blooming. This state is called the blooming suppression mode.

[0064] The channel potential of the drain transistor OG1 when it is off is lower than the channel potential of the transfer transistor TRX when it is off. As a result, the charge overflowing from the photodiode PD does not flow to the transfer transistor TRX, but flows to the overflow drain via the drain transistors OG1 and OG2.

[0065] As described above, according to the first embodiment, the photodiode PD is initialized by turning on both the discharge transistors OG1 and OG2. When exposure begins, the discharge transistor OG1 is turned off. Depending on whether the discharge transistor OG2 is turned on or off during the exposure period, the unit pixel 50 operates in either the high saturation charge mode or the blooming suppression mode. The user can select and switch between modes at will, for example, depending on the subject or the shooting scene.

[0066] Furthermore, the charge between the series-connected discharge transistors OG1 and OG2 is transferred to the floating diffusion FD via the charge holding unit MEM, thereby enabling more appropriate switching between the blooming suppression mode and the high saturation charge mode even during pipeline driving.

[0067] In the case of a single drain transistor, if the drain transistor is turned on during pipeline operation of exposure and readout of the charge storage unit MEM, there is a possibility that unpinning of the interface may occur. Furthermore, if the drain transistor is turned on at an on-voltage that does not unpin, it becomes difficult to suppress blooming. If an attempt is made to sufficiently suppress blooming even at a low on-voltage, the channel does not close sufficiently even when the transistor is off, resulting in a decrease in the saturation charge amount. In other words, when attempting to control the blooming suppression ratio with the on-voltage of the drain transistor under the constraints of maintaining pipeline operation and good dark characteristics, it is difficult to switch between the blooming suppression mode and the high saturation charge amount mode.

[0068] In contrast, in the first embodiment, when the drain transistor OG2 is turned on during the exposure period, the dark signal generated at the interface of the drain transistor OG2 is discharged to the overflow drain, thereby suppressing deterioration of the dark characteristics. Therefore, the on / off potential difference of the drain transistor OG2 can be increased, and the overflow barrier of the photodiode PD can be more dynamically modulated by the control voltage of the drain transistor OG2. This makes it possible to switch between the blooming suppression mode and the high saturation charge mode even during pipeline operation.

[0069] 7 is a circuit diagram showing an example of the configuration of a unit pixel 50 according to a second embodiment. The second embodiment differs from the first embodiment in that it takes into consideration the parasitic capacitance PC between the discharge transistor OG1 and the discharge transistor OG2.

[0070] It is desirable that no charge accumulate between the drain transistor OG1 and the drain transistor OG2. However, in reality, a maximum potential point may occur between the drain transistor OG1 and the drain transistor OG2. In this case, when both the drain transistors OG1 and OG2 are turned off, a signal may accumulate between the drain transistor OG1 and the drain transistor OG2. This portion is called a parasitic capacitance PC (parasitic PD capacitance).

[0071] Since the charge accumulated in the parasitic capacitance PC becomes a signal for the photodiode PD in the high saturation charge mode, it is thought that failure to read out the charge in the parasitic capacitance PC will cause transfer failures under high illuminance. Therefore, during global transfer to the charge holding unit MEM, the discharge transistor OG1 is turned on simultaneously with the transfer transistor TRX, and the discharge transistor OG1 is turned off while the transfer transistor TRX is on, thereby enabling the charge accumulated in the parasitic capacitance PC to be transferred (completely transferred) to the charge holding unit MEM.

[0072] Fig. 8 is a timing chart showing an example of the operation of the unit pixel 50 according to the second embodiment. Fig. 9 is a schematic diagram showing an example of the potential state of the unit pixel 50 according to the second embodiment.

[0073] At time t2, the drain transistor OG2 turns off. As described with reference to Fig. 4, the potential barrier of the photodiode PD becomes higher. The parasitic capacitance PC appears as a potential pocket (dip) between the drain transistor OG1 and the drain transistor OG2, as shown in Fig. 9.

[0074] At time t6, the discharge transistor OG1 is turned on. Thereafter, between time t6 and time t7, the discharge transistor OG1 is turned off. This allows the charge accumulated in the parasitic capacitance PC to be transferred to the charge holding unit MEM.

[0075] As in the second embodiment, the parasitic capacitance PC between the discharge transistor OG1 and the discharge transistor OG2 may be taken into consideration, and in this case, the same effects as in the first embodiment can be obtained.

[0076] 10 is a timing chart showing an example of the operation of a unit pixel 50 according to a third embodiment. Fig. 10 also shows the readout of the charge storage unit MEM, which is accessed and read out for each pixel row. The third embodiment differs from the first embodiment in that the blooming suppression mode and the high saturation charge mode are switched between during an exposure period (within one frame).

[0077] As shown in FIG. 10, the readout of the charge holding units MEM is performed row by row.

[0078] Even during the same exposure period, the mode can be switched by changing the control voltage of the discharge transistor OG2. Until the readout of the charge holding unit MEM is completed, the discharge transistor OG2 is in the on state, and the blooming suppression mode is executed. After the readout is completed (time t2), the discharge transistor OG2 is turned off, and the mode is switched to the high saturation charge amount mode. This makes it possible to suppress blooming during the charge holding period of the charge holding unit MEM, while increasing the saturation charge amount in the latter half of the exposure period when blooming becomes unnoticeable.

[0079] As in the third embodiment, the blooming suppression mode and the high saturation charge amount mode may be switched during the exposure period (within one frame), and in this case, the same effects as in the first embodiment can be obtained.

[0080] 11 is a timing chart showing an example of the operation of a unit pixel 50 according to a fourth embodiment. FIG. 12 is a schematic diagram showing an example of the potential state of a unit pixel 50 according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that the discharge transistor OG2 is driven by a control voltage of an intermediate potential.

[0081] As shown in FIG. 11, the drain transistor OG2 is driven by a control voltage (intermediate voltage) at an intermediate potential between High and Low during the exposure period. This allows the potential barrier of the photodiode PD to be lower than in the high saturation charge mode but higher than in the blooming suppression mode. This makes it possible to adjust the balance between increasing the saturation charge and suppressing blooming in multiple stages. This allows for settings that are more suited to the shooting scene.

[0082] 12, the control voltage of the drain transistor OG1 is not changed, but the channel potential of the drain transistor OG1 also changes due to the change in the control voltage of the drain transistor OG2, due to capacitive coupling.

[0083] As in the fourth embodiment, the drain transistor OG2 may be driven by a control voltage of intermediate potential, and in this case, the same effects as in the first embodiment can be obtained.

[0084] 13 is a circuit diagram showing an example of the configuration of a unit pixel 50 according to a fifth embodiment. Fig. 14 is a plan view showing an example of the layout of the unit pixel 50 according to the fifth embodiment. The fifth embodiment differs from the first embodiment in that a path is provided from the parasitic capacitance PC to the charge holding unit MEM.

[0085] In the example shown in FIG. 13, the transfer transistor TRX is also provided between the node (parasitic capacitance PC) between the discharge transistor OG1 and the discharge transistor OG2 and the charge holding unit MEM.

[0086] In the example shown in FIG. 14, the active region between the drain transistor OG1 and the drain transistor OG2 is electrically connected to the channel portion of the transfer transistor TRX.

[0087] The path that discharges charges from the photodiode PD to the overflow drain via the discharge transistors OG1 and OG2 and the path that transfers charges from the parasitic capacitance PC to the charge holding unit MEM via the discharge transistor OG1 and the photodiode PD have opposite charge transfer directions, so it is difficult to design (for example, design the potential gradient) appropriate for both paths.

[0088] 14, a path for directly transferring charges from the parasitic capacitance PC to the charge holding unit MEM can be provided, thereby enabling transfer design suitable for each path.

[0089] As in the fifth embodiment, a path may be provided from the parasitic capacitance PC to the charge holding unit MEM, and in this case, the same effect as in the first embodiment can be obtained.

[0090] 15 is a circuit diagram showing an example of the configuration of a unit pixel 50 according to a sixth embodiment. The sixth embodiment differs from the first embodiment in that a plurality of transistors are provided for switching the height of the potential barrier of the photodiode PD.

[0091] The unit pixel 50 further includes a drain transistor OG3. The drain transistor OG3 is connected between the drain transistor OG1 and the drain transistor OG2. The drain transistors OG2 and OG3 function as transistors that switch the height of the potential barrier of the photodiode PD.

[0092] 16 to 18 are schematic diagrams showing examples of potential states of a unit pixel 50 according to the sixth embodiment. Fig. 16 shows a case where the discharge transistors OG1 to OG3 are in the off state. Fig. 17 shows a case where the discharge transistor OG2 is in the on state and the discharge transistors OG1 and OG3 are in the off state. Fig. 18 shows a case where the discharge transistors OG2 and OG3 are in the on state and the discharge transistor OG1 is in the off state.

[0093] The channel potential of the drain transistor OG3 when it is off is between the channel potential of the drain transistor OG1 when it is off and the channel potential of the drain transistor OG2 when it is off.

[0094] A plurality of transistors are provided for switching the height of the potential barrier during the exposure period of the photodiode PD. This makes it possible to adjust the balance between the increase in the saturation charge amount and the suppression of blooming in multiple stages without increasing the number of intermediate potential power supplies according to the fourth embodiment described with reference to Fig. 11. This allows for settings that are more suited to the shooting scene without increasing the number of intermediate potential power supplies.

[0095] The number of transistors that switch the height of the potential barrier of the photodiode PD is not limited to two, namely, the drain transistors OG2 and OG3, but may be three or more.

[0096] As in the sixth embodiment, a plurality of transistors may be provided to switch the height of the potential barrier of the photodiode PD, and in this case, the same effects as in the first embodiment can be obtained.

[0097] 19 is a circuit diagram showing a configuration example of a unit pixel 50 according to a seventh embodiment. The seventh embodiment differs from the first embodiment in that elements of the unit pixel 50 are formed across a plurality of bonded substrates.

[0098] The CMOS image sensor 10 further includes a first chip CH1 and a second chip CH2. The second chip CH2 is stacked on the first chip CH1. The first chip CH1 and the second chip CH2 are bonded together by, for example, Cu-Cu bonding or bump bonding.

[0099] The first chip CH1 is, for example, a pixel substrate, and includes a photodiode PD, discharge transistors OG1 and OG2, transfer transistors TRX and TRG, a charge holding unit MEM, and the like.

[0100] The second chip CH2 is, for example, a pixel transistor substrate, and includes a floating diffusion FD, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and the like.

[0101] The elements of the unit pixel 50 are arranged on a separate substrate, reducing the number of elements on the same substrate. This allows for more area to be secured for the photodiode PD and the charge storage unit MEM, improving the saturation charge amount and enabling the unit pixel 50 to be miniaturized.

[0102] As in the seventh embodiment, the elements of the unit pixel 50 may be formed across a plurality of bonded substrates. In this case, the same effects as in the first embodiment can be obtained.

[0103] 20 is a cross-sectional view showing an example of the configuration of a unit pixel 50 according to an eighth embodiment. The eighth embodiment differs from the first embodiment in that the CMOS image sensor 10 has a backside illumination sensor structure.

[0104] 20, a microlens L, a color filter CF, a passivation film P, a semiconductor substrate S, and a wiring layer WL are stacked from the top. Light is irradiated onto the photodiode PD from the backside, which is the upper surface side of the semiconductor substrate S. In a configuration in which multiple transfer gates (discharge transistors OG1, OG2) are provided between the photodiode PD and the overflow drain, the number of elements increases, and the number of control lines for driving the elements also increases. Therefore, a back-illuminated configuration, which offers a high degree of wiring freedom, is preferable in miniaturizing the unit pixel 50.

[0105] The CMOS image sensor 10 further includes a light-shielding portion 30. Examples of the configuration of the light-shielding portion 30 that can realize a back-illuminated global shutter sensor include a configuration in which the charge holding portion MEM is shielded from light using the light-shielding portion 30 on the back surface side or a through trench and a non-through trench processed from the back surface.

[0106] The light-shielding portion 30 is formed of an inner portion having light-shielding properties and an outer portion surrounding the inner portion. The inner portion is made of a material containing at least one of light-shielding elements such as an elemental metal, a metal alloy, a metal nitride, and a metal silicide. Specifically, the inner layer may be made of aluminum (Al), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), chromium (Cr), iridium (Ir), platinum-iridium, titanium nitride (TiN), or a tungsten-silicon compound. This configuration is an example of a pixel structure that can realize a back-illuminated sensor, and other structures are also possible.

[0107] As in the eighth embodiment, the CMOS image sensor 10 may have a backside illumination sensor structure. In this case, the same effects as in the first embodiment can be obtained.

[0108] 21 is a cross-sectional view showing an example of the configuration of a unit pixel 50 according to a ninth embodiment. In the ninth embodiment, the configuration of the light-shielding portion 30 is different from that in the eighth embodiment.

[0109] An example of the configuration of the light shielding portion 30 that can realize a backside illuminated global shutter sensor is a configuration in which the charge holding portion MEM is shielded from light by a horizontal light shielding portion embedded in a trench or the semiconductor substrate S.

[0110] As in the ninth embodiment, the configuration of the light blocking portion 30 may be changed. In this case, the same effects as in the eighth embodiment can be obtained.

[0111] 22 is a circuit diagram showing an example of the configuration of a unit pixel 50 according to a tenth embodiment. The tenth embodiment differs from the first embodiment in that phase difference detection is performed from oblique incidence sensitivity difference information.

[0112] The CMOS image sensor 10 has two pixels 50a and 50b. The pixel 50a has a photodiode PDa, transfer transistors TRXa and TRGa, a drain transistor OG1a, and a charge holding unit MEMa. The pixel 50b has a photodiode PDb, transfer transistors TRXb and TRGb, a drain transistor OG1b, and a charge holding unit MEMb.

[0113] The overflow drain, the drain transistor OG2, the reset transistor RST, the floating diffusion FD, the amplification transistor AMP, and the selection transistor SEL are shared by the two pixels 50a and 50b.

[0114] Even in a configuration in which a phase difference is detected from oblique incidence sensitivity difference information of two divided photodiodes PD (photodiodes PDa and PDb), by providing multiple transfer gates (discharge transistors OG1 and OG2) between the photodiode PD and the overflow drain, it is possible to switch between the high saturation charge mode and the blooming suppression mode. Furthermore, in the tenth embodiment, the node between the discharge transistor OG1 and the discharge transistor OG2 can be short-circuited between the pixels 50a and 50b, allowing the discharge transistor OG2 to be shared between the pixels 50a and 50b. This reduces the number of elements, thereby further increasing the areas of the photodiode PD and the charge holding unit MEM and improving the saturation charge amount.

[0115] 23 and 24 are schematic diagrams showing examples of potential states of a unit pixel 50 according to the tenth embodiment. The left side of Fig. 23 shows the path in the circuit diagram shown in Fig. 22. The right side of Fig. 23 shows the potential state along the path shown on the left side of Fig. 23. The left side of Fig. 24 shows the path in the circuit diagram shown in Fig. 22. The right side of Fig. 24 shows the potential state along the path shown on the left side of Fig. 24.

[0116] As shown in (a) of Figures 23 and 24, when oblique light is incident only on photodiode PDb, initially, a signal is accumulated only in photodiode PDb. As shown in (b) of Figures 23 and 24, when a certain amount of charge accumulates in photodiode PDb, signals are accumulated in both photodiodes PDa and PDb. This is achieved by adjusting the impurities so that charge overflowing from photodiode PDb selectively flows into photodiode PDa. In other words, the potential barrier between photodiodes PDa and PDb is low. When signals are accumulated in both photodiodes PDa and PDb, the output ratio of pixels 50a and 50b no longer corresponds to the oblique incidence sensitivity ratio, and phase difference information is lost. As shown in (c) of Figures 23 and 24, as the amount of charge increases further, charge overflows from photodiodes PDa and PDb to the node between drain transistor OG1 and drain transistor OG2. However, as described above, the phase difference information has already been lost, and there is no problem even if the signals of the photodiodes PDa and PDb are mixed, so the node between the discharge transistor OG1 and the discharge transistor OG2 can be short-circuited between the pixels 50a and 50b, and the discharge transistor OG2 can be shared between the pixels 50a and 50b.

[0117] As in the tenth embodiment, phase difference detection may be performed from oblique incidence sensitivity difference information, and in this case, the same effects as in the first embodiment can be obtained.

[0118] (Application Example to Electronic Device) FIG. 25 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0119] The camera 2000 includes an optical unit 2001 including a group of lenses, an imaging device 2002 to which the above-described CMOS image sensor 10 or the like (hereinafter referred to as the CMOS image sensor 10, etc.) is applied, and a DSP (Digital Signal Processor) circuit 2003, which is a camera signal processing circuit. The camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to one another via a bus line 2009.

[0120] The optical unit 2001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 2002. The imaging device 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0121] The display unit 2005 is formed of a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 2002. The recording unit 2006 records the moving images or still images captured by the imaging device 2002 on a recording medium such as a hard disk or semiconductor memory.

[0122] An operation unit 2007, under the operation of a user, issues operation commands for various functions of the camera 2000. A power supply unit 2008 appropriately supplies various types of power to the DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, and operation unit 2007 as operating power sources.

[0123] As described above, by using the above-described CMOS image sensor 10 or the like as the imaging device 2002, it is possible to expect to obtain a good image.

[0124] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0125] FIG. 26 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0126] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 26, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0127] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0128] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0129] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0130] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0131] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0132] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0133] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0134] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0135] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 26, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0136] FIG. 27 is a diagram showing an example of the installation position of the imaging unit 12031.

[0137] In FIG. 27, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0138] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0139] 27 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0140] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0141] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0142] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0143] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0144] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the CMOS image sensor 10 shown in FIG. 1 or the like can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to ensure a high saturation level and suppress blooming, thereby realizing safer vehicle driving.

[0145] The present technology can be configured as follows: (1) A solid-state imaging device including: a photoelectric conversion unit that generates charges according to an amount of received light through photoelectric conversion, a plurality of transistors that are connected in series between the photoelectric conversion unit and a first reference voltage node, a first transfer transistor that has one end electrically connected to the photoelectric conversion unit and transfers charges accumulated in the photoelectric conversion unit, a charge holding unit that holds the charges transferred by the first transfer transistor, a second transfer transistor that transfers the charges held by the charge holding unit, and a charge accumulation unit that accumulates the charges transferred by the second transfer transistor, wherein the charges between the plurality of series-connected transistors are transferred to the charge accumulation unit via the charge holding unit. (2) The solid-state imaging device according to (1), wherein the plurality of series-connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, wherein a channel potential of the first transistor when off is lower than a channel potential of the first transfer transistor when off, and a channel potential of the second transistor when off is higher than a channel potential of the first transistor when off. (3) The solid-state imaging device according to (2), wherein a channel potential of the second transistor when off is substantially the same as a channel potential of the first transfer transistor when off. (4) The solid-state imaging device according to (2) or (3), wherein the plurality of series-connected transistors further include one or more third transistors connected between the first transistor and the second transistor, wherein a channel potential of the third transistor when off is between a channel potential of the first transistor when off and a channel potential of the second transistor when off.(5) The solid-state imaging device according to any one of (1) to (4), wherein the plurality of series-connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node, and a second transistor connected between the first transistor and the first reference voltage node, and an active region between the first transistor and the second transistor is electrically connected to a channel portion of the first transfer transistor. (6) The solid-state imaging device according to any one of (1) to (5), wherein the plurality of series-connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node, and a second transistor connected between the first transistor and the first reference voltage node, and the second transistor is in an on state at the start of an exposure period and is turned off during an exposure period after readout of the charge storage units of all pixel rows is completed. (7) The solid-state imaging device according to any one of (1) to (6), wherein the plurality of serially connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, and the second transistor is driven at an intermediate voltage between an on voltage and an off voltage during an exposure period. (8) The solid-state imaging device according to any one of (1) to (7), wherein the plurality of serially connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node; and further comprising a first pixel and a second pixel each having the photoelectric conversion unit, the first transistor, the first transfer transistor, the charge holding unit, and the second transfer transistor; the second transistor is shared by the first pixel and the second pixel; and a node between the first transistor and the second transistor is short-circuited between the first pixel and the second pixel.(9) The solid-state imaging device according to (8), wherein charge overflowing from the photoelectric conversion unit of one of the first pixel and the second pixel is accumulated in the photoelectric conversion unit of the other. (10) The solid-state imaging device according to any one of (1) to (9), further comprising: a first chip; and a second chip stacked on the first chip, wherein the photoelectric conversion unit, the plurality of series-connected transistors, the first transfer transistor, the charge holding unit, and the second transfer transistor are arranged on the first chip, and the charge accumulation unit is arranged on the second chip. (11) The solid-state imaging device according to any one of (1) to (10), which is a back-illuminated MOS type imaging device.

[0146] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0147] 10 CMOS image sensor, 50 unit pixel, 50a pixel, 50b pixel, CH1 first chip, CH2 second chip, MEM charge storage unit, OG1 discharge transistor, OG2 discharge transistor, OG3 discharge transistor, PC parasitic capacitance, PD photodiode, TRG transfer transistor, TRX transfer transistor

Claims

1. A solid-state imaging device comprising: a photoelectric conversion unit that generates charges according to the amount of light received through photoelectric conversion; a plurality of transistors connected in series between the photoelectric conversion unit and a first reference voltage node; a first transfer transistor having one end electrically connected to the photoelectric conversion unit and transferring charges accumulated in the photoelectric conversion unit; a charge holding unit that holds the charges transferred by the first transfer transistor; a second transfer transistor that transfers the charges held by the charge holding unit; and a charge accumulation unit that accumulates the charges transferred by the second transfer transistor; wherein the charges between the plurality of series-connected transistors are transferred to the charge accumulation unit via the charge holding unit.

2. The solid-state imaging device of claim 1, wherein the plurality of series-connected transistors include a first transistor connected between the photoelectric conversion unit and the first reference voltage node, and a second transistor connected between the first transistor and the first reference voltage node, wherein the channel potential of the first transistor when off is lower than the channel potential of the first transfer transistor when off, and the channel potential of the second transistor when off is higher than the channel potential of the first transistor when off.

3. The solid-state imaging device according to claim 2, wherein the channel potential of said second transistor when it is off is substantially the same as the channel potential of said first transfer transistor when it is off.

4. The solid-state imaging device according to claim 2, wherein the plurality of series-connected transistors further comprises one or more third transistors connected between the first transistor and the second transistor, and the channel potential of the third transistor when off is between the channel potential of the first transistor when off and the channel potential of the second transistor when off.

5. The solid-state imaging device of claim 1, wherein the plurality of series-connected transistors include a first transistor connected between the photoelectric conversion unit and the first reference voltage node, and a second transistor connected between the first transistor and the first reference voltage node, and an active region between the first transistor and the second transistor is electrically connected to a channel portion of the first transfer transistor.

6. The solid-state imaging device according to claim 1, wherein the plurality of series-connected transistors comprise: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node, and the second transistor is in an on state at the start of an exposure period and is turned off during the exposure period after completion of readout of the charge storage units of all pixel rows.

7. The solid-state imaging device according to claim 1, wherein the plurality of series-connected transistors include a first transistor connected between the photoelectric conversion unit and the first reference voltage node, and a second transistor connected between the first transistor and the first reference voltage node, and the second transistor is driven at an intermediate voltage between an on voltage and an off voltage during an exposure period.

8. The solid-state imaging device of claim 1, wherein the plurality of series-connected transistors include: a first transistor connected between the photoelectric conversion unit and the first reference voltage node; and a second transistor connected between the first transistor and the first reference voltage node; and further comprising a first pixel and a second pixel each having the photoelectric conversion unit, the first transistor, the first transfer transistor, the charge holding unit, and the second transfer transistor; the second transistor is shared by the first pixel and the second pixel; and a node between the first transistor and the second transistor is short-circuited between the first pixel and the second pixel.

9. The solid-state imaging device according to claim 8, wherein charges overflowing from the photoelectric conversion unit of one of the first pixel and the second pixel are accumulated in the photoelectric conversion unit of the other.

10. A solid-state imaging device as described in claim 1, further comprising: a first chip; and a second chip stacked on the first chip, wherein the photoelectric conversion unit, the plurality of transistors connected in series, the first transfer transistor, the charge holding unit, and the second transfer transistor are arranged on the first chip, and the charge storage unit is arranged on the second chip.

11. The solid-state imaging device according to claim 1, which is a back-illuminated MOS imaging device.

Images