Semiconductor storage device and method for supplying power to semiconductor storage device

Abstract

A semiconductor storage device (10) comprises: a memory cell array (24) divided into a plurality of sectors (20-23) to be sequentially accessed; and a power supply control circuit (30) that performs control for supplying a power supply voltage VDD to each of the plurality of sectors (20-23). When access is made to a first sector (for example, the sector (20)) from among the plurality of sectors (20-23), the power supply control circuit (30) performs control such that, to a second sector (for example, the sector (21)) to be accessed subsequently to the first sector, a first power supply voltage VDD necessary for the second sector to read and write data is supplied.

Description

Semiconductor memory device and power supply method for semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device and a power supply method for the semiconductor memory device, and more particularly to a technique for suppressing rush current that occurs when the semiconductor memory device is started up.

[0002] As semiconductor memory devices become larger in scale, when power is applied to the semiconductor memory device or when power is restored after being cut off (collectively referred to as "startup"), a rush current, i.e., an inrush current that flows suddenly when the semiconductor memory device starts up, occurs in the power supply line that supplies the power supply voltage to the semiconductor memory device. A large rush current causes power supply noise and can cause the semiconductor memory device to malfunction.

[0003] Conventionally, various techniques have been proposed for suppressing rush currents that occur when a semiconductor memory device is started up (see, for example, Patent Document 1). In Patent Document 1, a semiconductor memory device is configured with multiple functional blocks, and the multiple functional blocks are started up in sequence to distribute and suppress the rush current.

[0004] Japanese Patent Application Laid-Open No. 2007-267162

[0005] However, the technology of Patent Document 1 requires complex timing control to activate multiple functional blocks in sequence, and also requires waiting for the power supply voltage supplied to the functional block to stabilize after switching between functional blocks (i.e., "power supply stabilization wait").

[0006] Therefore, an object of the present disclosure is to provide a semiconductor memory device and a power supply method for a semiconductor memory device that can suppress rush current that occurs at startup without requiring complex timing control or waiting for power supply stabilization.

[0007] In order to achieve the above object, a semiconductor memory device according to one embodiment of the present disclosure includes a memory cell array divided into a plurality of sectors that are accessed sequentially, and a power supply control circuit that controls the supply of a power supply voltage to each of the plurality of sectors, wherein when a first sector of the plurality of sectors is being accessed, the power supply control circuit controls the supply of a first power supply voltage required for the second sector to read and write data to the second sector, the second sector being accessed next after the first sector.

[0008] In order to achieve the above object, a power supply method for a semiconductor memory device according to one embodiment of the present disclosure is a power supply method for a semiconductor memory device having a memory cell array divided into a plurality of sectors that are accessed sequentially, and includes a power supply control step of performing control to supply a power supply voltage to each of the plurality of sectors, wherein in the power supply control step, when a first sector of the plurality of sectors is being accessed, the control is performed so that a first power supply voltage required for the second sector to read and write data is supplied to a second sector that is accessed next after the first sector.

[0009] The present disclosure provides a semiconductor memory device and a power supply method for a semiconductor memory device that can suppress rush currents that occur at startup without requiring complex timing control or waiting for power supply stabilization.

[0010] FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment. FIG. 2 is a timing chart showing the operation of the semiconductor memory device according to the embodiment. FIG. 3 is a flowchart showing the operation of the semiconductor memory device according to the embodiment. FIG. 4 is a circuit diagram of a semiconductor memory device according to a first modified example of the embodiment. FIG. 5 is a timing chart showing the operation of the semiconductor memory device according to the first modified example of the embodiment. FIG. 6 is a circuit diagram of a semiconductor memory device according to a second modified example of the embodiment. FIG. 7 is a timing chart showing the operation of the semiconductor memory device according to the second modified example of the embodiment. FIG. 8 is a circuit diagram of a semiconductor memory device according to a third modified example of the embodiment. FIG. 9 is a timing chart showing the operation of the semiconductor memory device according to the third modified example of the embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each embodiment described below represents a specific example of the present disclosure. Numerical values, addresses, circuit elements, layout and connection of circuit elements, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical configurations are assigned the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "connection" means electrical connection, and includes not only cases where two circuit elements are directly connected, but also cases where two circuit elements are indirectly connected with another circuit element inserted between them.

[0012] 1 is a circuit diagram of a semiconductor memory device 10 according to an embodiment. The semiconductor memory device 10 is a memory device capable of suppressing rush currents that occur at startup without requiring complex timing control or waiting for power supply stabilization, and includes a memory cell array 24 and a power supply control circuit 30. Note that only circuit elements necessary for the operation of the present disclosure are shown in this diagram, and the semiconductor memory device 10 may also include peripheral circuits (e.g., address decoders, sense amplifier circuits, etc.) that are not shown.

[0013] The memory cell array 24 is a memory cell array made up of a plurality of sectors 20 to 23 that are accessed sequentially, and is, for example, an SRAM memory cell array, a DRAM memory cell array, etc. In this embodiment, it is assumed that sectors are accessed starting from sector 20, followed by sectors 21, 22, and 23 in that order.

[0014] Ten address lines RA0 to RA9 are connected to each of sectors 20 to 23, with sector 20 having memory cells (also referred to as "memory cell array 0" or "array 0") corresponding to addresses 0 to 255 (i.e., word lines WL0 to WL255), sector 21 having memory cells (also referred to as "memory cell array 1" or "array 1") corresponding to addresses 256 to 511 (i.e., word lines WL256 to WL511), sector 22 having memory cells (also referred to as "memory cell array 2" or "array 2") corresponding to addresses 512 to 767 (i.e., word lines WL512 to WL767), and sector 23 having memory cells (also referred to as "memory cell array 3" or "array 3") corresponding to addresses 768 to 1023 (i.e., word lines WL768 to WL1023).

[0015] In the figure, VDD0 to VDD3 (four terminals located on the left side of VDD0 to VDD3 in the figure) are power supply terminals that receive a power supply voltage VDD, which is an example of a first power supply voltage required for reading and writing data, to sectors 20 to 23. Also, "access" means that a specific address is input to memory cell array 24 via address lines RA0 to RA9 in order to read or write data from or to memory cell array 24.

[0016] The power supply control circuit 30 is a circuit that controls the supply of power supply voltage VDD to each of the multiple sectors 20 to 23 that make up the memory cell array 24, and is composed of inverters 31a, 31b, and 40b, AND gates 40a, 41a, 42a, and 43a, OR gates 41b, 42b, and 43b, buffer circuits 40c, 41c, 42c, and 43c, and transistors 40d to 40g, 41d to 41g, 42d to 42g, and 43d to 43g.

[0017] This power supply control circuit 30 controls so that when one of the multiple sectors 20 to 23 (this sector is called the "first sector" (e.g., sector 20)) is being accessed, the power supply voltage VDD is supplied to the sector that is accessed next after the first sector (this sector is called the "second sector" (e.g., sector 21)).

[0018] In this specification, the "sector that has been / is being accessed" is referred to as the "first sector" or "current sector," the next sector to be accessed is referred to as the "second sector" or "next sector," and the next-next sector to be accessed is referred to as the "third sector" or "next sector."

[0019] Furthermore, when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed, the power supply control circuit 30 performs control so that the supply of the power supply voltage VDD, which is an example of the first power supply voltage, to the first sector is stopped. Note that in this specification, "when a transition occurs to a state" may mean the same time as the transition to the state, or after or immediately after the transition to the state.

[0020] 2 is a timing chart showing the operation of the semiconductor memory device 10 according to the embodiment. This chart shows the timing of supplying the power supply voltage VDD to the power supply terminals VDD0 to VDD3 of the sequentially accessed sectors 20 to 23. In the timing chart, a high level indicates that the power supply voltage VDD is being supplied, and a low level indicates that the supply of the power supply voltage VDD is cut off (here, ground (0 V)).

[0021] As shown in this figure, a power supply voltage VDD is supplied to the power supply terminal VDD0 of sector 20 (i.e., array 0), and when sector 20 (i.e., array 0) is being accessed, the power supply voltage VDD required to read and write data is supplied to the power supply terminal VDD1 of sector 21 (i.e., array 1), which is accessed next after sector 20.

[0022] Specifically, in FIG. 1, when an address for accessing sector 20 (i.e., array 0) is input to power supply control circuit 30 via address lines RA0 to RA9, the address of the upper two digits of address lines RA8 and RA9 is decoded by inverters 31a and 31b and AND gates 40a to 43a, and only AND gate 40a of AND gates 40a to 43a is activated (output becomes High), and its output signal turns on transistors 40d to 40g via inverter 40b and buffer circuit 40c, supplying power supply voltage VDD to power supply terminal VDD0 of sector 20 (i.e., array 0), and also turns on transistors 41d to 41g via OR gate 41b and buffer circuit 41c, supplying power supply voltage VDD to power supply terminal VDD1 of sector 21 (i.e., array 1).

[0023] Next, as shown in FIG. 2, when the state transitions from one in which sector 20 (i.e., array 0) is being accessed to one in which sector 21 (i.e., array 1) is being accessed, the supply of power supply voltage VDD to power supply terminal VDD0 of sector 20 is stopped, and the power supply voltage VDD required to read and write data is supplied to power supply terminal VDD2 of sector 22 (i.e., array 2), which is accessed next after sector 21.

[0024] Specifically, in FIG. 1, when an address for accessing sector 21 (i.e., array 1) is input to power supply control circuit 30 via address lines RA0 to RA9, the address of the upper two digits of address lines RA8 and RA9 is decoded by inverters 31a and 31b and AND gates 40a to 43a, and only AND gate 41a of AND gates 40a to 43a is activated (output becomes High), and its output signal keeps transistors 41d to 41g on via OR gate 41b and buffer circuit 41c, maintaining the supply of power supply voltage VDD to sector 21 (i.e., array 1), and also turns on transistors 42d to 42g via OR gate 42b and buffer circuit 42c, so that power supply voltage VDD is also supplied to power supply terminal VDD2 of sector 22 (i.e., array 2). Furthermore, when the AND gate 40a is deactivated (the output becomes Low), its output signal turns off the transistors 40d to 40g via the inverter 40b and the buffer circuit 40c, and the supply of the power supply voltage VDD to the power supply terminal VDD0 of the sector 20 is stopped.

[0025] Thereafter, in a similar manner, when the state transitions from one in which sector 21 (i.e., array 1) is being accessed to one in which sector 22 (i.e., array 2) is being accessed, the supply of power supply voltage VDD to power supply terminal VDD1 of sector 21 is stopped, and the power supply voltage VDD required to read and write data is supplied to power supply terminal VDD3 of sector 23 (i.e., array 3), which is accessed next after sector 22.

[0026] Furthermore, similarly, when a transition occurs from a state in which sector 22 (i.e., array 2) is being accessed to a state in which sector 23 (i.e., array 3) is being accessed, the supply of power supply voltage VDD to power supply terminal VDD2 of sector 22 is stopped.

[0027] 3 is a flowchart showing the operation of the semiconductor memory device 10 according to the embodiment (i.e., a method of supplying power to the semiconductor memory device), which shows details of the power control steps in which the power supply control circuit 30 of the semiconductor memory device 10 controls the supply of the power supply voltage VDD to each of the multiple sectors 20 to 23.

[0028] 3A is a flowchart showing the power supply control steps for starting the power supply to the sector next to the sector being accessed. The power supply control circuit 30 determines whether one of the sectors 20-23 (i.e., the first sector) is being accessed (S10). If it is determined that the sector is not being accessed (No in S10), the power supply control circuit 30 repeats the determination. On the other hand, if it is determined that the sector is being accessed (Yes in S10), the power supply control circuit 30 controls the start of supply of the power supply voltage VDD required for reading and writing data to the sector to be accessed next to the first sector (i.e., the second sector) (S11). In this embodiment, as shown in the timing chart of FIG. 2, when a sector is accessed for the first time, the power supply to the next sector to be accessed is controlled to start.

[0029] 3B is a flowchart showing the power supply control steps for stopping the power supply to a sector that has finished being accessed. The power supply control circuit 30 determines whether a transition has occurred from a state in which one sector (i.e., the first sector) is being accessed to a state in which the next sector to be accessed (i.e., the second sector) is being accessed (S20). If it determines that a transition has not occurred (No in S20), the determination is repeated. On the other hand, if it determines that a transition has occurred (Yes in S20), the power supply control circuit 30 controls to stop the supply of power supply voltage VDD to the first sector (S21).

[0030] As described above, in the semiconductor memory device 10 according to the embodiment, the power supply to the memory cell array 24 is controlled on and off on a sector-by-sector basis, and further, the power supply is stopped after the access is completed. Therefore, compared to when the power supply is controlled on and off for the entire memory cell array (i.e., on a macro basis), lower power consumption is achieved, and the rush current at startup is dispersed and suppressed on a sector-by-sector basis.

[0031] Furthermore, according to the semiconductor memory device 10 of this embodiment, power supply to the next sector to be accessed is started based on the address information of the sector being accessed, so there is no need for complex timing control to sequentially start up multiple functional blocks as in the prior art.

[0032] Furthermore, according to the semiconductor memory device 10 of this embodiment, when the first sector is being accessed (in the embodiment, when the first sector is accessed for the first time), power supply to the second sector to be accessed next is started, so there is no need to wait for power stabilization, as in the prior art, in which the power supply voltage supplied to the functional block after switching between functional blocks is stabilized.

[0033] 4 is a circuit diagram of a semiconductor memory device 10a according to a first modification of the embodiment. This modification differs from the embodiment in that, instead of supplying ground (0 V) as a power supply voltage to the non-accessed sectors 20-23, a retention voltage VRE, which is an example of a second power supply voltage required for the sectors to retain data, is supplied. The retention voltage VRE is a voltage lower than the power supply voltage VDD required for reading and writing data.

[0034] To achieve this, the power supply control circuit 30a of the semiconductor memory device 10a according to this modification includes, in addition to the components included in the power supply control circuit 30 according to the embodiment, inverters 40h to 43h connected between the gates of transistors 40d to 43d and 40e to 43e that turn on and off the supply of the power supply voltage VDD and the gates of transistors 40f to 43f and 40g to 43g that turn on and off the supply of the retention voltage VRE. With this circuit configuration, the retention voltage VRE is supplied to the power supply terminals VDD0 to VDD3 of the sectors 20 to 23 when the power supply voltage VDD is not supplied.

[0035] 5 is a timing chart showing the operation of the semiconductor memory device 10a according to the first modification of the embodiment. Unlike the embodiment shown in FIG. 2, the power supply voltage supplied to the sectors (arrays) that are not accessed is the retention voltage VRE.

[0036] As described above, the semiconductor memory device 10a according to this modification has the feature that data in non-accessed sectors is retained without being erased, in addition to the features of the semiconductor memory device 10 according to the embodiment. Furthermore, since the power supply voltage supplied to non-accessed sectors is maintained at a retention voltage VRE lower than the power supply voltage VDD, lower power consumption is realized and leakage power is suppressed compared to when the power supply voltage VDD is supplied.

[0037] 6 is a circuit diagram of a semiconductor memory device 10b according to a second modification of the embodiment. This modification differs from the embodiment in that, when a transition occurs from a state in which a first sector is being accessed to a state in which a second sector is being accessed, the power supply line of the first sector is connected to the power supply line of a third sector that is accessed next after the second sector, thereby distributing the charge accumulated in the power supply line of the first sector to the power supply line of the third sector.

[0038] To achieve this, the power supply control circuit 30b of the semiconductor memory device 10b according to this modification includes, in addition to the components of the power supply control circuit 30 according to the embodiment, a transistor 44a for turning on and off the connection between the power supply line 20a of sector 20 and the power supply line 22a of sector 22, a transistor 44b for turning on and off the connection between the power supply line 21a of sector 21 and the power supply line 23a of sector 23, and a circuit (not shown) for controlling these transistors 44a and 44b. Note that in Figure 6, many of the components of the power supply control circuit 30b that are similar to those of the power supply control circuit 30 according to the embodiment are not shown.

[0039] With this circuit configuration, when the state transitions from one in which sector 20 is being accessed to one in which sector 21 is being accessed, the power supply line 20a of sector 20 is connected to the power supply line 22a of sector 22, thereby enabling the charge accumulated in the power supply line 20a of sector 20 to be distributed to the power supply line 22a of sector 22. More specifically, at this time, the power supply control circuit 30b first turns the signal POW_SW0 high to turn off the supply of power supply voltage VDD to sector 20, then turns the signal Con0 low to turn on the transistor 44a and connect the power supply line 20a of sector 20 to the power supply line 22a of sector 22, thereby performing charge distribution, then turns the signal Con0 high to turn off the transistor 44a and disconnect the power supply line 20a of sector 20 from the power supply line 22a of sector 22, and finally turns the signal POW_SW2 low to turn on the supply of power supply voltage VDD to sector 22. This reduces power consumption when supplying the power supply voltage VDD to the sector 22 .

[0040] Similarly, when a transition occurs from a state in which sector 21 is being accessed to a state in which sector 22 is being accessed, the power supply line 21a of sector 21 is connected to the power supply line 23a of sector 23, thereby enabling the charge accumulated in the power supply line 21a of sector 21 to be distributed to the power supply line 23a of sector 23. More specifically, at this time, the power supply control circuit 30b first turns off the supply of power supply voltage VDD to sector 21 by setting signal POW_SW1 to High, then turns on transistor 44b by setting signal Con1 to Low, thereby connecting the power supply line 21a of sector 21 to the power supply line 23a of sector 23, thereby performing charge distribution, then turns off transistor 44b by setting signal Con1 to High, thereby disconnecting the power supply line 21a of sector 21 from the power supply line 23a of sector 23, and finally turns on the supply of power supply voltage VDD to sector 23 by setting signal POW_SW3 to Low. This reduces the power consumption of the power supply voltage VDD supplied to the sector 23 .

[0041] 7 is a timing chart showing the operation of the semiconductor memory device 10b according to the second modification of the embodiment. Compared to FIG. 2 according to the embodiment, when the state transitions from when sector 20 is being accessed to when sector 21 is being accessed, the power supply line 20a of sector 20 and the power supply line 22a of sector 22 are connected, resulting in charge sharing, resulting in a stepped waveform. Furthermore, when the state transitions from when sector 21 is being accessed to when sector 22 is being accessed, the power supply line 21a of sector 21 and the power supply line 23a of sector 23 are connected, resulting in charge sharing, resulting in a stepped waveform.

[0042] Thus, according to the semiconductor memory device 10b of this modified example, in addition to the features of the semiconductor memory device 10 of the embodiment, when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed, the power supply line of the first sector and the power supply line of the third sector, which is accessed next after the second sector, are connected, and the charge accumulated in the power supply line of the first sector is distributed to the power supply line of the third sector, thereby reducing power consumption in the supply of the power supply voltage VDD to the third sector.

[0043] 8 is a circuit diagram of a semiconductor memory device 10c according to a third modification of the embodiment. The difference from the embodiment is that in this modification, in addition to turning on and off the power supply on a sector-by-sector basis as in the embodiment, the power supply to the word line drive circuit of that sector is also turned on and off.

[0044] This figure also shows word lines 60a-60b, 61a-61b, 62a-62b, and 63a-63b for each of sectors 20-23 of semiconductor memory device 10c, and their corresponding word line drive circuits 50a-50b, 51a-51b, 52a-52b, and 53a-53b.

[0045] Furthermore, the power supply control circuit 30c of the semiconductor memory device 10c according to this modification has the same configuration as the power supply control circuit 30 according to the embodiment, except that the connection configuration is changed from one in which the supply of the power supply voltage VDD is turned on and off on a sector-by-sector basis to one in which the supply of the power supply voltage VDD is turned on and off on a sector-by-word line drive circuit basis. Specifically, the drains of transistors 40d, 41d, 42d, and 43d are connected to the power supply terminals VDD0, VDD1, VDD2, and VDD3 of sectors 20, 21, 22, and 23, respectively, instead of the power supply terminals VDD0, VDD1, VDD2, and VDD3 of word line drive circuits 50a-50b, 51a-51b, 52a-52b, and 53a-53b.

[0046] 9 is a timing chart showing the operation of a semiconductor memory device 10c according to a third modification of the embodiment. The timing chart itself is the same as that shown in FIG. 2 according to the embodiment, but the names of the parts shown on the left of the timing chart itself include not only the power supply terminals but also the word line drive circuits (word line drive circuits 50a-50b, etc.).

[0047] Thus, in addition to the features of the semiconductor memory device 10 according to the embodiment, the semiconductor memory device 10c according to this modification not only turns on and off the power supply on a sector-by-sector basis, but also turns on and off the power supply to the word line drive circuit of that sector. Therefore, when the power supply to an unaccessed sector is stopped, the power supply to the word line drive circuit of that sector is also stopped, thereby achieving lower power consumption than the embodiment.

[0048] As described above, the semiconductor memory device 10 etc. according to the present embodiment etc. comprises a memory cell array 24 divided into a plurality of sectors 20-23 that are accessed sequentially, and a power supply control circuit 30 etc. that controls the supply of a power supply voltage VDD to each of the plurality of sectors 20-23, and the power supply control circuit 30 etc. controls so that when a first sector (e.g., sector 20) of the plurality of sectors 20-23 is being accessed, the second sector (e.g., sector 21) that is accessed next to the first sector is supplied with the first power supply voltage VDD required for the second sector to read and write data.

[0049] As a result, the power supply to the memory cell array 24 is controlled on and off on a sector-by-sector basis, which achieves lower power consumption than when the power supply is controlled on and off for the entire memory cell array (i.e., on a macro-by-macro basis), and also distributes and suppresses rush current at startup on a sector-by-sector basis.

[0050] In addition, because power supply to the next sector to be accessed is initiated based on the address information of the sector being accessed, there is no need for complex timing control to sequentially activate multiple functional blocks, as in the prior art. Furthermore, because power supply to the next sector to be accessed is initiated when the first sector is being accessed (in the embodiment, when the first sector is first accessed), there is no need to wait for power stabilization, as in the prior art, for the power supply voltage to be supplied to the functional block to stabilize after switching between functional blocks.

[0051] Furthermore, when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed, the power supply control circuit 30 and the like perform control so that the supply of the first power supply voltage VDD to the first sector is stopped. As a result, the power supply to the memory cell array 24 is controlled to be turned on and off on a sector-by-sector basis, and further, the power supply is stopped after the access is completed, thereby realizing low power consumption and suppressing leakage power.

[0052] Furthermore, when the state transitions from when the first sector is being accessed to when the second sector is being accessed, the power supply control circuit 30a according to the first modification controls the first sector to be supplied with a second power supply voltage VRE that is lower than the first power supply voltage VDD and is necessary for the second sector to retain data. This allows data in non-accessed sectors to be retained without being erased. Furthermore, because the power supply voltage supplied to non-accessed sectors is maintained at a retention voltage VRE that is lower than the power supply voltage VDD, lower power consumption is achieved and leakage power is suppressed compared to when the power supply voltage VDD is supplied.

[0053] Furthermore, when the state transitions from when the first sector is being accessed to when the second sector is being accessed, the power supply control circuit 30b according to the second modification connects the power supply line 20a of the first sector to the power supply line 22a of the third sector (e.g., sector 22) that is to be accessed after the second sector. This allows charge distribution from the power supply line of the current sector that has finished being accessed to the power supply line of the sector two stages later, thereby reducing power consumption when supplying the power supply voltage VDD to the third sector.

[0054] The semiconductor memory device 10c according to the third modification further includes a plurality of word line drive circuits 50a-50b etc. corresponding to the plurality of sectors 20-23, each of which drives a corresponding word line 60a-60b etc., and the power supply control circuit 30c controls to stop the supply of power supply voltage VDD to the word line drive circuits 50a-50b etc. corresponding to the first sector when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed. As a result, the power supply to the sectors that are not being accessed is stopped, and at the same time, the power supply to the word line drive circuits of those sectors is also stopped, thereby achieving even lower power consumption.

[0055] Furthermore, the power supply method for a semiconductor memory device according to the present embodiment is a power supply method for a semiconductor memory device 10 or the like having a memory cell array 24 divided into a plurality of sectors 20-23 that are accessed sequentially, and includes a power supply control step of controlling the supply of a power supply voltage VDD to each of the plurality of sectors 20-23, and in the power supply control step, when a first sector (e.g., sector 20) of the plurality of sectors 20-23 is being accessed, control is performed so that the first power supply voltage VDD required for the second sector (e.g., sector 21) to be accessed after the first sector is supplied to the second sector (e.g., sector 21) to read and write data (S10-S11 in (a) of Figure 3).

[0056] As a result, the power supply to the memory cell array 24 is controlled on and off on a sector-by-sector basis, which achieves lower power consumption than when the power supply is controlled on and off for the entire memory cell array, and also distributes and suppresses rush current at startup on a sector-by-sector basis.

[0057] In addition, because power supply to the next sector to be accessed is initiated based on the address information of the sector being accessed, there is no need for complex timing control to sequentially activate multiple functional blocks, as in the prior art. Furthermore, because power supply to the next sector to be accessed is initiated when the first sector is being accessed (in the embodiment, when the first sector is first accessed), there is no need to wait for power stabilization, as in the prior art, for the power supply voltage to be supplied to the functional block to stabilize after switching between functional blocks.

[0058] While the semiconductor memory device and the method of supplying power to the semiconductor memory device according to the present disclosure have been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art may make to the present embodiments and modifications, and other forms constructed by combining some of the components in the embodiments and modifications, are also included within the scope of the present disclosure.

[0059] For example, by combining the first and second variants of the embodiment, it is possible to supply a retention voltage to a sector that has finished being accessed to retain data (first variant), and to reduce power consumption in supplying power supply voltage VDD to the sector two stages after the current sector by charge distribution (second variant).

[0060] Similarly, by combining the second and third variants of the embodiment, charge distribution can reduce power consumption in supplying the power supply voltage VDD to the power supply lines of both the sector next to the current sector (second variant) and its word line drive circuit (third variant).

[0061] In the above embodiments, the memory cell array 24 is accessed in the order in which the addresses increment from 0 to 1023, but it may be accessed in the order in which the addresses decrement from 1023 to 0. In this case, this is realized by replacing the power supply control for sectors 20 to 23 with the power supply control for sectors 20 to 23, respectively.

[0062] Furthermore, in the above embodiments, an example has been shown in which all sectors 20 to 23 constituting memory cell array 24 are accessed sequentially, but this is not limited to such access, and the features of the present disclosure can be applied even when, for example, sector 21 is accessed sequentially, followed by sectors 22 and 23.

[0063] Furthermore, in the above-described embodiments, when the first sector is accessed for the first time, power supply to the second sector, which is to be accessed next, is started. However, the timing at which power supply to the second sector is started is not limited to this. For example, power supply to the second sector may be started when a predetermined address in the address range of the first sector (for example, the central address, or an address 100 addresses lower than the highest address) is accessed.

[0064] Furthermore, the method of supplying power to a semiconductor memory device according to the present disclosure may be realized by a program executed by a processor, by a non-transitory computer-readable recording medium such as a DVD on which the program is recorded, or as a program product.

[0065] The present disclosure can be used as a semiconductor memory device, such as an SRAM or DRAM, that has a function of suppressing rush current at startup.

[0066] 10, 10a to 10c Semiconductor memory device 20 to 23 Sectors 20a, 21a, 22a, 23a Power supply line 24 Memory cell array 30, 30a to 30c Power supply control circuit 31a, 31b, 40b, 40h, 41h, 42h, 43h Inverters 40a, 41a, 42a, 43a AND gates 41b, 42b, 43b OR gates 40c, 41c, 42c, 43c Buffer circuits 40d to 40g, 41d to 41g, 42d to 42g, 43d to 43g, 44a, 44b Transistors 50a to 50b, 51a to 51b, 52a to 52b, 53a to 53b Word line drive circuit

Claims

1. A semiconductor memory device comprising: a memory cell array divided into a plurality of sectors that are accessed sequentially; and a power supply control circuit that controls the supply of a power supply voltage to each of the plurality of sectors, wherein when a first sector of the plurality of sectors is being accessed, the power supply control circuit controls so that a first power supply voltage required for the second sector to read and write data is supplied to the second sector that is accessed next after the first sector.

2. The semiconductor memory device according to claim 1, wherein the power supply control circuit performs the control such that the supply of the first power supply voltage to the first sector is stopped when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed.

3. The semiconductor memory device according to claim 2, wherein the power supply control circuit performs the control so that, when a transition occurs from a state in which the first sector is being accessed to a state in which the second sector is being accessed, a second power supply voltage lower than the first power supply voltage and necessary for the second sector to retain data is supplied to the first sector.

4. The semiconductor memory device according to claim 1, wherein said power supply control circuit connects the power supply line of said first sector to the power supply line of a third sector that is accessed next to said second sector when a transition occurs from a state in which said first sector is being accessed to a state in which said second sector is being accessed.

5. The semiconductor memory device according to claim 2, further comprising a plurality of word line drive circuits corresponding to each of said plurality of sectors, said plurality of word line drive circuits driving word lines corresponding to each of said plurality of sectors, and wherein said power supply control circuit controls to stop supply of power supply voltage to said word line drive circuit corresponding to said first sector when a transition occurs from a state in which said first sector is being accessed to a state in which said second sector is being accessed.

6. A power supply method for a semiconductor memory device having a memory cell array divided into a plurality of sectors that are accessed sequentially, comprising a power supply control step of controlling the supply of a power supply voltage to each of the plurality of sectors, wherein in the power supply control step, when a first sector of the plurality of sectors is being accessed, the control is performed so that a first power supply voltage required for the second sector to read and write data is supplied to a second sector that is accessed next after the first sector.

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