Semiconductor substrate, method for manufacturing same, light-emitting element, method for manufacturing same, and electronic apparatus

Abstract

A semiconductor substrate (10) comprises: a template substrate (TS) including a seed region (S1) and a first non-seed region (D1) that includes a concave first concave surface (U1); a base layer (8) including a base portion (B) positioned above the seed region (S1) and a first wing portion (F1) connected to the base portion (B); and a first cavity (C1) positioned between the first concave surface (U1) and the first wing portion (F1), the first cavity (C1) having a downward convex lens shape.

Description

Semiconductor substrate and method for manufacturing the same, light emitting element and method for manufacturing the same, and electronic device

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] Patent Document 1 discloses a technique for forming a light emitting element on a laterally grown GaN-based semiconductor layer.

[0003] Japanese Patent Publication No. 2012-114263

[0004] The semiconductor substrate comprises a template substrate including a seed region and a first non-seed region including a first concave surface, a base layer including a base portion located above the seed region and a first wing portion connected to the base, and a first cavity located between the first concave surface and the first wing portion, at least a portion of which has a downwardly convex shape.

[0005] 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to the present embodiment; 2 is a plan view showing a configuration of a semiconductor substrate according to the present embodiment; 3 is a plan view showing a configuration of a semiconductor substrate according to the present embodiment; 4 is a cross-sectional view showing a configuration of a semiconductor substrate according to the present embodiment; 5 is a flowchart showing a method for manufacturing a semiconductor substrate; 6 is a flowchart showing a method for manufacturing a semiconductor substrate; 7 is a cross-sectional view showing a method for manufacturing a semiconductor substrate; 8 is a block diagram showing a manufacturing apparatus for a semiconductor substrate according to the present embodiment; 9 is a flowchart showing a method for manufacturing a light-emitting element; 10 is a cross-sectional view showing a method for manufacturing a light-emitting element; 11 is a plan view showing a method for manufacturing a light-emitting element; 12 is a block diagram showing a manufacturing apparatus for a light-emitting element according to the present embodiment; 13 is a cross-sectional view showing a method for manufacturing a light-emitting element; 14 is a cross-sectional view showing a method for manufacturing a light-emitting element; 15 is a cross-sectional view showing a method for manufacturing a light-emitting element; 16 is a cross-sectional view showing a method for manufacturing a light-emitting element; 17 is a plan view showing a method for manufacturing a light-emitting element; 18 is a cross-sectional view showing a method for manufacturing a light-emitting element; 19 is a cross-sectional view showing a method for manufacturing a light-emitting element; 20 is a cross-sectional view showing a method for manufacturing a light-emitting element; 21 is a cross-sectional view showing a configuration of a light-emitting element; 22 is a cross-sectional view showing a configuration of a light-emitting element; 23 is a cross-sectional view showing a method for manufacturing a light-emitting element; 24 is a cross-sectional view showing a configuration of a light-emitting element; 25 is a cross-sectional view showing a method for manufacturing a light-emitting element; 26 is a cross-sectional view showing a configuration of a light-emitting element; 27 is a cross-sectional view showing a method for manufacturing a 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present invention.

[0006]

[0023] Fig. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 2 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figs. 1 and 2, a semiconductor substrate 10 includes a template substrate TS including a seed region S1 and a first non-seed region D1 including a non-flat first concave surface U1, a base layer 8 including a base B located above the seed region S1 and a first wing portion F1 connected to the base B, and a first cavity C1 located between the first concave surface U1 and the first wing portion F1, at least a portion of which has a downwardly convex shape.

[0007] In the semiconductor substrate 10, a functional layer including a light-emitting active layer is formed on the first wing portion F1, and an optical element (e.g., a lens) is formed in the first cavity C1, thereby obtaining a light-emitting element with high characteristics such as light extraction efficiency. The semiconductor substrate 10 includes the first cavity C1, which allows the optical element to be formed on the underside of the first wing portion F1 without peeling the first wing portion F1 from the template substrate. Furthermore, the semiconductor substrate 10 includes the first cavity C1, which allows the optical element to be formed with a downwardly convex shape on the underside of the first wing portion F1. The semiconductor substrate 10 includes the first cavity C1, which allows the optical element to be easily formed on the underside of the first wing portion F1.

[0008] Here, the "uneven first concave surface" means that the surface (bottom) of the concave portion is not flat. For example, the surface (bottom) of the concave portion may be spherical, aspherical, a curved surface having one or more inflection points, a surface including multiple protrusions, or a surface including concaves and recesses. The "uneven first concave surface" may be a region on which an optical element (described below) can be formed (concave). Hereinafter, the expression "numerical value A to numerical value B" regarding a physical quantity means that the physical quantity is equal to or greater than A and equal to or less than B.

[0009] The template substrate TS may include a main substrate 1 (e.g., a heterogeneous substrate having a lattice constant different from that of the first wing portion F1), an underlayer 4 including a seed region S1, and a mask portion 5 including a first non-seed region D1. The first wing portion F1 may be a nitride semiconductor layer (e.g., a GaN-based semiconductor layer). The template substrate TS may include a second non-seed region D2 including a non-flat second concave surface U2. The base layer 8 may include a second wing portion F2 connected to the base portion B. A second cavity C2, at least a portion of which is convex downward, may be formed between the second concave surface U2 and the second wing portion F2. The first concave surface U1 may be a concave curved surface (first curved surface). The second concave surface U2 may be a concave curved surface (second curved surface).

[0010] Here, for convenience, the direction from the template substrate TS to the base layer 8 is referred to as "upward." In the following, a planar view refers to a view in the normal direction of the template substrate TS, and includes a perspective planar view. "Two members overlap in a planar view" may mean that "at least a portion of one member overlaps the other in a planar view seen in the normal direction of the main substrate 1," and when one of the two members is located above or below the other, the two members may overlap in a planar view.

[0011] With respect to the semiconductor substrate 10, the first and second non-seed regions D1 and D2 may be collectively referred to as the non-seed region D. With respect to the semiconductor substrate 10, the first and second concave surfaces U1 and U2 may be collectively referred to as the curved surface U. With respect to the semiconductor substrate 10, the first and second cavities C1 and C2 may be collectively referred to as the cavity C. With respect to the semiconductor substrate 10, the first and second wing portions F1 and F2 may be collectively referred to as the wing portion F.

[0012] A semiconductor substrate refers to a substrate containing a semiconductor. For example, the semiconductor may contain nitrogen. For example, the semiconductor is a nitride semiconductor. A nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1). Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples of GaN-based semiconductors include GaN, AlGaN, AlGaInN, and InGaN. The GaN-based semiconductor portion 8 contains a GaN-based semiconductor as a main component. The GaN-based semiconductor may be doped or non-doped.

[0013] The a-axis direction of the nitride semiconductor is, for example, the <11-20> direction, and the m-axis direction is, for example, the <1-100> direction. The thickness direction of the base layer 8 may be the c-axis direction of the nitride semiconductor (for example, the <0001> direction). In FIG. 1 and other figures, the first direction X may be the a-axis direction (hereinafter sometimes referred to as the lateral direction), the second direction Y may be the m-axis direction, and the third direction Z may be the c-axis direction (thickness direction).

[0014] Two nitride semiconductor crystals CR adjacent to each other in the first direction X may be located on the template substrate TS with a gap GP between them. The base layer 8, which is the nitride semiconductor crystal CR, may include an edge E1 located above the first non-seed region D1. By halting the growth of the nitride semiconductor crystals CR (source material halt) before they merge with each other, growing in opposite directions by ELO on the first non-seed region D1, island-shaped nitride semiconductor crystals CR (base layer 8) can be formed. For example, the first cavity C1 may have a shape including a curved surface that diverges and converges a light beam.

[0015] The template substrate TS includes a seed region S1 and a first non-seed region D1. The seed region S1 is a region where the template substrate TS and the base layer 8 are connected. For example, if the base layer 8 is a crystal grown by ELO (Epitaxial Lateral Overgrowth), the seed region S1 may be a region that serves as a starting point for growth of the base layer 8. The seed region S1 is adjacent to the first non-seed region D1. If the base layer 8 includes a nitride semiconductor, for example, the seed region S1 may have a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor. If the base layer 8 includes a nitride semiconductor, for example, the seed region S1 may have a shape whose transverse direction is the a-axis direction of the nitride semiconductor. The seed region S1 may include a semiconductor containing nitrogen. For example, the seed region S1 may include a nitride semiconductor. For example, the seed region S1 may include nitrogen and aluminum.

[0016] The first non-seed region D1 is a region of the template substrate TS that is adjacent to the seed region S1. The first non-seed region D1 is a region where the template substrate TS and the base layer 8 are not connected. When the base layer 8 includes a nitride semiconductor, for example, the first non-seed region D1 may have a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor. When the base layer 8 includes a nitride semiconductor, for example, the first non-seed region D1 may be located on the a-axis direction side of the nitride semiconductor with respect to the seed region S1.

[0017] For example, if the base layer 8 is a crystal grown by ELO (Epitaxial Lateral Overgrowth), the first non-seed region D1 may be a region that does not serve as a starting point for growth of the base layer 8. For example, the first non-seed region D1 may be a region of the template substrate TS that suppresses crystal growth so as not to serve as a starting point for growth of the base layer 8. The first and second non-seed regions D1 and D2 may be growth-suppressing regions (selective growth regions) that suppress growth in the c-axis direction.

[0018] The first non-seed region D1 includes a first concave surface U1. The first concave surface U1 may be a concave curved surface (first curved surface). The outer diameter of the first concave surface U1 in a plan view may be 1.0 to 300 μm. The first concave surface U1 may include at least one of an inclined surface inclined with respect to a normal to the template substrate TS and a curved surface. A cross section of the first concave surface U1 perpendicular to the second direction Y may have a downwardly convex shape. The width of the first concave surface U1 in the cross section perpendicular to the second direction Y is smaller than the width of the first wing portion F1.

[0019] The first non-seed region D1 may include a flat surface P1 located farther from the seed region S1 than the first concave surface U1. An edge E1 of the first wing portion F1 may be located above the flat surface P1. A gap J1 may be located between the flat surface P1 and the first wing portion F1. The gap J1 may be used to inject a lens material (e.g., a viscous organic material) into the first cavity C1. The flat surface P1 may be shaped along the lower surface of the first wing portion F1.

[0020] The template substrate TS includes a main substrate 1 primarily composed of a non-nitride semiconductor. The main substrate 1 may be a heterogeneous substrate having a different lattice constant from that of the first wing portion F1. The main substrate 1 may include a semiconductor (e.g., silicon or silicon carbide), or may not include a semiconductor. The template substrate TS is sometimes referred to as a growth substrate. The main substrate 1 may be a free-standing substrate (wafer). The main substrate 1 may be a substrate primarily composed of any one of silicon, silicon carbide, sapphire, and aluminum nitride. The main substrate 1 may be any one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, and an aluminum nitride substrate. The main substrate 1 may have a recess Q1 that overlaps with the first concave surface U1 in a plan view.

[0021] The template substrate TS may include an underlayer 4 located on the main substrate 1. A portion of the underlayer 4 may function as the seed region S1. The template substrate TS may have a mask pattern 6 including a mask portion 5 functioning as the first non-seed region D1 and an opening K exposing the seed region S1. The mask portion 5 may be a film containing silicon. For example, the mask portion 5 may include at least one of a silicon nitride film and a silicon oxide film. The underlayer 4 may have a single-layer structure of a seed layer (e.g., an AlN layer or a GaN-based semiconductor layer). The underlayer 4 may have a stacked structure including a buffer layer (e.g., an AlN layer) on the main substrate 1 side and a seed layer (GaN-based semiconductor layer) on the mask pattern 6 side.

[0022] The semiconductor substrate 10 may include a plurality of element formation portions FP, each including a cavity U and a wing portion F. In the semiconductor substrate 10, the plurality of element formation portions FP may be positioned in a matrix. For example, the plurality of element formation portions FP may be positioned so as to be aligned in the m-axis direction or the a-axis direction of the wing portion F. For example, the plurality of element formation portions FP may be positioned so as to be aligned in the m-axis direction and the a-axis direction of the wing portion F.

[0023] The base layer 8 has a base B and a first wing portion F1. The base B is a portion of the base layer 8 located above the seed region S1. The base B may extend upward from the seed region S1. The first wing portion F1 is connected to the base B. The first wing portion F1 is a portion of the base layer 8 extending from the base B. The first wing portion F1 is a portion of the base layer 8 extending from the base B above the first non-seed region S1. The first wing portion F1 may extend from the base B in the first direction X. The base B and the first wing portion F1 may be adjacent to each other in the first direction X. The first wing portion F1 may have a larger width in the first direction X than the base B. In a plan view, the entire first cavity C1 may overlap the first wing portion F1. The base B and the first wing portion F1 may be adjacent to each other in the first direction X. The first wing portion F1 may have a ratio of width to thickness in the first direction X of 3.0 or greater. The first wing portion F1 may include an edge E1 located above the first non-seed region S1.

[0024] The base layer 8 may be a crystal grown by ELO (Epitaxial Lateral Overgrowth) starting from the seed region S1. The base layer 8 may be a nitride semiconductor crystal CR. In the base layer 8, the threading dislocation density of the wing portions F may be 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the threading dislocation density of the base portion B. The threading dislocation density of the wing portions F may be 5×10 ６ / cm ２ The threading dislocation density of the base layer 8 can be determined by, for example, performing a CL (Cathode Luminescence) measurement. Specifically, the threading dislocations in the base portion 8 can be observed by, for example, mapping the peak shift of the CL measurement.

[0025] In the semiconductor substrate 10, a first cavity C1 is located between the first concave surface U1 and the first wing portion F1. The first cavity C1 has at least a portion that is convex downward. The first cavity C1 may have a lens shape. A lens shape is a shape that includes a curved surface that diverges and converges a light beam.

[0026] FIG. 3 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 4 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 3 and 4 , an injection channel V1 connecting to the first cavity C1 may be located between the first non-seed region D1 and the first wing portion F1. The injection channel V1 can be used to inject a lens material (e.g., a viscous organic material) into the first cavity C1. The injection channel V1 may have a shape extending in the second direction Y (the m-axis direction of the base layer 8). The injection channel V1 may have a shape extending from the first cavity C1 in the second direction Y. The injection channel V1 may extend from an end of the first cavity C1 on the second direction Y side. The injection channel V1 may extend from both ends of the first cavity C1 in the second direction Y. The area of ​​the injection channel V1 in a cross section perpendicular to the second direction Y is smaller than the area of ​​the first cavity C1 in a cross section perpendicular to the second direction Y. The height of the injection channel V1 in a cross section perpendicular to the second direction Y is smaller than the height of the first cavity C1 in a cross section perpendicular to the second direction Y. Multiple injection channels V1 may extend from the first cavity C1. The cross section of the injection channel V1 perpendicular to the second direction Y may have a downwardly convex shape.

[0027] Fig. 5 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. In the semiconductor substrate 10 of Fig. 3, a gap GP extending in the second direction Y is formed. As shown in Fig. 5, a gap GX extending in the first direction X and a gap GP extending in the second direction Y may also be formed. In this case, the lens material can be injected from the gap GX into the cavity C1 via the injection path V1.

[0028] 6 and 7 are flowcharts showing a method for manufacturing a semiconductor substrate. Fig. 8 is a cross-sectional view showing a method for manufacturing a semiconductor substrate. As shown in Fig. 6 and 8 , the method for manufacturing a semiconductor substrate includes a step S30 of preparing a template substrate TS including a seed region S1 and a first non-seed region D1 including a first non-planar concave surface U1, and a step S40 of growing, using the ELO method, a base layer 8 containing a nitride semiconductor above the template substrate TS. The base layer 8 has a base B located above the seed region S1 and a first wing portion F1 connected to the base B, and the first cavity C1 is located between the first concave surface U1 and the first wing portion F1 and has a downwardly convex shape (e.g., a lens shape). As shown in Figures 7 and 8, step S30 may be a process for forming a template substrate TS, including step S33 of preparing a main substrate 1 having a recess Q1 on its upper surface, step S35 of forming a planar base layer 4 on the main substrate 1, and step S37 of forming a mask pattern 6 (a mask portion 5 including a non-flat first recess U1 and an opening K) on the base layer 4.

[0029] The underlayer 4 may be, for example, a gallium nitride film (GaN), an aluminum nitride film (AlN), or a mixed crystal film of gallium and aluminum (AlGaN, InGaN, AlInGaN, etc.). The underlayer 4 may be formed by sputtering. Alternatively, the underlayer 4 may be formed by MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), or the like.

[0030] 9 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M30 that performs step S30 in FIG. 6, an apparatus M40 (e.g., an MOCVD apparatus) that performs step S40 in FIG. 6, and a control device M1 that controls the apparatuses M30 and M40.

[0031] FIG. 10 is a flowchart showing a method for manufacturing a light-emitting element. FIG. 11 is a cross-sectional view showing the method for manufacturing a light-emitting element. FIG. 12 is a plan view showing the method for manufacturing a light-emitting element. As shown in FIGS. 10 to 12, the method for manufacturing a light-emitting element includes a step S60 of preparing a semiconductor substrate 10, a step S70 of forming a first functional layer T1 on a base layer 8, and a step S80 of forming an optical element LS in a first cavity C1. The optical element LA may be a first lens L1. This reduces the distance between the first functional layer T1 and the first lens L1, resulting in a light-emitting element with high characteristics such as light extraction efficiency. The optical element may be, for example, a spherical lens, an aspherical lens, a meniscus lens, a Fresnel lens, or the like. The optical element may be, for example, a light-transmitting member other than a lens, such as a color filter.

[0032] The first functional layer T1 may include a compound semiconductor layer 9 including a light-emitting active layer (e.g., a quantum well structure of a nitride semiconductor), an anode EA, a cathode EC, a transparent electrode ET, an insulating film ZF, and a light-reflecting film LR. The compound semiconductor layer 9 may include a nitride semiconductor (e.g., a GaN-based semiconductor). The light-reflecting film LR may cover the side surfaces of the compound semiconductor layer 9. The light-reflecting film LR may cover the side surfaces of the anode EA. The light-reflecting film LR may be a DBR film. The transparent electrode ET may be, for example, an indium tin oxide (ITO) film. When viewed from a planar perspective, the first concave surface C1 may overlap the entire anode EA. When viewed from a planar perspective, the first concave surface C1 may overlap a portion of the anode EA. When viewed from a planar perspective, the first concave surface C1 does not have to overlap the cathode EC.

[0033] Fig. 13 is a block diagram showing a light-emitting device manufacturing apparatus 90 according to this embodiment. The light-emitting device manufacturing apparatus 90 includes an apparatus M60 that performs step S60 in Fig. 10, an apparatus M70 that performs step S70 in Fig. 10, an apparatus M80 that performs step S80 in Fig. 10, and a control device M2 that controls the apparatuses M60, M70, and M80.

[0034] 14 to 17 are cross-sectional views showing a method for manufacturing a light-emitting element. Fig. 18 is a plan view showing a method for manufacturing a light-emitting element. Fig. 19 is a cross-sectional view showing a method for manufacturing a light-emitting element. Figs. 20 to 22 are plan views showing a method for manufacturing a light-emitting element.

[0035] 14 to 17, after the first functional layer T1 is formed, the lens material LM is injected and cured, and then the mask portion 5 is removed. Then, the first wing portion F1 and the first functional layer T1 are mounted (transferred) to the support substrate SK, and the template substrate TS is peeled off. In other words, the first lens L1 may be formed and the mask portion 5 may be removed before the first functional layer T1 is bonded to the support substrate SK.

[0036] As shown in FIG. 14 , the template substrate TS may include a mask portion 5 that functions as a first non-seed region D1 and an opening K that exposes the seed region S1. The first non-seed region D1 may include a flat surface P1 located farther from the seed region S1 than the first concave surface U1. A gap J1 may be located between the flat surface P1 and a first wing portion F1, and the lens material LM may be injected into the first cavity C1 through the gap J1. The template substrate TS may include a second non-seed region D2 that includes a non-flat second concave surface U2. The base layer 8 may include a second wing portion F2 that connects to the base B. A second cavity C2, at least a portion of which has a downwardly convex shape, may be located between the second concave surface U2 and the second wing portion F2. The second wing portion F2 may extend from the base B to the opposite side of the first wing portion F1. A second functional layer T2 may be formed on the second wing portion F2 of the base layer 8, and a second lens L2 may be formed in the second cavity C2. The diameter of the first and second lenses L1 and L2 in the thickness direction may be 1.0 to 300 μm.

[0037] As shown in Figures 14 and 15, the first lens L1 to be bonded to the base layer 8 may be formed by hardening a viscous liquid lens material LM injected into the first cavity C1 into a solid lens material LJ. The lens material LM may be injected into the first cavity C1 by increasing the pressure on the lens material LM disposed outside the first cavity C1. In this case, the pressure on the lens material LM may be increased from vacuum pressure to atmospheric pressure. Examples of the lens material LM that can be used include acrylic resin (PMMA), cyclic olefin polymer (COC, COP, etc.), polycarbonate (PC), fluorene-based polyester, and thermoplastic polyimide (TPI). At least one of heat and light may be used to harden the lens material LM.

[0038] 14, the lens material LM may be poured into the first cavity C1 after being disposed so as to cover the base layer 8 and the first functional layer T1. A gap GP may be located facing the side surface of the first wing portion F1, and the lens material LM may be poured into the first cavity C1 through the gap GP and the air gap J1.

[0039] 18 , a step of patterning the base layer 8 may be included. As shown in FIGS. 4 and 18 , an injection channel V1 connecting to the first cavity C1 may be located between the first non-seed region D1 and the first wing portion F1, and the lens material LM may be injected into the first cavity C1 through the injection channel V1. When the injection channel V1 is formed, the lens material can be injected into the first cavity C1 through the injection channel V1, so that the first wing portion F1 and the mask portion 5 (first non-seed region D1) may be in contact with each other as shown in FIG.

[0040] 15 and 21, a trench TR may be formed in the base portion B of the base layer 8, reaching the opening K. As shown in FIG. 16, an etching solution may be introduced through the trench TR to etch the mask portion 5. When an insulating film ZF with low etchant resistance is used, the insulating film ZF may be covered (protected) with a resist RS and then the mask portion 5 may be removed. The mask portion 5 may include two layers with different etching rates and film qualities (e.g., a silicon nitride film and a silicon oxide film), and the layer with the higher etching rate and lower film quality (e.g., a silicon oxide film) may be removed.

[0041] 20 , after the trench TR is formed, the base layer 8 is held by the remnant TZ of the base portion B. As shown in FIGS. 17 , 21 , and 22 , by breaking the periphery of the remnant TZ, the template substrate TS can be peeled off from the base layer 8 (the base layer 8 and the underlayer 4 are separated), and the light-emitting element 20 can be obtained.

[0042] 17 , a step of bonding the first functional layer T1 to a support substrate SK may be performed before peeling off the template substrate TS. A step of peeling off the template substrate TS from the base layer 8 may be performed while the base layer 8 to which the first lens L1 is bonded and the first functional layer T1 are supported by the support substrate SK. The support substrate SK may include bumps BA and BC and pads PA and PC. The cathode EC of the first functional layer T1 may be connected to the pad PC via the bump BC and the solder layer H. The anode EA of the functional layer T1 may be connected to the pad PA via the bump BA and the solder layer H.

[0043] The template substrate TS includes a main substrate 1 whose main component is a non-nitride semiconductor, and an alignment mark may be included in the main substrate 1. The first functional layer T1 may be formed using the first cavity C1 as an alignment mark.

[0044] 23 to 25 are cross-sectional views showing a method for manufacturing a light-emitting element. In Figures 23 to 25, after the first functional layer T1 is formed, the first wing portion F1 and the first functional layer T1 are mounted (transferred) onto a support substrate SK, and then a lens material LM is injected and cured. Thereafter, the mask portion 5 is removed and the template substrate TS is peeled off.

[0045] 23 to 25, the first functional layer T1 may be bonded to the support substrate SK, and the lens material LM may be placed in contact with the semiconductor substrate 10 and the support substrate SK before being injected into the first cavity C1. The viscous lens material LM may be introduced through an injection hole HS formed in the support substrate SK, and then may be turned into a solid lens material LJ by at least one of heat and light.

[0046] As shown in FIG. 24 , a hole HG may be formed by removing a portion of the lens material LJ that contacts the side surface of the base layer 8 and the mask portion 5 (the portion located in the gap GP). As shown in FIG. 25 , an etching solution may be introduced through the hole HG to etch the mask portion 5. In this case, it is preferable to cover the insulating film ZF, which has low resistance to the etchant, with the lens material LJ. As shown in FIGS. 21 , 22 , and 25 , the template substrate TS can be peeled off from the base layer 8 (separating the base layer 8 and the underlayer 4) by fracturing the periphery of the remaining portion TZ, thereby obtaining the light-emitting element 20. The first functional layer T1 of the light-emitting element 20 may be covered with the lens material LJ.

[0047] 26 is a cross-sectional view showing a method for manufacturing a light-emitting element. As shown in Fig. 26, in the step of forming the hole HG, a through-hole H1 (connected to the injection hole HS) may be formed in the lens material LJ along the pattern of the support substrate SK. The through-hole H1 may be located between the anode EA and the cathode EC in plan view.

[0048] 27 and 28 are cross-sectional views showing the configuration of a light-emitting device. As shown in FIGS. 27 and 28, the light-emitting device 20 includes a nitride semiconductor portion F1, a functional layer T1 located below the nitride semiconductor portion F1, a lens L1 bonded to the upper surface of the nitride semiconductor portion F1, and a light-transmitting film TF made of the same material as the lens L1 and in contact with the upper surface of the nitride semiconductor portion F1. The nitride semiconductor portion F1 may be located above a support substrate SK (e.g., a submount substrate) and electrically connected to the support substrate SK. The nitride semiconductor portion may have a substantially rectangular shape, and may have, for example, a length in the m-axis direction of 3 to 350 μm, a length in the a-axis direction of 3 to 350 μm, and a length (thickness) in the c-axis direction of 0.5 to 10 μm. The light-transmitting film TF may contain substantially the same material as the lens L1 and be formed integrally with the lens L1.

[0049] The light-transmitting film TF may be thinner than the lens L1. The thickness of the lens L1 may be, for example, 1.0 to 100 μm. The thickness of the light-transmitting film TF may be, for example, 0.2 to 5.0 μm. The thickness of the light-transmitting film TF may be smaller than the thickness of the peripheral edge of the lens L1. The light-transmitting film TF may be connected to the entire outer edge of the lens L1. The light-transmitting film TF may have a shape extending from the outer edge of the lens L1 in the a-axis direction or m-axis direction of the nitride semiconductor portion F. In a plan view, the outer edge of the light-transmitting film TF may be spaced apart from the edge E1 of the nitride semiconductor portion F1. The diameter of the lens L1 may be 1.0 to 300 μm. As shown in FIG. 28 , the functional layer T1 may be covered with a lens material LJ.

[0050] The functional layer T1 may include a compound semiconductor layer 9 including a light-emitting active layer 9A (e.g., a quantum well structure of a nitride semiconductor), an anode EA, a cathode EC, a transparent electrode ET, an insulating film ZF, and a light-reflecting film LR. The compound semiconductor layer 9 may include a nitride semiconductor (e.g., a GaN-based semiconductor). The light-reflecting film LR may cover a side surface of the compound semiconductor layer 9. The light-reflecting film LR may cover a side surface of the anode EA. The light-reflecting film LR may be a DBR film. The transparent electrode ET may be, for example, an indium tin oxide (ITO) film.

[0051] When viewed from above, the lens L1 may overlap the entire anode EA, or may overlap a portion of the anode EA, or may not overlap the cathode EC.

[0052] When viewed from above, the light-transmitting film TF may overlap a portion of the anode EA, when viewed from above, the light-transmitting film TF may not overlap a portion of the anode EA, or when viewed from above, the light-transmitting film TF may overlap the entire cathode EC.

[0053] The compound semiconductor layer 9 may include a p-type layer 9P (e.g., a p-type GaN-based semiconductor) that overlaps the lens L1 in a planar view. The support substrate SK may include bumps BA and BC and pads PA and PC. The cathode EC of the functional layer T1 may be connected to the pad PC via the bump BC and a solder layer H. The anode EA of the functional layer T1 may be connected to the pad PA via the bump BA and a solder layer H. The bumps BA and BC may be light-reflective.

[0054] Fig. 29 is a cross-sectional view showing a method for manufacturing a light-emitting device. As shown in Fig. 29, a group of protrusions AP may be formed on the back surface of the first wing portion F1. The group of protrusions AP can be formed by wet etching the back surface of the base layer 8, which is a nitrogen polarity plane (-C plane). This increases the bonding strength between the first lens L1 (optical element LS) and the first wing portion F1.

[0055] 30 is a cross-sectional view showing a method for manufacturing a light-emitting element. As shown in Fig. 30, the first concave surface U1 may include a plurality of inclined surfaces SP (surfaces inclined with respect to the third direction Z). In this case, an optical element LS having a shape in which a plurality of quadrangular pyramids are aligned in the first direction X can be obtained. In a plan view, the optical element LS may overlap the compound semiconductor layer 9 on the first wing portion F1.

[0056] 31 to 35 are cross-sectional views showing the configuration of a semiconductor device. The semiconductor device 30 may include a plurality of light-emitting elements 20 and a support substrate SK (e.g., a submount substrate) electrically connected to the plurality of light-emitting elements 20. As shown in FIG. 31, a group of protrusions may be formed on the back surface of the first lens L1 (optical element LS). As shown in FIG. 32, the first lens L1 (optical element LS) may have a shape in which a plurality of quadrangular pyramids are arranged in the first direction X. As shown in FIG. 33, the first lens L1 (optical element LS) may have a mesa shape with a flat top surface and curved corners. As shown in FIG. 34, the first lens L1 (optical element LS) may be an annular convex lens that focuses light emitted from the periphery of the light-emitting region. As shown in FIG. 35, the optical element LS may be a light-shielding body (annular light-shielding wall) ST that narrows the light emitted from the light-emitting region.

[0057] 36 is a cross-sectional view showing the configuration of an electronic device 40. As shown in Fig. 36, an electronic device 40 may include a semiconductor device 30 including a plurality of light-emitting elements 20, a support substrate SK on which the plurality of light-emitting elements 20 are mounted and which is electrically connected to the plurality of light-emitting elements 20, and a condenser lens SL that condenses light from the plurality of light-emitting elements 20.

[0058] FIG. 37 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. In FIGS. 1 and 11 , the base layer 4 is located on the bottom surface of the recess Q1, but this is not limiting. As shown in FIG. 37 , the base layer 4 may not be located on the bottom surface of the recess Q1 (the base layer 4 on the bottom surface of the recess Q1 may be removed). In the semiconductor substrate 10 of FIG. 1 , unevenness reflecting the crystal plane orientation is generated in the base layer 4 on the bottom surface of the recess Q1. When a lens is formed in the recess Q1, fine unevenness (texture) is formed on the lens surface, improving light extraction efficiency. Furthermore, in the semiconductor substrate 10 of FIG. 37 , the base layer 4 is not located on the bottom surface of the recess Q1, so the first concave surface U1 (the surface of the mask portion 5) is mirror-finished. This makes it easier to peel off the lens (e.g., a resin film) when a lens is formed in the recess Q1.

[0059] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0060] Disclosure 1: A semiconductor substrate comprising: a template substrate including a first non-seed region having a non-flat first concave surface and a seed region adjacent to the first non-seed region; and a base layer including a base portion located above the seed region and a first wing portion connected to the base and located above the first non-seed region, wherein a first cavity having at least a downwardly convex shape is located between the first concave surface and the first wing portion.

[0061] Disclosure 2: The semiconductor substrate of Disclosure 1, wherein the first cavity is lens-shaped.

[0062] Disclosure 3: The semiconductor substrate according to Disclosure 1 or 2, wherein the first concave surface is a concave curved surface.

[0063] Disclosure 4: A semiconductor substrate according to any one of Disclosures 1 to 3, wherein the first concave surface includes at least one of an inclined surface inclined with respect to the normal to the template substrate and a curved surface.

[0064] Disclosure 5: A semiconductor substrate described in any one of Disclosures 1 to 4, wherein the first non-seed region includes a flat surface located farther from the seed region than the first concave surface, and an edge of the first wing portion is located above the flat surface.

[0065] Disclosure 6: The semiconductor substrate of Disclosure 5, wherein a gap is located between the flat surface and the first wing portion.

[0066] Disclosure 7: A semiconductor substrate according to any one of Disclosures 1 to 6, wherein an injection path leading to the first cavity is located between the first non-seed region and the first wing portion.

[0067] Disclosure 8: The semiconductor substrate according to any one of Disclosures 1 to 7, wherein the template substrate includes a main substrate mainly composed of a non-nitride semiconductor, the base layer includes a nitride semiconductor, and the main substrate has a recess that overlaps with the first concave surface in a planar view.

[0068] Disclosure 9: The semiconductor substrate of Disclosure 8, wherein the template substrate includes an underlayer located on the main substrate, and a portion of the underlayer functions as the seed region.

[0069] Disclosure 10: A semiconductor substrate described in any one of Disclosures 1 to 9, wherein the template substrate has a mask pattern including a mask portion that functions as a first non-seed region and an opening that exposes the seed region.

[0070] Disclosure 11: A semiconductor substrate according to any one of Disclosures 1 to 10, wherein the outer diameter of the first concave surface in a plan view is 1.0 to 300 μm.

[0071] Disclosure 12: The semiconductor substrate according to any one of Disclosures 1 to 11, wherein the template substrate has a main substrate that is one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, and an aluminum nitride substrate; the template substrate includes a second non-seed region that includes a non-flat second concave surface; the base layer includes second wing portions that are connected to the base; a second cavity, at least a portion of which is downwardly convex, is located between the second concave surface and the second wing portions; the seed region includes a nitride semiconductor; each of the first and second wing portions includes a GaN-based semiconductor; and a threading dislocation density in each of the first and second wing portions is 1 / 10 or less of the threading dislocation density in the base.

[0072] Disclosure 13: A semiconductor substrate described in any one of Disclosures 1 to 12, comprising a plurality of element formation portions each including the first cavity and the first wing portion, and the plurality of element formation portions are arranged in a matrix.

[0073] Disclosure 14: A method for manufacturing a semiconductor substrate, comprising: a step of preparing a template substrate including a first non-seed region and a seed region, the first non-seed region including a first non-flat concave surface; and a step of growing, using an ELO method, a base layer including a nitride semiconductor above the template substrate, the base layer having a base located above the seed region and first wing portions connected to the base, thereby forming a first cavity located between the first concave surface and the first wing portions, at least a portion of which is convex downward.

[0074] Disclosure 15: A semiconductor substrate manufacturing apparatus that performs each of the steps described in Disclosure 14.

[0075] Disclosure 16: A method for manufacturing a light-emitting element, comprising the steps of: preparing a semiconductor substrate according to Disclosure 1; forming a first functional layer on the base layer; and forming an optical element in the first cavity.

[0076] Disclosure 17: The method for manufacturing a light-emitting device according to Disclosure 16, wherein the front optical element is a first lens.

[0077] Disclosure 18: A method for manufacturing a light-emitting element as described in Disclosure 17, wherein the first lens bonded to the base layer is formed by hardening a lens material injected into the first cavity.

[0078] Disclosure 19: A method for manufacturing a light-emitting element as described in Disclosure 18, wherein the first non-seed region includes a flat surface located farther from the seed region than the first concave surface, a gap is located between the flat surface and the first wing portion, and the lens material is injected into the first cavity through the gap.

[0079] Disclosure 20: A method for manufacturing a light-emitting element described in Disclosure 18 or 19, wherein an injection channel leading to the first cavity is located between the first non-seed region and the first wing portion, and the lens material is injected into the first cavity through the injection channel.

[0080] Disclosure 21: A method for manufacturing a light-emitting element according to Disclosure 19 or 20, wherein the lens material is injected into the first cavity by increasing the air pressure on the lens material disposed outside the first cavity.

[0081] Disclosure 22: The method for manufacturing a light-emitting element according to Disclosure 21, wherein the pressure on the lens material is increased from vacuum pressure to atmospheric pressure.

[0082] Disclosure 23: A method for manufacturing a light-emitting device according to Disclosure 18, comprising the step of patterning the base layer.

[0083] Disclosure 24: A method for manufacturing a light-emitting element as described in Disclosure 19, wherein a gap facing a side surface of the first wing portion is located, and the lens material is injected into the first cavity through the gap and the void.

[0084] Disclosure 25: A method for manufacturing a light-emitting element according to Disclosure 18, comprising a step of bonding the first functional layer to a support substrate.

[0085] Disclosure 26: A method for manufacturing a light-emitting element described in Disclosure 25, in which the template substrate is peeled off from the base layer while the base layer to which the first lens is bonded and the first functional layer are supported by the support substrate.

[0086] Disclosure 27: A method for manufacturing a light-emitting element according to Disclosure 25, wherein the first lens is formed before bonding the first functional layer to a support substrate.

[0087] Disclosure 28: A method for manufacturing a light-emitting element according to Disclosure 27, wherein the lens material is disposed so as to cover the base layer and the first functional layer and then injected into the first cavity.

[0088] Disclosure 29: The method for manufacturing a light-emitting element described in Disclosure 23, wherein the template substrate includes a mask portion that functions as a first non-seed region and an opening that exposes the seed region, and a trench is formed in the base portion that reaches the opening.

[0089] Disclosure 30: The method for manufacturing a light-emitting element according to Disclosure 29, wherein an etching solution is introduced from the trench to etch the mask portion.

[0090] Disclosure 31: A method for manufacturing a light-emitting element as described in Disclosure 29, in which after the trench is formed, the base layer is held by the remaining portion of the base, and the template substrate is peeled off from the base layer by breaking the remaining portion.

[0091] Disclosure 32: A method for manufacturing a light-emitting element described in Disclosure 18, in which the first functional layer is bonded to a support substrate, and the lens material is placed in contact with the semiconductor substrate and the support substrate, and then injected into the first cavity.

[0092] Disclosure 33: The method for manufacturing a light-emitting element described in Disclosure 32, wherein the template substrate includes a mask portion that functions as a first non-seed region and an opening that exposes the seed region, and a hole is formed by removing a portion of the lens material that contacts the side of the base layer and the mask portion.

[0093] Disclosure 34: The method for manufacturing a light-emitting element according to Disclosure 33, wherein an etching solution is introduced through the hole to etch the mask portion.

[0094] Disclosure 35: A method for manufacturing a light-emitting element according to Disclosure 30 or 34, wherein the mask portion includes two layers with different etching rates and film qualities, and the layer with the higher etching rate and lower film quality is removed.

[0095] Disclosure 36: A method for manufacturing a light-emitting element according to any one of Disclosures 16 to 35, wherein the template substrate includes a main substrate primarily composed of a non-nitride semiconductor, the main substrate includes an alignment mark, and the first cavity is used as an alignment mark to form the first functional layer.

[0096] Disclosure 37: A method for manufacturing a light-emitting element described in any one of Disclosures 16 to 36, wherein the template substrate includes a second non-seed region including a non-flat second concave surface; the base layer includes a second wing portion connected to the base; a second cavity having at least a portion of a downwardly convex shape is located between the second concave surface and the second wing portion; a second functional layer is formed on the base layer; a second lens is formed in the second cavity; and the diameters of the first and second lenses are 1.0 to 300 μm.

[0097] Disclosure 38: A light-emitting device manufacturing apparatus that performs each of the steps described in any one of Disclosures 16 to 37.

[0098] Disclosure 39: A light-emitting device comprising: a nitride semiconductor portion; a functional layer located below the nitride semiconductor portion; a lens bonded to an upper surface of the nitride semiconductor portion; and a translucent film made of the same material as the lens and in contact with the upper surface of the nitride semiconductor portion.

[0099] Disclosure 40: The light-emitting element according to Disclosure 39, wherein the transparent film is thinner than the lens.

[0100] Disclosure 41: A light-emitting element according to Disclosure 39 or 40, wherein the transparent film is connected to the entire outer edge of the lens.

[0101] Disclosure 42: A light-emitting element according to any one of Disclosures 39 to 41, wherein the transparent film extends from the outer edge of the lens in the a-axis direction or the m-axis direction of the nitride semiconductor portion.

[0102] Disclosure 43: A light-emitting element according to any one of Disclosures 39 to 42, wherein, in a plan view, the outer edge of the transparent film is spaced apart from the edge of the nitride semiconductor portion.

[0103] Disclosure 44: The light-emitting element according to any one of Disclosures 39 to 43, wherein the diameter of the lens is 1.0 to 300 μm.

[0104] Disclosure 45: A light-emitting element according to any one of Disclosures 39 to 44, wherein the functional layer includes an active layer that overlaps with the lens in a planar view.

[0105] Disclosure 46: An electronic device comprising the light-emitting element according to any one of Disclosures 39 to 45 and a support substrate electrically connected to the light-emitting element.

[0106] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 5 Mask portion 6 Mask pattern 8 Base layer 9 Compound semiconductor layer 10 Semiconductor substrate 20 Light-emitting element (semiconductor device) 25 Electronic device TS Template substrate SK Support substrate S1 Seed portion (seed region) B Base L1 First lens L2 Second lens D1 First non-seed region (growth-inhibited region) D2 Second non-seed region (growth-inhibited region) F1 First wing portion (nitride semiconductor portion) F2 Second wing portion (nitride semiconductor portion) T1, T2 Functional layer

Claims

1. A semiconductor substrate comprising: a template substrate including a first non-seed region including a first concave surface and a seed region adjacent to the first non-seed region; and a base layer including a base portion located above the seed region and a first wing portion connected to the base and located above the first non-seed region, wherein a first cavity, at least a portion of which is convex downward, is located between the first concave surface and the first wing portion.

2. The semiconductor substrate of claim 1, wherein said first cavity is lens-shaped.

3. The semiconductor substrate according to claim 1 or 2, wherein the first concave surface is a concave curved surface.

4. The semiconductor substrate according to any one of claims 1 to 3, wherein the first concave surface includes at least one of an inclined surface inclined with respect to the normal to the template substrate and a curved surface.

5. A semiconductor substrate according to any one of claims 1 to 4, wherein the first non-seed region includes a flat surface located farther from the seed region than the first concave surface, and an edge of the first wing portion is located above the flat surface.

6. The semiconductor substrate of claim 5, wherein an air gap is located between said planar surface and said first wing portion.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein an injection path leading to the first cavity is located between the first non-seed region and the first wing portion.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein the template substrate has a mask pattern including a mask portion that functions as a first non-seed region and an opening that exposes the seed region.

9. The semiconductor substrate according to any one of claims 1 to 8, wherein the template substrate has a main substrate which is one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, and an aluminum nitride substrate, the template substrate includes a second non-seed region including a second concave surface, the base layer is connected to the base and includes second wing portions extending from the base to the opposite side of the first wing portions, a second cavity having at least a portion of a downwardly convex shape is located between the second concave surface and the second wing portions, the seed region includes a nitride semiconductor, each of the first and second wing portions includes a GaN-based semiconductor, and the threading dislocation density of each of the first and second wing portions is 1 / 10 or less of the threading dislocation density of the base.

10. The semiconductor substrate according to any one of claims 1 to 9, comprising a plurality of element formation portions each including the first cavity and the first wing portion, the plurality of element formation portions being arranged in a matrix.

11. A method for manufacturing a light-emitting element, comprising the steps of: preparing a semiconductor substrate according to any one of claims 1 to 10; forming a first functional layer on the base layer; and forming an optical element in the first cavity.

12. The method for manufacturing a light-emitting device according to claim 11, wherein the optical element is a first lens.

13. The method for manufacturing a light-emitting device according to claim 12, wherein the first lens bonded to the base layer is formed by hardening the lens material injected into the first cavity.

14. The method for manufacturing a light-emitting element described in claim 13, wherein the first non-seed region includes a flat surface located farther from the seed region than the first concave surface, a gap is located between the flat surface and the first wing portion, and the lens material is injected into the first cavity through the gap.

15. The method for manufacturing a light-emitting element according to claim 13, wherein an injection channel leading to the first cavity is located between the first non-seed region and the first wing portion, and the lens material is injected into the first cavity through the injection channel.

16. The method for manufacturing a light-emitting element according to claim 14 or 15, wherein the lens material is injected into the first cavity by increasing the air pressure on the lens material disposed outside the first cavity.

17. The method for manufacturing a light-emitting device according to claim 16, wherein the pressure on the lens material is increased from vacuum pressure to atmospheric pressure.

18. A method for manufacturing a light-emitting element according to any one of claims 13 to 17, wherein the template substrate includes a mask portion that functions as a first non-seed region and an opening that exposes the seed region, and the method comprises: a step of patterning the base layer, the step including forming a trench in the base that reaches the opening; and a step of introducing an etching solution from the trench to etch the mask portion.

19. The method for manufacturing a light-emitting device according to claim 14, wherein a gap is located facing a side surface of the first wing portion, and the lens material is injected into the first cavity through the gap and the void.

20. A method for manufacturing a light-emitting element according to any one of claims 13 to 19, comprising a step of bonding the first functional layer to a support substrate.

21. The method for manufacturing a light-emitting element according to claim 20, wherein the template substrate is peeled off from the base layer while the base layer and the first functional layer bonded to the first lens are supported by the support substrate.

22. The method for manufacturing a light-emitting element according to claim 20 or 21, wherein the first lens is formed before bonding the first functional layer to the support substrate.

23. The method for manufacturing a light-emitting element according to claim 22, wherein the lens material is injected into the first cavity after being disposed so as to cover the base layer and the first functional layer.

24. The method for manufacturing a light-emitting element according to claim 13, wherein the first functional layer is bonded to a support substrate, and the lens material is injected into the first cavity after being placed in contact with the semiconductor substrate and the support substrate.

25. A method for manufacturing a light-emitting element as described in claim 24, wherein the template substrate includes a mask portion that functions as a first non-seed region and an opening that exposes the seed region, and a hole is formed by removing a portion of the lens material that contacts the side surface of the base layer and the mask portion.

26. The method for manufacturing a light-emitting element according to claim 25, wherein an etching solution is introduced through the hole to etch the mask portion.

27. The method for manufacturing a light-emitting element according to claim 25 or 26, wherein the mask portion includes two layers with different etching rates and film qualities, and the layer with the higher etching rate and lower film quality is removed.

28. A method for manufacturing a light-emitting element according to any one of claims 11 to 27, wherein the template substrate includes a main substrate whose main component is a non-nitride semiconductor, the main substrate includes an alignment mark, and the first functional layer is formed using the first cavity as an alignment mark.

29. A method for manufacturing a light-emitting element according to any one of claims 11 to 28, wherein the template substrate includes a second non-seed region including a second concave surface, the base layer includes a second wing portion connected to the base portion, a second cavity having at least a portion of a downwardly convex shape is located between the second concave surface and the second wing portion, a second functional layer is formed on the base layer, a second lens is formed in the second cavity, and diameters of the first and second lenses are 1.0 to 300 μm.

30. A light-emitting device manufacturing apparatus that performs each of the steps described in claim 11.

31. A light-emitting element comprising: a nitride semiconductor portion; a functional layer located below the nitride semiconductor portion; a lens bonded to an upper surface of the nitride semiconductor portion; and a light-transmitting film made of the same material as the lens and in contact with the upper surface of the nitride semiconductor portion.

32. The light-emitting device according to claim 31, wherein the transparent film is thinner than the lens.

33. The light-emitting element according to claim 31 or 32, wherein the transparent film is continuous with the entire outer edge of the lens.

34. The light-emitting device according to any one of claims 31 to 33, wherein the transparent film extends from the outer edge of the lens in the a-axis direction or the m-axis direction of the nitride semiconductor portion.

35. The light-emitting element according to any one of claims 31 to 34, wherein, in a plan view, the outer edge of the transparent film is spaced apart from the edge of the nitride semiconductor portion.

36. The light-emitting element according to any one of claims 31 to 35, wherein the functional layer includes an active layer that overlaps with the lens in a plan view.

37. An electronic device comprising the light-emitting element according to any one of claims 31 to 36 and a support substrate electrically connected to the light-emitting element.

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