Semiconductor device and method for producing same

Abstract

Provided are a novel semiconductor device using a metallic delafossite-type oxide and a method for producing the same. According to one aspect of the present invention, provided is a semiconductor device having an electrode of PdCoO2 provided on a (001) plane of a compound semiconductor, a Schottky junction being formed between the compound semiconductor and the electrode.

Description

Semiconductor device and manufacturing method thereof REFERENCE TO RELATED APPLICATIONS

[0001] This application is the benefit of the priority rights of prior Japanese patent applications No. 2024-30870 (filing date: March 1, 2024) and No. 2024-71069 (filing date: April 25, 2024), the entire disclosures of which are incorporated herein by reference.

[0002] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0003] Semiconductor devices such as diodes and transistors have interfaces between metals and semiconductors. There are two types of interfaces: Schottky interfaces, which exhibit rectifying properties, and ohmic interfaces, which allow current to flow without loss. These interfaces can be created depending on the purpose. The work function of the metal is one of the parameters that determines whether a Schottky interface or an ohmic interface is formed. For example, at the interface with an n-type semiconductor, the larger the work function, the easier it is to form a Schottky interface, thereby increasing the breakdown voltage of the semiconductor device. Furthermore, the more stable a metal is in air, the more stable the Schottky interface characteristics are. While the work function varies depending on the type of metal, the work function of elemental metals that are stable in air is limited to a range of approximately 4.0 to 5.7 eV (Non-Patent Documents 16 and 17).

[0004] On the other hand, metallic delafossite-type oxides are stable materials with a large work function. ２ (A = Pd or Pt, M = Co, Cr, or Rh), and is a stable substance with high electrical conductivity (Non-Patent Documents 1 and 10). Therefore, by stacking a semiconductor and a metallic delafossite-type oxide, a stable and large Schottky interface can be formed at the interface between them, which enables the semiconductor device to have high breakdown voltage and high temperature operation. For example, Non-Patent Document 2 describes β-Ga ２ O ３ PdCoO on the (-201) plane ２By forming a layer, a large Schottky barrier is formed at the interface between the two. Note that the "-" in the notation of the plane orientation indicates a bar placed above the character immediately following it. Also, although the electrical properties of the interface are not shown, the PdCrO ２ There has also been reported an example of forming a layer (Non-Patent Document 3). Note that the barrier heights of representative metals are disclosed in Non-Patent Documents 18 and 19.

[0005] The metallic delafossite-type oxide is ＋ and [BO ２ ] － has a structure in which A is alternately stacked, ＋ and [BO ２ ] － It is also known that the work function changes depending on which of the two surfaces is the termination surface (Non-Patent Document 4).

[0006] In recent years, various methods have been reported for forming metallic delafossite-type oxide films. ２ O ３ PdCoO on the substrate ２ There have been reported methods for forming thin films of PdCoO by pulsed laser deposition (Non-Patent Document 5) and molecular beam epitaxy (Non-Patent Document 6). ２ By using the sintered body as a target, PdCoO ２ A method for forming a thin film has also been reported (Non-Patent Document 7).

[0007] In addition, applications of metallic delafossite-type oxides to transparent electrode layers (Non-Patent Document 5), catalysts (Non-Patent Document 8), and terahertz wave sources (Non-Patent Document 9) have also been reported.

[0008] In addition, β-gallium oxide (β-Ga) with a band gap of approximately 4.7 eV to 4.9 eV, which is larger than the band gap (3.3 eV to 3.4 eV) of silicon carbide (SiC) and gallium nitride (GaN), has been developed. ２ O ３ By using the substrate as a semiconductor, it is expected that the breakdown voltage of the semiconductor device will be further increased.

[0009] Gallium oxide (β-Ga ２O ３ Regarding β-Ga, for example, in addition to Non-Patent Document 2, Non-Patent Document 11 ２ O ３ PdCoO on the (-201) plane ２ Furthermore, Non-Patent Document 4 reports on the high frequency characteristics of a Schottky diode fabricated by forming a β-Ga ２ O ３ PdCoO on the (-201) plane ２ In this paper, a Schottky diode is fabricated by forming a layer and then forming a metal layer of Ni, Ti, Cr, Pt, etc. thereon, and the characteristics of the Schottky diode are reported. ２ O ３ PdCrO formed on the (-201) plane of ２ The analysis results of the layer by XRD (X-Ray Diffraction) and the β-Ga ２ O ３ (-201) plane of PdCrO ２ They report the properties of the Schottky interface at the interface with the layer.

[0010] However, the β-Ga used in the above Non-Patent Documents 2, 11 to 13 ２ O ３ The (-201) plane is prone to dislocation defects and stacking faults in the epitaxial layer, which is disadvantageous for achieving high breakdown voltage and high mobility, and is therefore unsuitable for application in power devices (Non-Patent Documents 14 and 15).

[0011] Takayuki Harada、"Surface and interface Properties of quasi-two-dimensional "metallic oxygenates", JSAP Review, Volume 2022, Page 220303, 2022 Takayuki Harada, his 2nd name, "Electric dipole effect in PdCoO2 / β-Ga2O3 Schottky diodes for high-temperature operation”, Science Assistance, Vol. 5, p. eaax5733, 2019, Jonathan M. Ok, and ten others, “Pulsed-laser epitaxis of metallic delafossify PdCrO2 films”, APL Materialis, Vol. 8, p. 051104, 2020, Chinese Ming Yim, and five others, “Quantisiparticulare interferencia and quántúm” Confinement in a correlated Rashba spin-split 2D electronic liquid", Science Advances, Volume 7, Page eabd7361, 2021 Takayuki Harada, his 2 names, "Highly conducive PdCoO2 ULTRATHIN FILMS FOR TRANSPARENT "electrode", APL Materials, Volume 6, Page 046107, 2018 Matthew Brahlek, 10 others, “Growth of metallic delafossify PdCoO2 by molecular biology”, Physician Insights, Vol. 3, p. 093401, 2019, Takayukii Harada, 3 others, “Sputter-grown c-axes-orientated PdCoO2 thiin films”, Journal of Applied Physics, Vol. 133, p. 085302, 2023, Filip Podjaski, et al., “Rational strait engineering in delafossituation for high"Efficient hydrogen evolution catalysis in acidic media," Nature Catalysis, Vol. 3, p. 55, 2020; Peter Yordanov and six others, "Generation of Terahertz Radiation via the Transverse Thermoelectric Effect," Advanced Materials, Vol. 35, p. 2305-622, 2023; R. D. Shannon and two others, "Chemistry of Noble Metal Oxides. I. "Syntheses and Properties of ABO2 Delafossite Compounds", Inorganic Chemistry Vol. 10, p. 713, 1971 Takayuki Harada, et al., “Dynamic characteristics of PdCoO2 / β-Ga2O3 Schottky junctions”, Applied Physics Letters, Volume 116, Page 232104, 2020 Takayuki Harada and 1 other person, “Control of Schottky barrier height in metal / β-Ga2O3 junctions by insertion of PdCoO2 layers”, APL Materials, Vol. 8, pp. 041109, 2020. T. Miyakawa and two others, “Inhomogeneous interface dipole effect at the Schottky junctions of PdCrO2 on β-Ga2O3 (-201) substrates”, Journal of Applied Materials Physics, Vol. 128, pp. 025302, 2020. O. Ueda and 8 others, "Structural evaluation of defects in β-Ga2O3 single crystals grown by edge-defined film-fed growth process," Japanese Journal of Applied PhysicsVol. 55, pp. 1202BD, 2016 E. Ahmadi and 1 other author, "Materials issues and devices of α- and β-Ga2O3," Journal of Applied Physics, Vol. 126, pp. 160901, 2019; W. M. Haynes, "CRC handbook of chemistry and physics," CRC Press, 2016; H. B. Michaelson and 1 other author, "The work function of the elements and its periodicity," Journal of Applied Physics, Vol. 126, pp. 160901, 2019. Physics, Vol. 48, pp. 4729-4733, 1977, AIP Publishing Q. Z. Liu, et al., “A review of the metal-GaN contact technology”, Solid-State Electronics, Vol. 42, pp. 677-691, 1998, Elsevier M. Vivona and 2 others, “Materials and processes for Schottky contacts on silicon carbide”, Materials, Vol. 15, No. 298, 2021, MDPI

[0012] An object of one aspect of the present invention is to provide a novel semiconductor device using a metallic delafossite-type oxide and a method for manufacturing the same.

[0013] The present invention includes the following inventions: [1] A compound semiconductor and a PdCoO layer provided on the compound semiconductor and having a Schottky junction formed between the compound semiconductor and the PdCoO layer. ２ and an electrode.

[0014] [2] The PdCoO ２ The semiconductor device according to the above [1], wherein the electrode is provided on the (001) plane of the compound semiconductor.

[0015] [3] The PdCoO ２The semiconductor device according to the above [1] or [2], wherein the electrode is an anode electrode of the Schottky barrier diode.

[0016] [4] The PdCoO ２ The semiconductor device according to the above [1] or [2], wherein the electrode is a gate electrode of a field effect transistor, and the compound semiconductor is an electron supply layer of the field effect transistor.

[0017] [5] The semiconductor device according to any one of [1] to [4] above, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

[0018] [6] The compound semiconductor is gallium nitride, and the PdCoO ２ [CoO ２ ] － The semiconductor device according to [5] above, wherein the semiconductor device is terminated with

[0019] [7] The semiconductor device according to any one of [1] to [3] above, wherein the compound semiconductor is gallium oxide.

[0020] [8] The semiconductor device according to [7] above, wherein the crystal structure of the gallium oxide is a β gallium structure.

[0021] [9] The PdCoO ２ The semiconductor device according to the above [7] or [8], wherein the c-axis is tilted from the normal direction of the (001) plane.

[0022]

[10] The normal direction of the surface of the compound semiconductor is shifted from the (001) direction, and the PdCoO ２ The semiconductor device according to any one of the above [1] to [9], wherein an electrode is provided.

[0023]

[11] PdCoO on a compound semiconductor, with a Schottky junction formed between the compound semiconductor and the PdCoO ２ forming an electrode on the semiconductor device;

[0024]

[12] The method for manufacturing a semiconductor device according to

[11] above, further comprising: subjecting the electrode to a heat treatment in an oxygen-containing atmosphere.

[0025]

[13] The method for manufacturing a semiconductor device according to

[12] above, wherein forming the electrode is performed in an oxygen-containing atmosphere, and the oxygen partial pressure in the oxygen-containing atmosphere when performing the heat treatment is higher than the oxygen partial pressure in the oxygen-containing atmosphere when forming the electrode.

[0026]

[14] The method for manufacturing a semiconductor device according to any one of

[11] to

[13] above, further comprising forming a cathode electrode of a Schottky barrier diode so as to be electrically connected to the compound semiconductor, the electrode being an anode electrode of the Schottky barrier diode.

[0027]

[15] The method for manufacturing a semiconductor device according to any one of

[11] to

[13] above, wherein the electrode is a gate electrode of a field effect transistor, and the compound semiconductor is an electron supply layer of the field effect transistor.

[0028]

[16] The method for manufacturing a semiconductor device according to any one of

[11] to

[15] above, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

[0029]

[17] The method for manufacturing a semiconductor device according to any one of

[11] to

[14] above, wherein the compound semiconductor is gallium oxide.

[0030]

[18] The normal direction of the surface of the compound semiconductor is shifted from the (001) direction, and the PdCoO ２ The method for manufacturing a semiconductor device according to

[11] above, wherein the electrode is formed.

[0031]

[19] A semiconductor device comprising: a compound semiconductor; and an electrode of a metallic delafossite oxide provided on the compound semiconductor and having a Schottky junction formed between the compound semiconductor and the electrode.

[0032] According to the present invention, it is possible to provide a novel semiconductor device using a metallic delafossite-type oxide and a method for manufacturing the same.

[0033] Fig. 1 is a schematic diagram showing the structure of metallic delafossite-type oxide. Fig. 2 is a diagram showing the electrical conductivity of various materials. Fig. 3 is a schematic diagram showing the polarization state of metallic delafossite-type oxide. Fig. 4 is a diagram showing the polarization state of PdCoO ２ 5 is a schematic diagram showing the relationship between the termination surface of a layer and the work function. FIG. 5 is an energy band diagram near the interface between a metal and a semiconductor. FIG. 6 is a schematic diagram showing the relationship between the termination surface of a layer and the work function. ２ O ３ and the (-201) plane of PdCoO ２ 7(a) is a schematic diagram showing the lattice mismatch between the (001) plane of wurtzite gallium nitride (GaN) and the oxide layer of PdCoO. ２ 7(b) is a schematic diagram showing the lattice mismatch between the (001) plane of 4H silicon carbide (4H—SiC) and the PdCoO ２ 8A and 8B are cross-sectional views (part 1) of the semiconductor device according to the first embodiment during the manufacturing process. FIG. 9 is a cross-sectional view (part 2) of the semiconductor device according to the first embodiment during the manufacturing process. FIG. 10 is a schematic diagram showing the lattice mismatch between the (001) plane of n-type GaN constituting the compound semiconductor layer according to the first embodiment and the PdCoO (001) plane constituting the anode electrode. ２ FIG. 11 is a diagram showing the results of XRD analysis of the anode electrode according to the first embodiment and the substrate and compound semiconductor layer thereunder. FIG. 12 is a diagram obtained by investigating the J (current density)-V (voltage) characteristics of the semiconductor device according to the first embodiment. FIG. 13 is a diagram obtained by investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device according to the first embodiment. FIG. 14 is a diagram showing the barrier height φ based on the results of FIGS. 12 and 13. ｂ ＪＶ , φ ｂ ＣＶ and PdCoO reported in Non-Patent Document 4. ２ CoO of ２15(a) and 15(b) are cross-sectional views of the semiconductor device according to the second embodiment during the manufacturing process. 16(a) and 16(b) are diagrams showing the (001) plane of 4H—SiC constituting the compound semiconductor substrate according to the second embodiment and the work function of PdCoO constituting the anode electrode. ２ FIG. 17 is a diagram showing the results of XRD analysis of the anode electrode 14 according to the second embodiment and the underlying compound semiconductor substrate 21. FIG. 18 is a diagram obtained by investigating the CV characteristics of the semiconductor device according to the second embodiment. FIG. 19 is a diagram showing the barrier height φ based on the results of FIG. 18. ｂ ＣＶ and PdCoO reported in Non-Patent Document 4. ２ CoO of ２ 20(a) and (b) are cross-sectional views (part 1) of a semiconductor device according to the third embodiment during manufacture. FIG. 21 is a cross-sectional view (part 2) of a semiconductor device according to the third embodiment during manufacture. FIG. 22 is a diagram showing the results of an XRD analysis of an evaluation sample. FIG. 23 is a diagram obtained by investigating the CV characteristics between the gate electrode and the electron transit layer of an evaluation sample. FIGS. 24(a) and (b) are cross-sectional views of a semiconductor device according to the fourth embodiment during manufacture. FIG. 25 is a cross-sectional view of a β-Ga ２ O ３ and the (001) plane of PdCoO ２ 26(a), (b), and (c) are cross-sectional views (part 1) of the semiconductor device according to the fifth embodiment during the manufacturing process. FIG. 27 is a cross-sectional view (part 2) of the semiconductor device according to the fifth embodiment during the manufacturing process. FIG. 28(a) is a cross-sectional view of the β-Ga ２ O ３ layer and PdCoO ２ 28(b) is a cross-sectional view schematically showing the state of FIG. 28(a). FIG. 29 is a diagram obtained by investigating the J (current density)-V (voltage) characteristics of the semiconductor device according to the fifth embodiment. FIG. 30 is a diagram obtained by investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device according to the fifth embodiment. FIG. 31 is a diagram obtained by investigating the barrier height φ based on the results of FIG. 30. ｂ ＣＶand PdCoO reported in Non-Patent Document 4. ２ 32 is a diagram showing the results of investigation of the breakdown voltage of the semiconductor device according to the fifth embodiment. FIG. 33 is a diagram showing the structure of a device according to another embodiment. FIG. 34 is a diagram showing the structure of PdCoO ２ FIG. 10 is a diagram showing the results of XRD analysis of the layer.

[0034] Prior to describing the present embodiment, the matters considered by the inventors of the present invention will be described.

[0035] (Issues Considered by the Inventors of the Present Application) Fig. 1 is a schematic diagram showing the structure of a metallic delafossite-type oxide. The metallic delafossite-type oxide is represented by the general formula AMO ２ (A = Pd or Pt, M = Co, Cr, or Rh), and are named "metallic" because they have a Fermi surface. ２ , PtCoO ２ , PdCrO ２ , and PdRhO ２ Indicates one of the following.

[0036] As shown in FIG. 1, the metallic delafossite-type oxide is ２ The metallic delafossite-type oxide is a quasi-two-dimensional layered compound formed by stacking two types of atomic layers: an oxide layer 1 consisting of element A and a metal layer 2 in which element A is arranged in a triangular lattice pattern in the (001) plane. Due to the atomic arrangement in the metal layer 2, the normal direction of the Fermi surface of the metallic delafossite-type oxide is perpendicular to the c-axis direction at most k-points in reciprocal lattice space. This restricts the movement of electrons to the plane spanned by the a-axis and b-axis directions, suppressing surface scattering of electrons, and allowing the metallic delafossite-type oxide to maintain high electrical conductivity even in an ultrathin film.

[0037] FIG. 2 is a diagram showing the electrical conductivity of various materials. As shown in FIG. ２ and PdCoO ２ exhibits electrical conductivity comparable to that of Au, and is about five times higher than the corresponding elemental metals Pt and Pd.

[0038] Furthermore, metallic delafossite-type oxides are stable substances and do not deteriorate in corrosive solutions such as acids and alkalis or in the atmosphere. ２ The layer is heat-resistant up to 800°C in air. Metallic delafossite-type oxides are layered crystals, but because they also have ionic bonds in the c-axis direction, they have mechanical strength and peel strength equivalent to other ceramic materials.

[0039] 3 is a schematic diagram showing the polarization state of a metallic delafossite-type oxide. ２ ] － and A in metal layer 2 ＋ Since the c-plane has an ionic charge, polarization occurs on the c-plane. Due to this surface polarization, metallic delafossite-type oxides exhibit an unprecedentedly large work function depending on the termination surface.

[0040] FIG. 4 shows PdCoO ２ 4 is a schematic diagram showing the relationship between the termination surface of the layer and the work function. ２ ] － PdCoO terminated with an oxide layer 1 ２ The work function φ ｍ ＣｏＯ２ is 7.8 eV, and Pd ＋ PdCoO terminated with metal layer 2 ２ The work function φ ｍ Ｐｄ (Non-Patent Document 4) Due to such a large work function, it is expected that a Schottky barrier with a large barrier height will be formed at the interface between the semiconductor and the metallic delafossite-type oxide.

[0041] Figure 5 shows an energy band diagram near the interface between a metal and a semiconductor. The equation in the figure corresponds to the Schottky model. As shown in Figure 5, when a metal and a semiconductor are in contact with each other, the barrier height at the interface is φ ｂ A Schottky barrier of metal work function φ ｍ is the vacuum level E ｖａｃ and Fermi energy E Ｆ It is defined as the difference between the electron affinity of the semiconductor and the ｓ is the vacuum level E ｖａｃand the energy difference between the minimum conduction band of the semiconductor. In this case, according to the Schottky model, φ ｂ =φ ｍ -χ ｓ In addition, the conduction band edge and Fermi energy E Ｆ The difference between ｃ Then, the built-in potential V ｂｉ and the product of the elementary charge q, q V ｂｉ and energy E ｃ The sum of these is the barrier height φ ｂ This becomes:

[0042] According to the Schottky model, the work function of a metal, φ ｍ The barrier height φ is proportional to ｂ Therefore, as described above, by stacking a metallic delafossite-type oxide layer having a large work function on a semiconductor layer, it is possible to realize an extremely large barrier height, and it is thought that this will enable the realization of novel semiconductor devices such as Schottky diodes that have extremely high breakdown voltage and high-temperature operation performance that have not been possible until now.

[0043] Furthermore, β-Ga ２ O ３ If a metallic delafossite-type oxide layer is formed on a semiconductor with a large band gap, the barrier height φ ｂ Not only can the resistance be increased, but also the breakdown voltage of the semiconductor device can be increased.

[0044] The laminated structure of the semiconductor layer and the metallic delafossite-type oxide layer is a heterostructure in which different material layers are laminated in the lower and upper layers. In order to obtain a good heterostructure in which lattice defects in the upper layer are suppressed, it is technically common knowledge to minimize the lattice mismatch between the surface of the lower layer and the upper layer. For example, in Non-Patent Document 2, ２ O ３ PdCoO on the (-201) plane ２ It forms layers.

[0045] FIG. 6 shows the β-Ga ２ O ３ and the (-201) plane of PdCoO ２1 is a schematic diagram showing the value of lattice mismatch with the oxide layer 1 of β-Ga. The value of lattice mismatch is defined as the percentage of the ratio of the lattice constants of the layers at the interface. ２ O ３ The (-201) plane of PdCoO ２ The lattice points are arranged in a hexagonal shape like the PdCoO ２ Therefore, the lattice mismatch value is small, about 3.2%, and the PdCoO oxide layer has a clean structure with few defects. ２ A layer can be formed.

[0046] On the other hand, PdCoO ２ If the plane on which the metallic delafossite oxide such as a layer is formed is limited to the (−201) plane, the range of application of the metallic delafossite oxide will be narrowed, and it will be difficult to provide a novel semiconductor device that is advantageous in achieving high breakdown voltage due to a high Schottky barrier height.

[0047] The present inventors have focused on the (001) plane as a plane other than the (-201) plane on which to form a metallic delafossite-type oxide layer. Since the (001) plane is widely used in the mass production processes of various semiconductor devices, if a metallic delafossite-type oxide layer can be formed on the (001) plane, it will be easy to apply the metallic delafossite-type oxide layer to the mass production process, and novel semiconductor devices can be provided to the market.

[0048] For example, Non-Patent Document 3 describes the formation of PdCrO on the (001) surface of 4H silicon carbide (4H—SiC). ２ The "4H" prefixed to SiC is a symbol that identifies one of the multiple crystal polymorphs of SiC, where "H" indicates a hexagonal crystal and "4" indicates the number of SiC unit cells contained in one period in the c-axis direction. According to Non-Patent Document 3, the (001) plane of 4HSiC and PdCrO ２ The lattice mismatch with the PdCrO layer is about 4.8%. This level of lattice mismatch is suitable for PdCrO, which has good crystallinity and few lattice defects. ２ This is considered to be the limit of the layer that can be formed, and in Non-Patent Document 3, PdCrO ２ In addition to the layer, the formation of an impurity phase has been observed.２ The electrical conductivity of the layer is not shown, and the 4H silicon carbide and PdCrO ２ The electrical properties of the layer interfaces have not been evaluated, and the Schottky barrier at the interfaces has not been determined.

[0049] However, as shown in FIG. ２ The electrical conductivity of PtCoO, another metallic delafossite-type oxide, is ２ and PdCoO ２ Therefore, there is still room for further reduction in the resistance of semiconductor devices such as Schottky barrier diodes.

[0050] Therefore, the inventors of the present invention have investigated the PdCrO ２ PdCoO has electrical conductivity three times higher than that of ２ (See Figure 2) and the (001) plane of the semiconductor layer and PdCoO ２ The degree of lattice mismatch between the two was calculated, and the results are shown in Figures 7(a) and 7(b).

[0051] FIG. 7(a) shows the (001) plane of wurtzite gallium nitride (GaN) and PdCoO ２ 7A is a schematic diagram showing the lattice mismatch between the (001) plane of GaN and the oxide layer 1 of PdCoO. ２ The lattice mismatch with this is as high as 11%.

[0052] FIG. 7(b) shows the (001) plane of 4H silicon carbide (4H—SiC) and PdCoO ２ 7(b) is a schematic diagram showing the lattice mismatch between the (001) plane of 4H—SiC and the oxide layer 1 of PdCoO ２ The lattice mismatch with this is as high as 7.8%.

[0053] When the lattice mismatch is large as shown in Figures 7(a) and 7(b), PdCoO ２ It is considered difficult to grow the layer without destroying its crystallinity. Therefore, in light of common technical knowledge, the (001) plane and PdCoO ２ Therefore, the inventors of the present application have decided to use PdCoO on the (001) plane. ２The layer cannot be formed, or even if it can be formed, it is PdCoO ２ Lattice defects occur in the PdCoO ２ However, contrary to such prediction, the PdCoO layer functions as a good Schottky electrode as in the following embodiments. ２ It has been found that an unexpected effect can be obtained in that a layer can be formed.

[0054] First Embodiment A semiconductor device according to a first embodiment will be described in detail below, following the manufacturing steps. In this embodiment, a semiconductor device is formed by using gallium nitride and PdCoO ２ A Schottky barrier diode is manufactured in which a Schottky barrier is formed at the interface between the semiconductor and the gate electrode.

[0055] 8A, 8B, and 9 are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

[0056] First, as shown in FIG. 8(a), sapphire (Al ２ O ３ ) A substrate 10 is prepared in which a GaN (wurtzite gallium nitride) layer 12 is formed on a substrate 11 to a thickness of 100 nm to 2000 nm, for example, 300 nm to 1700 nm, or 500 nm to 1500 nm, 1000 nm in this example. A GaN layer 12 thickness of 100 nm or greater can enhance the crystallinity of the GaN layer 12 and the compound semiconductor layer 13 grown thereon. The surface of the GaN layer 12 is the (001) plane. Instead of the sapphire substrate 11, a crystalline substrate made of another crystal, such as silicon carbide, may be used. Furthermore, instead of a stack of the sapphire substrate 11 and the GaN layer 12, a bulk GaN layer 12 not bonded to a substrate, such as the sapphire substrate 11, may be used. As an example, the thickness of the bulk GaN layer 12 is 0.1 mm to 1.2 mm, for example, 0.2 mm to 1.0 mm, or 0.3 mm to 0.8 mm, and is 0.40 mm here.

[0057] Next, an n-type wurtzite GaN layer is formed as compound semiconductor layer 13 by MOVPE (Metal Organic Vapor Phase Epitaxy) on the (001) plane of GaN layer 12 to a thickness of 0.2 μm to 200 μm, for example, 1.0 μm to 150 μm, 1.5 μm to 100 μm, or 2.0 μm to 50 μm, 2.4 μm in this example. If the thickness of compound semiconductor layer 13 or the GaN layer as compound semiconductor layer 13 is 0.2 μm or more, the withstand voltage can be sufficiently increased, and if it is 200 μm or less, the on-resistance can be sufficiently reduced.

[0058] When forming the compound semiconductor layer 13, impurities are not usually doped. However, n-type impurities such as silicon (Si) and germanium (Ge) are doped at a concentration of 1×10 １５ cm －３ 5x10 or more １７ cm －３ The following concentrations, e.g., 3×10 １５ cm －３ 1x10 or more １７ cm －３ The following concentrations, or 5 x 10 １５ cm －３ 5x10 or more １６ cm －３ The compound semiconductor layer 13 may be doped with n-type impurities at the following concentration. By doping the compound semiconductor layer 13 with n-type impurities at this concentration, the on-resistance can be reduced. For example, silicon may be doped at a concentration of 1×10 １６ cm －３ The compound semiconductor layer 13 is doped with Zn at a concentration of 0.1 to 1.0.

[0059] The surface of the compound semiconductor layer 13 is the (001) plane of n-type wurtzite GaN. The plane orientation of the surface (in this case, GaN) of the compound semiconductor layer 13 can be measured using an X-ray diffraction device (for example, an Empyrean 3 manufactured by Malvern Panalytical). Note that instead of MOVPE, the compound semiconductor layer 13 may be formed using MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), solid phase growth, or mist CVD.

[0060] Next, the process for obtaining the cross-sectional structure shown in Fig. 8B will be described. First, a PdCoO anode electrode 14 is deposited on the (001) surface of the compound semiconductor layer 13 by pulsed laser deposition in a chamber (not shown). ２ The layer is formed to a thickness of 1 nm to 200 nm, for example, 10 nm to 100 nm, or 20 nm to 50 nm, and here, 25 nm. ２ If the layer thickness is 1 nm or more, the Schottky barrier height at the interface can be increased, and if it is 200 nm or less, the on-resistance can be sufficiently reduced.

[0061] In pulsed laser deposition, the energy density is 0.5 J / cm ２ More than 4J / cm ２ Below, for example, 0.8 J / cm ２ 3J / cm or more ２ or less, or 1.2 J / cm ２ 2J / cm or more ２ Hereafter, 1.5 J / cm ２ The target is irradiated with a fourth harmonic (266 nm) of Nd:YAG laser light. ２ Pellets made by sintering the powder are used.

[0062] The film formation atmosphere is an atmosphere in which either oxygen gas or ozone gas is plasmatized, or an atmosphere in which both oxygen gas and ozone gas are plasmatized. If oxygen is contained in the film formation atmosphere, oxygen vacancies may be generated and PdCoO ２ In this example, the partial pressure of oxygen gas in the film formation atmosphere is set to 0.1 Pa to 300 Pa, for example, 5 Pa to 200 Pa, or 10 Pa to 100 Pa, and is set to 20 Pa here.

[0063] Furthermore, the substrate temperature during film formation is 400° C. or higher and 850° C. or lower, preferably 500° C. or higher and 750° C. or lower, and more preferably 650° C. or higher and 750° C. or lower, and in this example is 660° C. If the substrate temperature during film formation is 850° C. or lower, reductive decomposition of the grown thin film can be prevented.

[0064] Note that pulsed laser deposition is a type of physical vapor deposition (PVD), and the anode electrode 14 may be formed by a PVD method other than pulsed laser deposition. Examples of such PVD methods include evaporation, ion plating, ion beam deposition, sputtering, and molecular beam epitaxy. Alternatively, chemical vapor deposition methods such as hydride vapor phase epitaxy (HVPE), solid phase epitaxy, MOVPE, MOCVD, and mist CVD may be used instead of PVD.

[0065] In this way, PdCoO ２ When the layer is formed, the PdCoO ２ The layer is [CoO ２ ] － 4, the work function at the interface is larger than when the interface is terminated by the metal layer 2, and the Schottky barrier height can be increased.

[0066] Furthermore, the anode electrode 14 thus grown is treated with PdCoO ２ For example, a heat treatment may be performed to improve the crystallinity of PdCoO. ２ To prevent oxygen from being released from the anode electrode 14 and decomposing the anode electrode 14, the heat treatment is preferably performed in an oxygen-containing atmosphere, which is the same atmosphere as that used for forming the anode electrode 14. Furthermore, by performing the heat treatment in an oxygen-containing atmosphere with a higher oxygen partial pressure than the atmosphere used for forming the anode electrode 14, it is possible to prevent oxygen taken into the anode electrode 14 during film formation from being released. For example, the anode electrode 14 may be heat-treated in an oxygen-containing atmosphere with an oxygen gas partial pressure of 0.1 Pa or higher but lower than atmospheric pressure, e.g., atmospheric pressure, at a substrate temperature of 400°C or higher but lower than 900°C, e.g., 600°C or higher but lower than 850°C, or 700°C or higher but lower than 850°C (here, 800°C). The heat treatment can be performed in a furnace that flows air or oxygen at atmospheric pressure.

[0067] Thereafter, a resist pattern (not shown) is formed on the anode electrode 14, and the anode electrode 14 is patterned by etching using the resist pattern as a mask by reactive ion etching (RIE). The etching gas used in the RIE is, for example, Ar gas and BCl 2 . ３ The anode electrode 14 may be patterned by a lift-off method instead of etching.

[0068] 9 , an aluminum wire 15a is directly bonded to the compound semiconductor layer 13, and an indium layer 15b is pressure-bonded thereon to form a cathode electrode 15 electrically connected to the compound semiconductor layer 13 by an ohmic junction. The method for forming the cathode electrode 15 is not limited to this, and a metal layer such as a titanium layer or an aluminum layer may be deposited on the compound semiconductor layer 13 as the cathode electrode 15.

[0069] The above completes the basic structure of the semiconductor device 20 according to this embodiment. The semiconductor device 20 includes a compound semiconductor layer 13 and a PdCoO SiO 2 layer formed on the compound semiconductor layer 13 and having a Schottky junction with the compound semiconductor layer 13. ２ and an anode electrode 14, specifically a Schottky barrier diode in which a Schottky barrier is formed at the interface between the compound semiconductor layer 13 and the anode electrode 14. To apply a forward bias to the semiconductor device 20, the potential of the anode electrode 14 should be made higher than the potential of the cathode electrode 15. To apply a reverse bias to the semiconductor device 20, the potential of the anode electrode 14 should be made lower than the potential of the cathode electrode 15.

[0070] Next, the results of various investigations conducted by the inventors of the present invention will be described.

[0071] FIG. 10 shows the (001) plane of n-type GaN constituting the compound semiconductor layer 13 and the PdCoO ２1 is a high angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image of the interface between the

[0072] As shown in FIG. 7(a), the (001) plane of GaN and PdCoO ２ The lattice mismatch with PdCoO is as much as 11%. ２ The layer did not grow, or even if it did, the crystallinity was significantly impaired due to numerous lattice defects. ２ However, contrary to expectations, as shown in Figure 10, the PdCoO ２ The layers are well oriented in the c-axis direction and have good crystallinity. ２ It was found that a layer was obtained.

[0073] 11 is a diagram showing the results of analyzing the anode electrode 14 and the underlying substrate 10 and compound semiconductor layer 13 by XRD (X-ray diffraction). The XRD device used was an Empyrean 3 manufactured by Malvern Panalytical. The horizontal axis of FIG. 11 represents the diffraction angle (2θ) of X-rays, and the vertical axis represents the intensity of X-rays at an arbitrary intensity. In addition, in FIG. 11, the PdCoO ２ Diffraction peaks in the (00l) plane (l=1, 2, . . . ) are indicated by downward arrows.

[0074] As shown in FIG. ２ The diffraction peaks at the (001) plane (l = 1, 2, ...) of PdCoO are clearly visible. This result indicates that PdCoO is grown on the (001) plane of GaN, which has a lattice mismatch of 11%. ２ Even when a layer is formed, the PdCoO ２ It was found that a layer was obtained.

[0075] FIG. 12 is a graph obtained by investigating the J (current density)-V (voltage) characteristics of the semiconductor device 20. The J-V characteristics were measured using an Agilent Technologies 4155B semiconductor parameter analyzer. The horizontal axis of FIG. 12 represents the voltage between the anode electrode 14 and the cathode electrode 15, with a positive value representing a case where the potential of the anode electrode 14 is higher than that of the cathode electrode 15. The vertical axis of FIG. 12 represents the absolute value of the current density of the current flowing between the anode electrode 14 and the cathode electrode 15.

[0076] In this investigation, the anode electrode 14 was circular with a diameter D of 100 μm when viewed from above, and measurements were carried out at room temperature (298 K). ｂ ＪＶ The ideality factor n of the Schottky barrier was 1.03. The ideality factor n is defined by the following formula (1). In formula (1), A ＊＊ is the effective Richardson constant, T is the absolute temperature, q is the elementary charge, and k is the Boltzmann constant. In this investigation, the rising part of the J-V characteristic (J=10 －７ A / cm ２ ~10 －５ A / cm ２ The value of n was determined by comparing the slope of a linear fit of the region (region A) with the above equation. The closer the value of n is to 1, the more the J-V characteristics of the Schottky barrier can be expressed by ideal thermionic emission.

[0077] 13 is a graph obtained by investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device 20. A Keysight E4980A LCR meter was used to measure the C-V characteristics. The horizontal axis in FIG. 13 has the same meaning as the horizontal axis in FIG. 12, so its explanation will be omitted. The vertical axis in FIG. 13 represents the square of the ratio (S / C) between the area S of the anode electrode 14 in a top view and the depletion layer capacitance C in the Schottky barrier. ２ Shows.

[0078] As in the measurement of the J-V characteristics, the anode electrode 14 was also circular with a diameter D of 100 μm when viewed from above, and measurements were carried out at room temperature (298 K). ２ The built-in potential V is calculated by measuring the electric field strength and the electric field strength. ｂｉ can be calculated from the following formula (2).

[0079]

[0080] where k is the Boltzmann constant and T is the absolute temperature. From equation (2), the built-in potential V at room temperature (298 K) is ｂｉ As a result of calculating ｂｉ = 1.93 eV.

[0081] In addition, when the absolute value of the gradient of the fitting line in FIG. 13 is a, the doping density N Ｄ can be calculated from the following equation (3).

[0082]

[0083] where ε is the dielectric constant of the compound semiconductor layer 13. From equation (3), the doping density N Ｄ As a result of calculating Ｄ = 1.1 x 10 １６ cm －３ This is what happened.

[0084] As explained with reference to FIG. 5, the barrier height φ ｂ ＣＶ q.V ｂｉ and energy E ｃ It is equal to the sum of the energy E ｃ is the density of states in the conduction band, N ｃ , doping density N Ｄ , Boltzmann's constant k, and absolute temperature T, it can be calculated from the following equation (4).

[0085]

[0086] The doping density N in equation (4) ＤThe value calculated from the above formula (3) is used as the density of states N ｃ is calculated from the following equation (5).

[0087]

[0088] The derivation of equation (5) is described in, for example, the following paper 1.

[0089] (Paper 1) W. Goetz and 2 others, “Nitrogen donors in 4H silicon carbide”, Journal of Applied Physics, Vol. 73, No. 3332, 1993.

[0090] m in formula (5) ＊ is the effective mass of an electron, and in GaN it is m ＊ = 0.22 m ０ (Paper 2). However, m ０ is the effective mass of an electron in vacuum.

[0091] (Paper 2) P. Perlina and 10 others, "Determination of the effective mass of GaN from infrared reflectivity and Hall effect," Applied Physics Letters, Vol. 68, p. 1114, 1996

[0092] Furthermore, M in formula (5) ｃ is the number of bottoms of the conduction band included in the first Brillouin zone, and in GaN, M ｃ =1.

[0093] Using these, E ｃ = 0.14 eV, and q V ｂｉ Barrier height φ at room temperature ｂ ＣＶ was 2.07 eV.

[0094] FIG. 14 shows the barrier height φ based on the results of FIGS. 12 and 13. ｂ ＪＶ , φ ｂ ＣＶ and PdCoO reported in Non-Patent Document 4.２ CoO of ２ 14 is a diagram plotting the barrier height and work function of the termination surface. For comparison, Fig. 14 also plots the barrier height and work function of representative metals such as titanium (Ti), chromium (Cr), nickel (Ni), palladium (Pd), silver (Ag), platinum (Pt), gold (Au), and lead (Pb). The barrier heights are quoted from Non-Patent Document 18, and the work functions are quoted from Non-Patent Documents 16 and 17. Furthermore, for reference, the value of half the band gap Eg of GaN (0.5E ｇ ) is also listed.

[0095] In addition, while the CV characteristics give the average barrier height based on the area of ​​the junction interface, the JV characteristics give information on the region where the barrier is low and current flows easily. Therefore, the barrier height φ obtained from the JV characteristics is generally ｂ ＪＶ is the average barrier height φ of the surface obtained from the CV characteristics ｂ ＣＶ is lower than

[0096] Barrier height φ obtained from CV characteristics ｂ ＣＶ The barrier height φ obtained from the J-V characteristics ｂ ＪＶ The value subtracted is the standard deviation of the barrier height σ ｓ and equation (6) (Paper 3).

[0097]

[0098] (Paper 3) Juergen H. Werner, et al., “Barrier inhomogeneities at Schottky contacts”, Journal of Applied Physics Physics Letters, Volume 69, Page 1522, 1991

[0099] Equation (6) is φ ｂ ＣＶ and φ ｂ ＪＶThe larger the difference between φ and φ, the greater the variation in barrier height within the junction surface. This variation depends on the alignment of the crystal orientation at the interface, the amount of defects, and the doping amount of the semiconductor layer. φ is more reflective of the barrier height at an ideal interface. ｂ ＣＶ Therefore, φ ｂ ＪＶ than φ ｂ ＣＶ is more reliable.

[0100] The barrier height of the metal shown in FIG. 14 is at most about 1.3 eV, whereas the barrier height φ ｂ ＣＶ This result shows that the PdCoO ２ It has been revealed that when the anode electrode 14 is formed, a Schottky barrier having a very high barrier height of more than 2.0 eV is formed at the interface therebetween.

[0101] As a result, the semiconductor device 20 according to this embodiment is capable of operating at high temperatures and has a very high breakdown voltage, which would be impossible if the typical metals shown in FIG. 14 were used for the anode electrode 14, and a novel power device that is less likely to break down even when a reverse bias is applied can be realized.

[0102] Furthermore, as described with reference to FIG. ２ Since the metal has electrical conductivity comparable to that of Au, it is possible to realize not only a high breakdown voltage but also a large current and high speed of the semiconductor device 20. This also applies to the second, third, and fourth embodiments described later.

[0103] Moreover, since the (001) plane of GaN is widely used in the mass production of various semiconductor devices, it is not possible to form PdCoO ２ By forming the layers, the semiconductor device 20 can be mass-produced by utilizing existing mass-production processes.

[0104] In this embodiment, the plane orientation of the compound semiconductor layer 13 is set to the (001) direction, but the normal direction of the compound semiconductor layer 13 may be slightly shifted from the (001) direction as long as it does not significantly disturb the crystallinity of the anode electrode 14. As an example, the normal direction of the compound semiconductor layer 13 may be shifted from the (001) direction by 10° or less.

[0105] Second Embodiment Next, a semiconductor device according to a second embodiment will be described in detail, following the manufacturing steps. In this embodiment, silicon carbide and PdCoO ２ A Schottky barrier diode is manufactured in which a Schottky barrier is formed at the interface between the semiconductor and the gate electrode.

[0106] 15A and 15B are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

[0107] First, as shown in FIG. 15(a), nitrogen is added as an n-type impurity at a concentration of 1×10 １７ cm －３ 1x10 or more ２０ cm －３ The following concentrations, e.g., 5×10 １７ cm －３ 5x10 or more １９ cm －３ or 1 x 10 １８ cm －３ 1x10 or more １９ cm －３ The following concentration, here 8 x 10 １８ cm －３ A 4H—SiC substrate doped with nitrogen at this concentration is prepared as the compound semiconductor substrate 21. By doping the compound semiconductor substrate 21 with nitrogen at this concentration, the on-resistance can be reduced. The surface of the compound semiconductor substrate 21 is the (001) plane of the 4H—SiC.

[0108] Then, a PdCoO film was deposited as the anode electrode 14 on the (001) surface of the compound semiconductor substrate 21 using the same physical vapor deposition and patterning conditions as those in FIG. 8B of the first embodiment. ２ The layer is formed to a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm.

[0109] As in the first embodiment, even when the underlayer is a (001) surface of 4H—SiC as in this embodiment, PdCoO ２ By forming a PdCoO layer at the interface with the (001) surface of 4H—SiC, ２ The majority of the layer is [CoO ２ ] － As a result, the work function at the interface becomes larger than when the interface is terminated by the metal layer 2 as shown in FIG. 4, and the Schottky barrier height can be increased.

[0110] As described in the first embodiment, the anode electrode 14 may be heat-treated in an oxygen-containing atmosphere to prevent oxygen from being released from the anode electrode 14 .

[0111] 15(b), a nickel layer is formed on each of the compound semiconductor substrate 21 and the anode electrode 14 by vapor deposition or sputtering, and the nickel layer is patterned to form the cathode electrode 22 electrically connected to the compound semiconductor substrate 21. Thereafter, the cathode electrode 22 is heat-treated to convert it into a silicide, and the junction at the interface between the compound semiconductor substrate 21 and the cathode electrode 22 becomes an ohmic junction. For example, when the heat treatment is performed for 5 minutes under conditions of an oxygen partial pressure of 0.3 Pa and a substrate temperature of 750° C., the PdCoO ２ The cathode electrode 22 can be nickel silicided while maintaining the crystallinity of the layer. The thickness of the cathode electrode 22 is not particularly limited, and in this example, the cathode electrode 22 is formed to a thickness of 10 nm to 200 nm, for example, 20 nm to 100 nm, or 30 nm to 80 nm, and here, a thickness of 50 nm. If the thickness of the cathode electrode 22 is 10 nm or more, the influence of surface oxidation of the nickel layer before silicidation can be reduced, and if it is 200 nm or less, peeling of the nickel layer can be prevented.

[0112] The above completes the basic structure of the semiconductor device 30 according to this embodiment. The semiconductor device 30 includes a compound semiconductor substrate 21 and a PdCoO SiO 2 film formed on the compound semiconductor substrate 21 and having a Schottky junction with the compound semiconductor substrate 21.２ Specifically, the semiconductor device 30 is a Schottky barrier diode in which a Schottky barrier is formed at the interface between the compound semiconductor substrate 21 and the anode electrode 14. To apply a forward bias to the semiconductor device 30, the potential of the anode electrode 14 should be made higher than the potential of the cathode electrode 22. To apply a reverse bias, the potential of the anode electrode 14 should be made lower than the potential of the cathode electrode 22.

[0113] Next, the results of various investigations conducted by the inventors of the present invention will be described.

[0114] 16(a) and 16(b) show the (001) plane of 4H—SiC constituting the compound semiconductor substrate 21 and the PdCoO ２ 16(a) and 16(b) are HAADF-STEM images of the interface between the two materials. Note that the imaged interface regions are different between FIG. 16(a) and FIG. 16(b).

[0115] As shown in FIG. 7(b), the (001) plane of 4H—SiC and PdCoO ２ The lattice mismatch with PdCoO is 7.8%. ２ The layer did not grow, or even if it did, the crystallinity was significantly impaired due to numerous lattice defects. ２ However, contrary to expectations, as shown in Figures 16(a) and 16(b), the PdCoO ２ The layers are well oriented in several directions, making the PdCoO layer an excellent Schottky electrode. ２ It was found that a layer was obtained.

[0116] Furthermore, as shown in Fig. 16(a) and Fig. 16(b), PdCoO ２ It was also revealed that the orientation direction (c-axis direction) of the layers was different. This is because multiple domains with different c-axis directions are PdCoO ２ This means that PdCoO exists on the (001) surface of 4H—SiC. ２ The reason for this polycrystalline structure is that PdCoO is easily oriented on the 4H—SiC (001) surface. ２ The surface is PdCoO ２This is thought to be because there are multiple planes other than the (001) plane.

[0117] 17 is a diagram showing the results of XRD analysis of the anode electrode 14 and the underlying compound semiconductor substrate 21. The meanings of the vertical and horizontal axes in FIG. 17 are the same as those in FIG. 11, and therefore the explanation thereof will be omitted. In addition, in FIG. 17, as in FIG. 11, the PdCoO ２ Diffraction peaks in the (00l) plane (l=1, 2, . . . ) are indicated by downward arrows.

[0118] As shown in FIG. ２ The diffraction peaks of the (001) plane (l = 1, 2, ...) of PdCoO are clearly visible. This result indicates that PdCoO is deposited on the (001) plane of 4H-SiC, which has a lattice mismatch of 7.8%. ２ Even when a layer is formed, most of it is (001) oriented, with few lattice defects and excellent crystallinity. ２ It was found that a layer was obtained.

[0119] Fig. 18 is a diagram obtained by investigating the CV characteristics of the semiconductor device 30. The vertical and horizontal axes in Fig. 18 have the same meanings as those in Fig. 13, and therefore a description thereof will be omitted.

[0120] In this investigation, the anode electrode 14 was formed into a circle having a diameter D of 200 μm when viewed from above, and measurements were carried out at room temperature (298 K). ２ was measured, and a fitting line fitting the measured values ​​was obtained. From the fitting line, q V at room temperature (298 K) was calculated based on the above-mentioned formula (2). ｂｉ The donor concentration N of the compound semiconductor substrate 21 calculated from the above formula (3) was 2.77 eV. Ｄ is 7.7 x 10 １８ cm －３ This is what happened.

[0121] In 4H—SiC, m in formula (5) ＊ is 0.19m ０ (Paper 1), M ｃ is 12. The density of states N ｃ and the donor concentration NＤ (7.7 x 10 １８ cm －３ ) into equation (4), for 4H—SiC, E ｃ = 0.03 eV. As a result, q V ｂｉ NI E ｃ Barrier height φ at room temperature (298 K) ｂ ＣＶ is 2.80 eV, and the barrier height φ ｂ ＣＶ (=2.05 eV).

[0122] FIG. 19 shows the barrier height φ based on the results of FIG. ｂ ＣＶ and PdCoO reported in Non-Patent Document 4. ２ CoO of ２ 19 is a diagram plotting the barrier height and work function of the termination surface. For comparison, in Fig. 19, the barrier height and work function of representative metals are plotted in region A. Metals included in region A include Ni, Pt, Au, Ir, Ta, Ti, W, and Mo. The barrier heights are cited from Non-Patent Document 19, and the work functions are cited from Non-Patent Documents 16 and 17.

[0123] The barrier height of each metal shown in FIG. 19 is at most about 1.8 eV, whereas the barrier height φ ｂ ＣＶ As a result, when PdCoO is formed on the (001) plane of the 4H—SiC compound semiconductor substrate 21 as in this embodiment, ２ It was revealed that when the anode electrode 14 was formed, a Schottky barrier having a very high barrier height of 2.82 eV was formed at the interface therebetween.

[0124] As a result, the semiconductor device 30 according to this embodiment has a very high breakdown voltage and operating temperature range that would be impossible to achieve if the metals shown in FIG. 19 were used for the anode electrode 14, and a novel power device that is less likely to break down even when a reverse bias is applied can be realized.

[0125] Moreover, since the (001) plane of 4H—SiC is widely used in the mass production of various semiconductor devices, it is preferable to deposit PdCoO on the (001) plane of 4H—SiC as in this embodiment. ２ By forming the layers, the semiconductor device 30 can be mass-produced by utilizing existing mass-production processes.

[0126] In this embodiment, a 4H—SiC substrate is used as the compound semiconductor substrate 21. However, a substrate of other hexagonal crystal polytype of silicon carbide may be used as the compound semiconductor substrate 21, and PdCoO ２ The anode electrode 14 may be formed in such a crystal polytype. Examples of such crystal polytypes include 2H, 6H, 8H, and 10H. The (001) plane of these crystal polytypes has hexagonally arranged lattice points similar to 4H—SiC, and therefore, PdCoO 2 is well oriented in the c-axis direction similar to 4H—SiC. ２ It is expected that a layer can be formed.

[0127] In this embodiment, the plane orientation of the compound semiconductor substrate 21 is set to the (001) direction, but the normal direction of the compound semiconductor substrate 21 may be slightly shifted from the (001) direction as long as it does not significantly disturb the crystallinity of the anode electrode 14. As an example, the normal direction of the compound semiconductor substrate 21 may be shifted from the (001) direction by 10° or less.

[0128] Third Embodiment Next, a semiconductor device according to a third embodiment will be described in detail, following its manufacturing process. In this embodiment, a GaN-HEMT (High Electron Mobility Transistor) is manufactured as the semiconductor device, using GaN-based compound semiconductor layers for the electron supply layer and electron transit layer, as follows.

[0129] 20A, 20B, and 21 are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

[0130] 20( a), an undoped GaN layer is formed by MOVPE as an electron transit layer 42 to a thickness of 0.2 μm to 4 μm, for example, 1.0 μm to 3.5 μm, or 1.5 μm to 3.2 μm, 3 μm in this example, on a SiC substrate 41. If the thickness of the electron transit layer 42 is 0.2 μm or more, the crystallinity of the electron transit layer 42 can be improved, and if it is 4 μm or less, flatness can be ensured.

[0131] Then, an AlGaN layer having a thickness of 10 nm to 50 nm, for example, 15 nm to 45 nm, or 20 nm to 40 nm, 30 nm in this example, is formed by MOVPE on the electron transit layer 42 as the main layer 43a of the electron supply layer 43. If the thickness of the main layer 43a or the AlGaN layer is 10 nm or more, it is possible to reduce the gate leakage current. ２ The effect of the work function of the electrode can be enhanced.

[0132] When the main layer 43a is formed, impurities are not usually doped. However, n-type impurities such as silicon (Si) and germanium (Ge) are doped at a concentration of 1×10 １６ cm －３ 7 x 10 or more １８ cm －３ For example, 5 x 10 １６ cm －３ 6 x 10 or more １８ cm －３ or 1 x 10 １７ cm －３ 6 x 10 or more １８ cm －３ The doping concentration of silicon may be 5×10. By doping the main body layer 43a with n-type impurities at this concentration, the two-dimensional electron gas concentration can be increased. For example, silicon may be doped at a concentration of 5×10. １８ cm －３ The main body layer 43a is doped with Zn at a concentration of 0.1%.

[0133] Then, silicon (Si) or germanium (Ge) is implanted as n-type impurities on the main body layer 43a at a concentration of 1×10 １６ cm －３ 7 x 10 or more １８ cm －３ For example, 5 x 10１６ cm －３ 6 x 10 or more １８ cm －３ or 1 x 10 １７ cm －３ 6 x 10 or more １８ cm －３ Here, 5 x 10 １８ cm －３ An n-type wurtzite GaN layer doped with an n-type impurity at this concentration is formed by MOVPE, and this n-type GaN layer serves as the compound semiconductor layer 43b of the electron supply layer 43. By forming a wurtzite GaN layer doped with an n-type impurity at this concentration on the main body layer 43a, it is possible to improve the HEMT characteristics. Note that an undoped wurtzite GaN layer may also be formed as the compound semiconductor layer 43b.

[0134] Furthermore, wurtzite aluminum gallium nitride (Al ｘ Ga １－ｘ The compound semiconductor layer 43b may be formed of a (N: 0<x<1) layer. Alternatively, the compound semiconductor layer 43b may be formed of a wurtzite aluminum nitride layer. The thickness of the compound semiconductor layer 43b is not particularly limited and may be 5 nm to 20 nm, for example, 6 nm to 15 nm or 8 nm to 12 nm, and is 10 nm in this example. The surface of the compound semiconductor layer 43b is a (001) plane.

[0135] Next, as shown in FIG. 20(b), the compound semiconductor layer 43b is patterned to expose the surface of the main body layer 43a, and then a titanium layer and an aluminum layer are formed in this order on the main body layer 43a, and these films serve as the source electrode 45a and the drain electrode 45b.

[0136] The electrodes 45a, 45b have a Schottky junction with the main layer 43a and the compound semiconductor layer 43b as they are, which makes it difficult to effectively inject carriers from the electrodes 45a, 45b into these layers 43a, 43b.

[0137] Therefore, it is preferable to perform a heat treatment after forming the source electrode 45a and the drain electrode 45b to cause slight interdiffusion between each electrode 45a, 45b and each layer 43a, 43b, thereby converting the above-mentioned Schottky junction into an ohmic junction.

[0138] Subsequently, as shown in FIG. 21, PdCoO ２ The layer is formed to a thickness of 1 nm to 200 nm, for example, 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm, and further the PdCoO ２ The layer is patterned to form a gate electrode 51. ２ The layer growth conditions and patterning conditions are the same as those for the anode electrode 14 of the first embodiment (see FIG. 8B), and therefore a description thereof will be omitted. In the above, the gate electrode 51 is formed after the electrodes 45 a and 45 b are formed, but conversely, the gate electrode 51 may be formed first and then the electrodes 45 a and 45 b may be formed.

[0139] The (001) plane of the n-type GaN constituting the compound semiconductor layer 43b and the PdCoO ２ A Schottky barrier is formed between the layer and the gate electrode. As described in the first embodiment, the barrier height φ of the Schottky barrier is ｂ ＣＶ is an extremely high value exceeding 2.0 eV that cannot be achieved by any of titanium (Ti), chromium (Cr), nickel (Ni), palladium (Pd), silver (Ag), platinum (Pt), gold (Au), and lead (Pb).

[0140] The above completes the basic structure of the semiconductor device 60 according to this embodiment. The semiconductor device 60 includes a compound semiconductor layer 43b and a PdCoO ２The device is equipped with a gate electrode 51 of the layer. Specifically, it is a GaN-HEMT, and two-dimensional electron gas is induced in the electron transit layer 42 between the electrodes 45 a and 45 b. The width of the depletion layer of the Schottky junction is controlled by the gate voltage applied to the gate electrode 51, thereby controlling the flow of the two-dimensional electron gas.

[0141] According to this embodiment, a Schottky barrier with a very high barrier height is formed between the compound semiconductor layer 43b of the electron supply layer 43 and the gate electrode 51 as described above, so that a novel semiconductor device 60 with a small off-current can be provided.

[0142] Moreover, since the (001) plane of GaN is widely used in the mass production of various semiconductor devices, it is not possible to form PdCoO ２ By forming the layers, the semiconductor device 20 can be mass-produced by utilizing existing mass-production processes.

[0143] The inventors of the present application evaluated the crystallinity of the gate electrode 51 according to this embodiment as follows. ２ O ３ A GaN main layer 43a is formed on the substrate, and a wurtzite aluminum gallium nitride (Al GaN) compound semiconductor layer 43b is formed thereon. ０．０３ Ga ０．９７ N) layer was formed. ０．０３ Ga ０．９７ PdCoO on the (001) surface of the N layer ２ A gate electrode 51 was formed to prepare a sample for evaluation.

[0144] 22 shows the results of analyzing the sample by XRD. The horizontal axis of FIG. 22 indicates the diffraction angle (2θ) of X-rays, and the vertical axis indicates the intensity of X-rays (counts / second). In FIG. 22, similarly to FIG. 11, the PdCoO ２ Diffraction peaks in the (00l) plane (l=1, 2, . . . ) are indicated by downward arrows.

[0145] As shown in FIG. ２ The diffraction peaks of the (00l) plane (l = 3, 6, 9, ...) of Al are clearly visible.０．０３ Ga ０．９７ PdCoO with few lattice defects and excellent crystallinity on the (001) plane of N ２ It has become clear that the gate electrode 51 can be formed.

[0146] 23 is a graph obtained by investigating the CV characteristics between the gate electrode 51 and the electron transit layer 43 in the above sample. The vertical axis of FIG. 23 is the square of the reciprocal of the depletion layer capacitance C per unit area of ​​the gate electrode 51 in top view (1 / C ２ 23 indicates the voltage between the gate electrode 51 and the electron transit layer 43. As in the first embodiment, an E4980A LCR meter manufactured by Keysight was used to measure the CV characteristics.

[0147] In this investigation, the gate electrode 51 was made circular with a diameter D of 200 μm when viewed from above, and measurements were carried out at room temperature (298 K). ２ was measured, and a fitting line fitting the measured values ​​was obtained. From the fitting line, q V at room temperature (298 K) was calculated based on the above-mentioned formula (2). ｂｉ The value of Al calculated from the above formula (3) was 1.72 eV. ０．０３ Ga ０．９７ Donor concentration of N Ｄ is 1.1 x 10 １６ cm －３ This is what happened.

[0148] As described in the aforementioned paper 2, in GaN, m ＊ = 0.22 m ０ In addition, as described in the following paper 4, Al ０．２ Ga ０．８ In N, m ＊ = 0.42 m ０ is.

[0149] (Paper 4)D. Wines, F. Ersan, C. Ataca, “Engineering the Electronic, Thermoelectric, and Excitonic Properties of Two-Dimensional Group-III Nitrides through Alloying for Optoelectronic Devices (B １－ｘ Al ｘ N, Al １－ｘ Ga ｘ N, and Ga １－ｘ In ｘ N)”, ACS Applied Materials & Interfaces, Vol. 12, No. 41, pp. 46416-46428, 2020, ACS Publications

[0150] Therefore, by linear approximation, Al ０．０３ Ga ０．９７ In N, m in formula (5) ＊ is 0.25m ０ It is estimated that. ｃ is 1. The density of states N ｃ and the donor concentration N Ｄ (1.1 x 10 １６ cm －３ ) into formula (4), Al ０．０３ Ga ０．９７ In N, E at room temperature (298K) ｃ = 0.15 eV. As a result, q V ｂｉ NI E ｃ Barrier height φ at room temperature (298 K) ｂ ＣＶ This resulted in the formation of aluminum gallium nitride (Al ０．０３ Ga ０．９７ N) on the compound semiconductor layer 43b. ２ It has become clear that by forming the gate electrode 51 of this type, it is possible to realize a barrier height higher than that of any of the metals shown in FIG.

[0151] Fourth Embodiment Next, a semiconductor device according to a fourth embodiment will be described in detail, following the steps of manufacturing the semiconductor device. ２ A vertical Schottky barrier diode is manufactured in which a Schottky barrier is formed at the interface with the semiconductor.

[0152] 24A and 24B are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

[0153] First, as shown in Fig. 24(a), a SiC (001) or GaN (001) substrate, for example, is prepared as an n-type highly conductive compound semiconductor substrate 46. To reduce the on-resistance of the diode, it is desirable that the compound semiconductor substrate 46 have low resistivity. For this reason, the compound semiconductor substrate 46 is doped with n-type impurities at a concentration of 1 x 10 １８ cm －３ 1x10 or more ２１ cm －３ For example, 3 x 10 １８ cm －３ 5x10 or more ２０ cm －３ Below, 5 x 10 １８ cm －３ 5x10 or more １９ cm －３ Here, 1 x 10 １９ cm －３ The compound semiconductor substrate 46 has a first main surface 46a and a second main surface 46b facing each other, and the first main surface 46a is a (001) surface.

[0154] Next, a compound semiconductor layer 47 is epitaxially grown by chemical vapor deposition (CVD) on the first main surface 46a of the compound semiconductor substrate 46 to a thickness of 0.2 μm to 200 μm, for example, 1 μm to 100 μm, 2 μm to 50 μm, or 3 μm to 25 μm, 5 μm in this example. If the thickness of the compound semiconductor layer 47 is 0.2 μm or more, the withstand voltage can be sufficiently increased, and if it is 200 μm or less, the on-resistance can be sufficiently reduced.

[0155] For example, if the compound semiconductor substrate 46 is a SiC (001) substrate, a 4H—SiC layer is formed as the compound semiconductor layer 47, and if the compound semiconductor substrate 46 is a GaN (001) substrate, a wurtzite gallium nitride layer is formed as the compound semiconductor layer 47. In either case, the surface of the compound semiconductor layer 47 is the (001) plane.

[0156] Furthermore, when the compound semiconductor layer 47 is grown, impurities are not usually doped. However, n-type impurities are doped at 1×10 １５ cm －３ 5x10 or more １７ cm －３ Doping may be performed at the following concentrations: Note that instead of the CVD method, sputtering, MBE, HVPE, solid phase growth, or mist CVD may also be used.

[0157] Next, a PdCoO film was deposited as the anode electrode 14 on the (001) surface of the compound semiconductor layer 47 using the same physical vapor deposition and patterning conditions as those in FIG. 8B of the first embodiment. ２ The layer is formed to a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm.

[0158] Next, the cathode electrode 15 is deposited on the second main surface 46b of the compound semiconductor substrate 46. If the compound semiconductor substrate 46 is a GaN substrate, a metal layer such as a titanium layer or an aluminum layer is deposited to form the cathode electrode 15. If the compound semiconductor substrate 46 is a SiC substrate, the cathode electrode 15 is formed by depositing a nickel layer and then silicidating it by heat treatment under the same conditions as those in FIG. 15B of the second embodiment.

[0159] The above completes the basic structure of the semiconductor device 70 according to this embodiment. The semiconductor device 70 includes a compound semiconductor layer 47 and a PdCoO ２Specifically, the semiconductor device 70 is a vertical Schottky barrier diode in which a Schottky barrier is formed at the interface between the compound semiconductor layer 47 and the anode electrode 14. To apply a forward bias to the semiconductor device 70, the potential of the anode electrode 14 is made higher than the potential of the cathode electrode 15. To apply a reverse bias, the potential of the anode electrode 14 is made lower than the potential of the cathode electrode 15.

[0160] In this embodiment, the plane orientation of the first main surface 46 a of the compound semiconductor substrate 46 is the (001) direction, but the normal direction of the first main surface 46 a may be slightly shifted from the (001) direction as long as it does not significantly disturb the crystallinity of the anode electrode 14. As an example, the normal direction of the first main surface 46 a may be shifted from the (001) direction by 10° or less.

[0161] In addition, to prevent electric field concentration at the periphery of the anode electrode 14, an edge termination or passivation layer may be deposited.

[0162] Although each embodiment has been described in detail above, each embodiment is not limited to the above. ２ The layer may also function as any one of wiring, transparent electrode layer, catalyst, and terahertz wave oscillation source.

[0163] Fifth Embodiment Prior to describing this embodiment, the matters examined by the inventors of the present application will be described.

[0164] (Matters Considered by the Inventors of the Present Application) In addition to the matters (matters considered by the inventors of the present application) in the first embodiment, the following matters were also considered. ２ O ３ The (-201) plane of PdCoO ２ The lattice points are arranged in a hexagonal shape like the PdCoO ２ Since the lattice constant is about the same as that of the oxide layer 1, the lattice mismatch value is small at about 3.2%, and the PdCoO ２ A layer can be formed.

[0165] However, β-Ga ２ O３ The (-201) plane of β-Ga is a crystal plane that is prone to dislocations and stacking faults, and the defects make it difficult to sufficiently increase the breakdown voltage and electron mobility of semiconductor devices such as Schottky diodes. ２ O ３ If a metallic delafossite-type oxide layer is formed on the (-201) plane of β-Ga, which has a large band gap and high breakdown voltage, ２ O ３ The features of

[0166] Therefore, the inventors of the present invention have investigated the β-Ga as a surface on which a metallic delafossite-type oxide layer is to be formed other than the (-201) surface. ２ O ３ We focused on the (001) plane of the silicon dioxide.

[0167] FIG. 25 shows the β-Ga ２ O ３ and the (001) plane of PdCoO ２ 1A and 1B are schematic diagrams of the oxide layer 1 (see FIG. 1 ).

[0168] β-Ga ２ O ３ The (001) plane of PdCoO is less susceptible to dislocation defects and stacking faults than the (-201) plane, and therefore is less susceptible to defects-induced deterioration in breakdown voltage and mobility. On the other hand, as shown in FIG. 25, the atomic arrangement of gallium atoms on the (001) plane is rectangular, and ２ The symmetry of the PdCoO oxide layer 1 is different from that of the hexagonal atomic arrangement of the PdCoO oxide layer 1. ２ If only the a-axis or b-axis direction is expanded and contracted, ２ O ３ (001) plane of PdCoO ２ The atomic arrangements of the PdCoO alloys are not identical, and in light of common technical knowledge, they have excellent crystallinity and excellent Schottky characteristics. ２ However, contrary to such a prediction, PdCoO, which functions as a good Schottky electrode, as in the present embodiment described below, can be formed. ２ It has been found that an unexpected effect can be obtained in that a layer can be formed.

[0169] The semiconductor device according to this embodiment will be described in detail with reference to the manufacturing method thereof. ２ O ３ (001) plane of PdCoO ２ A Schottky barrier diode is manufactured in which a Schottky barrier is formed at the interface between the semiconductor and the gate electrode.

[0170] 26A, 26B, 26C, and 27 are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

[0171] First, as shown in FIG. 26(a), β-Ga doped with a high concentration of n-type impurities is ２ O ３ On the substrate 81, β-Ga with low carrier density is ２ O ３ A substrate 80 is prepared on which a layer 82 is epitaxially grown to a thickness of 100 nm to 100 μm, for example, 1 μm to 80 μm, 3 μm to 50 μm, or 5 μm to 25 μm, and here, 11 μm. ２ O ３ If the thickness of the layer 82 is 100 nm or more, the withstand voltage can be sufficiently increased, and if it is 100 μm or less, the on-resistance can be sufficiently reduced.

[0172] The concentration of n-type impurities in the substrate 80 is not particularly limited. ２ O ３ The substrate 81 contains 1×10 Si or Sn as an n-type impurity. １７ cm －３ 1x10 or more ２０ cm －３ The following concentrations, e.g., 1×10 １７ cm －３ 2 x 10 or more １９ cm －３ or 1 x 10 １８ cm －３ 1x10 or more １９ cm －３ It is doped with the following concentration: ２ O ３ The carrier density of layer 82 is 1×10 １５ cm －３ 1x10 or more １７ cm－３ The following concentrations, e.g., 5×10 １５ cm －３ 8 x 10 or more １６ cm －３ The following concentration, or 8 x 10 １５ cm －３ 5x10 or more １６ cm －３ The concentration is as follows. By doping the substrate 80 with n-type impurities in this way, the on-resistance of the diode can be reduced. ２ O ３ The carrier density of the layer 82 is β-Ga ２ O ３ By making the carrier density lower than that of the substrate 81, the anode electrode to be formed later and β-Ga ２ O ３ The width of the depletion layer near the interface with the layer 82 can be increased, and the breakdown voltage can be increased.

[0173] The substrate 80 has a first main surface 80a and a second main surface 80b facing each other. The first main surface 80a is made of β-Ga ２ O ３ The layer 82 is configured with the (001) plane.

[0174] Next, as shown in FIG. 26( b ), a PdCoO 3 film is deposited as an anode electrode 84 on the first main surface 80 a of the substrate 80 by pulsed laser deposition in a chamber (not shown). ２ The layer is formed to a thickness of 1 nm to 100 nm, for example, 5 nm to 80 nm, or 10 nm to 50 nm, here 20 nm. In the pulsed laser deposition method, the energy density is 0.5 J / cm ２ More than 4J / cm ２ Below, for example, 0.8 J / cm ２ 3J / cm or more ２ or less, or 1.2 J / cm ２ 2J / cm or more ２ Hereafter, 1.5 J / cm ２ The target is irradiated with a fourth harmonic (266 nm) of Nd:YAG laser light. ２A pellet made by sintering the powder of the above is used. The film formation atmosphere and the substrate temperature during film formation are the same as those in the first embodiment, and therefore a description thereof will be omitted. The anode electrode 84 may also be formed by a method other than pulsed laser deposition. As an example of such a method, the method described in the first embodiment will be mentioned, and therefore a description thereof will be omitted.

[0175] Furthermore, similarly to the first embodiment, PdCoO ２ A heat treatment may be performed to improve the crystallinity of the silicon nitride film. The atmosphere, partial pressure of oxygen gas, substrate temperature, and heat treatment apparatus used in the heat treatment are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0176] Next, as shown in FIG. 26( c), a metal laminate film 85 is formed on the anode electrode 84 by vapor deposition or sputtering, with a nickel layer 85a and a gold layer 85b in this order. The thickness of each layer is not particularly limited; the nickel layer 85a is 5 nm to 100 nm, for example, 10 nm to 80 nm, 15 nm to 60 nm, or 20 nm to 50 nm, and is set to 30 nm here. A thickness of 5 nm or greater can reduce the effects of surface oxidation, while a thickness of 100 nm or less can prevent the nickel layer 85a from peeling. The gold layer 85b is 5 nm to 300 nm, for example, 20 nm to 275 nm, 40 nm to 250 nm, or 60 nm to 200 nm, and is set to 150 nm here. A thickness of 5 nm or greater can reduce the surface resistance of the metal laminate film, while a thickness of 300 nm or less can ensure the flatness of the gold layer 85b.

[0177] Thereafter, a resist pattern (not shown) is formed on the laminated film 85, and the laminated film 85 and the anode electrode 84 are patterned by etching using RIE (Reactive Ion Etching) using the resist pattern as a mask. The etching gas used in the RIE is, for example, Ar and BCl. ３ There is a mixed gas of the above. Then, the resist pattern is removed.

[0178] Next, as shown in FIG. 27 , a titanium layer 86a and a gold layer 86b are formed in this order on the second main surface 80b of the substrate 80 by vapor deposition or sputtering, thereby obtaining a cathode electrode 86 electrically connected to the substrate 80. The thickness of the cathode electrode 86 is not particularly limited. Heat treatment may also be performed to reduce the interfacial resistance between the cathode electrode 86 and the substrate 81. In this example, the titanium layer 86a is formed to a thickness of 2 nm to 100 nm, e.g., 10 nm to 90 nm, 20 nm to 80 nm, or 30 nm to 70 nm, e.g., 50 nm here. A thickness of 2 nm or more reduces the effects of surface oxidation, while a thickness of 100 nm or less sufficiently reduces the on-resistance. The gold layer 86b is formed to a thickness of 5 nm to 300 nm, e.g., 10 nm to 275 nm, 20 nm to 250 nm, or 30 nm to 225 nm, e.g., 200 nm here. If the thickness of the gold layer 86b is 5 nm or more, the on-resistance can be sufficiently low, and if the thickness is 300 nm or less, the flatness of the gold layer 86b can be ensured.

[0179] The above completes the basic structure of the semiconductor device 90 according to this embodiment. ２ O ３ layer 82 and β-Ga ２ O ３ β-Ga ２ O ３ PdCoO with a Schottky junction formed between it and layer 82 ２ Specifically, the anode electrode 84 is β-Ga ２ O ３ The semiconductor device 90 is a Schottky barrier diode in which a Schottky junction is formed at the interface between the layer 82 and the anode electrode 84. To apply a forward bias to the semiconductor device 90, the potential of the anode electrode 84 should be made higher than the potential of the cathode electrode 86. To apply a reverse bias, the potential of the anode electrode 84 should be made lower than the potential of the cathode electrode 86.

[0180] Next, the results of various investigations conducted by the inventors of the present invention will be described.

[0181] FIG. 28(a) shows the β-Ga２ O ３ layer 82 and PdCoO ２ 1 is a high angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image of the interface between the

[0182] As shown in FIG. ２ O ３ and PdCoO ２ Since the symmetry of the atomic arrangement is different between PdCoO and PdCoO, it is considered that ２ The crystallinity of PdCoO is destroyed, resulting in PdCoO having excellent Schottky characteristics. ２ However, contrary to this expectation, as shown in FIG. ２ The layer has a c-axis direction of β-Ga ２ O ３ The layers grew at an angle to the normal direction, and the crystallinity was not significantly affected.

[0183] Fig. 28(b) is a cross-sectional view showing the state of Fig. 28(a). As shown in Fig. 28(b), PdCoO ２ The c-axis of the layer is β-Ga ２ O ３ By tilting the layer from the normal direction n of the (001) plane, atomic layers are stacked in the c-axis direction, resulting in PdCoO with good crystallinity. ２ An unexpected phenomenon was found in which a layer was formed. In this example, the angle θ between the c-axis direction and the normal direction n was 22.4°. With the angle θ at this value, the β-Ga ２ O ３ PdCoO at the interface with the layer ２ The symmetry of the atomic arrangement of the layer is β-Ga ２ O ３ The symmetry of the atomic arrangement of the PdCoO layer matches the symmetry of the atomic arrangement of the (001) plane of the PdCoO layer. ２ It is believed that a layer was formed.

[0184] While the crystallinity is good, PdCoO ２ The entire bottom atomic layer of the layer is β-Ga ２O ３ The edge of each atomic layer is not in contact with the β-Ga ２ O ３ The inventors of the present invention have conducted research to confirm whether good Schottky characteristics can be obtained with this structure.

[0185] FIG. 29 is a graph obtained by investigating the J (current density)-V (voltage) characteristics of the semiconductor device 90. The J-V characteristics were measured using an Agilent Technologies 4155B semiconductor parameter analyzer. The horizontal axis of FIG. 29 represents the voltage between the anode electrode 84 and the cathode electrode 86, with a positive value representing a case where the potential of the anode electrode 84 is higher than that of the cathode electrode 86. The vertical axis of FIG. 29 represents the absolute value of the current density of the current flowing between the anode electrode 84 and the cathode electrode 86.

[0186] In this investigation, the anode electrode 84 was circular with a diameter D of 200 μm when viewed from above, and measurements were carried out at room temperature (298 K). ｂ ＪＶ The interface resistance of the Schottky barrier in the on state was 25 mΩ cm ２ This is what happened.

[0187] Furthermore, the ideality factor n of the Schottky barrier was 1.10. The ideality factor n is defined by the above-mentioned formula (1).

[0188] 30 is a diagram obtained by investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device 90. The C-V characteristics were measured using an E4980A LCR meter manufactured by Keysight. The meaning of the horizontal axis in FIG. 30 is the same as that of the horizontal axis in FIG. 29, so its explanation will be omitted. The vertical axis in FIG. 30 is the square of the reciprocal of the depletion layer capacitance C in the Schottky barrier, 1 / C ２ Shows.

[0189] As in the measurement of the J-V characteristics, the anode electrode 84 was circular with a diameter D of 200 μm when viewed from above, and the measurement was carried out at room temperature (298 K). ２The intercept of the fitted line with the horizontal axis is defined as b, and the built-in potential V at room temperature (298 K) is ｂｉ is calculated from the above formula (2), and in this example, q·V ｂｉ = 1.88 eV.

[0190] In addition, the absolute value of the slope of the fitting line in FIG. 30 is a, and ２ O ３ Doping density N of layer 82 Ｄ is calculated from the above formula (3), and in this example, N Ｄ = 5.7 x 10 １５ cm －３ However, in the above formula (3), ε is β-Ga ２ O ３ is the dielectric constant of layer 82.

[0191] As explained with reference to FIG. 5, the barrier height φ ｂ ＣＶ q.V ｂｉ and energy E ｃ It is equal to the sum of the energy E ｃ can be calculated from the above-mentioned formula (4).

[0192] The doping density N in the above formula (4) Ｄ The value calculated from the above-mentioned formula (3) is used as the density of states N ｃ is calculated from the above-mentioned formula (5).

[0193] Furthermore, M in the above formula (5) ｃ is the number of bottoms of the conduction band included in the first Brillouin zone, and β-Ga ２ O ３ Well then, M ｃ =1.

[0194] Using these, β-Ga ２ O ３ At room temperature (298K), ｃ = 0.17 eV, and q V ｂｉ Barrier height φ at room temperature ｂ ＣＶ was 2.05 eV.

[0195] FIG. 31 shows the barrier height φ based on the results of FIG. ｂ ＣＶ and PdCoO reported in Non-Patent Document 4. ２ 31 is a diagram showing the barrier height and work function of the typical metals nickel (Ni) and platinum (Pt). For comparison, the barrier height and work function of the typical metals nickel (Ni) and platinum (Pt) are also plotted. The barrier height is taken from Non-Patent Document 2, and the work function is taken from Non-Patent Documents 16 and 17.

[0196] As explained in the first embodiment, the barrier height φ obtained from the JV characteristics is generally ｂ ＪＶ is the average barrier height φ of the surface obtained from the CV characteristics ｂ ＣＶ is lower than

[0197] As explained in the first embodiment, the barrier height φ obtained from the CV characteristics ｂ ＣＶ The barrier height φ obtained from the J-V characteristics ｂ ＪＶ The value subtracted is the standard deviation of the barrier height σ ｓ and the aforementioned equation (6) (Paper 3).

[0198] As explained in the first embodiment, the above-mentioned equation (6) is ｂ ＣＶ and φ ｂ ＪＶ The larger the difference between φ and φ, the greater the variation in barrier height within the junction surface. This variation depends on the alignment of the crystal orientation at the interface, the amount of defects, and the doping amount of the semiconductor layer. φ is more reflective of the barrier height at an ideal interface. ｂ ＣＶ Therefore, φ ｂ ＪＶ than φ ｂ ＣＶ is more reliable.

[0199] The barrier height of each metal shown in FIG. 31 is at most about 1.45 eV, whereas the barrier height φ ｂ ＣＶThis result shows that even if the c-axis direction is tilted from the normal direction n as shown in Figures 28(a) and 28(b), the Schottky barrier exceeds the barrier height of a typical metal. ２ O ３ The (001) plane of the layer and PdCoO ２ It was revealed that it can be formed at the interface with the layer.

[0200] As a result, the semiconductor device 90 according to this embodiment is capable of operating at high temperatures and has a very high breakdown voltage, which would be impossible if the typical metals shown in FIG. 31 were used for the anode electrode 84, and a novel power device that is less likely to break down even when a reverse bias is applied can be realized.

[0201] Furthermore, in this embodiment, it is difficult to increase the breakdown voltage and mobility of β-Ga due to dislocation defects and stacking faults. ２ O ３ The (-201) plane of β-Ga ２ O ３ The anode electrode 84 is formed on the (001) surface of the layer 82. Therefore, the β-Ga ２ O ３ This makes it possible to fully utilize the advantages of the above and further increase the breakdown voltage of the semiconductor device 90. To confirm this, the inventors of the present application investigated the breakdown voltage of the semiconductor device 90. The results are shown in FIG.

[0202] 32 is a diagram showing the results of investigation of the breakdown voltage of the semiconductor device 90. The horizontal axis of Fig. 32 represents the reverse bias voltage value, and the vertical axis represents the absolute value of the current density of the current flowing between the anode electrode 84 and the cathode electrode 86.

[0203] As shown in FIG. 32, in this embodiment, breakdown did not occur even when a reverse bias of −500 eV was applied, and breakdown finally occurred at a reverse bias of about −530 eV. ２ O ３ It has been confirmed that forming the anode electrode 84 on the (001) surface of the layer 82 is effective in increasing the breakdown voltage of the semiconductor device 90 .

[0204] (Other Embodiments) In the first embodiment, gallium nitride and PdCoO ２ In this embodiment, a Schottky barrier diode is formed in which a Schottky barrier is formed at the interface with the layer. ０．０７ Ga ０．９３ N), and PdCoO was deposited on the (001) surface. ２ A layer was formed.

[0205] FIG. 33 is a diagram showing the structure of the device according to this embodiment, and FIG. 34 is a diagram showing the PdCoO ２ 33 shows the results of analyzing the PdCoO layer by XRD. ２ XRD analysis of the PdCoO layer was performed. ２ The diffraction peaks at the (00l) plane (l = 1, 2, ...) of In are clearly visible. ０．０７ Ga ０．９３ PdCoO on the (001) surface of N ２ Even when a layer is formed, the PdCoO ２ The composition ratio of indium gallium nitride is not particularly limited, and the composition formula is In ｘ Ga １－ｘ The value of x in N may be selected arbitrarily from the range of 0<x<1. Furthermore, indium nitride InN may be used instead of indium gallium nitride.

[0206] Although the present embodiment has been described in detail above, the present embodiment is not limited to the above. For example, in the present embodiment, the plane orientation of the first main surface 80a (see FIG. 26A) of the substrate 80 is β-Ga. ２ O ３ However, the normal direction of the first main surface 80a may be slightly deviated from the (001) direction within a range in which a good Schottky barrier can be obtained between the first main surface 80a and the anode electrode 84. As an example, the normal direction of the first main surface 80a may be deviated from the (001) direction within a range of 10° or less.

[0207] Furthermore, in order to prevent the electric field from concentrating on the periphery of the anode electrode 84 in the semiconductor device 90 (see FIG. 27), an edge termination or passivation layer may be deposited. ２ O ３ To prevent the electric field from concentrating in the layer 82, ２ O ３ A trench structure may be fabricated in layer 82 .

[0208] The anode electrode 84 is made of PdCoO ２ The layer may also function as any one of wiring, transparent electrode layer, catalyst, and terahertz wave oscillation source.

[0209] Furthermore, PdCoO as a metallic delafossite-type oxide ２ , PdCrO ２ , PdRhO ２ and PtCoO ２ Considering the commonality of the properties of bulk single crystals of PdCoO and the commonality of the properties of palladium and platinum, chromium and cobalt, and rhodium, ２ Other than PdCrO ２ , PdRhO ２ and PtCoO ２ In the metallic delafossite oxide of PdCoO, the PdCoO confirmed by the embodiment described above was ２ It is thought that a large Schottky barrier can be induced at the interface by the same mechanism as that of the PdCoO ２ layer, PdCoO ２ Schottky barrier diode with PdCoO layer - Patents.com ２ It is naturally considered that the matters relating to the manufacturing method of the layers are also common.

[0210] 1...oxide layer, 2...metal layer, 10...substrate, 11...alumina base material, 12...GaN layer, 13...compound semiconductor layer, 14...anode electrode, 15, 22...cathode electrode, 15a...aluminum layer, 15b...indium layer, 20, 30, 60, 70...semiconductor device, 21...compound semiconductor substrate, 41...SiC substrate, 42...electron transit layer, 43...electron supply layer, 43a...main body layer, 43b...compound semiconductor layer, 45a...source electrode, 45b...drain electrode, 46...compound semiconductor substrate, 46a...first main surface, 46b...second main surface, 47...compound semiconductor layer, 51...gate electrode, 80...substrate, 81...β-Ga ２ O ３ Substrate, 82...β-Ga ２ O ３ layer, 84...anode electrode, 85...metal laminated film, 85a...nickel layer, 85b...gold layer, 86...cathode electrode, 86a...titanium layer, 86b...gold layer, 90...semiconductor device.

Claims

1. A compound semiconductor; and PdCoO provided on the compound semiconductor and forming a Schottky junction between the compound semiconductor and the PdCoO. ２ and an electrode.

2. The PdCoO ２ 2. The semiconductor device according to claim 1, wherein the electrode is provided on a (001) plane of the compound semiconductor.

3. The PdCoO ２ 3. The semiconductor device according to claim 1, wherein the electrode is an anode electrode of the Schottky barrier diode.

4. The PdCoO ２ 3. The semiconductor device according to claim 1, wherein the electrode is a gate electrode of a field effect transistor, and the compound semiconductor is an electron supply layer of the field effect transistor.

5. The semiconductor device according to any one of claims 1 to 4, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

6. The compound semiconductor is gallium nitride, and the PdCoO ２ [CoO ２ ] － 6. The semiconductor device according to claim 5, wherein the terminal is terminated with 7. The semiconductor device according to any one of claims 1 to 3, wherein the compound semiconductor is gallium oxide.

8. The semiconductor device according to claim 7, wherein the crystal structure of said gallium oxide is a β gallium structure.

9. The PdCoO ２ 9. The semiconductor device according to claim 7, wherein the c-axis of said crystal is inclined from the normal direction of the (001) plane.

10. The normal direction of the surface of the compound semiconductor is shifted from the (001) direction, and the PdCoO ２ 2. The semiconductor device according to claim 1, further comprising an electrode.

11. PdCoO on a compound semiconductor, with a Schottky junction formed between the compound semiconductor and the PdCoO ２ forming an electrode of the semiconductor device.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising: subjecting the electrode to a heat treatment in an oxygen-containing atmosphere.

13. The method for manufacturing a semiconductor device according to claim 12, wherein forming the electrode is performed in an oxygen-containing atmosphere, and the oxygen partial pressure in the oxygen-containing atmosphere when performing the heat treatment is higher than the oxygen partial pressure in the oxygen-containing atmosphere when forming the electrode.

14. A method for manufacturing a semiconductor device according to any one of claims 11 to 13, further comprising forming a cathode electrode of a Schottky barrier diode so as to be electrically connected to the compound semiconductor, the electrode being an anode electrode of the Schottky barrier diode.

15. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the electrode is a gate electrode of a field effect transistor, and the compound semiconductor is an electron supply layer of the field effect transistor.

16. The method for manufacturing a semiconductor device according to any one of claims 11 to 15, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

17. The method for manufacturing a semiconductor device according to any one of claims 11 to 14, wherein the compound semiconductor is gallium oxide.

18. The normal direction of the surface of the compound semiconductor is shifted from the (001) direction, and the PdCoO ２ The method for manufacturing a semiconductor device according to claim 11, further comprising forming an electrode of the formula (I).

19. A semiconductor device comprising: a compound semiconductor; and an electrode of a metallic delafossite oxide provided on the compound semiconductor and having a Schottky junction formed between the compound semiconductor and the electrode.

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