Pixel circuit, driving method, display substrate, and display apparatus

Abstract

Provided are a pixel circuit, a driving method, a display substrate, and a display apparatus. The pixel circuit comprises: a first sub-pixel driving circuit used for driving a first sub-pixel; and a second sub-pixel driving circuit used for driving a second sub-pixel. The first sub-pixel comprises a first sub-light-emitting element, the second sub-pixel comprises a second sub-light-emitting element, and the first sub-pixel and the second sub-pixel are two adjacent sub-pixels in a first direction or a second direction. The pixel circuit further comprises a first data signal line. The first data signal line is configured to provide data signals for both the first sub-pixel driving circuit and the second sub-pixel driving circuit. The data signals include a first sub-data signal and a second sub-data signal. The first sub-data signal is generated by the first data signal line in a third time period. The second sub-data signal is generated by the first data signal line in a fourth time period. The third time period and the fourth time period do not overlap.

Description

Pixel circuit, driving method, display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display substrate, and a display device. Background Art

[0002] With the advancement of display technology, full-screen displays offer a more extreme visual experience, leading to a growing demand for ultra-narrow bezel and low-cost display products. High-pixel-density display products require more traces and vias, resulting in dense wiring and high device stability requirements. Common display products also have numerous data signal lines, requiring more IC channels and increasing IC costs.

[0003] How to optimize the pixel circuit of display products, reduce the number of wiring and lower costs is one of the important research topics for R&D personnel.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0005] Summary of the Invention

[0006] In one aspect, a pixel circuit is provided, comprising: a first sub-pixel driving circuit for driving a first sub-pixel; a second sub-pixel driving circuit for driving a second sub-pixel, wherein the first sub-pixel includes a first sub-light-emitting element, the second sub-pixel includes a second sub-light-emitting element, the first sub-pixel and the second sub-pixel are two sub-pixels adjacent in a first direction or a second direction, and the first direction and the second direction intersect; the pixel circuit also comprises a first data signal line, the first data signal line is configured to provide data signals to both the first sub-pixel driving circuit and the second sub-pixel driving circuit, wherein the data signals include a first sub-data signal and a second sub-data signal, the first sub-data signal is generated by the first data signal line in a third time period, and the second sub-data signal is generated by the first data signal line in a fourth time period, wherein the third time period does not overlap with the fourth time period.

[0007] According to some exemplary embodiments, the pixel circuit includes: a data writing sub-circuit, the data writing sub-circuit is coupled to a data signal terminal, a first scanning signal terminal and a second node, wherein the data signal terminal is coupled to the first data signal line, the data writing sub-circuit is configured to write the data signal received at the data signal terminal to the second node in response to the first scanning signal received at the first scanning signal terminal, wherein the first sub-pixel driving circuit and the second sub-pixel driving circuit are coupled to the second node, the data writing sub-circuit writes the first sub-data signal to the first sub-pixel driving circuit through the second node; and the data writing sub-circuit writes the second sub-data signal to the second sub-pixel driving circuit through the second node.

[0008] According to some exemplary embodiments, the first sub-pixel driving circuit includes: a first driving sub-circuit, the first driving sub-circuit is coupled to the first node first sub-node, the second node and the third node first sub-node, the first driving sub-circuit is configured to generate a first driving current in response to the voltage of the first node first sub-node, wherein the first driving current is used to drive the first sub-light-emitting element to emit light; and a first compensation sub-circuit, the first compensation sub-circuit is coupled to the second scan signal terminal, the first node first sub-node and the third node first sub-node, the first compensation sub-circuit is configured to transmit the first sub-data signal from the data signal terminal to the first node first sub-node in response to the second scan signal received at the second scan signal terminal.

[0009] According to some exemplary embodiments, the second sub-pixel driving circuit includes: a second driving sub-circuit, the second driving sub-circuit is coupled to the first node second sub-node, the second node and the third node second sub-node, the second driving sub-circuit is configured to generate a second driving current in response to the voltage of the first node second sub-node, wherein the second driving current is used to drive the second sub-light-emitting element to emit light; and a second compensation sub-circuit, the second compensation sub-circuit is coupled to the third scan signal terminal, the first node second sub-node and the third node second sub-node, the second compensation sub-circuit is configured to transmit the second sub-data signal from the data signal terminal to the first node second sub-node in response to the third scan signal received at the third scan signal terminal.

[0010] According to some exemplary embodiments, the data writing sub-circuit, the first driving sub-circuit, and the second driving sub-circuit are all coupled to the second node.

[0011] According to some exemplary embodiments, the first sub-pixel driving circuit further includes: a first light-emitting control sub-circuit, the first light-emitting control sub-circuit being coupled to the first voltage terminal, the light-emitting control terminal and the second node, the first light-emitting control sub-circuit being configured to write the first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal; a first storage sub-circuit, the first storage sub-circuit being coupled to the first node, the first sub-node and the first voltage terminal; the second sub-pixel driving circuit further includes: a third light-emitting control sub-circuit, the third light-emitting control sub-circuit being coupled to the second voltage terminal, the light-emitting control terminal and the second node, the third light-emitting control sub-circuit being configured to write the second voltage received at the second voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal, a second storage sub-circuit, the second storage sub-circuit being coupled to the first node, the second sub-node and the second voltage terminal.

[0012] According to some exemplary embodiments, the pixel circuit includes: a first light-emitting control subcircuit, the first light-emitting subcircuit is coupled to the first voltage terminal, the light-emitting control terminal and the second node, wherein the first light-emitting control subcircuit is configured to write the first voltage received at the first voltage terminal into the first sub-pixel driving circuit and the second sub-pixel driving circuit respectively through the second node in response to the light-emitting control signal received at the light-emitting control terminal; a first storage subcircuit, the first storage subcircuit is coupled to the first node, the first sub-node and the first voltage terminal, the first storage subcircuit is configured to store the stored voltage in the first sub-pixel driving circuit; and a second storage subcircuit, the second storage subcircuit is coupled to the second sub-node of the first node and the first voltage terminal, the second storage subcircuit is configured to store the stored voltage in the second sub-pixel driving circuit.

[0013] According to some exemplary embodiments, the first sub-pixel driving circuit further includes: a first initialization sub-circuit, the first initialization sub-circuit being coupled to the first reset signal terminal, the first initialization signal terminal, and the first node first sub-node, the first initialization sub-circuit being configured to transmit the first initialization signal received at the first initialization signal terminal to the first node first sub-node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the first node first sub-node; a second initialization sub-circuit, the second initialization sub-circuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the first sub-light-emitting element, the second initialization sub-circuit being configured to transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the first sub-light-emitting element in response to the second reset signal received at the second reset signal terminal, so as to initialize the potential of the first electrode of the first sub-light-emitting element; and a second light-emitting control sub-circuit, the second light-emitting control sub-circuit being coupled to the third node first sub-node, the light-emitting control terminal, and the first electrode of the first sub-light-emitting element, the second light-emitting control sub-circuit being configured to output the first driving current transmitted to the third node first sub-node to the first sub-light-emitting element in response to the light-emitting control signal received at the light-emitting control terminal.

[0014] According to some exemplary embodiments, the second sub-pixel driving circuit further includes: a third initialization sub-circuit, the third initialization sub-circuit being coupled to the first reset signal terminal, the first initialization signal terminal, and the first node second sub-node, the third initialization sub-circuit being configured to transmit the first initialization signal received at the first initialization signal terminal to the first node second sub-node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the first node second sub-node; a fourth initialization sub-circuit, the fourth initialization sub-circuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being coupled to the first reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being coupled to the first reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being coupled to the first reset signal terminal, the first ... The initialization subcircuit is configured to transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the second sub-light-emitting element in response to the second reset signal received at the second reset signal terminal to initialize the potential of the first electrode of the second sub-light-emitting element; and a fourth light-emitting control subcircuit, the fourth light-emitting control subcircuit is coupled to the second sub-node of the third node, the light-emitting control terminal and the first electrode of the second sub-light-emitting element, and the fourth light-emitting control subcircuit is configured to output the second driving current transmitted to the second sub-node of the third node to the second sub-light-emitting element in response to the light-emitting control signal received at the light-emitting control terminal.

[0015] According to some exemplary embodiments, the data writing sub-circuit includes a data writing transistor, the control electrode of the data writing transistor is coupled to the first scanning signal terminal, the first electrode of the data writing transistor is coupled to the second node, and the second electrode of the data writing transistor is coupled to the data signal terminal; the first light-emitting control sub-circuit includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first voltage terminal, and the second electrode of the first light-emitting control transistor is coupled to the second node; and the third light-emitting control sub-circuit includes a third light-emitting control transistor, the control electrode of the third light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the third light-emitting control transistor is coupled to the second voltage terminal, and the second electrode of the third light-emitting control transistor is coupled to the second node.

[0016] According to some exemplary embodiments, the data writing sub-circuit includes a data writing transistor, the control electrode of the data writing transistor is coupled to the first scanning signal terminal, the first electrode of the data writing transistor is coupled to the second node, and the second electrode of the data writing transistor is coupled to the data signal terminal; and the first light-emitting control sub-circuit includes a light-emitting control transistor, the control electrode of the light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the light-emitting control transistor is coupled to the first voltage terminal, and the second electrode of the light-emitting control transistor is coupled to the second node.

[0017] According to some exemplary embodiments, the pixel circuit includes: a first light-emitting control subcircuit, the first light-emitting control subcircuit is coupled to a first voltage terminal, a light-emitting control terminal and the second node, wherein the first light-emitting control subcircuit is configured to write the first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal, wherein the first sub-pixel driving circuit and the second sub-pixel driving circuit are coupled at the second node, and the first light-emitting control subcircuit writes the first voltage into the first sub-pixel driving circuit and the second sub-pixel driving circuit respectively through the second node; and a first initialization subcircuit, the first initialization subcircuit is coupled to a first reset signal terminal, a first initialization signal terminal and the second node, and the first initialization subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the second node in response to a first reset signal received at the first reset signal terminal to initialize the potential of the second node.

[0018] According to some exemplary embodiments, the first sub-pixel driving circuit further includes: a first data writing sub-circuit, the first data writing sub-circuit being coupled to the data signal terminal, the first scan signal terminal and the first sub-node of the third node, the first data writing sub-circuit being configured to write the data signal received at the data signal terminal into the first sub-node of the third node in response to the first scan signal received at the first scan signal terminal; and the second sub-pixel driving circuit further includes: a second data writing sub-circuit, the second data writing sub-circuit being coupled to the data signal terminal, the first scan signal terminal and the second sub-node of the third node, the second data writing sub-circuit being configured to write the data signal received at the data signal terminal into the second sub-node of the third node in response to the first scan signal received at the first scan signal terminal, wherein the data signal terminal coupled to the first data writing sub-circuit and the data signal terminal coupled to the second data writing sub-circuit are coupled to the same data signal line.

[0019] According to some exemplary embodiments, the first sub-pixel driving circuit includes: a first storage sub-circuit, the first storage sub-circuit coupled to the first node, the first sub-node and the first voltage terminal; a first compensation sub-circuit, the first compensation sub-circuit coupled to the second scan signal terminal, the first sub-node of the first node and the second node, the first compensation sub-circuit being configured to transmit the first sub-data signal from the data signal terminal to the first node, the first sub-node in response to the second scan signal received at the second scan signal terminal; a first driving sub-circuit, the first driving sub-circuit coupled to the first sub-node of the first node, the second node and the first sub-node of the third node, the first driving sub-circuit being configured to generate a first driving current in response to the voltage of the first node, the first sub-node, wherein the first driving current is used to drive the first sub-light-emitting element to emit light; and a second sub-pixel driving circuit. The circuit includes: a second storage subcircuit, the second storage subcircuit is coupled to the first node, the second subnode and the first voltage terminal, wherein the first storage subcircuit and the second storage subcircuit are coupled at the first voltage terminal; a second compensation subcircuit, the second compensation subcircuit is coupled to the third scan signal terminal, the first node, the second subnode and the second node, and the second compensation subcircuit is configured to transmit the second sub-data signal from the data signal terminal to the first node, the second subnode in response to the third scan signal received at the third scan signal terminal; a second driving subcircuit, the second driving subcircuit is coupled to the first node, the second subnode, the second node and the third node, and the second driving subcircuit is configured to generate a second driving current in response to the voltage of the first node, the second subnode, wherein the second driving current is used to drive the second sub-light-emitting element to emit light.

[0020] According to some exemplary embodiments, the first light-emitting control sub-circuit includes a light-emitting control transistor, the control electrode of the light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the light-emitting control transistor is coupled to the first voltage terminal, and the second electrode of the light-emitting control transistor is coupled to the second node; the first initialization sub-circuit includes an initialization transistor, the control electrode of the initialization transistor is coupled to the first reset signal terminal, the first electrode of the initialization transistor is coupled to the second node, and the second electrode of the initialization transistor is coupled to the first initialization signal terminal; the first data writing sub-circuit includes a first data writing transistor, and the second data writing sub-circuit includes a second data writing transistor, wherein the control electrode of the first data writing transistor is coupled to the first scan signal terminal, the first electrode of the first data writing transistor is coupled to the first sub-node of the third node, the second electrode of the first data writing transistor is coupled to the first electrode of the second data writing transistor, the control electrode of the second data writing transistor is coupled to the first scan signal terminal, and the second electrode of the second data writing transistor is coupled to the second sub-node of the third node.

[0021] According to some exemplary embodiments, the pixel circuit includes: a first light-emitting control subcircuit, the first light-emitting subcircuit being coupled to a first voltage terminal, a light-emitting control terminal, and the second node, wherein the first light-emitting control subcircuit is configured to write a first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal, wherein the first sub-pixel driving circuit and the second sub-driving circuit are electrically connected at the second node, the first light-emitting control subcircuit writing the first voltage into the first sub-pixel driving circuit via the second node; and the first light-emitting control subcircuit writing the first voltage into the second sub-pixel driving circuit via the second node; A reference voltage writing subcircuit, wherein the second reference voltage writing subcircuit is coupled to the second reset signal terminal, the second reference voltage terminal and the second node, wherein the second reference voltage writing subcircuit is configured to write the second reference voltage received at the second reference voltage terminal into the second node in response to the second reset signal received at the second reset signal terminal; the first sub-pixel driving circuit further includes: a first data writing subcircuit, wherein the first data writing subcircuit is coupled to the data signal terminal, the second scan signal terminal and the first sub-node of the fourth node, and the first data writing subcircuit is configured to write the data signal received at the data signal terminal into the fourth node in response to the second scan signal received at the second scan signal terminal. a first subnode; a first storage subcircuit, the first storage subcircuit being coupled to the first subnode of the first node and the first subnode of the fourth node; a third storage subcircuit, the third storage subcircuit being coupled to the first subnode of the fourth node and the first voltage terminal; the second subpixel driving circuit further comprising: a second data writing subcircuit, the second data writing subcircuit being coupled to the data signal terminal, the third scan signal terminal and the second subnode of the third node, the second data writing subcircuit being configured to write the data signal received at the data signal terminal into the second subnode of the third node in response to the third scan signal received at the third scan signal terminal; a second storage subcircuit, the second storage subcircuit being coupled to the second subnode of the first node and the first voltage terminal; a second sub-node of the fourth node; a fourth storage sub-circuit, the fourth storage sub-circuit coupled to the second sub-node of the fourth node and the first voltage terminal, wherein the first data writing sub-circuit and the second data writing sub-circuit share the same data routing; the pixel driving circuit further comprising a first reference voltage first writing sub-circuit and a first reference voltage second writing sub-circuit, wherein the first reference voltage first writing sub-circuit is coupled to the first sub-node of the fourth node, the second reset signal terminal and the first reference voltage signal terminal, and the first reference voltage first writing sub-circuit is configured to write the first reference voltage received at the first reference voltage signal terminal into the first sub-node of the fourth node in response to the second reset signal received at the second reset signal terminal;The first reference voltage second writing sub-circuit is coupled to the fourth node second sub-node, the second reset signal terminal, and the first reference voltage signal terminal, and the first reference voltage second writing sub-circuit is configured to write the first reference voltage received at the first reference voltage signal terminal into the fourth node second sub-node in response to a second reset signal received at the second reset signal terminal.

[0022] On the other hand, a pixel driving method is provided, which is applied to the pixel circuit as described in any of the above items, wherein the pixel driving method includes: in a third time period, in response to the first scanning signal and the second scanning signal, the data writing sub-circuit and the first compensation sub-circuit are both turned on, so that the first sub-data signal from the data signal end is transmitted to the first node and the first sub-node; in a fourth time period, in response to the first scanning signal and the third scanning signal, the data writing sub-circuit and the second compensation sub-circuit are both turned on, so that the second sub-data signal from the data signal end is transmitted to the first node and the second sub-node, wherein the third time period and the fourth time period are in the writing stage of an image frame, the fourth time period is after the third time period and the fourth time period does not overlap with the third time period.

[0023] According to some exemplary embodiments, in a first time period, in response to a light emitting control signal from a light emitting control terminal, the first sub-pixel and the second sub-pixel stop emitting light, and the first sub-pixel driving circuit and the second sub-pixel driving circuit start to reset; in a second time period, in response to a first reset signal from a first reset signal terminal, the first initialization sub-circuit is turned on and the third initialization sub-circuit is turned on, so that the first initialization signal from the first initialization signal terminal is transmitted to the first node, the first sub-node and the first node, the second sub-node, respectively, wherein the first time period and the second time period are in the reset stage of an image frame, the first time period is before the second time period, the second time period is between the first time period and the third time period, and the first time period, the second time period and the third time period do not overlap with each other.

[0024] According to some exemplary embodiments, in the first sub-stage of the first time period, in response to the first reset signal and the second scanning signal, the first initialization sub-circuit and the first compensation sub-circuit are both turned on, so that the first initialization signal from the first initialization signal terminal is output to the first sub-node of the first node; in the second sub-stage of the first time period, in response to the first reset signal and the third scanning signal, the third initialization sub-circuit and the second compensation sub-circuit are both turned on, so that the first initialization signal from the first initialization signal terminal is output to the second sub-node of the first node, wherein the first sub-stage of the first time period and the second sub-stage of the first time period are in the reset stage of an image frame, the first sub-stage of the first time period is before the second sub-stage of the first time period, and the first sub-stage of the first time period and the second sub-stage of the first time period do not overlap.

[0025] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a pixel circuit as described in any one of the above items arranged on the base substrate, wherein the pixel circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit; and a light-emitting element arranged on the base substrate, wherein the light-emitting element includes a first sub-light-emitting element and a second sub-light-emitting element, wherein the first sub-light-emitting element is coupled to the first sub-pixel driving circuit, and the second sub-light-emitting element is coupled to the second sub-pixel driving circuit.

[0026] On the other hand, a display substrate is provided, wherein the display substrate comprises: a base substrate; a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits, the plurality of pixel circuits being used to drive the plurality of sub-pixels, wherein the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being two adjacent sub-pixels in the first direction or the second direction, the plurality of pixel circuits comprising a first sub-pixel driving circuit for driving the first sub-pixel and a second sub-pixel driving circuit for driving the second sub-pixel, and the first direction and the second direction intersect; the display substrate comprises: a first semiconductor layer arranged on the base substrate; a first conductive layer arranged on a side of the first semiconductor layer away from the base substrate; a third conductive layer arranged on a side of the first conductive layer away from the base substrate; and a third conductive layer arranged on a side of the third conductive layer away from the base substrate. a fourth conductive layer on one side of the base substrate; the display substrate further comprises a first scanning signal line extending along a first direction and a data signal line extending along a second direction, the first scanning signal line is located in the first conductive layer, and the data signal line is located in the fourth conductive layer; the first sub-pixel driving circuit and the second sub-pixel driving circuit share a data writing sub-circuit and a data signal line, the data writing sub-circuit comprises a data writing transistor, the data writing transistor comprises a data writing active layer, a control electrode and a second electrode, the data writing active layer is located in the first semiconductor layer, and the second electrode is located in the third conductive layer; and the orthographic projection of the data writing active layer on the base substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the base substrate, and the overlapping portion of the first scanning signal line and the data writing active layer is the control electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the data signal line through a first via.

[0027] According to some exemplary embodiments, the first sub-pixel driving circuit and the second sub-pixel driving circuit share a first light-emission control sub-circuit, the first light-emission control sub-circuit including a light-emission control transistor, the light-emission control transistor including a light-emission control active layer, a control electrode, and a first electrode, the light-emission control active layer being located in the first semiconductor layer, and the first electrode of the light-emission control transistor being located in the third conductive layer; the display substrate further including a light-emission control line extending along a first direction, the orthographic projection of the light-emission control active layer on the base substrate at least partially overlapping with the orthographic projection of the light-emission control line on the base substrate, the overlapping portion of the light-emission active layer and the light-emission control line being the control electrode of the light-emission control transistor; the display substrate further including a first conductive transition portion, the first conductive transition portion being located in the third conductive layer, the first electrode of the light-emission control transistor being electrically connected to a first power line via the first conductive transition portion, wherein the first power line includes a first power sub-line and a second power sub-line, the first power sub-line and the second power sub-line being spaced apart in the first direction and extending in the second direction, the first conductive transition portion being electrically connected to the first power sub-line via a second via hole; and the first conductive transition portion being electrically connected to the second power sub-line via a third via hole.

[0028] According to some exemplary embodiments, the data writing active layer and the light emitting control active layer extend continuously in the second direction; the orthographic projections of both the data writing active layer and the first light emitting control active layer on the substrate at least partially overlap with the orthographic projection of the data signal line on the substrate; and the orthographic projection of the data signal line on the substrate falls into the gap between the orthographic projections of the first power sub-line and the second power sub-line on the substrate.

[0029] According to some exemplary embodiments, the first conductive transition portion includes a first conductive transition sub-portion and a second conductive transition sub-portion, the first conductive transition sub-portion extends along the second direction, and the second conductive transition sub-portion extends along the first direction, wherein the orthographic projection of the first conductive transition sub-portion on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control active layer on the base substrate; the orthographic projection of the second via on the base substrate falls within the orthographic projection of the first end of the second conductive transition sub-portion on the base substrate, and the orthographic projection of the third via on the base substrate falls within the orthographic projection of the second end of the second conductive transition sub-portion on the base substrate.

[0030] According to some exemplary embodiments, the data writing active layer extends along the second direction, the light emitting control active layer extends along the second direction, the data writing active layer and the light emitting control active layer are spaced apart along the first direction; and the orthographic projection of the data writing active layer on the base substrate falls within the orthographic projection of the second power sub-line on the base substrate; the orthographic projection of the light emitting control active layer on the base substrate falls within the orthographic projection of the first power sub-line on the base substrate.

[0031] According to some exemplary embodiments, the first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, wherein the first driving active layer and the second driving active layer respectively extend in a zigzag shape in the first direction; and the first driving active layer and the second driving active layer are symmetrical about the data signal line.

[0032] According to some exemplary embodiments, a first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, wherein the first driving active layer extends in a straight line along the first direction, the second driving active layer extends in a straight line along the first direction, and the first driving active layer and the second driving active layer are spaced apart in the second direction; the light-emitting control active layer, the first driving active layer and the second driving active layer are electrically connected to each other.

[0033] According to some exemplary embodiments, the display substrate further includes a second conductive layer located between the first conductive layer and the third conductive layer; the first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, wherein the first plate and the third plate are located in the first conductive layer, and the first plate and the third plate are spaced apart in the first direction; the second plate and the fourth plate are located in the second conductive layer, and the second plate and the fourth plate are electrically connected.

[0034] According to some exemplary embodiments, the display substrate further includes a second conductive layer located between the first conductive layer and the third conductive layer; the first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, wherein the first plate and the third plate are located in the first conductive layer, the first plate and the third plate are spaced apart in the second direction and at least partially overlap in the first direction; the second plate and the fourth plate are located in the second conductive layer, and the second plate and the fourth plate are electrically connected.

[0035] According to some exemplary embodiments, the first conductive transfer portion includes a first conductive transfer sub-portion and a second conductive transfer sub-portion, wherein the first end of the first conductive transfer sub-portion is electrically connected to the first power sub-line through a second via, and the second end of the first conductive transfer sub-portion is electrically connected to the second electrode plate through a sixth via; the second conductive transfer sub-portion is electrically connected to the second power sub-line through a third via; and the second conductive transfer sub-portion is electrically connected to the fourth capacitor electrode plate through a seventh via, wherein the orthographic projections of any two of the second conductive transfer sub-portion, the fourth capacitor electrode plate and the second power sub-line on the substrate at least partially overlap.

[0036] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits, the plurality of pixel circuits being used to drive the plurality of sub-pixels, wherein the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are two sub-pixels adjacent to each other in the first direction or the second direction, the plurality of pixel circuits include a first sub-pixel driving circuit for driving the first sub-pixel and a second sub-pixel driving circuit for driving the second sub-pixel, and the first direction and the second direction intersect; the display substrate includes: a first semiconductor layer provided on the base substrate; a first conductive layer provided on a side of the first semiconductor layer away from the base substrate; a third conductive layer provided on a side of the first conductive layer away from the base substrate; and a fourth conductive layer provided on a side of the third conductive layer away from the base substrate; the display substrate also includes a first reset signal line and a light emitting control line extending along the first direction; and a data line extending along the second direction. signal line and a first power line, the first reset signal line and the light-emitting control line are located in the first conductive layer, and the data signal line and the first power line are located in the fourth conductive layer; the first sub-pixel driving circuit and the second sub-pixel driving circuit share a first initialization sub-circuit and a first light-emitting control sub-circuit, wherein the first initialization sub-circuit includes an initialization transistor, the initialization transistor includes an initialization active layer and a control electrode, the initialization active layer extends along the second direction, the orthographic projection of the initialization active layer on the substrate overlaps with the orthographic projection of the first reset signal line on the substrate at least partially, and the overlapping portion of the initialization active layer and the first reset signal layer is the control electrode of the initialization transistor; and the first light-emitting control sub-circuit includes a light-emitting control transistor, the light-emitting control transistor includes a light-emitting control active layer and a first electrode, the light-emitting active layer extends along the second direction; the orthographic projection of the light-emitting active layer on the substrate falls within the orthographic projection of the first power line on the substrate; the first electrode of the light-emitting control transistor is electrically connected to the first power line through a first conductive transition portion.

[0037] According to some exemplary embodiments, the first sub-pixel driving circuit includes a first data writing sub-circuit, the first data writing sub-circuit includes a first data writing transistor, the first data writing transistor includes a first data writing active layer and a second pole; the second sub-pixel driving circuit includes a second data writing sub-circuit, the second data writing sub-circuit includes a second data writing transistor, the second data writing transistor includes a second data writing active layer and a first pole, wherein the first data writing active layer includes a main body extending along the second direction; the second data writing active layer includes a main body extending along the second direction, the first data writing active layer and the second data writing active layer share a overlapping portion, the overlapping portion extends along the first direction, and the second pole of the first data writing transistor and the first pole of the second data writing transistor are both electrically connected to the data signal line through a fourth via.

[0038] According to some exemplary embodiments, the first sub-pixel driving circuit includes a first compensation sub-circuit, the first compensation sub-circuit includes a first compensation transistor, and the first compensation transistor includes a first compensation active layer; the second sub-pixel driving circuit includes a second compensation sub-circuit, the second compensation sub-circuit includes a second compensation transistor, and the second compensation transistor includes a second compensation active layer, wherein the first compensation active layer and the second compensation active layer both extend along the first direction; and the first compensation active layer and the second compensation active layer are both spaced apart in the first direction and the second direction.

[0039] According to some exemplary embodiments, the first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, wherein the first plate and the third plate are located in the first conductive layer, and the first plate and the third plate are spaced apart in the second direction; the second plate and the fourth plate are located in the second conductive layer, and the second plate and the fourth plate are electrically connected.

[0040] According to some exemplary embodiments, the first conductive transition portion is electrically connected to the first power line through a fifth via; the first conductive transition portion is electrically connected to the fourth electrode plate through an eighth via; the display substrate also includes a third conductive transition portion located in the third conductive layer, the first compensation transistor includes a second electrode, the second compensation transistor includes a first electrode, and the second electrode of the first compensation transistor is electrically connected to the first electrode of the second compensation transistor through the third conductive transition portion.

[0041] According to some exemplary embodiments, a first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, wherein the first driving active layer extends in a straight line along the first direction, the second driving active layer extends in a straight line along the first direction, and the first driving active layer and the second driving active layer are spaced apart in the second direction; the light-emitting control active layer, the first driving active layer and the second driving active layer are electrically connected to each other.

[0042] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0044] FIG1 is a schematic plan view of a display device according to some embodiments of the present disclosure;

[0045] FIG2 is a schematic diagram of a sub-pixel structure according to some embodiments of the present disclosure;

[0046] FIG3 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0047] FIG4A is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0048] FIG4B is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0049] FIG5 is an operation timing diagram of at least one embodiment of a driving method for the pixel shown in FIG4A;

[0050] FIG6 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0051] FIG7 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0052] FIG8 is an operation timing diagram of at least one embodiment of a driving method for the pixel shown in FIG7 ;

[0053] FIG9 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0054] FIG10 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0055] FIG11 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0056] FIG12 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0057] FIG13 is an operation timing diagram of at least one embodiment of a driving method for the pixel shown in FIG12 ;

[0058] FIG14 is a schematic structural diagram of a display substrate according to some exemplary embodiments of the present disclosure;

[0059] 15A is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG15B is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG15C is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG15D is a schematic diagram illustrating a portion of a via hole according to an exemplary embodiment of the present disclosure; FIG15E is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG15F is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG16A is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG16B is a partial cross-sectional schematic diagram of a pixel circuit according to an embodiment of the present disclosure taken along line AA′ in FIG16A;

[0060] 17A is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG17B is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG17C is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG17D is a schematic diagram illustrating a portion of a via hole according to an exemplary embodiment of the present disclosure; FIG17E is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG17F is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; and FIG18 is a schematic diagram illustrating a planar structure of a combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0061] 19A is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG19B is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG19C is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG19D is a schematic diagram illustrating a portion of a via hole according to an exemplary embodiment of the present disclosure; FIG19E is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG19F is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; and FIG20 is a schematic diagram illustrating a planar structure of a combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0062] [Corrected on 27.03.2024 according to Rule 91] Figure 21A is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21B is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21D is a schematic diagram showing a partial via according to an exemplary embodiment of the present disclosure; Figure 21E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21F is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 22 is a schematic diagram showing the planar structure of the combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0065] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0066] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0067] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0068] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0069] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0070] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0071] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0072] Embodiments of the present disclosure provide at least one pixel circuit, comprising: a first sub-pixel driving circuit for driving a first sub-pixel; and a second sub-pixel driving circuit for driving a second sub-pixel, wherein the first sub-pixel includes a first sub-light-emitting element and the second sub-pixel includes a second sub-light-emitting element, the first sub-pixel and the second sub-pixel being adjacent in a first direction or a second direction, the first direction and the second direction intersecting; and the pixel circuit further comprising a first data signal line configured to provide data signals to both the first sub-pixel driving circuit and the second sub-pixel driving circuit, wherein the data signals include a first sub-data signal and a second sub-data signal, the first sub-data signal being generated by the first data signal line in a third time period and the second sub-data signal being generated by the first data signal line in a fourth time period, wherein the third time period and the fourth time period do not overlap. By designing adjacent sub-pixels to share a single data signal line, the number of data signal lines can be reduced by half, saving wiring space and facilitating a narrow frame of a display substrate. Simultaneously, by reducing the number of data signal lines by half, the number of required IC channels is also reduced, thereby reducing the number of ICs and lowering costs.

[0073] FIG1 is a schematic plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device. Referring to FIG1 , the display device 1000 may include a display substrate 1100, a gate driver 1200, a data driver 1300, and a controller 1400. The display substrate 1100 may include a plurality of pixels PX and pixel circuits for driving the plurality of pixels PX. The display substrate 1100 may include a display area AA and a non-display area NA. The plurality of pixels PX are arranged in an array in the display area AA in a first direction D1 or a second direction D2, where the first direction D1 and the second direction D2 intersect. Signals generated by the gate driver 1200 may be applied to the pixels PX via signal lines such as scan signal lines GL, and signals generated by the data driver 1300 may be applied to the pixels PX via signal lines such as data lines DL. For example, the plurality of pixels PX may include a first sub-pixel SP1 and a second sub-pixel SP2 adjacent to each other. The first sub-pixel SP1 may include a first light-emitting unit L1 and a first sub-pixel driving circuit DX1, and the second sub-pixel may include a second light-emitting unit L2 and a second sub-pixel driving circuit DX2. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 may be electrically connected to the same data signal line and may receive data signals transmitted from the same data signal line.

[0074] For example, each pixel PX may include a plurality of sub-pixels, eg, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0075] For example, the display substrate may be an array substrate for an OLED display panel.

[0076] The display substrate may further include a driver located within the non-display area NA. For example, the driver may be located on at least one side of the display area AA. The driver may be used to drive each pixel in the display substrate for display. For example, the driver may include a gate driver 1200 and a data driver 1300. The data driver 1300 is used to sequentially latch the input data according to the clock signal timing and convert the latched data into an analog signal and then input it to each data signal line of the display substrate. The data driver 1300 includes a plurality of IC chips for writing control signals to the plurality of data signal lines, wherein the number of required IC chips is related to the number of data signal lines. The more data signal lines there are, the more IC chips are required accordingly. The gate driver 1200 is usually implemented by a shift register, which converts the clock signal into an on / off voltage and outputs it to each scan signal line of the display substrate respectively.

[0077] It should be noted that, although FIG. 1 shows that the driver is located on the left and upper side of the display area AA, the embodiments of the present disclosure are not limited thereto, and the driver circuit may be located at any appropriate position in the non-display area NA.

[0078] For example, the driver can adopt GOA technology, i.e., Gate Driver on Array (GDA). In GOA technology, the gate driver circuit is directly arranged on the array substrate, replacing the external driver chip. Each GOA unit acts as a shift register, and each shift register is connected to a gate line. The shift registers at each level sequentially output the turn-on voltage to achieve row-by-row scanning of pixels. In some embodiments, each shift register can also be connected to multiple gate lines. This can adapt to the development trend of high-resolution and narrow-frame display substrates.

[0079] It should be noted that the figure exemplarily shows that the shape of the orthographic projection of the sub-pixel on the substrate is a rectangle, but the embodiments of the present disclosure are not limited to this. For example, the shape of the orthographic projection of the sub-pixel on the substrate can be other shapes such as a rounded rectangle, a hexagon, a pentagon, a square, and a circle.

[0080] A plurality of sub-pixels are arranged in an array along a first direction D1 and a second direction D2 on a base substrate 1. It should be noted that although in the illustrated embodiment, the first direction D1 and the second direction D2 are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.

[0081] It should be understood that in the embodiments of the present disclosure, each sub-pixel includes a pixel circuit and a light-emitting element. For example, the light-emitting element may be an OLED light-emitting element, including a stacked anode, a light-emitting layer, and a cathode. The pixel circuit may include multiple thin-film transistors and at least one storage capacitor.

[0082] FIG2 is a schematic structural diagram of a sub-pixel according to some embodiments of the present disclosure.

[0083] As shown in FIG2 , two adjacent sub-pixels include: a first sub-pixel L1, a first sub-pixel driver circuit DX1 coupled to the first sub-pixel L1; and a second sub-pixel L2, and a second sub-pixel driver circuit DX2 coupled to the second sub-pixel L2. The first sub-pixel driver circuit DX1 is configured to provide a driving current to the first sub-pixel L1 to drive the first sub-pixel L1 to operate (i.e., emit light), and the second sub-pixel driver circuit DX2 is configured to provide a driving current to the second sub-pixel L2 to drive the second sub-pixel L2 to operate. The first sub-pixel driver circuit DX1 and the second sub-pixel driver circuit DX2 can be coupled to the same data signal line, such as the first data signal line DL1. The first data signal line DL1 can provide data signals to both the first sub-pixel driver circuit DX1 and the second sub-pixel driver circuit DX2, respectively, to control the first sub-pixel L1 and the second sub-pixel L2 to emit light. The data signals received by the first sub-pixel driver circuit DX1 and the second sub-pixel driver circuit DX2 can be received at different times and have different magnitudes.

[0084] For example, the data signal may include a first sub-data signal and a second sub-data signal. The first sub-data signal may be generated by the first data signal line DL1 during a third time period, and the second sub-data signal may be generated by the first data signal line DL1 during a fourth time period, wherein the third time period and the fourth time period do not overlap. The same data signal line can provide data signals to two adjacent sub-pixels at different time periods, thereby illuminating multiple pixels. This can save data signal lines and wiring space, facilitating a narrow-frame display substrate. Furthermore, reducing the number of data signal lines also reduces the number of supporting IC chips, thereby lowering costs.

[0085] Exemplarily, the light-emitting element includes a current-driven element. Further, the light-emitting element L can be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), a quantum dot light-emitting diode (Quantum Light Emitting Diode, QLED) or an organic light-emitting diode (Organic Light Emitting Diode, OLED). Exemplarily, the first electrode and the second electrode of the light-emitting element L are the anode and cathode of the light-emitting diode, respectively.

[0086] Figure 3 is a block diagram of a pixel circuit according to some embodiments of the present disclosure; Figure 4A is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure. It should be noted that in the following description, a 7T1C pixel circuit is used as an example of a driving circuit for a single sub-pixel to describe the structure of the pixel circuit in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel circuit. Other known pixel circuit structures can be applied to the embodiments of the present disclosure unless there is a conflict.

[0087] For example, in some embodiments of the present disclosure, referring to FIG3 , a pixel driving circuit includes a first sub-pixel driving circuit DX1 and a second sub-pixel driving circuit DX2. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a data writing sub-circuit 21. The data writing sub-circuit 21 is coupled to a data signal terminal Data, a first scan signal terminal Gate, and a second node N2. The data signal terminal Data is coupled to a first data signal line DL1. The data writing sub-circuit 21 is configured to write a data signal received at the data signal terminal Data into the second node N2 in response to a first scan signal received at the first scan signal terminal Gate. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 are coupled to the second node N2. The data writing sub-circuit 21 writes a first sub-data signal DL11 into the first sub-pixel driving circuit DX1 via the second node N2. The data writing sub-circuit 21 writes a second sub-data signal DL12 into the second sub-pixel driving circuit DX2 via the second node N2.

[0088] The driving circuits of adjacent sub-pixels can share at least a part of the circuit, such as the data writing sub-circuit, wherein the data writing sub-circuit includes at least one transistor. By designing that adjacent sub-pixel driving circuits share transistors, the number of transistors and the number of vias can be reduced, which is beneficial to improving the yield of the display substrate process section and is also beneficial to the layout of subsequent high-resolution products.

[0089] For example, with continued reference to FIG3 , the first sub-pixel driver circuit DX1 may further include: a first driver sub-circuit 311 and a first compensation sub-circuit 411. The first driver sub-circuit 311 is coupled to the first node (first sub-node N1-1), the second node (N2), and the third node (first sub-node N3-1). The first driver sub-circuit 311 is configured to generate a first drive current in response to the voltage of the first node (first sub-node N1-1), wherein the first drive current is used to drive the first sub-light-emitting element L1 to emit light. The first compensation sub-circuit 411 is coupled to the second scan signal terminal Gate1, the first node (first sub-node N1-1), and the third node (first sub-node N3-1). The first compensation sub-circuit 411 is configured to transmit a first sub-data signal DL11 from the data signal terminal Data to the first node (first sub-node N1-1) in response to the second scan signal received at the second scan signal terminal Gate1. The second sub-pixel driver circuit DX2 may further include: a second driver sub-circuit 312 and a second compensation sub-circuit 412. The second driving sub-circuit 312 is coupled to the first node second sub-node N1-2, the second node N2 and the third node second sub-node N3-2, and the second driving sub-circuit 312 is configured to generate a second driving current in response to the voltage of the first node second sub-node N1-2, wherein the second driving current is used to drive the second sub-light-emitting element to emit light L2; the second compensation sub-circuit 412 is coupled to the third scan signal terminal Gate2, the first node second sub-node N1-2 and the third node second sub-node N3-2, and the second compensation sub-circuit 412 is configured to transmit the second sub-data signal DL12 from the data signal terminal Data to the first node second sub-node N1-2 in response to the third scan signal received at the third scan signal terminal Gate2.

[0090] Exemplarily, the data writing sub-circuit 21, the first driving sub-circuit 311, and the second driving sub-circuit 312 are all coupled to the second node N2. The data writing sub-circuit 21 writes data signals into the first driving sub-circuit 311 and the second driving sub-circuit 312 via the second node N2, thereby controlling the first sub-light-emitting element L1 and the second sub-light-emitting element L2 to emit light, respectively, to display different display effects.

[0091] For example, with continued reference to FIG3 , the first sub-pixel driver circuit DX1 may further include: a first light-emitting control sub-circuit 511 and a first storage sub-circuit 611. The first light-emitting control sub-circuit 511 is coupled to the first voltage terminal VDD1, the light-emitting control terminal EM, and the second node N2. The first light-emitting control sub-circuit 511 is configured to write the first voltage received at the first voltage terminal VDD1 to the second node N2 in response to a light-emitting control signal received at the light-emitting control terminal EM. The first storage sub-circuit 611 is coupled to the first node, the first sub-node N1-1, and the first voltage terminal VDD. The first storage sub-circuit 611 may be used to store the stored voltage in the first sub-pixel driver circuit. The second sub-pixel driver circuit DX2 may further include: a third light-emitting control sub-circuit 513 and a second storage sub-circuit 612. The third light-emitting control sub-circuit 513 is coupled to the second voltage terminal VDD2, the light-emitting control terminal EM and the second node N2. The third light-emitting control sub-circuit 513 is configured to write the second voltage received at the second voltage terminal VDD2 into the second node N2 in response to the light-emitting control signal received at the light-emitting control terminal EM. The second storage sub-circuit 612 is coupled to the first node, the second sub-node N1-2 and the second voltage terminal VDD2.

[0092] Exemplarily, both the first voltage terminal VDD1 and the second voltage terminal VDD2 may provide a high-level voltage, such as 5V, and the first voltage provided by the first voltage terminal VDD1 and the second voltage provided by the second voltage terminal VDD2 may be the same.

[0093] 3 , the first sub-pixel driving circuit DX1 may further include: a first initialization sub-circuit 711, a second initialization sub-circuit 712, and a second light-emitting control sub-circuit 512. The first initialization sub-circuit 711 is coupled to the first reset signal terminal Reset1, the first initialization signal terminal Vinit1, and the first node first sub-node N1-1. The first initialization sub-circuit 711 is configured to, in response to the first reset signal received at the first reset signal terminal Reset1, transmit the first initialization signal received at the first initialization signal terminal Vinit1 to the first node first sub-node N1-1 to initialize the potential of the first node first sub-node N1-1. The second initialization sub-circuit 712 is coupled to the second reset signal terminal Reset2, the second initialization signal terminal Vinit2, and the first electrode L11 of the first sub-light-emitting element L1. 712 is configured to transmit the second initialization signal received at the second initialization signal terminal Vinit2 to the first electrode L11 of the first sub-light-emitting element L1 in response to the second reset signal received at the second reset signal terminal Reset2, so as to initialize the potential of the first electrode L11 of the first sub-light-emitting element L1; the second light-emitting control sub-circuit 512 is coupled to the third node first sub-node N3-1, the light-emitting control terminal EM and the first electrode L11 of the first sub-light-emitting element L1, and the second light-emitting control sub-circuit 512 is configured to output the first driving current transmitted to the third node first sub-node N3-1 to the first sub-light-emitting element in response to the light-emitting control signal received at the light-emitting control terminal EM.

[0094] 3 , the second sub-pixel driving circuit DX2 may further include: a third initialization sub-circuit 713, a fourth initialization sub-circuit 714, and a fourth light-emitting control sub-circuit 514. The third initialization sub-circuit 713 is coupled to the first reset signal terminal Reset1, the first initialization signal terminal Vinit1, and the first node second sub-node N1-2. The third initialization sub-circuit 713 is configured to, in response to the first reset signal received at the first reset signal terminal Reset1, transmit the first initialization signal received at the first initialization signal terminal Vinit1 to the first node second sub-node N1-2 to initialize the potential of the first node second sub-node N1-2. The fourth initialization sub-circuit 714 is coupled to the second reset signal terminal Reset2, the second initialization signal terminal Vinit2, and the first electrode L21 of the second sub-light-emitting element L2. 14 is configured to transmit the second initialization signal received at the second initialization signal terminal Vinit2 to the first electrode L21 of the second sub-light-emitting element L2 in response to the second reset signal received at the second reset signal terminal Reset2, so as to initialize the potential of the first electrode L21 of the second sub-light-emitting element L2; the fourth light-emitting control sub-circuit 514 is coupled to the third node second sub-node N3-2, the light-emitting control terminal EM and the first electrode L21 of the second sub-light-emitting element L2, and the second light-emitting control sub-circuit 514 is configured to output the second driving current transmitted to the third node second sub-node N3-2 to the second sub-light-emitting element L2 in response to the light-emitting control signal received at the light-emitting control terminal EM.

[0095] By sharing the data writing sub-circuit and data signal line of the driving circuits of two adjacent sub-pixels, on the one hand, the number of data signal lines can be reduced, wiring space can be saved, and it is conducive to achieving a narrow frame of the display substrate; on the other hand, reducing the number of data signal lines is also conducive to reducing the number of supporting IC chips, which is conducive to reducing costs; at the same time, adjacent sub-pixel driving circuits share at least some transistors, such as data writing transistors, which can reduce the number of transistors and the number of vias, which is conducive to improving the yield of the display substrate process section and is also conducive to the layout of subsequent high-resolution products.

[0096] It should be understood that in the pixel circuit provided in the embodiments of the present disclosure, the first node first subnode N1-1, the first node second subnode N1-2, the second node N2, the third node first subnode N3-1, and the third node second subnode N3-2 do not necessarily represent actual existing components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit, that is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0097] For example, in some embodiments of the present disclosure, referring to FIG4A , in the first sub-pixel driving circuit DX1, the data writing sub-circuit 21 includes a data writing transistor T4, the first driving sub-circuit 311 includes a first driving transistor T31, the first compensation sub-circuit 411 includes a first compensation transistor T21, the first light-emitting control sub-circuit 511 includes a first light-emitting control transistor T51, the second light-emitting control sub-circuit 512 includes a second light-emitting control transistor T61, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second initialization sub-circuit 712 includes a second initialization transistor T71, and the first storage sub-circuit 611 includes a first capacitor C1.

[0098] For example, continuing to refer to Figure 4A, in the second sub-pixel driving circuit DX2, the data writing sub-circuit 21 includes a data writing transistor T4, the second driving sub-circuit 312 includes a second driving transistor T32, the second compensation sub-circuit includes a second compensation transistor T22, the third light-emitting control sub-circuit 513 includes a third light-emitting control transistor T52, the fourth light-emitting control sub-circuit 514 includes a fourth light-emitting control transistor T62, the third initialization sub-circuit 713 includes a third initialization transistor T12, the fourth initialization sub-circuit 714 includes a fourth initialization transistor T72, and the second storage sub-circuit 612 includes a second capacitor C2.

[0099] The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share data writing transistors and data signal lines, which can reduce the number of wiring and vias, and is conducive to achieving narrow frame and improving yield. At the same time, it can save the number of IC chips and help reduce costs.

[0100] It should be noted that each transistor includes a control electrode of the transistor, that is, a gate; a first electrode of the transistor, that is, one of a source or a drain; and a second electrode of the transistor, that is, the other of the source or the drain.

[0101] The control electrode of the data writing transistor T4 is electrically connected to the first scanning signal terminal Gate, the first electrode of the data writing transistor T4 is electrically connected to the second node N2, and the second electrode of the data writing transistor T4 is electrically connected to the data signal terminal Data. For example, the data writing transistor T4 is used to provide a data signal.

[0102] The control electrode of the first driving transistor T31 is electrically connected to the first node first subnode N1-1; the first electrode of the first driving transistor T31 is electrically connected to the second node N2; and the second electrode of the first driving transistor T31 is electrically connected to the third node first subnode N3-1.

[0103] The control electrode of the first compensation transistor T21 is electrically connected to the second scan signal terminal Gate1 , the first electrode of the first compensation transistor T21 is electrically connected to the first node first subnode N1 - 1 , and the second electrode of the first compensation transistor T21 is electrically connected to the third node first subnode N3 - 1 .

[0104] A control electrode of the first light emitting control transistor T51 is electrically connected to the light emitting control terminal EM, a first electrode of the first light emitting control transistor T51 is electrically connected to the first voltage terminal VDD1, and a second electrode of the first light emitting control transistor T51 is electrically connected to the second node N2.

[0105] The control electrode of the second light-emitting control transistor T61 is electrically connected to the light-emitting control terminal EM, the first electrode of the second light-emitting control transistor T61 is electrically connected to the third node first sub-node N3-1, and the second electrode of the second light-emitting control transistor T61 is electrically connected to the first electrode L11 of the first sub-light-emitting element.

[0106] The control electrode of the first initialization transistor T11 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first initialization transistor T11 is electrically connected to the first initialization signal terminal Vinit1, and the second electrode of the first initialization transistor T11 is electrically connected to the first node first subnode N1-1.

[0107] The control electrode of the second initialization transistor T71 is electrically connected to the second reset signal terminal Reset2, the first electrode of the second initialization transistor T71 is electrically connected to the first electrode L11 of the first sub-light emitting element, and the second electrode of the second initialization transistor T71 is electrically connected to the second initialization signal terminal Vinit2.

[0108] The first capacitor C1 may include a first plate C1a and a second plate C1b. The first plate C1a of the first capacitor C1 is electrically connected to the first electrode of the first light emission control transistor T51, and the second plate C1b is electrically connected to the first node and the first subnode N1-1.

[0109] The control electrode of the second driving transistor T32 is electrically connected to the first node second subnode N1-2; the first electrode of the second driving transistor T32 is electrically connected to the second node N2; and the second electrode of the second driving transistor T32 is electrically connected to the third node second subnode N3-2.

[0110] The control electrode of the second compensation transistor T22 is electrically connected to the third scan signal terminal Gate2, the first electrode of the second compensation transistor T22 is electrically connected to the third node second subnode N3-2, and the second electrode of the second compensation transistor T22 is electrically connected to the first node second subnode N1-2.

[0111] A control electrode of the third light emitting control transistor T52 is electrically connected to the light emitting control terminal EM, a first electrode of the third light emitting control transistor T52 is electrically connected to the second voltage terminal VDD2, and a second electrode of the third light emitting control transistor T52 is electrically connected to the second node N2.

[0112] The control electrode of the fourth light-emitting control transistor T62 is electrically connected to the light-emitting control terminal EM, the first electrode of the fourth light-emitting control transistor T62 is electrically connected to the third node second sub-node N3-2, and the second electrode of the fourth light-emitting control transistor T62 is electrically connected to the first electrode L21 of the second sub-light-emitting element.

[0113] The control electrode of the third initialization transistor T12 is electrically connected to the first reset signal terminal Reset1, the first electrode of the third initialization transistor T12 is electrically connected to the first node second subnode N1-2, and the second electrode of the third initialization transistor T12 is electrically connected to the first initialization signal terminal Vinit1.

[0114] The control electrode of the fourth initialization transistor T72 is electrically connected to the second reset signal terminal Reset2, the first electrode of the fourth initialization transistor T72 is electrically connected to the first electrode L21 of the second sub-light emitting element, and the second electrode of the fourth initialization transistor T72 is electrically connected to the second initialization signal terminal Vinit2.

[0115] The second capacitor C2 may include a third plate C2a and a fourth plate C2b. The third plate C2a of the second capacitor C2 is electrically connected to the first electrode of the third light emitting control transistor T52, and the fourth plate C2b is electrically connected to the first node and the second sub-node N1-2.

[0116] The second electrode of the first sub-light emitting element is electrically connected to the third voltage terminal. The second electrode of the second sub-light emitting element is electrically connected to the fourth voltage terminal. The third voltage terminal and the fourth voltage terminal are used to provide a low voltage.

[0117] In the embodiment of the present disclosure, the initialization signals provided by the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 may be the same or different.

[0118] In the embodiment of the present disclosure, the reset signals provided by the first reset signal terminal Reset1 and the second reset signal terminal Reset2 may be the same or different.

[0119] In the embodiment of the present disclosure, the transistor included in the pixel circuit may be a P-type transistor, an N-type transistor, or a combination of multiple transistors including a P-type transistor and an N-type transistor.

[0120] In an embodiment of the present disclosure, the transistors included in the pixel circuit may include one or more combinations of oxide thin film transistors, low-temperature polysilicon transistors, and thin film transistors.

[0121] FIG. 4B is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0122] In some embodiments of the present disclosure, as shown in FIG4A , the first emission control subcircuit 511 including the first emission control transistor T51 and the third emission control subcircuit 513 including the third emission control transistor T52 can share the same transistor. For example, the first emission control transistor T51 and the third emission control transistor T52 can share the emission control transistor T5 as shown in FIG4B .

[0123] The difference from the embodiment of FIG4A is that the emission control transistor T5 in FIG4B provides emission control signals to both the first sub-pixel driving circuit and the second sub-pixel driving circuit. Furthermore, the connection between the first capacitor C1 and the second capacitor C2 and the emission control transistor T5 is different. For example, the first capacitor C1 may include a first plate C1a and a second plate C1b, with the first plate C1a of the first capacitor C1 electrically connected to the first electrode of the emission control transistor T5, and the second plate C1b electrically connected to the first node, the first sub-node N1-1. The second capacitor C2 may include a third plate C2a and a fourth plate C2b, with the third plate C2a of the second capacitor C2 electrically connected to the first electrode of the emission control transistor T5, and the fourth plate C2b electrically connected to the first node, the second sub-node N1-2. The connection of the other transistors may be the same as that of the corresponding transistors in FIG4A. FIG5 is an operation timing diagram of at least one embodiment of the driving method of the pixel shown in FIG4A.

[0124] For example, in some embodiments of the present disclosure, with reference to FIG3 to FIG5 , the pixel circuit may include five stages set in sequence when operating, including:

[0125] In the first time period t1 , in response to the light emitting control signal of the light emitting control terminal EM, the first sub-pixel SP1 and the second sub-pixel SP2 stop emitting light, and the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 start to reset.

[0126] In the second time period t2, in response to the first reset signal of the first reset signal terminal Reset1, the first initialization sub-circuit 711 is turned on and the third initialization sub-circuit 713 is turned on, so that the first initialization signal from the first initialization signal terminal Vinit1 is transmitted to the first node first sub-node N1-1 and the first node second sub-node N1-2, respectively, wherein the first time period t1 and the second time period t2 are in the reset stage of an image frame, and the first time period t1 is before the second time period t2.

[0127] In the third time period t3, in response to the first scan signal Gate and the second scan signal Gate1, the data writing sub-circuit 21 and the first compensation sub-circuit 411 are both turned on, so that the first sub-data signal DL11 from the data signal terminal Data is transmitted to the first node and the first sub-node N1-1;

[0128] In the fourth time period t4, in response to the first scanning signal Gate and the third scanning signal Gate2, the data writing sub-circuit 21 and the second compensation sub-circuit 412 are both turned on, so that the second sub-data signal DL12 from the data signal terminal Data is transmitted to the first node second sub-node N1-2, wherein the third time period t3 and the fourth time period t4 are in the writing stage of an image frame, the fourth time period t4 is after the third time period t3 and the fourth time period t4 does not overlap with the third time period t3.

[0129] When the data writing subcircuit is turned on, by controlling the first compensation subcircuit 411 and the second compensation subcircuit 412 to be turned on at different time periods, the data signal provided by the same data signal line can be written into the first sub-pixel driving circuit and the second sub-pixel driving circuit in two different time periods. Because the third time period t3 and the fourth time period t4 do not overlap, the data signals of the two sub-pixel driving circuits do not interfere with each other, thereby achieving the purpose of providing data signals to two different sub-pixels. For example, the first sub-data signal DL11 is provided to the first sub-pixel driving circuit during the third time period t3, and the second sub-data signal DL12 is provided to the second sub-pixel driving circuit during the fourth time period t4.

[0130] In the fifth time period t5, in response to the light-emitting control signal of the light-emitting control terminal, the first light-emitting control sub-circuit 511, the second light-emitting control sub-circuit 512, the third light-emitting control sub-circuit 513 and the fourth light-emitting control sub-circuit 514 are all turned on, and the first sub-light-emitting element L1 and the second sub-light-emitting element L2 emit light.

[0131] For example, the first sub-data signal DL11 and the second sub-data signal DL12 may be the same or different, and thus the light-emitting states of the first sub-light-emitting unit L1 and the second sub-light-emitting unit L2 may also be the same or different.

[0132] FIG6 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG7 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0133] For example, in some embodiments of the present disclosure, referring to FIG6 , a pixel driving circuit includes a first sub-pixel driving circuit DX1 and a second sub-pixel driving circuit DX2. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a data writing sub-circuit 21 and a first light-emitting control sub-circuit 511. The data writing sub-circuit 21 is coupled to a data signal terminal Data, a first scan signal terminal Gate, and a second node N2. The data signal terminal Data is coupled to a first data signal line DL1. The data writing sub-circuit 21 is configured to write a data signal received at the data signal terminal Data to the second node N2 in response to a first scan signal received at the first scan signal terminal Gate. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 are coupled to a second node N2. The data writing sub-circuit 21 writes a first sub-data signal DL11 to the first sub-pixel driving circuit DX1 via the second node N2. The data writing sub-circuit 21 writes a second sub-data signal DL12 to the second sub-pixel driving circuit DX2 via the second node N2. The first light-emitting control sub-circuit 511 is coupled to the first voltage terminal VDD1, the light-emitting control terminal EM and the second node N2, wherein the first light-emitting control sub-circuit 511 is configured to respond to the light-emitting control signal received at the light-emitting control terminal EM and write the first voltage received at the first voltage terminal VDD into the first sub-pixel driving circuit and the second sub-pixel driving circuit through the second node respectively.

[0134] The driver circuits of adjacent sub-pixels can share at least a portion of their circuitry, for example, a shared data write sub-circuit and a shared first light emission control sub-circuit. These shared circuits include at least a portion of shared transistors. For example, the data write sub-circuit may include a data write transistor, and the first light emission control sub-circuit may include a first light emission control transistor. By designing shared transistors in the driver circuits of adjacent sub-pixels, the number of transistors and vias can be reduced, improving the yield of the display substrate process and facilitating the design and layout of subsequent high-resolution products.

[0135] For example, with continued reference to FIG6 , the first sub-pixel driver circuit DX1 may further include: a first driver sub-circuit 311 and a first compensation sub-circuit 411. The first driver sub-circuit 311 is coupled to the first node (first sub-node N1-1), the second node (N2), and the third node (first sub-node N3-1). The first driver sub-circuit 311 is configured to generate a first drive current in response to the voltage of the first node (first sub-node N1-1), wherein the first drive current is used to drive the first sub-light-emitting element L1 to emit light. The first compensation sub-circuit 411 is coupled to the second scan signal terminal Gate1, the first node (first sub-node N1-1), and the third node (first sub-node N3-1). The first compensation sub-circuit 411 is configured to transmit a first sub-data signal DL11 from the data signal terminal Data to the first node (first sub-node N1-1) in response to a second scan signal received at the second scan signal terminal Gate1. The second sub-pixel driver circuit DX2 may further include: a second driver sub-circuit 312 and a second compensation sub-circuit 412. The second driving sub-circuit 312 is coupled to the first node second sub-node N1-2, the second node N2 and the third node second sub-node N3-2, and the second driving sub-circuit 312 is configured to generate a second driving current in response to the voltage of the first node second sub-node N1-2, wherein the second driving current is used to drive the second sub-light-emitting element to emit light L2; the second compensation sub-circuit 412 is coupled to the third scan signal terminal Gate2, the first node second sub-node N1-2 and the third node second sub-node N3-2, and the second compensation sub-circuit 412 is configured to transmit the second sub-data signal DL12 from the data signal terminal Data to the first node second sub-node N1-2 in response to the third scan signal received at the third scan signal terminal Gate2.

[0136] Exemplarily, the data writing subcircuit 21, the first light-emitting control subcircuit 511, the first driver subcircuit 311, and the second driver subcircuit 312 are all coupled to the second node N2. The data writing subcircuit 21 writes the data signal into the first driver subcircuit 311 and the second driver subcircuit 312 via the second node N2, and the first light-emitting control subcircuit 511 writes the first voltage into the first sub-pixel driver circuit and the second sub-pixel driver circuit via the second node. By sharing the data writing subcircuit and the first light-emitting control subcircuit, the number of wiring, transistors, and vias in the driver circuit can be reduced, which helps save wiring space and achieve a narrow frame on the display substrate. The reduction in transistors and vias also helps improve the yield of the display substrate.

[0137] For example, with continued reference to FIG6 , the first sub-pixel driver circuit DX1 may further include a first storage sub-circuit 611 coupled to the first node (first sub-node N1-1) and the first voltage terminal VDD1. The first storage sub-circuit 611 may be configured to store a stored voltage in the first sub-pixel driver circuit. The second sub-pixel driver circuit DX2 may further include a second storage sub-circuit 612 coupled to the first node (second sub-node N1-2) and the first voltage terminal VDD1. The second storage sub-circuit is configured to store a stored voltage in the second sub-pixel driver circuit.

[0138] 6 , the first sub-pixel driving circuit DX1 may further include: a first initialization sub-circuit 711, a second initialization sub-circuit 712, and a second light-emitting control sub-circuit 512. The first initialization sub-circuit 711 is coupled to the first reset signal terminal Reset1, the first initialization signal terminal Vinit1, and the third node first sub-node N3-1. The first initialization sub-circuit 711 is configured to, in response to the first reset signal received at the first reset signal terminal Reset1, sequentially transmit the first initialization signal received at the first initialization signal terminal Vinit1 to the third node first sub-node N3-1 and the first node first sub-node N1-1 to initialize the potential of the first node first sub-node N1-1. The second initialization sub-circuit 712 is coupled to the second reset signal terminal Reset2, the second initialization signal terminal Vinit2, and the first electrode L11 of the first sub-light-emitting element L1. The second initialization sub-circuit 712 is configured to transmit the second initialization signal received at the second reset signal terminal Reset2 to the first electrode L11 of the first sub-light-emitting element L1 in response to the second reset signal received at the second reset signal terminal Reset2, so as to initialize the potential of the first electrode L11 of the first sub-light-emitting element L1; the second light-emitting control sub-circuit 512 is coupled to the third node first sub-node N3-1, the light-emitting control terminal EM and the first electrode L11 of the first sub-light-emitting element L1, and the second light-emitting control sub-circuit 512 is configured to output the first driving current transmitted to the third node first sub-node N3-1 to the first sub-light-emitting element in response to the light-emitting control signal received at the light-emitting control terminal EM.

[0139] 6 , the second sub-pixel driving circuit DX2 may further include: a third initialization sub-circuit 713, a fourth initialization sub-circuit 714, and a fourth light-emitting control sub-circuit 514. The third initialization sub-circuit 713 is coupled to the first reset signal terminal Reset1, the first initialization signal terminal Vinit1, and the third node second sub-node N3-2. The third initialization sub-circuit 713 is configured to, in response to the first reset signal received at the first reset signal terminal Reset1, transmit the first initialization signal received at the first initialization signal terminal Vinit1 to the third node second sub-node N3-2 and the first node second sub-node N1-2 in sequence to initialize the potential of the first node second sub-node N1-2. The fourth initialization sub-circuit 714 is coupled to the second reset signal terminal Reset2, the second initialization signal terminal Vinit2, and the first electrode L21 of the second sub-light-emitting element L2. The fourth initialization sub-circuit 714 is configured to respond to the second reset signal received at the second reset signal terminal Reset2, and transmit the second initialization signal received at the second initialization signal terminal Vinit2 to the first electrode L21 of the second sub-light-emitting element L2 to initialize the potential of the first electrode L21 of the second sub-light-emitting element L2; the fourth light-emitting control sub-circuit 514 is coupled to the third node second sub-node N3-2, the light-emitting control terminal EM and the first electrode L21 of the second sub-light-emitting element L2, and the second light-emitting control sub-circuit 514 is configured to respond to the light-emitting control signal received at the light-emitting control terminal EM, and output the second driving current transmitted to the third node second sub-node N3-2 to the second sub-light-emitting element L2.

[0140] By sharing the data writing sub-circuit, the first light-emitting control sub-circuit and the data signal line of the driving circuits of two adjacent sub-pixels, on the one hand, the number of data signal lines can be reduced, the wiring space can be saved, and it is conducive to achieving a narrow frame of the display substrate; on the other hand, reducing the number of data signal lines is also conducive to reducing the number of supporting IC chips, which is conducive to reducing costs; at the same time, the adjacent sub-pixel driving circuits share at least some transistors, such as the data writing transistors, which can reduce the number of transistors and the number of vias, which is conducive to improving the yield of the display substrate process section and is also conducive to the layout of subsequent high-resolution products.

[0141] For example, in some embodiments of the present disclosure, with reference to FIG6 and FIG7 , the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit share a data writing sub-circuit 21 and a first light emission control sub-circuit 511. The data writing sub-circuit 21 includes a data writing transistor T4, whose control electrode is coupled to the first scan signal terminal Gate, whose first electrode is coupled to the second node N2, and whose second electrode is coupled to the data signal terminal Data. The first light emission control sub-circuit 511 includes a light emission control transistor T5, whose control electrode is coupled to the light emission control terminal EM, whose first electrode is coupled to the first voltage terminal VDD1, and whose second electrode is coupled to the second node N2.

[0142] For example, continuing to refer to Figures 6 and 7, in the first sub-pixel driving circuit DX1, the first driving sub-circuit 311 includes a first driving transistor T31, the first compensation sub-circuit includes a first compensation transistor T21, the second light-emitting control sub-circuit 512 includes a second light-emitting control transistor T61, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second initialization sub-circuit 712 includes a second initialization transistor T71, and the first storage sub-circuit 611 includes a first capacitor C1.

[0143] In the second sub-pixel driving circuit DX2, the second driving sub-circuit 312 includes a second driving transistor T32, the second compensation sub-circuit 412 includes a second compensation transistor T22, the fourth light-emitting control sub-circuit 514 includes a fourth light-emitting control transistor T62, the third initialization sub-circuit 713 includes a third initialization transistor T12, the fourth initialization sub-circuit 714 includes a fourth initialization transistor T72, and the second storage sub-circuit 612 includes a second capacitor C2.

[0144] The control electrode of the first driving transistor T31 is electrically connected to the first node first subnode N1-1; the first electrode of the first driving transistor T31 is electrically connected to the second node N2; and the second electrode of the first driving transistor T31 is electrically connected to the third node first subnode N3-1.

[0145] The control electrode of the first compensation transistor T21 is electrically connected to the second scan signal terminal Gate1 , the first electrode of the first compensation transistor T21 is electrically connected to the first node first subnode N1 - 1 , and the second electrode of the first compensation transistor T21 is electrically connected to the third node first subnode N3 - 1 .

[0146] The control electrode of the second light-emitting control transistor T61 is electrically connected to the light-emitting control terminal EM, the first electrode of the second light-emitting control transistor T61 is electrically connected to the third node first sub-node N3-1, and the second electrode of the second light-emitting control transistor T61 is electrically connected to the first electrode L11 of the first sub-light-emitting element.

[0147] The control electrode of the first initialization transistor T11 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first initialization transistor T11 is electrically connected to the third node first subnode N3-1, and the second electrode of the first initialization transistor T11 is electrically connected to the first initialization signal terminal Vinit1.

[0148] The control electrode of the second initialization transistor T71 is electrically connected to the second reset signal terminal Reset2, the first electrode of the second initialization transistor T71 is electrically connected to the first electrode L11 of the first sub-light emitting element, and the second electrode of the second initialization transistor T71 is electrically connected to the second initialization signal terminal Vinit2.

[0149] The first capacitor C1 may include a first plate C1a and a second plate C1b. The first plate C1a of the first capacitor C1 is electrically connected to the first electrode of the first light emission control transistor T51, and the second plate C1b is electrically connected to the first node and the first subnode N1-1.

[0150] The control electrode of the second driving transistor T32 is electrically connected to the first node second subnode N1-2; the first electrode of the second driving transistor T32 is electrically connected to the second node N2; and the second electrode of the second driving transistor T32 is electrically connected to the third node second subnode N3-2.

[0151] The control electrode of the second compensation transistor T22 is electrically connected to the third scan signal terminal Gate2, the first electrode of the second compensation transistor T22 is electrically connected to the third node second subnode N3-2, and the second electrode of the second compensation transistor T22 is electrically connected to the first node second subnode N1-2.

[0152] The control electrode of the fourth light-emitting control transistor T62 is electrically connected to the light-emitting control terminal EM, the first electrode of the fourth light-emitting control transistor T62 is electrically connected to the third node second sub-node N3-2, and the second electrode of the fourth light-emitting control transistor T62 is electrically connected to the first electrode L21 of the second sub-light-emitting element.

[0153] The control electrode of the third initialization transistor T12 is electrically connected to the first reset signal terminal Reset1, the first electrode of the third initialization transistor T12 is electrically connected to the first initialization signal terminal Vinit1, and the second electrode of the third initialization transistor T12 is electrically connected to the third node second subnode N3-2.

[0154] The control electrode of the fourth initialization transistor T72 is electrically connected to the second reset signal terminal Reset2, the first electrode of the fourth initialization transistor T72 is electrically connected to the first electrode L21 of the second sub-light emitting element, and the second electrode of the fourth initialization transistor T72 is electrically connected to the second initialization signal terminal Vinit2.

[0155] The second capacitor C2 may include a third plate C2a and a fourth plate C2b. The third plate C2a of the second capacitor C2 is electrically connected to the first electrode of the first light emitting control transistor T5, and the fourth plate C2b is electrically connected to the first node and the second sub-node N1-2.

[0156] FIG. 8 is an operation timing diagram of at least one embodiment of a driving method for the pixel shown in FIG. 7 .

[0157] For example, in some embodiments of the present disclosure, with reference to FIG6 to FIG8 , the pixel circuit may include the following stages when operating, including:

[0158] In the first sub-stage t1-1 of the first time period, in response to the first reset signal Reset1 and the second scan signal Gate1, the first initialization sub-circuit 711 and the first compensation sub-circuit 411 are both turned on, so that the first initialization signal from the first initialization signal terminal Vinit1 is output to the first node and the first sub-node N1-1;

[0159] In the second sub-stage t1-2 of the first time period, in response to the first reset signal Reset1 and the third scan signal Gate3, the third initialization sub-circuit 713 and the second compensation sub-circuit 412 are both turned on, so that the first initialization signal from the first initialization signal terminal Vinit1 is output to the first node second sub-node N1-2.

[0160] The first sub-stage t1-1 of the first time period and the second sub-stage t1-2 of the first time period are in the reset stage of an image frame, the first sub-stage t1-1 of the first time period is before the second sub-stage t1-2 of the first time period, and the first sub-stage t1-1 of the first time period and the second sub-stage t1-2 of the first time period do not overlap.

[0161] Through timing control, the first initialization signal can be sequentially written into the first node, the first subnode N1-1, and the first node, the second subnode N1-2 in different time periods to achieve voltage resetting.

[0162] In the third time period t3, in response to the first scan signal Gate and the second scan signal Gate1, the data writing sub-circuit 21 and the first compensation sub-circuit 411 are both turned on, so that the first sub-data signal DL11 from the data signal terminal Data is transmitted to the first node and the first sub-node N1-1;

[0163] In the fourth time period t4, in response to the first scanning signal Gate and the third scanning signal Gate2, the data writing sub-circuit 21 and the second compensation sub-circuit 412 are both turned on, so that the second sub-data signal DL12 from the data signal terminal Data is transmitted to the first node second sub-node N1-2, wherein the third time period t3 and the fourth time period t4 are in the writing stage of an image frame, the fourth time period t4 is after the third time period t3 and the fourth time period t4 does not overlap with the third time period t3.

[0164] When the data writing subcircuit is turned on, by controlling the first compensation subcircuit 411 and the second compensation subcircuit 412 to be turned on at different time periods, the data signal provided by the same data signal line can be written into the first sub-pixel driving circuit and the second sub-pixel driving circuit in two different time periods. Because the third time period t3 and the fourth time period t4 do not overlap, the data signals of the two sub-pixel driving circuits do not interfere with each other, thereby achieving the purpose of providing data signals to two different sub-pixels. For example, the first sub-data signal DL11 is provided to the first sub-pixel driving circuit during the third time period t3, and the second sub-data signal DL12 is provided to the second sub-pixel driving circuit during the fourth time period t4.

[0165] In the fifth time period, in response to the light-emitting control signal of the light-emitting control terminal, the first light-emitting control sub-circuit 511, the second light-emitting control sub-circuit 512, the third light-emitting control sub-circuit 513 and the fourth light-emitting control sub-circuit 514 are all turned on, and the first sub-light-emitting element L1 and the second sub-light-emitting element L2 emit light.

[0166] FIG9 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG10 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0167] For example, in some embodiments of the present disclosure, referring to FIG. 9 , a first sub-pixel driver circuit and a second sub-pixel driver circuit share a first emission control sub-circuit 511 and a first initialization sub-circuit 711. The first emission control sub-circuit 511 is coupled to a first voltage terminal VDD1, an emission control terminal EM, and a second node N2. The first emission control sub-circuit 511 is configured to write a first voltage received at the first voltage terminal VDD1 to the second node N2 in response to an emission control signal received at the emission control terminal EM. The first sub-pixel driver circuit and the second sub-pixel driver circuit are coupled at a second node N2. The first emission control sub-circuit 511 writes the first voltage to the first sub-pixel driver circuit and the second sub-pixel driver circuit, respectively, via the second node N2. The first initialization sub-circuit 711 is coupled to a first reset signal terminal Reset1, a first initialization signal terminal Vinit1, and a second node N2. The first initialization sub-circuit 711 is configured to transmit a first initialization signal received at the first initialization signal terminal Vinit1 to the second node N2 in response to a first reset signal received at the first reset signal terminal Reset1, thereby initializing the potential of the second node N2.

[0168] The first sub-pixel driving circuit and the second sub-pixel driving circuit share at least a portion of transistors, thereby reducing the number of transistors in the driving circuit, which is beneficial to improving product resolution and yield.

[0169] For example, in some embodiments of the present disclosure, continuing with reference to 9, the first sub-pixel driving circuit may further include a first data writing sub-circuit 211, which is coupled to the data signal terminal Data, the first scan signal terminal Gate and the third node first sub-node N3-1. The first data writing sub-circuit 211 is configured to write the data signal received at the data signal terminal Data to the third node first sub-node N3-1 in response to the first scan signal received at the first scan signal terminal Gate. The second sub-pixel driving circuit may further include a second data writing sub-circuit 212, which is coupled to the data signal terminal Data, the first scan signal terminal Gate, and the third node, the second sub-node N3-2. The second data writing sub-circuit 212 is configured to write a data signal received at the data signal terminal Data into the third node, the second sub-node N3-2, in response to the first scan signal received at the first scan signal terminal Gate. The data signal terminal coupled to the first data writing sub-circuit 211 and the data signal terminal coupled to the second data writing sub-circuit 212 may be coupled to the same data signal line, for example, the first data signal line DL1. In other words, the first sub-pixel driving circuit and the second sub-pixel driving circuit may share a data signal line. This reduces the number of data signal lines, saves wiring space and IC chips, achieves a narrow frame for the display substrate, and reduces costs.

[0170] 9 , the first sub-pixel driving circuit includes: a first storage sub-circuit 611, a first compensation sub-circuit 411, and a first driver sub-circuit 311. The first storage sub-circuit 611 is coupled to the first node, the first sub-node N1-1, and the first voltage terminal VDD1. The first compensation sub-circuit 411 is coupled to the second scan signal terminal Gate1, the first node, the first sub-node N1-1, and the second node N2. The first compensation sub-circuit 411 is configured to transmit a first sub-data signal from the data signal terminal Data to the first node, the first sub-node N1-1, in response to a second scan signal received at the second scan signal terminal Gate1. The first driver sub-circuit 311 is coupled to the first node, the first sub-node N1-1, the second node N2, and the third node, the first sub-node N3-1. The second sub-pixel driving circuit includes: a second storage sub-circuit 612, a second compensation sub-circuit 412, and a second driver sub-circuit 312. Among them, the second storage sub-circuit 612 is coupled to the first node second sub-node N1-2 and the first voltage terminal VDD1, that is, the first storage sub-circuit 611 and the second storage sub-circuit 612 are coupled at the first voltage terminal VDD1; the second compensation sub-circuit 412 is coupled to the third scan signal terminal Gate2, the first node second sub-node N1-2 and the second node N2, and the second compensation sub-circuit 412 is configured to respond to the third scan signal received at the third scan signal terminal Gate2, and transmit the second sub-data signal from the data signal terminal Data to the first node second sub-node N1-2; the second driving sub-circuit 312 is coupled to the first node second sub-node N1-2, the second node N2 and the third node second sub-node N3-2, and the second driving sub-circuit 312 is configured to generate a second driving current in response to the voltage of the first node second sub-node N1-2, wherein the second driving current is used to drive the second sub-light-emitting element to emit light.

[0171] Illustratively, the first sub-pixel driving circuit may further include a second light-emitting control sub-circuit 512 and a second initialization sub-circuit 712. The second light-emitting control sub-circuit 512 is coupled to the light-emitting control terminal EM, the third node, the first sub-node N3-1, and the first electrode L11 of the first sub-light-emitting element; the second initialization sub-circuit 712 is coupled to the second reset signal terminal Reset2, the first electrode L11 of the first sub-light-emitting element, and the second initialization signal terminal Vinit2. The second sub-pixel driving circuit may further include a fourth light-emitting control sub-circuit 514 and a fourth initialization sub-circuit 714. The fourth light-emitting control sub-circuit 514 is coupled to the light-emitting control terminal EM, the third node, the second sub-node N3-2, and the first electrode L21 of the second sub-light-emitting element; the fourth initialization sub-circuit 714 is coupled to the second reset signal terminal Reset2, the first electrode L21 of the second sub-light-emitting element, and the second initialization signal terminal Vinit2.

[0172] For example, in some embodiments of the present disclosure, referring to FIG10 , the first light-emitting control subcircuit 511 includes a light-emitting control transistor T5, the control electrode of the light-emitting control transistor T5 is coupled to the light-emitting control terminal EM, the first electrode of the light-emitting control transistor T5 is coupled to the first voltage terminal VDD 1, and the second electrode of the light-emitting control transistor T5 is coupled to the second node N2.

[0173] The first initialization sub-circuit 711 includes an initialization transistor T1 , a control electrode of the initialization transistor T1 coupled to the first reset signal terminal Reset1 , a first electrode of the initialization transistor T1 coupled to the second node N2 , and a second electrode of the initialization transistor T1 coupled to the first initialization signal terminal Vinit1 .

[0174] The first data write sub-circuit 211 includes a first data write transistor T41, and the second data write sub-circuit 212 includes a second data write transistor T42, wherein the control electrode of the first data write transistor T41 is coupled to the first scan signal terminal Gate, the first electrode of the first data write transistor T41 is coupled to the third node first sub-node N3-1, the second electrode of the first data write transistor T41 is coupled to the first electrode of the second data write transistor T42, the control electrode of the second data write transistor T42 is coupled to the first scan signal terminal Gate, and the second electrode of the second data write transistor T42 is coupled to the third node second sub-node N3-2.

[0175] Exemplarily, the first storage sub-circuit 611 may further include a first capacitor C1, the first compensation sub-circuit 411 may further include a first compensation transistor T21, the first driving sub-circuit 311 may further include a first driving transistor T31, the second light-emitting control sub-circuit 512 may further include a second light-emitting control transistor T61, and the second initialization sub-circuit 712 may further include a second initialization transistor T71.

[0176] Exemplarily, the second storage sub-circuit 612 may further include a second capacitor C2, the second compensation sub-circuit 412 may further include a second compensation transistor T22, the second driving sub-circuit 312 may further include a second driving transistor T32, the fourth light-emitting control sub-circuit 514 may further include a fourth light-emitting control transistor T62, and the fourth initialization sub-circuit 714 may further include a fourth initialization transistor T72.

[0177] For example, in some embodiments of the present disclosure, the timing of the equivalent circuit diagram in FIG10 may be the same as the timing in FIG8 , and will not be described in detail here.

[0178] FIG11 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG12 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0179] For example, in some embodiments of the present disclosure, referring to FIG. 11 , the first sub-pixel driving circuit and the second sub-pixel driving circuit share a first light-emission control sub-circuit 511 and a second reference voltage writing sub-circuit 81. The first light-emission control sub-circuit 511 is coupled to the first voltage terminal VDD1, the light-emission control terminal EM, and the second node N2. The first light-emission control sub-circuit 511 is configured to write a first voltage received at the first voltage terminal VDD to the second node N2 in response to a light-emission control signal received at the light-emission control terminal EM. The second reference voltage writing sub-circuit 81 is coupled to the second reset signal terminal Reset2, the second reference voltage terminal Vref2, and the second node N2. The second reference voltage writing sub-circuit 81 is configured to write a second reference voltage received at the second reference voltage terminal Vref2 to the second node N2 in response to a second reset signal received at the second reset signal terminal Reset2.

[0180] For example, with continued reference to FIG. 11 , the first sub-pixel driving circuit further includes: a first data writing sub-circuit 211, a first storage sub-circuit 611, and a third storage sub-circuit 613. The first data writing sub-circuit 211 is coupled to the data signal terminal Data, the second scan signal terminal Gate1, and the fourth node first sub-node N4-1. The first data writing sub-circuit 211 is configured to write a data signal received at the data signal terminal Data to the fourth node first sub-node N4-1 in response to a second scan signal received at the second scan signal terminal Gate1. The first storage sub-circuit 611 is coupled to the first node first sub-node N1-1 and the fourth node first sub-node N4-1. The third storage sub-circuit 613 is coupled to the fourth node first sub-node N4-1 and the first voltage terminal VDD1. The second sub-pixel driving circuit further includes: a second data writing sub-circuit 212, a second storage sub-circuit 612, and a fourth storage sub-circuit 614. Among them, the second data writing sub-circuit 212 is coupled to the data signal terminal Data, the third scan signal terminal Gate2 and the fourth node second sub-node N4-2, and the second data writing sub-circuit 212 is configured to respond to the third scan signal received at the third scan signal terminal Gate2, and write the data signal received at the data signal terminal Data into the fourth node second sub-node N4-2; the second storage sub-circuit 612 is coupled to the first node second sub-node N1-2 and the fourth node second sub-node N4-2; the fourth storage sub-circuit 614 is coupled to the fourth node second sub-node N4-2 and the first voltage terminal VDD1.

[0181] For example, the first data writing sub-circuit 211 and the second data writing sub-circuit 212 share the same data line, thereby reducing the number of data signal lines, facilitating narrow frame, reducing the number of driver ICs, and lowering costs.

[0182] The pixel driving circuit also includes a first reference voltage first sub-circuit 911 and a first reference voltage second sub-circuit 912, wherein the first reference voltage first sub-circuit 911 is coupled to the fourth node first sub-node N4-1, the first reset signal terminal Reset1 and the first reference voltage signal terminal Vref1, and the first reference voltage first write sub-circuit 911 is configured to write the first reference voltage received at the first reference voltage signal terminal Vref1 to the fourth node first sub-node N4-1 in response to the first reset signal received at the first reset signal terminal Reset1; the first reference voltage second sub-circuit 912 is coupled to the fourth node second sub-node N4-2, the first reset signal terminal Reset1 and the first reference voltage signal terminal Vref1, and the first reference voltage second sub-circuit 912 is configured to write the first reference voltage received at the first reference voltage signal terminal Vref1 to the fourth node second sub-node N4-2 in response to the first reset signal received at the first reset signal terminal Reset1.

[0183] Exemplarily, the first sub-pixel driving circuit may further include a first compensation sub-circuit 411, a first driving sub-circuit 311, a first initialization sub-circuit 711, and a second light-emitting control sub-circuit 512. The first compensation sub-circuit 411 is coupled to the first scan signal terminal Gate, the first node (first sub-node N1-1), and the third node (first sub-node N3-1); the first driving sub-circuit 311 is coupled to the first node (first sub-node N1-1), the second node N2, and the third node (first sub-node N3-1); the first initialization sub-circuit 711 is coupled to the first reset signal terminal Reset1, the third node (first sub-node N3-1), and the first initialization signal terminal Vinit1; and the second light-emitting control sub-circuit 512 is coupled to the light-emitting control terminal EM, the third node (first sub-node N3-1), and the first electrode L11 of the first sub-light-emitting element.

[0184] The second sub-pixel driving circuit DX2 may further include a second compensation sub-circuit 412, a second driving sub-circuit 312, a third initialization sub-circuit 713, and a fourth light-emitting control sub-circuit 514. The second compensation sub-circuit 412 is coupled to the first scan signal terminal Gate, the first node second sub-node N1-2, and the third node second sub-node N3-2; the second driving sub-circuit 312 is coupled to the first node second sub-node N1-2, the second node N2, and the third node second sub-node N3-2; the third initialization sub-circuit 713 is coupled to the first reset signal terminal Reset1, the third node second sub-node N3-2, and the first initialization signal terminal Vinit1; and the fourth light-emitting control sub-circuit 514 is coupled to the light-emitting control terminal EM, the third node second sub-node N3-2, and the first electrode L21 of the second sub-light-emitting element.

[0185] For example, with reference to Figures 11 and 12, the first light-emitting control sub-circuit 511 includes a light-emitting control transistor T5, the second reference voltage writing sub-circuit 81 includes a second reference voltage writing transistor T9, the first data writing sub-circuit 211 includes a first data writing transistor T41, the first storage sub-circuit 611 includes a first capacitor C1, the third storage sub-circuit 613 includes a third capacitor C3, the first reference voltage first sub-circuit 911 includes a first reference voltage first sub-transistor T81, and the first reference voltage second writing sub-circuit 912 includes a first reference voltage second sub-transistor T 82, the first compensation sub-circuit 411 includes a first compensation transistor T21, the first driving sub-circuit 311 includes a first driving transistor T31, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second light-emitting control sub-circuit 512 includes a second light-emitting control transistor T61, the second compensation sub-circuit 412 includes a second compensation transistor T22, the second driving sub-circuit 312 includes a second driving transistor T32, the third initialization sub-circuit 713 includes a third initialization transistor T12, and the fourth light-emitting control sub-circuit 514 includes a fourth light-emitting control transistor T62.

[0186] Exemplarily, a control electrode of the first reference voltage first sub-transistor T81 is coupled to the first reset signal terminal Reset1, a first electrode of the first reference voltage first sub-transistor T81 is coupled to the fourth node first sub-node N4-1, and a second electrode of the first reference voltage first sub-transistor T81 is coupled to the first reference voltage line Vref1. A control electrode of the first reference voltage second sub-transistor T82 is coupled to the first reset signal terminal Reset1, a first electrode of the first reference voltage second sub-transistor T82 is coupled to the first reference voltage line Vref1, and a second electrode of the first reference voltage second sub-transistor T82 is coupled to the fourth node second sub-node N4-2.

[0187] FIG. 13 is an operation timing diagram of at least one embodiment of a driving method for the pixel shown in FIG. 12 .

[0188] For example, in some embodiments of the present disclosure, with reference to FIG. 11 to FIG. 13 , the pixel circuit may include the following stages when operating, including:

[0189] In the first time period t1, in response to the first scan signal provided by the first scan signal terminal Gate and the first reset signal provided by the first reset signal terminal Reset1, the first initialization sub-circuit 711 and the first compensation sub-circuit 411, the third initialization sub-circuit 713 and the second compensation sub-circuit 412, the first reference voltage first sub-circuit 911 and the first reference voltage second sub-circuit 912 are all turned on to charge the first node first sub-node N1-1 and the first node second sub-node N1-2.

[0190] In the second time period t2, in response to the second reset signal of the second reset signal terminal Reset2 and the first scan signal provided by the first scan signal terminal Gate, the second reference voltage writing sub-circuit 81, the first compensation sub-circuit 411 and the second compensation sub-circuit 412 are all turned on, so that the second reference voltage from the second reference voltage line Vref2 is transmitted to the first node first sub-node N1-1 and the first node second sub-node N1-2 respectively.

[0191] In the third time period t3, in response to the second scan signal of the second scan signal terminal Gate1, the first data writing sub-circuit 211 is turned on, so that the data signal from the data signal line is transmitted to the fourth node first sub-node N4-1; the data signal is written into the first node first sub-node N1-1 by utilizing the bootstrap effect of the capacitor (that is, the voltage across the capacitor cannot suddenly change, and when the voltage at one end increases, the other end still maintains the voltage difference between the other end and the previous end).

[0192] In the fourth time period t4, in response to the third scan signal of the third scan signal terminal Gate2, the second data writing sub-circuit 212 is turned on, so that the data signal from the data signal line is transmitted to the fourth node second sub-node N4-2; the data signal is written into the first node second sub-node N1-2 using the bootstrap effect of the capacitor.

[0193] In the fifth time period, in response to the light control signal of the light control terminal, the first light control subcircuit 511, the second light control subcircuit 512 and the fourth light control subcircuit 514 are all turned on, and the first sub-light emitting element L1 and the second sub-light emitting element L2 emit light.

[0194] By utilizing a voltage-jump data signal writing method, data signals can be written to the first node first subnode N1-1 and the first node second subnode N1-2 instantly, thereby improving the situation where the display substrate is insufficiently charged, for example, improving the problem of insufficient charging time caused by an increase in the driving frequency of a high-resolution display substrate.

[0195] FIG. 14 is a schematic structural diagram of a display substrate according to some exemplary embodiments of the present disclosure.

[0196] 14 , the present disclosure illustratively provides a display substrate 1100, including a base substrate 1; a pixel circuit DX disposed on the base substrate 1, wherein the pixel circuit DX includes a first sub-pixel driving circuit DX1 and a second sub-pixel driving circuit DX2; and light-emitting elements L disposed on the base substrate, wherein the light-emitting elements include a first sub-light-emitting element L1 and a second sub-light-emitting element L2, wherein the first sub-light-emitting element L1 is coupled to the first sub-pixel driving circuit DX1, and the second sub-light-emitting element L2 is coupled to the second sub-pixel driving circuit DX2. The first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 may share a data signal line.

[0197] Figure 15A is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 15B is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 15C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 15D is a schematic diagram showing a partial via according to an exemplary embodiment of the present disclosure; Figure 15E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 15F is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 16A is a schematic diagram showing the planar structure of the combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 16B is a partial cross-sectional schematic diagram of the pixel circuit according to an embodiment of the present disclosure taken along the center line AA' of Figure 16A.

[0198] Exemplarily, in combination with reference to Figure 1 and Figures 15A to 16A, in some embodiments of the present disclosure, the display substrate 1100 includes a base substrate 1; a plurality of sub-pixels SP provided on the base substrate 1, the plurality of sub-pixels SP are arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits DX, the plurality of pixel circuits DX are used to drive the plurality of sub-pixels SP, wherein the plurality of sub-pixels SP include a first sub-pixel SP1 and a second sub-pixel SP2, the first sub-pixel SP1 and the second sub-pixel SP2 are two adjacent sub-pixels in the first direction or the second direction, the plurality of pixel circuits DX include a first sub-pixel driving circuit DX1 for driving the first sub-pixel SP1 and a second sub-pixel driving circuit DX2 for driving the second sub-pixel SP2, and the first direction and the second direction intersect.

[0199] Referring to Figure 16B, the display substrate 1100 includes: a first semiconductor layer 2 arranged on the base substrate 1; a first conductive layer 3 arranged on the side of the first semiconductor layer 2 away from the base substrate 1; a second conductive layer 4 arranged on the side of the first conductive layer 3 away from the base substrate 1; a third conductive layer 5 arranged on the side of the second conductive layer 4 away from the base substrate 1; and a fourth conductive layer 6 arranged on the side of the third conductive layer 4 away from the base substrate 1.

[0200] The display substrate 110 further includes first scan signal lines Gate extending along the first direction D1 and data signal lines DL extending along the second direction D2 . The first scan signal lines Gate are located in the first conductive layer 3 , and the data signal lines DL are located in the fourth conductive layer 6 .

[0201] Exemplarily, the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a data writing sub-circuit 21 and a data signal line DL, the data writing sub-circuit 21 includes a data writing transistor T4, the data writing transistor T4 includes a data writing active layer ACT4, a control electrode G4 and a second electrode S4, the data writing active layer ACT4 is located in the first semiconductor layer 2, and the second electrode S4 is located in the third conductive layer 5.

[0202] The orthographic projection of the data write active layer ACT4 on the base substrate 1 at least partially overlaps with the orthographic projection of the first scan signal line Gate on the base substrate 1. The overlapping portion of the first scan signal line Gate and the data write active layer ACT4 serves as the control electrode G4 of the data write transistor 21. The second electrode S4 of the data write transistor is electrically connected to the data signal line DL via a first via VH1. The second electrode S4 of the data write transistor is electrically connected to the second electrode region of the data write active layer ACT4 via a nineteenth via VH19.

[0203] By designing adjacent sub-pixels to share data signal lines and data write transistors, wiring space can be saved, facilitating narrow bezels, reducing IC chips, and lowering costs. Sharing at least some transistors can also reduce the number of transistors and vias on the display substrate, improving the display substrate's yield and facilitating the subsequent development of high-resolution products.

[0204] The first sub-pixel driving circuit DX1 further includes a first driving sub-circuit 311, a first compensation sub-circuit 411, a first light emission control sub-circuit 511, a first storage sub-circuit 611, a first initialization sub-circuit 711, a second initialization sub-circuit 712, and a second light emission control sub-circuit 512. The first driving sub-circuit 311 includes a first driving transistor T31, the first compensation sub-circuit 411 includes a first compensation transistor T21, the first light emission control sub-circuit 511 includes a first light emission control transistor T51, the first storage sub-circuit 611 includes a first capacitor C1, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second initialization sub-circuit 712 includes a second initialization transistor T71, and the second light emission control sub-circuit 512 includes a second light emission control transistor T61.

[0205] The second sub-pixel driving circuit DX2 further includes a second driving sub-circuit 312, a second compensation sub-circuit 412, a third emission control sub-circuit 513, a second storage sub-circuit 612, a third initialization sub-circuit 713, a fourth initialization sub-circuit 714, and a fourth emission control sub-circuit 514. The second driving sub-circuit 312 includes a second driving transistor T32, the second compensation sub-circuit 412 includes a second compensation transistor T22, the third emission control sub-circuit 513 includes a third emission control transistor T52, the second storage sub-circuit 611 includes a second capacitor C2, the third initialization sub-circuit 713 includes a third initialization transistor T12, the fourth initialization sub-circuit 714 includes a fourth initialization transistor T72, and the fourth emission control sub-circuit 514 includes a fourth emission control transistor T62.

[0206] For example, multiple transistors in the first sub-pixel driving circuit DX1 and multiple transistors in the second sub-pixel driving circuit DX2 can be mirrored on the left and right sides of the data signal line. It should be noted that although this embodiment shows that adjacent sub-pixel driving circuits are mirrored on the left and right sides, the embodiments of the present disclosure are not limited thereto, and adjacent sub-pixel driving circuits can also be mirrored on the top and bottom sides.

[0207] For example, the plurality of transistors may include an active layer ACT, and the active layer ACT may be located in the first semiconductor layer 2. The orthographic projection of the active layer ACT on the substrate at least partially overlaps with the orthographic projection of the first conductive layer 2 on the substrate, and the overlapping portion of the active layer ACT and the first conductive layer 2 may form control electrodes of the plurality of transistors.

[0208] For example, the first driving transistor T31 includes a first driving active layer ACT31, and the second driving transistor T32 includes a second driving active layer ACT32. The first driving active layer ACT31 and the second driving active layer ACT32 extend in a straight line in the first direction respectively, and the first driving active layer ACT31 and the second driving active layer ACT32 are symmetrical about the data signal line DL.

[0209] Exemplarily, the first emission control transistor T51 includes a first emission control active layer ACT51, and the third emission control transistor T52 includes a third emission control active layer ACT52. At least a portion of the first emission control active layer ACT51 and the third emission control active layer ACT52 can be located on both sides of the data signal line.

[0210] Exemplarily, the data writing active layer ACT4 , the first driving active layer ACT31 , the second driving active layer ACT32 , the first light emission control active layer ACT51 , and the third light emission control active layer ACT52 may intersect at the second node N2 .

[0211] The display substrate may further include a second scan signal line Gate1, a third scan signal line Gate2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reset signal line Reset1, a second reset signal line Reset2, and an emission control line EM extending along the first direction, as well as a first power line VDD1 and a second power line VDD2 extending along the second direction. The second scan signal line Gate1, the third scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the emission control line EM are located in the first conductive layer 3, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the third conductive layer 5, and the first power line VDD1 and the second power line VDD2 are located in the fourth conductive layer 6. The data signal line DL may be located between the first power line VDD1 and the second power line VDD2.

[0212] Exemplarily, the first capacitor C1 may include a first plate C1a and a second plate C1b, and the second capacitor C2 includes a third plate C2a and a fourth plate C2b, wherein the first plate C1a and the third plate C2a are located in the first conductive layer 3, and the first plate C1a and the third plate C2a are spaced apart in the first direction; the second plate C1b and the fourth plate C2b are located in the second conductive layer 4, and the second plate C1b and the fourth plate C2b are electrically connected.

[0213] The following describes the connection method of the multiple transistors by taking the multiple transistors in the first sub-pixel driving circuit as an example.

[0214] Exemplarily, the first initialization transistor T11 may include a first initialization active layer ACT11, a control electrode G11, a first electrode D11, and a second electrode S11. The first initialization active layer ACT11 extends along the second direction. The portion where the first initialization active layer ACT11 overlaps with the first reset signal line Reset1 serves as the control electrode G11 of the first initialization transistor T11. The first electrode D11 of the first initialization transistor T11 is electrically connected to the first initialization signal line Vinit1 via a tenth via VH10.

[0215] Exemplarily, the first compensation transistor T21 may include a first compensation active layer ACT21, a control electrode G21, a first electrode D21, and a second electrode S21. The first compensation active layer ACT21 extends along a first direction. The portion where the first compensation active layer ACT21 overlaps with the second scan signal line Gate1 serves as the control electrode G21 of the first compensation transistor T21. The first electrode D21 of the first compensation transistor T21 and the second electrode S11 of the first initialization transistor T11 are electrically connected to the third node, the first subnode N3-1, via an eleventh via VH11, a twelfth via VH12, and a sixth conductive transition portion m6. The second electrode S21 of the first compensation transistor T21 is electrically connected to the first node, the first subnode N1-1, via a fifteenth via VH15, a sixteenth via VH16, and a third conductive transition portion m3. The third conductive transition portion m3 is located in the third conductive layer 5.

[0216] The first driving transistor T31 also includes a control electrode G31, a first electrode D31 and a second electrode S31. The portion where the active layer ACT31 of the first driving transistor T31 overlaps with the first electrode plate C1a is the control electrode of the first driving transistor T31. The first electrode D31 of the first driving transistor T31 is electrically connected to the second node N2, and the second electrode S31 of the first driving transistor T31 is electrically connected to the third node first subnode N3-1.

[0217] The data writing transistor T4 further includes a first electrode D4 , and the first electrode D4 of the data writing transistor T4 is electrically connected to the second node N2 .

[0218] The first light-emitting control transistor T51 also includes a control electrode G51, a first electrode D51, and a second electrode S51. The portion where the active layer ACT51 of the first light-emitting control transistor T51 overlaps with the light-emitting control line EM is the control electrode G51 of the first light-emitting control transistor T51. The first electrode D51 of the first light-emitting control transistor T51 is electrically connected to the first power line VDD1 through the second via VH2, the seventeenth via VH17, and the first conductive transition portion m1. The first electrode D51 of the first light-emitting control transistor T51 can also be electrically connected to the second electrode plate C1b through the eighteenth via VH18. The second electrode S51 of the first light-emitting control transistor T51 is electrically connected to the second node N2.

[0219] The second light-emitting control transistor T61 also includes an active layer ACT61, a control electrode G61, a first electrode D61 and a second electrode S61. The portion where the active layer ACT61 of the second light-emitting control transistor T61 overlaps with the light-emitting control line EM is the control electrode of the second light-emitting control transistor T61. The first electrode D61 of the second light-emitting control transistor T61 is electrically connected to the third node and the first sub-node N3-1 through the twelfth via VH12. The second electrode S61 of the second light-emitting control transistor T61 is electrically connected to the first electrode L11 of the first sub-light-emitting element through the thirteenth via VH13 and the seventh wire transfer portion m7.

[0220] The second initialization transistor T71 also includes an active layer ACT71, a control electrode G71, a first electrode D71 and a second electrode S71. The part where the active layer ACT71 of the second initialization transistor T71 overlaps with the second reset signal line Reset2 is the control electrode G71 of the second initialization transistor T71. The first electrode D71 of the second initialization transistor T71 is electrically connected to the first electrode L11 of the first sub-light-emitting element through the thirteenth via VH13 and the seventh wire transfer portion m7. The second electrode S71 of the second initialization transistor T71 is electrically connected to the second initialization signal line Vinit2 through the fourteenth via VH14.

[0221] For example, the connection manner of the corresponding transistors in the second sub-pixel driving circuit may be the same as the connection manner of the corresponding transistors in the first sub-pixel driving circuit, which will not be described in detail here.

[0222] It should be noted that although the pixel circuit shown in the embodiment of the present disclosure is a 7T1C driving circuit, the present disclosure is not limited thereto and the embodiments of the present disclosure are also applicable to various other known driving circuits, such as 3T1C, 5T1C, 5T2C, 8T2C and other driving circuits.

[0223] Figure 17A is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 17B is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 17C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 17D is a schematic diagram showing a partial via according to an exemplary embodiment of the present disclosure; Figure 17E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 17F is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 18 is a schematic diagram showing the planar structure of the combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure.

[0224] For example, in some embodiments of the present disclosure, referring to FIG. 1 and FIG. 17A-FIG . 18 , the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a data writing sub-circuit, a data signal line DL and a first light emitting control sub-circuit.

[0225] The display substrate 1100 includes: a first semiconductor layer 2 arranged on a base substrate 1; a first conductive layer 3 arranged on a side of the first semiconductor layer 2 away from the base substrate 1; a second conductive layer 4 arranged on a side of the first conductive layer 3 away from the base substrate 1; a third conductive layer 5 arranged on a side of the second conductive layer 4 away from the base substrate 1; and a fourth conductive layer 6 arranged on a side of the third conductive layer 4 away from the base substrate 1.

[0226] The display substrate may further include a first scan signal line Gate, a second scan signal line Gate1, a third scan signal line Gate2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reset signal line Reset1, a second reset signal line Reset2, and an emission control line EM extending along a first direction, and a first power line VDD1 and a data signal line DL extending along a second direction. The first scan signal line Gate, the second scan signal line Gate1, the third scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the emission control line EM are located in the first conductive layer 3, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the third conductive layer 5, and the first power line VDD1 and the data signal line DL are located in the fourth conductive layer 6.

[0227] The data write sub-circuit includes a data write transistor T4, which includes a data write active layer ACT4, a control electrode G4, and a second electrode S4. The data write active layer ACT4 is located in the first semiconductor layer 2, and the second electrode S4 is located in the third conductive layer 5. The orthographic projection of the data write active layer ACT4 on the base substrate 1 at least partially overlaps with the orthographic projection of the first scan signal line Gate on the base substrate 1. The overlapping portion between the first scan signal line Gate and the data write active layer ACT4 serves as the control electrode G4 of the data write transistor 21. The second electrode S4 of the data write transistor is electrically connected to the data signal line DL via a first via VH1. The second electrode S4 of the data write transistor is electrically connected to the second electrode region of the data write active layer ACT4 via a nineteenth via VH19.

[0228] The first light-emission control subcircuit 511 includes a light-emission control transistor T5, which includes a light-emission control active layer ACT5, a control electrode G5, and a first electrode D5. The light-emission control active layer ACT5 is located in the first semiconductor layer 2, and the first electrode D5 of the light-emission control transistor is located in the third conductive layer 5. The display substrate also includes a light-emission control line EM extending along a first direction. The orthographic projection of the light-emission control active layer ACT5 on the base substrate at least partially overlaps with the orthographic projection of the light-emission control line EM on the base substrate. The overlapping portion of the light-emission active layer ACT5 and the light-emission control line EM serves as the control electrode of the light-emission control transistor T5.

[0229] Exemplarily, the data writing active layer ACT4 and the light emitting control active layer ACT5 extend continuously in the second direction D2; the orthographic projections of both the data writing active layer ACT4 and the light emitting control active layer ACT5 on the substrate at least partially overlap with the orthographic projection of the data signal line DL on the substrate; or, the orthographic projections of both the data writing active layer ACT4 and the light emitting control active layer ACT5 on the substrate fall within the orthographic projection of the data signal line DL on the substrate.

[0230] By designing adjacent sub-pixels to share data signal lines, data write transistors, and the first light-emission control transistor, wiring space can be saved, facilitating narrow bezels, reducing IC chips, and lowering costs. Sharing at least a portion of the transistors also reduces the number of transistors and vias on the display substrate, improving the yield of the display substrate and facilitating the subsequent development of high-resolution products.

[0231] The display substrate further includes a first conductive transition portion m1, which is located in the third conductive layer 5. The first electrode D5 of the first light-emitting control transistor is electrically connected to the first power line VDD1 through the first conductive transition portion m1.

[0232] Among them, the first power line VDD1 includes a first power sub-line VDD11 and a second power sub-line VDD12, the first power sub-line VDD11 and the second power sub-line VDD12 are spaced apart in the first direction and extend along the second direction, the first conductive transition portion m1 is electrically connected to the first power sub-line VDD11 through the second via VH2; and the first conductive transition portion m1 is electrically connected to the second power sub-line VDD12 through the third via VH3.

[0233] The first conductive transition portion m1 includes a first conductive transition sub-portion m11 and a second conductive transition sub-portion m12, the first conductive transition sub-portion m11 extends along the second direction, and the second conductive transition sub-portion m12 extends along the first direction, wherein the orthographic projection of the first conductive transition sub-portion m11 on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control active layer ACT5 on the base substrate; the orthographic projection of the second via VH2 on the base substrate falls within the orthographic projection of the first end of the second conductive transition sub-portion m12 on the base substrate, and the orthographic projection of the third via VH3 on the base substrate falls within the orthographic projection of the second end of the second conductive transition sub-portion m12 on the base substrate.

[0234] Exemplarily, the orthographic projection of the data signal line DL on the base substrate falls into a gap between the orthographic projections of the first power sub-line VDD11 and the second power sub-line VDD12 on the base substrate.

[0235] The first sub-pixel driving circuit DX1 further includes a first driving sub-circuit 311, a first compensation sub-circuit 411, a first storage sub-circuit 611, a first initialization sub-circuit 711, a second initialization sub-circuit 712, and a second emission control sub-circuit 512. The first driving sub-circuit 311 includes a first driving transistor T31, the first compensation sub-circuit 411 includes a first compensation transistor T21, the first storage sub-circuit 611 includes a first capacitor C1, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second initialization sub-circuit 712 includes a second initialization transistor T71, and the second emission control sub-circuit 512 includes a second emission control transistor T61.

[0236] The second sub-pixel driving circuit DX2 further includes a second driving sub-circuit 312, a second compensation sub-circuit 412, a second storage sub-circuit 612, a third initialization sub-circuit 713, a fourth initialization sub-circuit 714, and a fourth light emission control sub-circuit 514. The second driving sub-circuit 312 includes a second driving transistor T32, the second compensation sub-circuit 412 includes a second compensation transistor T22, the second storage sub-circuit 611 includes a second capacitor C2, the third initialization sub-circuit 713 includes a third initialization transistor T12, the fourth initialization sub-circuit 714 includes a fourth initialization transistor T72, and the fourth light emission control sub-circuit 514 includes a fourth light emission control transistor T62.

[0237] Exemplarily, the first driving transistor T31 includes a first driving active layer ACT31 , and the second driving transistor T32 includes a second driving active layer ACT32 . The first driving active layer ACT31 and the second driving active layer ACT32 extend in a zigzag shape.

[0238] For example, the settings of the first driving transistor T31, the first compensation transistor T21, the first capacitor C1, the first initialization transistor T11, the second initialization transistor T71, the second light-emitting control transistor T61, the second driving transistor T32, the second compensation transistor T22, the second capacitor C2, the third initialization transistor T12, the fourth initialization transistor T72 and the fourth light-emitting control transistor T62 in the display substrate of the embodiment of Figure 18 can be the same as the settings of the corresponding transistors and capacitors of the display substrate of the embodiment of Figure 16A, and are not repeated here.

[0239] Figure 19A is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 19B is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 19C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 19D is a schematic diagram showing a partial via according to an exemplary embodiment of the present disclosure; Figure 19E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 19F is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 20 is a schematic diagram showing the planar structure of the combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure.

[0240] For example, in some embodiments of the present disclosure, referring to FIG. 1 and FIG. 19A-FIG . 20 , the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a data writing sub-circuit 21 , a data signal line DL and a first light emitting control sub-circuit 511 .

[0241] The display substrate 1100 includes: a first semiconductor layer 2 arranged on a base substrate 1; a first conductive layer 3 arranged on a side of the first semiconductor layer 2 away from the base substrate 1; a second conductive layer 4 arranged on a side of the first conductive layer 3 away from the base substrate 1; a third conductive layer 5 arranged on a side of the second conductive layer 4 away from the base substrate 1; and a fourth conductive layer 6 arranged on a side of the third conductive layer 4 away from the base substrate 1.

[0242] The display substrate may further include a first scan signal line Gate, a second scan signal line Gate1, a third scan signal line Gate2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reset signal line Reset1, a second reset signal line Reset2, and an emission control line EM extending along a first direction, and a first power line VDD1 and a data signal line DL extending along a second direction. The first scan signal line Gate, the second scan signal line Gate1, the third scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the emission control line EM are located in the first conductive layer 3, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the third conductive layer 5, and the first power line VDD1 and the data signal line DL are located in the fourth conductive layer 6.

[0243] The data write sub-circuit 21 includes a data write transistor T4, which includes a data write active layer ACT4, a control electrode G4, and a second electrode S4. The data write active layer ACT4 is located in the first semiconductor layer 2, and the second electrode S4 is located in the third conductive layer 5. The orthographic projection of the data write active layer ACT4 on the base substrate 1 at least partially overlaps with the orthographic projection of the first scan signal line Gate on the base substrate 1. The overlapping portion between the first scan signal line Gate and the data write active layer ACT4 serves as the control electrode G4 of the data write transistor 21. The orthographic projection of the data write active layer ACT4 on the base substrate may not overlap with the orthographic projection of the data signal line on the base substrate. The second electrode S4 of the data write transistor is electrically connected to the data signal line DL via the second conductive transition portion m2 and the first via VH1.

[0244] The first light-emission control subcircuit 511 includes a light-emission control transistor T5, which includes a light-emission control active layer ACT5, a control electrode G5, and a first electrode D5. The light-emission control active layer ACT5 is located in the first semiconductor layer 2, and the first electrode D5 of the light-emission control transistor is located in the third conductive layer 5. The display substrate also includes a light-emission control line EM extending along a first direction. The orthographic projection of the light-emission control active layer ACT5 on the base substrate at least partially overlaps with the orthographic projection of the light-emission control line EM on the base substrate. The overlapping portion of the light-emission active layer ACT5 and the light-emission control line EM serves as the control electrode of the light-emission control transistor T5.

[0245] By designing adjacent sub-pixels to share data signal lines, data write transistors, and the first light-emission control transistor, wiring space can be saved, facilitating narrow bezels, reducing IC chips, and lowering costs. Sharing at least a portion of the transistors also reduces the number of transistors and vias on the display substrate, improving the yield of the display substrate and facilitating the subsequent development of high-resolution products.

[0246] Exemplarily, the first sub-pixel driving circuit DX1 includes a first driving sub-circuit 311, the first driving sub-circuit 311 includes a first driving transistor T31, the first driving transistor T31 includes a first driving active layer ACT31, the second sub-pixel driving circuit DX2 includes a second driving sub-circuit 312, the second driving sub-circuit 312 includes a second driving transistor T32, the second driving transistor T32 includes a second driving active layer ACT32, wherein the first driving active layer ACT31 extends in a straight line along the first direction, the second driving active layer ACT32 extends in a straight line along the first direction, and the first driving active layer ACT31 and the second driving active layer ACT32 are spaced apart in the second direction.

[0247] Illustratively, the data writing active layer ACT4 , the light emission control active layer ACT5 , the first driving active layer ACT31 , and the second driving active layer ACT32 are electrically connected to one another.

[0248] By adopting a straight-line design for the active layer of the driving transistor, the length and width consistency of each driving transistor can be ensured, which is beneficial to improving the performance consistency of the driving transistor and thus improving the grayscale uniformity of the display substrate.

[0249] The display substrate also includes a first conductive transition portion m1, which is located in the third conductive layer 5. The first electrode D5 of the first light-emitting control transistor is electrically connected to the first power line VDD1 through the second via VH2 and the first conductive transition portion m1, wherein the first power line VDD1 includes a first power sub-line VDD11 and a second power sub-line VDD12, and the first power sub-line VDD11 and the second power sub-line VDD12 are spaced apart in the first direction and extend along the second direction.

[0250] Exemplarily, the data writing active layer ACT4 extends along the second direction, the first light-emitting control active layer ACT5 extends along the second direction, and the data writing active layer ACT4 and the light-emitting control active layer ACT5 are spaced apart along the first direction; the orthographic projection of the data writing active layer ACT4 on the base substrate falls within the orthographic projection of the second power sub-line VDD12 on the base substrate; the orthographic projection of the light-emitting control active layer ACT5 on the base substrate falls within the orthographic projection of the first power sub-line VDD11 on the base substrate.

[0251] Exemplarily, the second electrode S4 of the data writing transistor is electrically connected to the data signal line DL through the second conductive transition portion m2 and the first via hole VH1.

[0252] Illustratively, the first sub-pixel driving circuit DX1 includes a first storage sub-circuit 611, the first storage sub-circuit 611 includes a first capacitor C1, the first capacitor C1 includes a first plate C1a and a second plate C1b, the second sub-pixel driving circuit DX2 includes a second storage sub-circuit 612, the second storage sub-circuit 612 includes a second capacitor C2, the second capacitor C2 includes a third plate C2a and a fourth plate C2b, wherein the first plate C1a and the third plate C2a are located in the first conductive layer 3, the first plate C1a and the third plate C2a are spaced apart in the second direction and at least partially overlap in the first direction; the second plate C1b and the fourth plate C2b are located in the second conductive layer, and the second plate C1b and the fourth plate C2b are electrically connected.

[0253] The first conductive transition portion m1 includes a first conductive transition sub-portion m11 and a second conductive transition sub-portion m12. The first end of the first conductive transition sub-portion m11 is electrically connected to the first power sub-line VDD11 through the second via VH2, and the second end of the first conductive transition sub-portion m11 is electrically connected to the second electrode plate C1b through the sixth via VH2. The second conductive transition sub-portion m12 is electrically connected to the second power sub-line VDD12 through the third via VH3. The second conductive transition sub-portion m2 is electrically connected to the fourth capacitor electrode plate C2b through the seventh via VH7. The orthographic projections of any two of the second conductive transition sub-portion m12, the fourth capacitor electrode plate C2b, and the second power sub-line VDD12 on the substrate at least partially overlap. Since the second electrode plate C1b and the fourth electrode plate C2b are electrically connected, the first power sub-line VDD11 and the second power sub-line VDD12 can be electrically connected through the first conductive transition portion m1, the second electrode plate C1b, and the fourth electrode plate C2b.

[0254] The first sub-pixel driving circuit DX1 further includes a first compensation sub-circuit 411, a first initialization sub-circuit 711, a second initialization sub-circuit 712, and a second light emission control sub-circuit 512. The first compensation sub-circuit 411 includes a first compensation transistor T21, the first initialization sub-circuit 711 includes a first initialization transistor T11, the second initialization sub-circuit 712 includes a second initialization transistor T71, and the second light emission control sub-circuit 512 includes a second light emission control transistor T61.

[0255] The second sub-pixel driving circuit DX2 further includes a second compensation sub-circuit 412, a third initialization sub-circuit 713, a fourth initialization sub-circuit 714, and a fourth light emission control sub-circuit 514. The second compensation sub-circuit 412 includes a second compensation transistor T22, the third initialization sub-circuit 713 includes a third initialization transistor T12, the fourth initialization sub-circuit 714 includes a fourth initialization transistor T72, and the fourth light emission control sub-circuit 514 includes a fourth light emission control transistor T62.

[0256] Exemplarily, the first initialization transistor T11 may include a first initialization active layer ACT11, a control electrode G11, a first electrode D11, and a second electrode S11. The first initialization active layer ACT11 extends along the second direction. The portion where the first initialization active layer ACT11 overlaps with the first reset signal line Reset1 serves as the control electrode G11 of the first initialization transistor T11. The first electrode D11 of the first initialization transistor T11 is electrically connected to the first initialization signal line Vinit1 via a tenth via VH10.

[0257] Exemplarily, the first compensation transistor T21 may include a first compensation active layer ACT21, a control electrode G21, a first electrode D21, and a second electrode S21. The first compensation active layer ACT21 extends along a first direction. The portion where the first compensation active layer ACT21 overlaps with the second scan signal line Gate1 serves as the control electrode G21 of the first compensation transistor T21. The first electrode D21 of the first compensation transistor T21 and the second electrode S11 of the first initialization transistor T11 are electrically connected to the third node, the first subnode N3-1, via an eleventh via VH11, a twelfth via VH12, and a sixth conductive transition portion m6. The second electrode S21 of the first compensation transistor T21 is electrically connected to the first node, the first subnode N1-1, via a fifteenth via VH15, a sixteenth via VH16, and a third conductive transition portion m3. The third conductive transition portion m3 is located in the third conductive layer 5.

[0258] The second light-emitting control transistor T61 also includes an active layer ACT61, a control electrode G61, a first electrode D61 and a second electrode S61. The portion where the active layer ACT61 of the second light-emitting control transistor T61 overlaps with the light-emitting control line EM is the control electrode of the second light-emitting control transistor T61. The first electrode D61 of the second light-emitting control transistor T61 is electrically connected to the third node and the first sub-node N3-1 through the twelfth via VH12. The second electrode S61 of the second light-emitting control transistor T61 is electrically connected to the first electrode L11 of the first sub-light-emitting element through the thirteenth via VH13 and the seventh wire transfer portion m7.

[0259] The second initialization transistor T71 also includes an active layer ACT71, a control electrode G71, a first electrode D71 and a second electrode S71. The part where the active layer ACT71 of the second initialization transistor T71 overlaps with the second reset signal line Reset2 is the control electrode G71 of the second initialization transistor T71. The first electrode D71 of the second initialization transistor T71 is electrically connected to the first electrode L11 of the first sub-light-emitting element through the thirteenth via VH13 and the seventh wire transfer portion m7. The second electrode S71 of the second initialization transistor T71 is electrically connected to the second initialization signal line Vinit2 through the fourteenth via VH14.

[0260] For example, the second compensation transistor T22, the third initialization transistor T12, the fourth initialization transistor T72 and the fourth light-emitting control transistor T62 in the display substrate of the embodiment of Figure 20 can be set in the same or corresponding connection method as the first compensation transistor T21, the first initialization transistor T11, the second initialization transistor T71 and the second light-emitting control transistor T61, and are not repeated here.

[0261] Figure 21A is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21B is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21D is a schematic diagram showing a partial via according to an exemplary embodiment of the present disclosure; Figure 21E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21F is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 21 is a schematic diagram showing the planar structure of the combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure.

[0262] For example, in some embodiments of the present disclosure, in combination with reference to Figures 1 and 21A-22, the display substrate 1100 includes a base substrate 1; a plurality of sub-pixels SP provided on the base substrate 1, the plurality of sub-pixels SP being arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits DX, the plurality of pixel circuits DX being used to drive the plurality of sub-pixels SP, wherein the plurality of sub-pixels SP include a first sub-pixel SP1 and a second sub-pixel SP2, the first sub-pixel SP1 and the second sub-pixel SP2 being two adjacent sub-pixels in the first direction or the second direction, and the plurality of pixel circuits DX include a first sub-pixel driving circuit DX1 for driving the first sub-pixel SP1 and a second sub-pixel driving circuit DX2 for driving the second sub-pixel SP2, and the first direction and the second direction intersect.

[0263] The display substrate 1100 includes: a first semiconductor layer 2 arranged on a base substrate 1; a first conductive layer 3 arranged on a side of the first semiconductor layer 2 away from the base substrate 1; a second conductive layer 4 arranged on a side of the first conductive layer 3 away from the base substrate 1; a third conductive layer 5 arranged on a side of the second conductive layer 4 away from the base substrate 1; and a fourth conductive layer 6 arranged on a side of the third conductive layer 4 away from the base substrate 1.

[0264] The display substrate 1100 also includes a first reset signal line Reset1 and a light-emitting control line EM extending along the first direction D1; and a data signal line DL and a first power line VDD1 extending along the second direction D2, the first reset signal line Reset1 and the light-emitting control line EM are located in the first conductive layer 3, and the data signal line DL and the first power line VDD1 are located in the fourth conductive layer 6.

[0265] Illustratively, the first sub-pixel driving circuit DX1 and the second sub-pixel driving circuit DX2 share a first initialization sub-circuit 711, a first light-emitting control sub-circuit 511 and a data signal line DL, wherein the first initialization sub-circuit 711 includes an initialization transistor T1, the initialization transistor T1 includes an initialization active layer ACT1 and a control electrode G1, the initialization active layer ACT1 extends along the second direction, the orthographic projection of the initialization active layer ACT1 on the substrate at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate, and the overlapping portion of the initialization active layer ACT1 and the first reset signal layer Reset1 is the control electrode G1 of the initialization transistor; the first light-emitting control sub-circuit 511 includes a light-emitting control transistor T5, the light-emitting control transistor T5 includes a light-emitting control active layer ACT5 and a first electrode D5, the light-emitting control active layer ACT5 extends along the second direction; the orthographic projection of the light-emitting control active layer ACT5 on the substrate falls within the orthographic projection of the first power line VDD1 on the substrate; the first electrode D1 of the light-emitting control transistor is electrically connected to the first power line VDD1 through the first conductive transition portion m1 and the fifth via VH5.

[0266] Exemplarily, the first sub-pixel driving circuit DX1 includes a first data writing sub-circuit 211, the first data writing sub-circuit 211 includes a first data writing transistor T41, the first data writing transistor T41 includes a first data writing active layer ACT41 and a second pole S41; the second sub-pixel driving circuit DX2 includes a second data writing sub-circuit 212, the second data writing sub-circuit 212 includes a second data writing transistor T42, the second data writing transistor includes a second data writing active layer ACT42 and a first pole D42, wherein the first data writing active layer ACT41 includes a main body 411 extending along the second direction; the second data writing active layer ACT42 includes a main body 421 extending along the second direction, the first data writing active layer ACT41 and the second data writing active layer ACT42 share a overlapping portion 400, the overlapping portion 400 extends along the first direction, and the second pole S41 of the first data writing transistor and the first pole D42 of the second data writing transistor are both electrically connected to the data signal line DL through the second conductive transition portion m2 and the fourth via VH4.

[0267] By designing shared data signal lines, the number of wiring in pixel driving can be reduced, saving wiring space, which is beneficial for narrow-frame display. At the same time, the number of IC chips can be reduced, which helps reduce costs.

[0268] Exemplarily, the first sub-pixel driving circuit DX1 includes a first compensation sub-circuit, the first compensation sub-circuit includes a first compensation transistor T21, and the first compensation transistor T21 includes a first compensation active layer ACT21; the second sub-pixel driving circuit DX2 includes a second compensation sub-circuit, the second compensation sub-circuit includes a second compensation transistor T22, and the second compensation transistor T22 includes a second compensation active layer ACT22, wherein the first compensation active layer ACT21 and the second compensation active layer ACT22 both extend along the first direction; the first compensation active layer ACT21 and the second compensation active layer ACT22 are both spaced apart in the first direction and the second direction.

[0269] Illustratively, the first sub-pixel driving circuit DX1 includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor C1, the first capacitor C1 includes a first plate C1a and a second plate C1b, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor C2, the second capacitor C2 includes a third plate C2a and a fourth plate C2b, wherein the first plate C1a and the third plate C2a are located in the first conductive layer 3, and the first plate C1a and the third plate C2a are spaced apart in the second direction; the second plate C1b and the fourth plate C2b are located in the second conductive layer, and the second plate C1b and the fourth plate C2b are electrically connected.

[0270] Exemplarily, the first conductive transition portion m1 is electrically connected to the first power line VDD1 through the fifth via hole VH5 ; the first conductive transition portion m1 is electrically connected to the fourth electrode plate C2 b through the eighth via hole VH8 .

[0271] Exemplarily, the display substrate further includes a third conductive transition portion m3 located in the third conductive layer 5. The first compensation transistor T21 includes a first electrode D21 and a second electrode S21. The second compensation transistor T22 includes a first electrode D22 and a second electrode S22. The second electrode S21 of the first compensation transistor T21 is electrically connected to the first electrode D22 of the second compensation transistor T22 via a via VH42, a via VH43, and the third conductive transition portion m3. The first electrode D21 of the first compensation transistor T21 is electrically connected to the first node, the first subnode N1-1, via a forty-first conductive transition portion m41. The second electrode S22 of the second compensation transistor T22 is electrically connected to the first node, the second subnode N1-2, via a forty-second conductive transition portion m42.

[0272] Exemplarily, the first sub-pixel driving circuit DX1 includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor T31, the first driving transistor T31 includes a first driving active layer ACT31, the second sub-pixel driving circuit DX2 includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor T32, the second driving transistor T32 includes a second driving active layer ACT32, wherein the first driving active layer ACT31 extends in a straight line along the first direction, the second driving active layer ACT32 extends in a straight line along the first direction, and the first driving active layer ACT31 and the second driving active layer ACT32 are spaced apart in the second direction; the first light-emitting control active layer ACT5, the first driving active layer ACT31 and the second driving active layer ACT32 are electrically connected to each other.

[0273] By adopting a straight-line design for the active layer of the driving transistor, the length and width consistency of each driving transistor can be ensured, which is beneficial to improving the performance consistency of the driving transistor and thus improving the grayscale uniformity of the display substrate.

[0274] The first sub-pixel driving circuit DX1 includes a second light-emission control sub-circuit, which includes a second light-emission control transistor T61. The second light-emission control transistor T61 includes a second light-emission control active layer ACT61, a first electrode D61, and a second electrode S61. The first electrode D61 of the second light-emission control transistor is electrically connected to the first electrode D31 of the first driving transistor T31 via a fourth conductive transition m4. The second electrode S61 of the second light-emission control transistor is electrically connected to the first electrode of the first light-emitting element via a forty-third conductive transition m43.

[0275] The second sub-pixel driver circuit DX2 includes a fourth light-emission control sub-circuit, which includes a fourth light-emission control transistor T62. The fourth light-emission control transistor T62 includes a fourth light-emission control active layer ACT62 and a second electrode S62. The second light-emission control active layer ACT61 and the fourth light-emission control active layer ACT62 extend along the second direction and are spaced apart along the first direction. The second electrode S62 of the fourth light-emission control transistor T62 is electrically connected to the first electrode of the second light-emitting element via a forty-fourth conductive transition portion m44. Referring to FIG. 1 , at least some embodiments of the present disclosure further provide a display device. The display device 1000 may include the display substrate described above.

[0276] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0277] It should be understood that the display panel and display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that: The pixel circuit includes: a first sub-pixel driving circuit for driving a first sub-pixel; a second sub-pixel driving circuit for driving a second sub-pixel, wherein the first sub-pixel includes a first sub-light-emitting element, the second sub-pixel includes a second sub-light-emitting element, the first sub-pixel and the second sub-pixel are two sub-pixels adjacent to each other in a first direction or a second direction, and the first direction and the second direction intersect; the pixel circuit also includes a first data signal line, wherein the first data signal line is configured to provide data signals to both the first sub-pixel driving circuit and the second sub-pixel driving circuit, wherein the data signals include a first sub-data signal and a second sub-data signal, the first sub-data signal is generated by the first data signal line in a third time period, and the second sub-data signal is generated by the first data signal line in a fourth time period, wherein the third time period does not overlap with the fourth time period.

2. The pixel circuit according to claim 1, wherein: The pixel circuit includes: a data writing sub-circuit, the data writing sub-circuit coupled to a data signal terminal, a first scanning signal terminal, and a second node, wherein the data signal terminal is coupled to the first data signal line, and the data writing sub-circuit is configured to write a data signal received at the data signal terminal to the second node in response to a first scanning signal received at the first scanning signal terminal. In which, the first sub-pixel driving circuit and the second sub-pixel driving circuit are coupled to the second node, the data writing sub-circuit writes the first sub-data signal into the first sub-pixel driving circuit through the second node; and the data writing sub-circuit writes the second sub-data signal into the second sub-pixel driving circuit through the second node.

3. The pixel circuit according to claim 2, wherein: The first sub-pixel driving circuit includes: a first driving sub-circuit coupled to the first node (first sub-node), the second node, and the third node (first sub-node), the first driving sub-circuit configured to generate a first driving current in response to a voltage of the first node (first sub-node), wherein the first driving current is used to drive the first sub-light-emitting element to emit light; and a first compensation sub-circuit, the first compensation sub-circuit is coupled to the second scan signal terminal, the first node first sub-node and the third node first sub-node, the first compensation sub-circuit is configured to transmit the first sub-data signal from the data signal terminal to the first node first sub-node in response to the second scan signal received at the second scan signal terminal.

4. The pixel circuit according to claim 3, wherein: The second sub-pixel driving circuit includes: a second driving sub-circuit coupled to the first node and the second sub-node, the second node, and the third node and the second sub-node, the second driving sub-circuit being configured to generate a second driving current in response to a voltage of the first node and the second sub-node, wherein the second driving current is used to drive the second sub-light-emitting element to emit light; and a second compensation sub-circuit, the second compensation sub-circuit is coupled to the third scan signal terminal, the second sub-node of the first node and the second sub-node of the third node, and the second compensation sub-circuit is configured to transmit the second sub-data signal from the data signal terminal to the second sub-node of the first node in response to the third scan signal received at the third scan signal terminal.

5. The pixel circuit according to claim 4, wherein: The data writing sub-circuit, the first driving sub-circuit, and the second driving sub-circuit are all coupled to the second node.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The first sub-pixel driving circuit further includes: a first light-emitting control subcircuit coupled to a first voltage terminal, a light-emitting control terminal, and the second node, the first light-emitting control subcircuit being configured to write a first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal; a first storage sub-circuit coupled to the first node, a first sub-node and the first voltage terminal; The second sub-pixel driving circuit further includes: a third light-emitting control subcircuit coupled to the second voltage terminal, the light-emitting control terminal, and the second node, and configured to write a second voltage received at the second voltage terminal to the second node in response to a light-emitting control signal received at the light-emitting control terminal; The second storage sub-circuit is coupled to the first node, the second sub-node and the second voltage terminal.

7. The pixel circuit according to any one of claims 1 to 5, wherein: The pixel circuit comprises: a first light-emitting control subcircuit coupled to a first voltage terminal, a light-emitting control terminal, and the second node, wherein the first light-emitting control subcircuit is configured to write a first voltage received at the first voltage terminal into the first sub-pixel driving circuit and the second sub-pixel driving circuit via the second node in response to a light-emitting control signal received at the light-emitting control terminal; a first storage sub-circuit coupled to the first node, a first sub-node and a first voltage terminal, the first storage sub-circuit being configured to store a storage voltage in the first sub-pixel driving circuit; and The second storage sub-circuit is coupled to the first node, the second sub-node and the first voltage terminal, and is configured to store a storage voltage in the second sub-pixel driving circuit.

8. The pixel circuit according to any one of claims 1 to 7, wherein: The first sub-pixel driving circuit further includes: a first initialization sub-circuit, the first initialization sub-circuit being coupled to the first reset signal terminal, the first initialization signal terminal, and the first node first sub-node, the first initialization sub-circuit being configured to, in response to a first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the first node first sub-node, so as to initialize a potential of the first node first sub-node; a second initialization sub-circuit coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the first sub-light-emitting element, the second initialization sub-circuit being configured to, in response to a second reset signal received at the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the first sub-light-emitting element to initialize the potential of the first electrode of the first sub-light-emitting element; and a second light-emitting control subcircuit, wherein the second light-emitting control subcircuit is coupled to the first sub-node of the third node, the light-emitting control terminal and the first electrode of the first sub-light-emitting element, and the second light-emitting control subcircuit is configured to output the first driving current transmitted to the first sub-node of the third node to the first sub-light-emitting element in response to a light-emitting control signal received at the light-emitting control terminal.

9. The pixel circuit according to any one of claims 1 to 8, wherein: The second sub-pixel driving circuit further includes: a third initialization sub-circuit, the third initialization sub-circuit being coupled to the first reset signal terminal, the first initialization signal terminal, and the second sub-node of the first node, the third initialization sub-circuit being configured to, in response to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the second sub-node of the first node, so as to initialize the potential of the second sub-node of the first node; a fourth initialization sub-circuit, the fourth initialization sub-circuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the second sub-light-emitting element, the fourth initialization sub-circuit being configured to, in response to the second reset signal received at the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the second sub-light-emitting element to initialize the potential of the first electrode of the second sub-light-emitting element; and a fourth light-emitting control subcircuit, wherein the fourth light-emitting control subcircuit is coupled to the second sub-node of the third node, the light-emitting control terminal and the first electrode of the second sub-light-emitting element, and the fourth light-emitting control subcircuit is configured to output the second drive current transmitted to the second sub-node of the third node to the second sub-light-emitting element in response to a light-emitting control signal received at the light-emitting control terminal.

10. The pixel circuit according to claim 6, wherein: The data writing sub-circuit includes a data writing transistor, wherein a control electrode of the data writing transistor is coupled to the first scanning signal terminal, a first electrode of the data writing transistor is coupled to the second node, and a second electrode of the data writing transistor is coupled to the data signal terminal; The first light emission control subcircuit includes a first light emission control transistor, wherein a control electrode of the first light emission control transistor is coupled to the light emission control terminal, a first electrode of the first light emission control transistor is coupled to the first voltage terminal, and a second electrode of the first light emission control transistor is coupled to the second node; as well as The third light-emitting control subcircuit includes a third light-emitting control transistor, the control electrode of the third light-emitting control transistor is coupled to the light-emitting control end, the first electrode of the third light-emitting control transistor is coupled to the second voltage end, and the second electrode of the third light-emitting control transistor is coupled to the second node.

11. The pixel circuit according to claim 7, wherein: The data writing sub-circuit includes a data writing transistor, wherein a control electrode of the data writing transistor is coupled to the first scanning signal terminal, a first electrode of the data writing transistor is coupled to the second node, and a second electrode of the data writing transistor is coupled to the data signal terminal; as well as The first light-emitting control subcircuit includes a light-emitting control transistor, a control electrode of the light-emitting control transistor is coupled to the light-emitting control end, a first electrode of the light-emitting control transistor is coupled to the first voltage end, and a second electrode of the light-emitting control transistor is coupled to the second node.

12. The pixel circuit according to claim 1, wherein: The pixel circuit comprises: a first light-emitting control subcircuit coupled to a first voltage terminal, a light-emitting control terminal, and the second node, wherein the first light-emitting control subcircuit is configured to write a first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal, wherein the first sub-pixel driving circuit and the second sub-pixel driving circuit are coupled at the second node, and the first light-emitting control subcircuit writes the first voltage into the first sub-pixel driving circuit and the second sub-pixel driving circuit, respectively, via the second node; and A first initialization sub-circuit is coupled to the first reset signal terminal, the first initialization signal terminal and the second node, and the first initialization sub-circuit is configured to respond to the first reset signal received at the first reset signal terminal by transmitting the first initialization signal received at the first initialization signal terminal to the second node to initialize the potential of the second node.

13. The pixel circuit according to claim 12, wherein: The first sub-pixel driving circuit further includes: a first data writing sub-circuit coupled to the data signal terminal, the first scan signal terminal, and the first sub-node of the third node, the first data writing sub-circuit configured to write a data signal received at the data signal terminal into the first sub-node of the third node in response to a first scan signal received at the first scan signal terminal; and The second sub-pixel driving circuit further includes: a second data writing sub-circuit coupled to the data signal terminal, the first scan signal terminal, and the second sub-node of the third node, wherein the second data writing sub-circuit is configured to write the data signal received at the data signal terminal into the second sub-node of the third node in response to the first scan signal received at the first scan signal terminal; The data signal terminal coupled to the first data writing sub-circuit and the data signal terminal coupled to the second data writing sub-circuit are coupled to the same data signal line.

14. The pixel circuit according to claim 13, wherein: The first sub-pixel driving circuit includes: a first storage sub-circuit coupled to the first node, a first sub-node and a first voltage terminal; a first compensation sub-circuit coupled to the second scan signal terminal, the first node and the first sub-node, and the second node, the first compensation sub-circuit configured to transmit the first sub-data signal from the data signal terminal to the first node and the first sub-node in response to a second scan signal received at the second scan signal terminal; a first driving sub-circuit, the first driving sub-circuit being coupled to the first node (a first sub-node), the second node, and the third node (a first sub-node), the first driving sub-circuit being configured to generate a first driving current in response to a voltage of the first node (a first sub-node), wherein the first driving current is used to drive the first sub-light-emitting element to emit light; and The second sub-pixel driving circuit includes: a second storage sub-circuit, the second storage sub-circuit being coupled to the first node, a second sub-node and a first voltage terminal, wherein the first storage sub-circuit and the second storage sub-circuit are coupled at the first voltage terminal; a second compensation sub-circuit, the second compensation sub-circuit being coupled to the third scan signal terminal, the second sub-node of the first node, and the second node, the second compensation sub-circuit being configured to transmit the second sub-data signal from the data signal terminal to the second sub-node of the first node in response to a third scan signal received at the third scan signal terminal; A second driving sub-circuit is coupled to the first node second sub-node, the second node and the third node second sub-node, and the second driving sub-circuit is configured to generate a second driving current in response to the voltage of the first node second sub-node, wherein the second driving current is used to drive the second sub-light-emitting element to emit light.

15. The pixel circuit according to claim 13 or 14, wherein: The first light emitting control subcircuit includes a light emitting control transistor, wherein a control electrode of the light emitting control transistor is coupled to the light emitting control terminal, a first electrode of the light emitting control transistor is coupled to the first voltage terminal, and a second electrode of the light emitting control transistor is coupled to the second node; The first initialization sub-circuit includes an initialization transistor, a control electrode of the initialization transistor is coupled to the first reset signal terminal, a first electrode of the initialization transistor is coupled to the second node, and a second electrode of the initialization transistor is coupled to the first initialization signal terminal; The first data writing sub-circuit includes a first data writing transistor, the second data writing sub-circuit includes a second data writing transistor, In which, the control electrode of the first data write transistor is coupled to the first scan signal end, the first electrode of the first data write transistor is coupled to the first sub-node of the third node, the second electrode of the first data write transistor is coupled to the first electrode of the second data write transistor, the control electrode of the second data write transistor is coupled to the first scan signal end, and the second electrode of the second data write transistor is coupled to the second sub-node of the third node.

16. The pixel circuit according to claim 1, wherein: The pixel circuit comprises: a first light-emitting control subcircuit, the first light-emitting subcircuit being coupled to a first voltage terminal, a light-emitting control terminal, and the second node, wherein the first light-emitting control subcircuit is configured to write a first voltage received at the first voltage terminal into the second node in response to a light-emitting control signal received at the light-emitting control terminal, wherein the first sub-pixel driving circuit and the second sub-pixel driving circuit are electrically connected at the second node, and the first light-emitting control subcircuit writes the first voltage into the first sub-pixel driving circuit via the second node; and the first light-emitting control subcircuit writes the first voltage into the second sub-pixel driving circuit via the second node; a second reference voltage writing subcircuit coupled to the second reset signal terminal, the second reference voltage terminal, and the second node, wherein the second reference voltage writing subcircuit is configured to write a second reference voltage received at the second reference voltage terminal into the second node in response to a second reset signal received at the second reset signal terminal; The first sub-pixel driving circuit further includes: a first data writing sub-circuit coupled to the data signal terminal, the second scan signal terminal, and the first sub-node of the fourth node, the first data writing sub-circuit being configured to write a data signal received at the data signal terminal into the first sub-node of the fourth node in response to a second scan signal received at the second scan signal terminal; a first storage sub-circuit coupled to the first node, a first sub-node, and a fourth node, a first sub-node; a third storage sub-circuit, the third storage sub-circuit being coupled to the first sub-node of the fourth node and the first voltage terminal; The second sub-pixel driving circuit further includes: a second data writing sub-circuit coupled to the data signal terminal, the third scan signal terminal, and the second sub-node of the third node, the second data writing sub-circuit being configured to write a data signal received at the data signal terminal into the second sub-node of the third node in response to a third scan signal received at the third scan signal terminal; a second storage sub-circuit coupled to the second sub-node of the first node and the second sub-node of the fourth node; a fourth storage sub-circuit, the fourth storage sub-circuit being coupled to the fourth node, the second sub-node, and the first voltage terminal; Wherein, the first data writing sub-circuit and the second data writing sub-circuit share the same data wiring; The pixel driving circuit further includes a first reference voltage first writing subcircuit and a first reference voltage second writing subcircuit, wherein the first reference voltage first writing sub-circuit is coupled to the first sub-node of the fourth node, the second reset signal terminal, and the first reference voltage signal terminal, and the first reference voltage first writing sub-circuit is configured to write the first reference voltage received at the first reference voltage signal terminal into the first sub-node of the fourth node in response to a second reset signal received at the second reset signal terminal; and The first reference voltage second write sub-circuit is coupled to the fourth node second sub-node, the second reset signal terminal and the first reference voltage signal terminal, and the first reference voltage second write sub-circuit is configured to write the first reference voltage received at the first reference voltage signal terminal into the fourth node second sub-node in response to the second reset signal received at the second reset signal terminal.

17. A pixel driving method, applied to the pixel circuit according to any one of claims 1 to 16, wherein: The pixel driving method includes: In a third time period, in response to the first scan signal and the second scan signal, the data writing sub-circuit and the first compensation sub-circuit are both turned on, so that the first sub-data signal from the data signal terminal is transmitted to the first node and the first sub-node; In a fourth time period, in response to the first scan signal and the third scan signal, the data writing sub-circuit and the second compensation sub-circuit are both turned on, so that the second sub-data signal from the data signal terminal is transmitted to the first node and the second sub-node. The third time period and the fourth time period are in a writing phase of an image frame, the fourth time period is after the third time period and the fourth time period does not overlap with the third time period.

18. The pixel driving method according to claim 17, wherein: In a first time period, in response to a light emitting control signal from the light emitting control terminal, the first sub-pixel and the second sub-pixel stop emitting light, and the first sub-pixel driving circuit and the second sub-pixel driving circuit start to reset; In the second time period, in response to the first reset signal at the first reset signal terminal, the first initialization sub-circuit is turned on and the third initialization sub-circuit is turned on, so that the first initialization signal from the first initialization signal terminal is transmitted to the first node, the first sub-node and the first node, the second sub-node, respectively. The first time period and the second time period are in the reset phase of an image frame, the first time period is before the second time period, the second time period is between the first time period and the third time period, and the first time period, the second time period and the third time period do not overlap with each other.

19. The pixel driving method according to claim 17, wherein: In a first sub-phase of a first time period, in response to a first reset signal and a second scan signal, the first initialization sub-circuit and the first compensation sub-circuit are both turned on, so that a first initialization signal from the first initialization signal terminal is output to the first node and the first sub-node; In the second sub-phase of the first time period, in response to the first reset signal and the third scan signal, the third initialization sub-circuit and the second compensation sub-circuit are both turned on, so that the first initialization signal from the first initialization signal terminal is output to the second sub-node of the first node. The first sub-stage of the first time period and the second sub-stage of the first time period are in the reset stage of an image frame, the first sub-stage of the first time period is before the second sub-stage of the first time period, and the first sub-stage of the first time period and the second sub-stage of the first time period do not overlap.

20. A display substrate, wherein: The display substrate comprises: substrate; A pixel circuit according to any one of claims 1 to 16 provided on the substrate, wherein the pixel circuit comprises a first sub-pixel driving circuit and a second sub-pixel driving circuit; and A light emitting element is provided on the base substrate, wherein the light emitting element includes a first sub-light emitting element and a second sub-light emitting element, The first sub-light emitting element is coupled to the first sub-pixel driving circuit, and the second sub-light emitting element is coupled to the second sub-pixel driving circuit.

21. A display substrate, wherein: The display substrate comprises: substrate; A plurality of sub-pixels are provided on the base substrate, wherein the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits, the plurality of pixel circuits being configured to drive the plurality of sub-pixels; The plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are two adjacent sub-pixels in a first direction or a second direction, the plurality of pixel circuits include a first sub-pixel driving circuit for driving the first sub-pixel and a second sub-pixel driving circuit for driving the second sub-pixel, and the first direction and the second direction intersect; The display substrate comprises: a first semiconductor layer provided on the base substrate; a first conductive layer provided on a side of the first semiconductor layer away from the base substrate; a third conductive layer provided on a side of the first conductive layer away from the base substrate; and a fourth conductive layer provided on a side of the third conductive layer away from the base substrate; the display substrate further comprises a first scan signal line extending along a first direction and a data signal line extending along a second direction, the first scan signal line being located in the first conductive layer, and the data signal line being located in the fourth conductive layer; The first sub-pixel driving circuit and the second sub-pixel driving circuit share a data writing sub-circuit and a data signal line, the data writing sub-circuit includes a data writing transistor, the data writing transistor includes a data writing active layer, a control electrode and a second electrode, the data writing active layer is located in the first semiconductor layer, and the second electrode is located in the third conductive layer; and The orthographic projection of the data writing active layer on the base substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the base substrate, and the overlapping part of the first scanning signal line and the data writing active layer is the control electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the data signal line through a first via.

22. The display substrate according to claim 21, wherein The first sub-pixel driving circuit and the second sub-pixel driving circuit share a first light-emission control sub-circuit, the first light-emission control sub-circuit comprising a light-emission control transistor, the light-emission control transistor comprising a light-emission control active layer, a control electrode, and a first electrode, the light-emission control active layer being located in the first semiconductor layer, and the first electrode of the light-emission control transistor being located in the third conductive layer; The display substrate further includes a light-emitting control line extending along a first direction, an orthographic projection of the light-emitting control active layer on the base substrate at least partially overlaps with an orthographic projection of the light-emitting control line on the base substrate, and the overlapping portion of the light-emitting active layer and the light-emitting control line serves as a control electrode of the light-emitting control transistor; The display substrate further includes a first conductive transition portion, the first conductive transition portion is located in the third conductive layer, and the first electrode of the light emitting control transistor is electrically connected to the first power line through the first conductive transition portion. In which, the first power line includes a first power sub-line and a second power sub-line, the first power sub-line and the second power sub-line are arranged at intervals in the first direction and extend along the second direction, the first conductive transition portion is electrically connected to the first power sub-line through a second via; and the first conductive transition portion is electrically connected to the second power sub-line through a third via.

23. The display substrate according to claim 22, wherein: The data writing active layer and the light emitting control active layer extend continuously in the second direction; The orthographic projections of the data writing active layer and the first light emitting control active layer on the base substrate at least partially overlap with the orthographic projection of the data signal line on the base substrate; as well as The orthographic projection of the data signal line on the base substrate falls into a gap between the orthographic projections of the first power sub-line and the second power sub-line on the base substrate.

24. The display substrate according to claim 22 or 23, wherein: The first conductive transition portion includes a first conductive transition sub-portion and a second conductive transition sub-portion, the first conductive transition sub-portion extends along the second direction, and the second conductive transition sub-portion extends along the first direction. The orthographic projection of the first conductive adapter portion on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control active layer on the base substrate; The orthographic projection of the second via on the base substrate falls within the orthographic projection of the first end of the second conductive transfer sub-portion on the base substrate, and the orthographic projection of the third via on the base substrate falls within the orthographic projection of the second end of the second conductive transfer sub-portion on the base substrate.

25. The display substrate according to claim 21, wherein The data writing active layer extends along the second direction, the light emitting control active layer extends along the second direction, and the data writing active layer and the light emitting control active layer are spaced apart from each other along the first direction; as well as The orthographic projection of the data writing active layer on the base substrate falls within the orthographic projection of the second power sub-line on the base substrate; the orthographic projection of the light emitting control active layer on the base substrate falls within the orthographic projection of the first power sub-line on the base substrate.

26. The display substrate according to claim 24, wherein: The first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, Wherein, the first driving active layer and the second driving active layer extend in a zigzag shape in the first direction respectively; and The first driving active layer and the second driving active layer are symmetrical with respect to the data signal line.

27. The display substrate according to claim 25, wherein: The first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, The first driving active layer extends in a straight line along the first direction, the second driving active layer extends in a straight line along the first direction, and the first driving active layer and the second driving active layer are spaced apart in the second direction; The light emission control active layer, the first driving active layer, and the second driving active layer are electrically connected to each other.

28. The display substrate according to claim 26, wherein: The display substrate further includes a second conductive layer located between the first conductive layer and the third conductive layer; The first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, The first electrode plate and the third electrode plate are located in the first conductive layer, and are spaced apart from each other in the first direction; the second electrode plate and the fourth electrode plate are located in the second conductive layer, and are electrically connected to each other.

29. The display substrate according to claim 27, wherein: The display substrate further includes a second conductive layer located between the first conductive layer and the third conductive layer; The first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, The first electrode plate and the third electrode plate are located in the first conductive layer, the first electrode plate and the third electrode plate are spaced apart in the second direction and at least partially overlap in the first direction; the second electrode plate and the fourth electrode plate are located in the second conductive layer, and the second electrode plate and the fourth electrode plate are electrically connected.

30. The display substrate according to claim 29, wherein The first conductive transition portion includes a first conductive transition sub-portion and a second conductive transition sub-portion, The first end of the first conductive adapter sub-section is electrically connected to the first power sub-line through the second via hole, the second end of the first conductive adapter sub-section is electrically connected to the second electrode plate through the sixth via hole; the second conductive adapter sub-section is electrically connected to the second power sub-line through the third via hole; and the second conductive adapter sub-section is electrically connected to the fourth capacitor electrode plate through the seventh via hole. The orthographic projections of any two of the second conductive adapter portion, the fourth capacitor plate and the second power supply sub-line on the base substrate at least partially overlap.

31. A display substrate, wherein: The display substrate comprises: substrate; A plurality of sub-pixels are provided on the base substrate, wherein the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the base substrate; and a plurality of pixel circuits, the plurality of pixel circuits being configured to drive the plurality of sub-pixels; The plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are two adjacent sub-pixels in a first direction or a second direction, the plurality of pixel circuits include a first sub-pixel driving circuit for driving the first sub-pixel and a second sub-pixel driving circuit for driving the second sub-pixel, and the first direction and the second direction intersect; The display substrate comprises: a first semiconductor layer provided on the base substrate; a first conductive layer provided on a side of the first semiconductor layer away from the base substrate; a third conductive layer provided on a side of the first conductive layer away from the base substrate; and a fourth conductive layer provided on a side of the third conductive layer away from the base substrate. The display substrate further includes a first reset signal line and a light emitting control line extending in a first direction; and a data signal line and a first power supply line extending in a second direction, wherein the first reset signal line and the light emitting control line are located in the first conductive layer, and the data signal line and the first power supply line are located in the fourth conductive layer; The first sub-pixel driving circuit and the second sub-pixel driving circuit share a first initialization sub-circuit and a first light emission control sub-circuit. The first initialization sub-circuit includes an initialization transistor, the initialization transistor includes an initialization active layer and a control electrode, the initialization active layer extends along the second direction, the orthographic projection of the initialization active layer on the base substrate at least partially overlaps with the orthographic projection of the first reset signal line on the base substrate, and the overlapping portion of the initialization active layer and the first reset signal layer serves as the control electrode of the initialization transistor; and The first light-emitting control subcircuit includes a light-emitting control transistor, which includes a light-emitting control active layer and a first electrode, and the light-emitting active layer extends along the second direction; the orthographic projection of the light-emitting active layer on the base substrate falls within the orthographic projection of the first power line on the base substrate; the first electrode of the light-emitting control transistor is electrically connected to the first power line through a first conductive adapter.

32. The display substrate according to claim 31, wherein The first sub-pixel driving circuit includes a first data writing sub-circuit, the first data writing sub-circuit includes a first data writing transistor, the first data writing transistor includes a first data writing active layer and a second electrode; the second sub-pixel driving circuit includes a second data writing sub-circuit, the second data writing sub-circuit includes a second data writing transistor, the second data writing transistor includes a second data writing active layer and a first electrode, The first data writing active layer includes a main body portion extending along the second direction; the second data writing active layer includes a main body portion extending along the second direction; the first data writing active layer and the second data writing active layer share a lap portion, and the lap portion extends along the first direction. The second electrode of the first data writing transistor and the first electrode of the second data writing transistor are both electrically connected to the data signal line through a fourth via hole.

33. The display substrate according to claim 32, wherein: The first sub-pixel driving circuit includes a first compensation sub-circuit, the first compensation sub-circuit includes a first compensation transistor, and the first compensation transistor includes a first compensation active layer; The second sub-pixel driving circuit includes a second compensation sub-circuit, the second compensation sub-circuit includes a second compensation transistor, and the second compensation transistor includes a second compensation active layer. The first compensation active layer and the second compensation active layer both extend along the first direction; the first compensation active layer and the second compensation active layer are spaced apart in the first direction and the second direction.

34. The display substrate according to claim 33, wherein: The first sub-pixel driving circuit includes a first storage sub-circuit, the first storage sub-circuit includes a first capacitor, the first capacitor includes a first plate and a second plate, the second sub-pixel driving circuit includes a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, the second capacitor includes a third plate and a fourth plate, The first electrode plate and the third electrode plate are located in the first conductive layer, and are spaced apart from each other in the second direction; the second electrode plate and the fourth electrode plate are located in the second conductive layer, and are electrically connected to each other.

35. The display substrate according to claim 34, wherein: The first conductive transition portion is electrically connected to the first power line through the fifth via hole; the first conductive transition portion is electrically connected to the fourth electrode plate through the eighth via hole; The display substrate further includes a third conductive transition portion located in the third conductive layer, the first compensation transistor includes a second electrode, the second compensation transistor includes a first electrode, and the second electrode of the first compensation transistor is electrically connected to the first electrode of the second compensation transistor through the third conductive transition portion.

36. The display substrate according to claim 35, wherein: The first sub-pixel driving circuit includes a first driving sub-circuit, the first driving sub-circuit includes a first driving transistor, the first driving transistor includes a first driving active layer, the second sub-pixel driving circuit includes a second driving sub-circuit, the second driving sub-circuit includes a second driving transistor, the second driving transistor includes a second driving active layer, The first driving active layer extends in a straight line along the first direction, the second driving active layer extends in a straight line along the first direction, and the first driving active layer and the second driving active layer are spaced apart in the second direction; The light emission control active layer, the first driving active layer, and the second driving active layer are electrically connected to each other.

37. A display device comprising the display substrate according to any one of claims 20 to 36.

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