Architectural method for variable instruction of processor

Abstract

The present application relates to the field of computation acceleration. Provided is an architectural method for a variable instruction of a processor. The method comprises: executing a custom instruction to specify an FPGA to complete a custom operation, wherein the custom instruction comprises configuration data or a data address pointing to the configuration data; when the custom instruction comprises the configuration data, the FPGA loading the configuration data to complete the custom operation; and when the custom instruction comprises the data address, the FPGA accessing the data address to load the configuration data, so as to complete the custom operation; and in response to the custom instruction, the FPGA storing a result of the custom operation in a register or a memory. A custom instruction carries configuration data or a data address pointing to the configuration data, and the custom instruction is executed to specify an FPGA to complete a custom operation, and thus the FPGA is used for completing a custom operation task.

Description

A processor variable instruction architecture method Technical Field

[0001] The present application relates to the field of computing acceleration, and in particular to an architectural method for processor variable instructions. Background Art

[0002] In data processing for areas such as automatic control, digital signal processing, communications, video, and imaging, the performance of multiplication and division operations directly impacts the chip's overall data processing capabilities. To improve chip performance and reduce the computational burden on the CPU core, an effective approach is to design a coprocessor or dedicated multiplier / divider circuit specifically for multiplication and division and related arithmetic operations within a microcontroller or dedicated chip. Summary of the Invention

[0003] In order to shorten the time required for calculation, the present application provides an architectural method for processor variable instructions.

[0004] The present application provides a processor variable instruction architecture method, including: executing a custom instruction to specify an FPGA to complete a custom operation.

[0005] By adopting the above technical solution, FPGA (Field-Programmable Gate Array) is used to complete custom computing tasks to achieve computing acceleration, especially the acceleration of complex calculations.

[0006] Preferably, the custom instruction includes configuration data, and the FPGA loads the configuration data to perform the custom operation.

[0007] By adopting the above technical solution, when the configuration data is short, the FPGA directly loads the configuration data in the custom instruction to complete the custom operation.

[0008] Preferably, the custom instruction includes a data address pointing to configuration data; and the FPGA accesses the data address to load the configuration data to complete the custom operation.

[0009] By adopting the above technical solution, when the configuration data is long, the FPGA directly accesses the data address to load the configuration data, without the need for other processing units to move the configuration data, which helps to shorten the time to obtain custom calculation results.

[0010] Preferably, the processor variable instruction architecture method further includes: the FPGA responding to the custom instruction to store the result of the custom operation back into the register or memory.

[0011] By adopting the above technical solution, the result of the custom operation is easily read.

[0012] In summary, this application includes at least one of the following beneficial technical effects:

[0013] 1. Custom instructions carry configuration data or data addresses pointing to configuration data. Execute custom instructions to specify the FPGA to complete custom operations. Utilize the FPGA to complete custom operations and achieve computational acceleration.

[0014] 2. When the configuration data is long, the FPGA directly accesses the data address to load the configuration data, without the need for other processing units to move the configuration data, which helps shorten the time to obtain custom calculation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a flow chart of an architectural method for processor variable instructions. DETAILED DESCRIPTION

[0016] The present application is further described in detail below with reference to the accompanying drawings.

[0017] 1 , an embodiment of the present application discloses an architecture method for processor variable instructions, including: executing a custom instruction to specify an FPGA to perform a custom operation.

[0018] Specifically: Custom instructions include configuration data or data addresses pointing to configuration data; engineers create corresponding custom instructions based on required operations, data, functions, etc.

[0019] When the custom instruction includes configuration data, the FPGA loads the configuration data to complete the custom operation; when the custom instruction includes a data address, the FPGA accesses the data address to load the configuration data and complete the custom operation.

[0020] The FPGA responds to the custom instruction to store the result of the custom operation back into a register or memory.

[0021] The implementation principle of an architectural method for processor variable instructions in an embodiment of the present application is as follows: custom instructions carry configuration data or data addresses pointing to configuration data, execute custom instructions to specify FPGA to complete custom operations, and use FPGA (Field-Programmable Gate Array) to complete custom operation tasks to achieve computing acceleration.

[0022] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A method for architecture of processor variable instructions, characterized in that: include: Execute custom instructions to specify the FPGA to complete custom operations.

2. The processor variable instruction architecture method according to claim 1, characterized in that: The custom instruction includes configuration data, and the FPGA loads the configuration data to complete the custom operation.

3. The processor variable instruction architecture method according to claim 1, wherein: The custom instruction includes a data address pointing to configuration data; and the FPGA accesses the data address to load the configuration data to complete the custom operation.

4. The processor variable instruction architecture method according to claim 1, wherein: Also includes: The FPGA stores the result of the custom operation back into a register or memory in response to the custom instruction.

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