Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display region, a binding region located on one side of the display region, and a first peripheral region located on the side of the binding region close to the display region. The display panel comprises a substrate, and a first conductive layer, a second conductive layer, a third conductive layer, and a cover plate which are sequentially arranged on the substrate, and an ink layer is arranged on the side of the cover plate close to the substrate. In the first peripheral region, the first conductive layer comprises a plurality of first signal lines, the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are sequentially arranged and have the same extension direction. The orthographic projection of the ink layer on the substrate at least partially overlaps the first peripheral region. The orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate at least partially overlaps the orthographic projection of the ink layer on the substrate.

Description

Display panel and display device

[0001] The present application claims priority from the Chinese Patent Application No. 202410245344.2 filed on March 04, 2024 and entitled "Display panel and display device", the contents of which should be understood as incorporated by reference into the present application. TECHNICAL FIELD

[0002] The present document relates to, but is not limited to, display technology, and in particular to a display panel and a display device. BACKGROUND

[0003] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as a light emitting element and controlled by a thin film transistor (TFT) have become the mainstream products in the current display field.

[0004] However, the lower frame of the display panel has a light leakage problem. SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, the embodiments of the present disclosure provide a display panel, comprising a display area, a binding area located on one side of the display area, and a first peripheral area located on a side of the binding area close to the display area; the display panel comprises a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a cover plate arranged in sequence on the substrate, and the cover plate is provided with an ink layer on a side close to the substrate; in the first peripheral area, the first conductive layer comprises a plurality of first signal lines, the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and have the same extension direction; the ink layer has an orthographic projection on the substrate, and the orthographic projection of the ink layer on the substrate at least partially overlaps the first peripheral area; the third conductive layer has an orthographic projection on the substrate, and the orthographic projection of the third conductive layer on the substrate covers the orthographic projection of the plurality of first signal lines and the plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate at least partially overlaps the orthographic projection of the ink layer on the substrate.

[0007] In an exemplary embodiment, in the first peripheral area, in a direction away from the display area, the overlapping size of the third conductive layer and the ink layer is a first overlapping size, and the first overlapping size is greater than or equal to 18 microns.

[0008] In an exemplary embodiment, the display panel further comprises a second peripheral area located on the periphery of the display area and away from one side of the binding area, the first peripheral area and the second peripheral area being in communication to surround the display area; the display panel further comprises a first dam and a second dam, the first dam and the second dam surrounding the display area respectively, the second dam being located on the side of the first dam away from the display area.

[0009] In an exemplary embodiment, the display panel further comprises a fourth conductive layer, a first planar layer, a fifth conductive layer, a second planar layer, a third planar layer and a pixel definition layer arranged in sequence on the side of the second conductive layer away from the substrate; the third conductive layer is located between the second planar layer and the third planar layer, and the pixel definition layer is located on the side of the third planar layer away from the substrate; the first dam comprises a first dam base and a third dam base stacked, the third dam base being located on the side of the first dam base away from the substrate; the second dam comprises a second dam base and a fourth dam base stacked, the fourth dam base being located on the side of the second dam base away from the substrate; the first dam base and the second dam base are located on the third planar layer; the third dam base and the fourth dam base are located on the pixel definition layer.

[0010] In an exemplary embodiment, the display panel further comprises a second power line; in the first peripheral area and the second peripheral area, the second power line extends to the lower side of the second dam close to the substrate.

[0011] In an exemplary embodiment, the second power line is located on the fourth conductive layer; or, the second power line is located on the fourth conductive layer and the fifth conductive layer, and the second power line between different conductive layers is connected through a via.

[0012] In an exemplary embodiment, the second power line comprises a second conductive part and a fourth conductive part, the second conductive part being located on the fourth conductive layer, and the fourth conductive part being located on the fifth conductive layer; the second conductive part, the fourth conductive part and the second power line located on the third conductive layer are connected in sequence through a via, and the second power line located on the third conductive layer extends to the lower side of the second dam close to the substrate.

[0013] In an exemplary embodiment, in the first peripheral area, in the direction away from the display area, the edge of the second conductive part orthogonally projected on the substrate is located within the range of the first planar layer orthogonally projected on the substrate; and the edge of the fourth conductive part orthogonally projected on the substrate is located within the range of the second planar layer orthogonally projected on the substrate.

[0014] In an example embodiment, a projection of the fourth conductive portion on the substrate covers an edge of a projection of the second conductive portion on the substrate in the first peripheral area in a direction away from the display area.

[0015] In an example embodiment, the third planar layer includes a third planar portion, a projection of the third planar portion on the substrate covers an edge of a projection of the second planar layer on the substrate in the first peripheral area in a direction away from the display area.

[0016] In an example embodiment, a dimension between an edge of the third planar portion and an edge of the second planar layer is a fifth overlap dimension in the first peripheral area in a direction away from the display area, the fifth overlap dimension is greater than or equal to 18 microns.

[0017] In an example embodiment, a height of the third planar portion in a direction perpendicular to the substrate is greater than a height of the first dam base in the direction perpendicular to the substrate.

[0018] In an example embodiment, in the second peripheral area, the display panel further includes a connection electrode, the connection electrode is located on a side of the third planar layer away from the substrate, the connection electrode is connected with the second power supply line, in the second peripheral area, the connection electrode extends to below a side of the second dam close to the substrate.

[0019] In an example embodiment, in the second peripheral area in a direction away from the display area, an edge of a projection of the fourth conductive layer on the substrate is located within a range of a projection of the first planar layer on the substrate; the edge of the projection of the fourth conductive layer on the substrate, the edge of the projection of the first planar layer on the substrate, the edge of the projection of the fifth conductive layer on the substrate and the edge of the projection of the third conductive layer on the substrate are located within a range of a projection of the third dam base on the substrate.

[0020] In an example embodiment, in the second peripheral area in a direction away from the display area, a projection of the third conductive layer on the substrate covers an edge of a projection of the fifth conductive layer on the substrate.

[0021] In an example embodiment, in the second peripheral area, the first dam further includes a fifth dam base, the second dam further includes a sixth dam base; the fifth dam base is located on a side of the third dam base away from the substrate, the sixth dam base is located on a side of the fourth dam base away from the substrate.

[0022] In an exemplary embodiment, the display panel further comprises a third dam surrounding the display area and located on a side of the second dam away from the display area; the display panel further comprises a second power supply line; in the first peripheral area and the second peripheral area, the second power supply line extends to below a side of the third dam close to the substrate after passing through the first dam and the second dam.

[0023] In an exemplary embodiment, the third dam comprises a seventh dam base, an eighth dam base and a ninth dam base, the seventh dam base is located on the first flat layer, the eighth dam base is located on the second flat layer, and the ninth dam base is located on the third flat layer.

[0024] In an exemplary embodiment, in a direction away from the display area, a distance between the second dam and the third dam is an eighth distance, the eighth distance is a minimum distance between opposite side surfaces of the second dam and the third dam, the eighth distance is greater than or equal to 36 microns and less than or equal to 44 microns.

[0025] In a second aspect, the embodiments of the present disclosure provide a display device comprising the display panel as described above.

[0026] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0027] SUMMARY

[0028] The accompanying drawings are included to provide a further understanding of the present technical solution, and constitute a part of the specification, together with the embodiments of the present disclosure, for explaining the technical solution of the present disclosure, and do not constitute a limitation on the technical solution of the present disclosure.

[0029] FIG. 1 is a structural schematic diagram of a display panel in some technologies;

[0030] FIG. 2 is a partial cross-sectional schematic diagram of a display area in FIG. 1;

[0031] FIG. 3 is a cross-sectional view of AA in FIG. 1;

[0032] FIG. 4 is a cross-sectional view of AA in FIG. 1 in an exemplary embodiment;

[0033] FIG. 5 is a cross-sectional view of AA in FIG. 1 in another exemplary embodiment;

[0034] FIG. 6 is a schematic diagram of a connection electrode damage in an exemplary embodiment;

[0035] FIG. 7 is a schematic diagram of a fifth overlap size in an exemplary embodiment;

[0036] FIG. 8 is a diagram of the positional relationship of the first dam, the second dam, and the second power line boundary at the right side frame in an exemplary embodiment;

[0037] FIG. 9 is a diagram of the stacking of the first dam and the second dam at the right side frame in an exemplary embodiment;

[0038] FIG. 10 is a cross-sectional view of FIG. 1 in AA direction in yet another exemplary embodiment;

[0039] FIG. 11 is a diagram of the positional relationship of the first dam, the second dam, the third dam, and the second power line boundary at the right side frame in an exemplary embodiment;

[0040] FIG. 12 is a diagram of the stacking of the first dam, the second dam, and the third dam at the right side frame in an exemplary embodiment;

[0041] FIG. 13 is a diagram of the stacking of the first dam, the second dam, and the third dam at the right side frame in yet another exemplary embodiment.

[0042] DETAILED DESCRIPTION

[0043] The present disclosure describes a number of embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that numerous embodiments and implementations can be made without departing from the scope of the embodiments described in the disclosure. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically intended otherwise, any feature or element of any embodiment can be used in combination with any other feature or element of any other embodiment, or in combination with any other feature or element of the same embodiment.

[0044] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed herein can also be combined with any conventional features or elements to form a unique application that is defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other applications to form another unique application that is defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be used, alone or in any appropriate combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the attached claims.

[0045] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of such steps, the method or process is not limited to the performance of the steps in the specific order described. One of ordinary skill in the art, with the benefit of this disclosure, will appreciate that other steps can be performed and the method or process presented herein is intended to cover any and all methods and processes comprising performance of such steps in any order.

[0046] In the drawings, the size, the thickness or the region of one or more constituent elements shown in the drawings can be exaggerated for clarity. Further, the present disclosure is not limited to the shape, the numerical value, etc. shown in the drawings.

[0047] The ordinal numbers "first", "second", "third" and the like in the specification are used to avoid confusion among constituent elements, and are not intended to indicate or imply a specific order or a specific relative position among the constituent elements. The "a plurality of" in the present disclosure indicates a number of two or more.

[0048] In the present specification, the words "include" and "comprise" and the like used herein specify the presence of the stated elements but do not preclude the presence or addition of one or more other elements. In the present specification, the words "example" and "exemplary" are used herein to mean an instance of the general case, and for purposes of explanation and illustration. If it is stated herein that a component "can" or "can not" be included in a composition or method, it is intended that the component can or can not be included in the composition or method, as desired.

[0049] In the present specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate parts, or internal communication of two elements. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the circumstances.

[0050] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain terminal, a drain region, or a drain electrode) and the source electrode (a source terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0051] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current flowing in a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0052] In this specification, "electrically connected" includes the case where components are connected through an element having some function. An element having some function is not particularly limited as long as it can transmit an electrical signal between components to be connected. Examples of an element having some function include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0053] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0054] Embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0055] FIG. 1 is a structural schematic diagram of a display panel in some technologies. As shown in FIG. 1, the display panel provided in the embodiments includes a display area 100 and a non-display area located at the periphery of the display area 100. The non-display area includes a binding area 400 located at one side of the display area 100 along a second direction Y, a first peripheral area 200 located between the display area 100 and the binding area 400, and a second peripheral area 300 located at the periphery of the display area 100 and away from the side of the binding area 400. The first peripheral area 200 and the second peripheral area 300 are in communication and surround the display area 100. The display area 100 includes at least a plurality of pixel units arranged in a regular manner, for example, the plurality of pixel units can be arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y are perpendicular to each other. The plurality of pixel units are configured to display dynamic pictures or static images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display panel can be deformable, for example, curled, bent, folded or rolled up. The display panel includes an upper side frame and a lower side frame oppositely arranged along the second direction Y, and a left side frame and a right side frame oppositely arranged along the first direction X, and the lower side frame is the side frame on the side of the binding area 400, and the side frame on the side opposite to the binding area 400 along the second direction Y can be referred to as the upper side frame, and the right side frame is located on one side of the left side frame along the first direction X.

[0056] In an exemplary embodiment, the shape of the display area 100 can be a quadrilateral, a circle, an ellipse, a polygon of other shapes or an irregular shape, etc., and the corner shape of the display area 100 can be a rounded corner, which is not limited in the present disclosure.

[0057] In an exemplary embodiment, the first peripheral area 200 includes at least a dam and a power supply line for transmitting a voltage signal to the plurality of pixel units. The binding area 400 includes a circuit for connecting a signal line of the plurality of pixel units to an external driving device. The second peripheral area 300 includes at least a dam and a power supply line for transmitting a voltage signal to the plurality of pixel units. The dams of the first peripheral area 200 and the second peripheral area 300 can form a ring structure surrounding the display area 100. The binding area 400 includes a plurality of bonding pads configured to be bonded to an external flexible printed circuit (FPC) or chip on flex (COF).

[0058] As shown in FIG. 1, the power lines can include a first power line 210 and a second power line 220, the first power line 210 can be connected with a high-voltage power line (VDD) of the display area 100 and configured to transmit a high-voltage signal to the plurality of display units of the display area 100. The second power line 220 is connected with a low-voltage power line (VSS) of the display area 100 to transmit a low-voltage signal to the plurality of pixel units of the display area 100, and the second power line 220 can be distributed in the first peripheral area 200 and the second peripheral area 300, and the second power line 220 can surround the display area 100.

[0059] As shown in FIG. 1, the main body part of the first power line 210 of the first peripheral area 200 can extend along the first direction X, and the first power line 210 further includes an extension part, one end of the extension part can be connected with the main body part, and the other end of the extension part can be connected with a pad corresponding to the binding area 400 to receive a corresponding high-voltage signal. The second power line 220 of the first peripheral area 200 can be arranged on both sides of the first power line 210 along the first direction X, and the second power line 220 in the second peripheral area 300 can be arranged to surround the display area 100, one end of the second power line 220 of the first peripheral area 200 can be connected with the second power line 220 of the second peripheral area 300, and the other end of the second power line 220 of the first peripheral area 200 can be connected with a pad corresponding to the binding area 400 to receive a corresponding low-voltage signal. In an exemplary embodiment, the first direction X can be a direction of extension parallel to the edge of the display area 100 close to the side of the first peripheral area 200. That is, the first direction X is a direction of extension parallel to the display area edge 110. In an exemplary embodiment, the display area 100 has an edge on the upper frame, the lower frame, the left frame and the right frame respectively, and the display area edge 110 is the edge of the display area 100 on the side of the lower frame, and the "direction away from the display area" or "direction away from the display area edge" in the embodiment of the present disclosure refers to a direction away from the display area range and perpendicular to the edge of the display area at the frame in the display area plane.

[0060] In an exemplary embodiment, the shapes of the display area edges at different frames are different from each other and vary with the shape of the display area, for example, can be straight lines, curves, broken lines and the like, and the present disclosure does not limit this.

[0061] As shown in FIG. 1, the dam can include a first dam 410 and a second dam 420, and the second dam 420 can be located on a side of the first dam 410 away from the display area 100. In the second peripheral area 300, the orthographic projection of the first dam 410 on the display panel can overlap the orthographic projection of the second power line 220 on the substrate, the orthographic projection of the second dam 420 on the display panel can overlap the orthographic projection of the second power line 220 on the display panel, and the orthographic projection of the second dam 420 can surround the orthographic projection of the second power line 220 on the display panel, that is, in the second peripheral area 300, the second power line 220 can extend below the second dam 420, and the present disclosure does not make any limitation in this regard.

[0062] In an example embodiment, the binding area 400 can include a fan-out area, a driving chip area and a binding pin area arranged in sequence in a direction away from the display area 100. The fan-out area is connected to the display area 100 and can include at least a plurality of parallel data lead-out lines. For example, the first power line 210 can be connected to the high-voltage power line of the display area 100 through fan-out wiring, and the second power line 220 can be connected to the low-voltage power line of the display area 100 through fan-out wiring. The driving chip area can include at least an integrated circuit (IC) configured to be connected to the plurality of data fan-out lines. The binding pin area can include at least a plurality of bonding pads configured to be connected to an external flexible printed circuit (FPC).

[0063] In an example embodiment, the binding area 400 can further include a bending area, which can be located between the fan-out area and the driving chip area, and the bending area connected to the fan-out area can include a composite insulating layer provided with a groove and configured to bend the binding area 400 to the back of the display area 100.

[0064] FIG. 2 is a schematic diagram of a partial cross-section of the display area in FIG. 1. In FIG. 2, the structure of one sub-pixel of the display area is taken as an example for illustration. In this example, the same type of multiple transistors in the pixel driving circuit is taken as an example for illustration, for example, the multiple transistors in the pixel driving circuit can all be low-temperature polysilicon thin film transistors or all be oxide thin film transistors.

[0065] In a direction perpendicular to the display panel, the display panel of the display area 100 can include a circuit structure layer, a light emitting structure layer, an encapsulation layer, a touch layer, a polarizer, and a cover plate, etc. As shown in FIG. 2, the display panel of the display area 100 can include a substrate 10, and a buffer layer 501, a semiconductor layer, a first gate insulating layer 502, a first conductive layer 11, a first insulating layer 12, a second conductive layer 13, a second insulating layer 14, a fourth conductive layer 15, a first planarization layer 16, a fifth conductive layer 17, a second planarization layer 18, a third conductive layer 19, a third planarization layer 20, an anode layer 503, a pixel definition layer 21, a cathode layer 504, a first inorganic layer 505, an organic layer 506, a second inorganic layer 507, a touch layer 508, a polarizer 509, and a cover plate 24 which are sequentially arranged on the substrate 10. In the exemplary embodiment, the first conductive layer 11 can be referred to as a first gate layer, the second conductive layer 13 can be referred to as a second gate layer, the fourth conductive layer 15 can be referred to as a first source-drain electrode layer, the fifth conductive layer 17 can be referred to as a second source-drain electrode layer, and the third conductive layer 19 can be referred to as a third source-drain electrode layer.

[0066] In the exemplary embodiment, the circuit structure layer can include film layers between the buffer layer 501 and the third conductive layer 19. The buffer layer 501 can prevent harmful substances in the substrate 10 from invading the inside of the display panel, and can also increase the adhesion of the film layers in the display panel to the substrate 10. The transistor T1 can include an active layer, a gate, a first electrode, and a second electrode, the active layer can be located in the semiconductor layer, the gate can be located in the first conductive layer 11, and the first electrode and the second electrode can be located in the fourth conductive layer 15. The capacitor can include a second plate C2 and a first plate C1, the second plate C2 and the first plate C1 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide, the first plate C1 can be located in the first conductive layer 11, and the second plate C2 can be located in the second conductive layer 13. The transistor T1 can be connected by a first conversion electrode 175 and a second conversion electrode 195 and the anode layer 503, the first conversion electrode 175 can be located in the fifth conductive layer 17, and the second conversion electrode 195 can be located in the third conductive layer 19.

[0067] In an example embodiment, the light-emitting structure layer can include a pixel definition layer 21 and a plurality of light-emitting elements. For example, each light-emitting element can include a stacked anode layer 503, an organic light-emitting layer 600, and a cathode layer 504. The anode layer 503 can be disposed on the first planar layer 16 and electrically connected to the first electrode of the transistor T1 through a pixel via hole of the first planar layer 16. The pixel definition layer 21 can be disposed on the anode layer 503 and the first planar layer 16, and the pixel definition layer 21 can be provided with a plurality of pixel openings, each of which can expose at least part of the surface of a corresponding anode layer 503. At least part of the organic light-emitting layer 600 can be disposed in one pixel opening and connected to the corresponding anode layer 503. The cathode layer 504 can be disposed on the organic light-emitting layer 600 and connected to the organic light-emitting layer 600. The organic light-emitting layer 600 can emit light of a corresponding color under the drive of the anode layer 503 and the cathode layer 504. In an example embodiment, a spacer (PS) 601 can be disposed on the side of the pixel definition layer 21 away from the substrate 10, but the present disclosure is not limited thereto.

[0068] In an example embodiment, the organic light-emitting layer 600 of the light-emitting element can include an emitting layer (EML) and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the anode layer 503 and the cathode layer 504, the organic material can emit light according to the required gray scale by utilizing the light-emitting property of the organic material.

[0069] In the example embodiments, the light-emitting layers of the light-emitting elements emitting different colors of light can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and the isolation can be achieved by the surface step of the formed film layer or by surface treatment and the like. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0070] In the example embodiments, the encapsulation layer can include a first inorganic layer 505, an organic layer 506, and a second inorganic layer 507 stacked, wherein the first inorganic layer 505 and the second inorganic layer 507 can adopt inorganic materials, the second encapsulation layer 142 can adopt an organic material, and the organic layer 506 can be arranged between the first inorganic layer 505 and the second inorganic layer 507 to ensure that external water vapor cannot enter the light-emitting element. However, the present embodiment is not limited thereto. For example, the encapsulation layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0071] In the example embodiments, the touch layer 508 can include multiple layers of metal film layers, and the present disclosure does not limit the structure of the touch layer 508 and the principle of realizing the touch function.

[0072] FIG. 3 is a cross-sectional view of FIG. 1 in AA direction, omitting the film layer structure of the display panel. As shown in FIG. 3, in the direction perpendicular to the display panel, the display panel of the lower bezel can include the substrate 10, and the first conductive layer 11, the first insulating layer 12, the second conductive layer 13, the second insulating layer 14, the fourth conductive layer 15, the first planar layer 16, the fifth conductive layer 17, the second planar layer 18, the third conductive layer 19, the third planar layer 20, the pixel definition layer 21, the organic light-emitting layer 600, the cathode layer 504, the encapsulation layer, and the touch layer 508 arranged in sequence on the substrate 10. In FIG. 3, the film layer on the side of the pixel definition layer 21 away from the substrate 10 is omitted and replaced by a reference numeral 22. The cover plate 24 corresponding to the position of the lower bezel is also provided with an ink layer 23 on the side of the cover plate 24 close to the substrate 10. After the cover plate 24 is attached, the orthographic projection of the ink layer 23 on the substrate 10 at least partially covers the first peripheral region, which can prevent light leakage of the lower bezel of the display panel. The first conductive layer 11 can include a plurality of first signal lines 111, and the second conductive layer 13 can include a plurality of second signal lines 131. The first signal lines 111 and the second signal lines 131 can extend in the same direction and be arranged alternately. The types of signals transmitted by the first signal lines 111 and the second signal lines 131 can be set as needed. The fourth conductive layer 15 can include a first power line 210 and a second power line 220. The first power line 210 is located on the side of the second power line 220 close to the display area 100. The orthographic projection of the second planar layer 18 on the substrate 10 can cover the orthographic projection of the first planar layer 16 on the substrate 10. The third planar layer 20 can include a third planar portion 201 covering the third conductive layer 19, a first dam base 202, and a second dam base 203. The first dam base 212 is used to form the first dam 410, and the second dam base 213 is used to form the second dam 420. The pixel definition layer 21 can include a pixel definition portion 211 on the side of the third planar portion 201 away from the substrate 10, a third dam base 212 on the side of the first dam base 202 away from the substrate 10, and a fourth dam base 213 on the side of the second dam base 203 away from the substrate 10. The first dam 410 is composed of the first dam base 202 and the third dam base 212, and the second dam 420 is composed of the second dam base 203 and the fourth dam base 213. The second power line 220 can extend directly below the second dam 420. In the embodiments of the present disclosure, "below the dam" or "directly below the dam" means on the side of the dam close to the substrate 10. In the case where the dam includes different dam bases, "below the dam" or "directly below the dam" can mean on the side of any one dam base close to the substrate 10.

[0073] The present inventors have found that the coating film precision of the ink layer 23 is about 170 microns, and the maximum value is about 340 microns. In the case of a narrow frame, for example, in the case where the distance from the lower frame edge to the display area edge 110 is less than or equal to 626 microns, the ink layer 23 cannot completely cover the lower frame, and the side of the lower frame close to the display area edge 110 will be exposed, forming a light leakage area as shown by the D area in FIG. 3. Since the first signal lines 111 and the second signal lines 131 extend in the same direction and are arranged alternately, the surfaces of the first insulating layer 12 and the second insulating layer 14 are uneven, and the surface of the second power supply line 220 located on the side of the second insulating layer 14 away from the substrate 10 also presents an uneven topography. After the natural light L is incident on the display panel from the side of the cover plate 24, the light will be diffusely reflected on the surface of the second power supply line 220, and the reflected light will be emitted from the cover plate 24 of the D area, causing the user to see the light leakage of the lower frame of the display panel.

[0074] The display panel provided by the embodiments of the present disclosure includes a display area, a binding area located on one side of the display area, and a first peripheral area located on the side of the binding area close to the display area; the display panel includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer, and a cover plate arranged on the substrate in sequence, and the cover plate is provided with an ink layer on the side close to the substrate; in the first peripheral area, the first conductive layer includes a plurality of first signal lines, the second conductive layer includes a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and extend in the same direction; the ink layer is at least partially overlapped with the first peripheral area in the orthographic projection on the substrate; the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and the plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate are at least partially overlapped.

[0075] The display panel provided by the embodiments of the present disclosure can shield the lower frame area not covered by the ink by the mutual overlap of the third conductive layer of the lower frame and the ink layer in the direction perpendicular to the substrate, thereby solving the problem of light leakage of the lower frame of the display panel.

[0076] FIG. 4 is a cross-sectional view of AA in FIG. 1 in an exemplary embodiment, and the rest of the structure of the display panel is omitted. The difference between FIG. 4 and FIG. 3 is that the size of the third conductive layer 19 is different, and the rest can be referred to the description of FIG. 3 above, which will not be repeated here.

[0077] As shown in FIG. 4, at the lower bezel, the orthographic projection of the third conductive layer 19 on the substrate 10 and the orthographic projection of the ink layer 23 on the substrate 10 overlap each other. In the direction away from the display area 100, the overlapping size of the third conductive layer 19 and the ink layer 23 is a first overlapping size Z1, which can be set to be greater than or equal to 18 microns, for example, the first overlapping size Z1 can be set to be greater than or equal to 20 microns, which is not limited in the present disclosure.

[0078] In an exemplary embodiment, the display panel can include a touch layer, the orthographic projection of the metal film layer in the touch layer on the substrate 10 can overlap the orthographic projection of the ink layer 23 on the substrate 10, and in the direction away from the display area 100 near the lower bezel, the distance between the edge of the touch layer and the display area edge 110 is greater than the distance between the edge of the third conductive layer 19 and the display area edge 110, so that the touch layer can continue to shield light in the position not covered by the third conductive layer 19, which is not limited in the present disclosure.

[0079] The present inventors have found through research that, in the display panel shown in FIGS. 3 and 4, in order to form the first dam 410 and the second dam 420, the first planar layer 16 near the first dam 410 and the second dam 420 needs to be excavated, so that the fourth conductive layer 15 is exposed, and in the subsequent process of forming the fifth conductive layer 17, the metal of the fourth conductive layer 15 is prone to over-etching, undercutting occurs at the edge of the fourth conductive layer 15, and cracks occur in the subsequently formed film layer. For example, in the case where the fourth conductive layer 15 adopts a titanium / aluminum / titanium (Ti / AL / Ti) stacked structure, the aluminum metal layer of the fourth conductive layer 15 will be over-etched in the process of forming the fifth conductive layer 17. During reliability testing or in the process of using the display panel, these cracks are prone to cause gaps or breakage of the encapsulation layer, and water vapor in the atmosphere will enter the display panel along the gaps, and the invading water vapor is prone to oxidize the organic material in the light-emitting structure layer, forming a failure area that cannot emit light. As the water vapor continuously invades the light-emitting device along the gap, the failure area gradually expands, causing the display panel to display poorly, forming a growing dark spot (GDS), and the GDS at the lower bezel of the display panel is called GDSX defect.

[0080] FIG. 5 is a cross-sectional view of AA in FIG. 1 in another exemplary embodiment, and the rest of the structure of the display panel is omitted. The difference between FIG. 5 and FIG. 4 is that the structures of the first power supply line 210 and the second power supply line 220 are different, and the rest of the structure can be referred to the description of FIG. 4 above, which will not be described here.

[0081] As shown in FIG. 5, at the lower frame, the fourth conductive layer 15 includes a first conductive part 151 and a second conductive part 152 insulated from each other, the second conductive part 152 is located on the side of the first conductive part 151 away from the display area 100, the orthographic projection of the first conductive part 151 and the second conductive part 152 on the substrate 10 is located within the range of the orthographic projection of the first planar layer 16 on the substrate 10, in the direction away from the display area 100 at the lower frame, the size between the edge of the second conductive part 152 and the edge of the first planar layer 16 is a second overlap size Z2, that is, the size of the edge of the second conductive part 152 covered by the first planar layer 16. In an exemplary embodiment, the second overlap size Z2 can be greater than or equal to 9 microns, for example, the second overlap size Z2 can be greater than or equal to 10 microns, which is not limited in the present disclosure. By setting the edge of the second conductive part 152 covered by the first planar layer 16, when the metal film layer is subsequently formed above the fourth conductive layer 15, the edge of the second conductive part 152 will not be over-etched, which helps to maintain the edge profile of the second conductive part 152 and avoids cracks in the film layer of the display panel. The orthographic projection of the second conductive part 152 on the substrate 10 does not overlap the orthographic projection of the first dam 410 on the substrate 10.

[0082] As shown in FIG. 5, the fifth conductive layer 17 includes a third conductive part 171 and a fourth conductive part 172 insulated from each other, the fourth conductive part 172 is located on the side of the third conductive part 171 away from the display area 100, the orthographic projection of the third conductive part 171 and the fourth conductive part 172 on the substrate 10 can be located within the range of the orthographic projection of the second planar layer 18 on the substrate 10, in the direction away from the display area 100, the size between the edge of the fourth conductive part 172 and the edge of the second planar layer 18 is a third overlap size Z3, that is, the size of the edge of the fourth conductive part 172 covered by the second planar layer 18. In an exemplary embodiment, the third overlap size Z3 can be greater than or equal to 4.5 microns, for example, the third overlap size Z3 can be greater than or equal to 5 microns, in some examples, the third overlap size Z3 can be greater than or equal to 10 microns, which is not limited in the present disclosure. By setting the edge of the fourth conductive part 172 covered by the second planar layer 18, when the metal film layer is subsequently formed above the fifth conductive layer 17, the edge of the fourth conductive part 172 will not be over-etched, which helps to maintain the edge profile of the fourth conductive part 172 and avoids cracks in the film layer of the display panel.

[0083] In an example embodiment, the fourth conductive part 172 can cover the orthogonal projection of the second conductive part 152 on the substrate 10. In the direction away from the display area 100, the size between the edge of the fourth conductive part 172 and the edge of the second conductive part 152 is a fourth overlap size Z4, that is, the size of the edge of the second conductive part 152 covered by the fourth conductive part 172. In an example embodiment, the fourth overlap size Z4 can be greater than or equal to 4.5 microns, for example, the fourth overlap size Z4 can be greater than or equal to 5 microns, in some examples, the fourth overlap size Z4 can be greater than or equal to 30 microns, which is not limited in the present disclosure. By setting the fourth conductive part 172 to cover the edge of the second conductive part 152, so that when the fourth conductive part 172 is formed, the edge of the second conductive part 152 is shielded by the fourth conductive part 172, further avoiding the second conductive part 152 from being etched, and avoiding the film layer of the display panel from cracking. The orthogonal projection of the fourth conductive part 172 on the substrate 10 does not overlap with the orthogonal projection of the first dam 410 on the substrate 10.

[0084] In an example embodiment, the orthogonal projection of the third conductive part 171 on the substrate 10 can overlap with the orthogonal projection of the first conductive part 151 on the substrate 10, for example, the orthogonal projection of the third conductive part 171 on the substrate 10 can coincide with the orthogonal projection of the first conductive part 151 on the substrate 10.

[0085] In an example embodiment, the first power line 210 can include the first conductive part 151 and the third conductive part 171, and the first conductive part 151 and the third conductive part 171 can be connected through a via hole (not shown in the figure).

[0086] As shown in FIG. 5, the third conductive layer 19 can extend directly below the second dam 420, and the second power line 220 can include the second conductive part 152, the fourth conductive part 172, and part of the third conductive layer 19, and the second conductive part 152, the fourth conductive part 172, and part of the third conductive layer 19 can be connected in sequence through a via hole (not shown in the figure). In the direction away from the display area 100 at the lower frame, the overlap size between the edge of the third flat part 201 and the edge of the second flat layer 18 is a fifth overlap size Z5, that is, the size of the edge of the second flat layer 18 covered by the third flat part 201. In an example embodiment, the fifth overlap size Z5 can be greater than or equal to 18 microns, for example, the fifth overlap size Z5 can be greater than or equal to 20 microns, which is not limited in the present disclosure. By setting the fifth overlap size Z5 to be greater than or equal to 18 microns, the edge of the third flat part 201 can have a relatively gentle slope, and the organic material of the organic layer 506 is not easy to overflow during the subsequent formation of the encapsulation layer, which can ensure the success rate and encapsulation effect of the encapsulation.

[0087] In the exemplary embodiments, the display panel is provided with a connecting electrode at the upper, left and right side frames, which can be provided in the same layer as the anode layer 503 of the display panel, and can be connected with the second power supply line 220, thereby helping to reduce the voltage drop of the low voltage signal during transmission. However, the connecting electrode is prone to damage during preparation.

[0088] FIG. 6 is a schematic diagram of the damage of the connecting electrode in an exemplary embodiment, which illustrates the cross-sectional view of the display panel in the direction of BB in FIG. 1, and omits the film layer structure of the display panel. The case of the connecting electrode at the upper and left side frames can be similar to that at the right side frame, and will not be described herein again. As shown in FIG. 6, it is found by the inventors of the present application that, since the height H of the first dam base 202 of the first dam 410 in the direction perpendicular to the substrate 10 is relatively high, after the anode layer film A1 is formed and the photoresist P1 is coated, the photoresist P1 cannot cover the anode layer film A1 located above the first dam 410, and thus the anode layer film A1 located above the first dam base 202 is damaged after exposure, which causes the connecting electrode to be disconnected near the first dam base 202, thereby affecting the display uniformity of the display panel. Moreover, after the pixel definition layer 21 is formed, the first dam base 202 is covered by the third dam base 212, and the damage of the connecting electrode is covered by the first dam 410, thereby making it difficult to find the cause of the damage of the connecting electrode. In FIG. 6, the film layer between the substrate 10 and the fourth conductive layer 15 is denoted by reference numeral 31, and this part of the structure can be designed as needed, which is not limited in the present disclosure.

[0089] In order to solve the problem of the damage of the connecting electrode, the height of the first dam base 202 can be set to be less than the height of the third flat part 201 provided in the same layer, thereby reducing the height of the anode layer film A1 protruding above the first dam base 202, so that the photoresist P1 can completely cover the anode layer film A1 located above the first dam 410. In the exemplary embodiments, the different heights of the third flat layer 20 at different positions can be realized by using mask plates with different light transmittances, for example, the first dam base 202 can be formed by using a halftone mask, and the third flat part 201 can be formed by using a general mask. In this way, the height of the first dam base 202 is about half of the height of the third flat part 201. Other methods for realizing the different heights of the third flat layer 20 at different positions can also be used, which is not limited in the present disclosure. By reducing the height of the first dam 410, it is helpful to increase the flatness of the ink jet printing (IJP) organic material at the edge of the encapsulation layer, thereby ensuring the success rate and encapsulation effect of encapsulation.

[0090] FIG. 7 is a schematic diagram of a fifth overlap size in an example embodiment, and the rest of the structure of the display panel is omitted. In an example embodiment, the edge of the second flat portion 201 at the lower bezel can be formed by a common mask plate and a half-tone mask plate together, and the mask plates with different transmittances make the edge slope of the second flat portion 201 appear different. As shown in FIG. 7, the first slope surface can be formed by using a common mask plate near one side of the display area 100, and the second slope surface can be formed by using a half-tone mask plate away from the display area 100, and the fifth overlap size Z5 in FIG. 5 can be the distance between the edge of the second slope surface and the edge of the second flat layer 18 in the direction away from the display area 100. In an example embodiment, the distance between the edge of the first slope surface and the edge of the second flat layer 18 can be a first size S1, the distance between the edge of the first slope surface and the edge of the second slope surface can be a second size S2, and the fifth overlap size Z5 can be the sum of the first size S1 and the second size S2. In an example embodiment, the first size S1 can be greater than or equal to 9 microns, for example, the first size S1 can be greater than or equal to 10 microns, and the second size S2 can be greater than or equal to 9 microns, for example, the second size S2 can be greater than or equal to 10 microns, which is not limited in the present disclosure.

[0091] FIG. 8 is a positional relationship diagram of the first dam, the second dam, and the second power line boundary at the right bezel in an example embodiment, and the film layer structure of the display panel is omitted, and the positional relationship of the first dam, the second dam, and the second power line boundary at the upper bezel and the left bezel of the display panel can be the same as that at the right bezel, which will not be described herein. As shown in FIG. 8, the orthographic projection of the boundary T1 of the second power line 220 away from the display area 100 on the substrate 10 can be located within the orthographic projection of the second dam 420 on the substrate 10. The second power line 220 can be a single-layer structure or a stacked structure, for example, the second power line 220 can be located on the fourth conductive layer 15, or the second power line 220 can be located on the fourth conductive layer 15 and the fifth conductive layer 17, or the second power line 220 can be located on the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19, which is not limited in the present disclosure.

[0092] FIG. 9 is a schematic view of the stack of the first dam and the second dam at the right side frame in an exemplary embodiment, and the film layer structure of the display panel is omitted. The stack of the first dam and the second dam at the upper side frame and the left side frame of the display panel can be the same as that at the right side frame, and thus is not described herein. As shown in FIG. 9, the second power line 220 can be located on the fourth conductive layer 15, the fifth conductive layer 17 and the third conductive layer 19, and the fourth conductive layer 15, the fifth conductive layer 17 and the third conductive layer 19 contact each other and extend to directly below the second dam 420 at the right side frame. The edge of the fourth conductive layer 15 on the substrate 10 is projected within the projection of the first planar layer 16 on the substrate 10, so that the edge of the fourth conductive layer 15 can be protected. In the direction away from the display area 100, the size between the edge of the fourth conductive layer 15 and the edge of the first planar layer 16 is the sixth overlap size Z6. In an exemplary embodiment, the sixth overlap size Z6 can be greater than or equal to 4.5 microns, for example, the sixth overlap size Z6 can be greater than or equal to 5 microns, which is not limited in the present disclosure. The edge of the third conductive layer 19 on the substrate 10 covers the edge of the fifth conductive layer 17 on the substrate 10, and in the direction away from the display area 100, the size between the edge of the third conductive layer 19 and the edge of the fifth conductive layer 17 is the seventh overlap size Z7. In an exemplary embodiment, the seventh overlap size Z7 can be greater than or equal to 4.5 microns, for example, the seventh overlap size Z7 can be greater than or equal to 5 microns, which is not limited in the present disclosure. The first dam base 202 can be formed by a half-tone mask, so that the height of the first dam base 202 is less than the height of the second dam base 203. The projection of the third dam base 203 on the substrate 10 can cover the edges of the fourth conductive layer 15, the first planar layer 16, the fifth conductive layer 17 and the third conductive layer 19 on the substrate 10, so as to protect these metal film layers. The connecting electrode 301 can be directly connected to the third conductive layer 19, so as to transmit a low voltage signal. The projection of the connecting electrode 301 on the substrate 10 can cover the projection of the first dam base 202 on the substrate 10, and the projection of the connecting electrode 301 on the substrate 10 can at least partially overlap the projection of the second dam base 203 on the substrate 10. At the right side frame, the first dam 410 can further include a fifth dam base 302 located on the side of the third dam base 212 away from the substrate 10, and the projection of the fifth dam base 302 on the substrate 10 can be located within the projection of the third dam base 212 on the substrate 10. The second dam 420 can further include a sixth dam base 303 located on the side of the fourth dam base 213 away from the substrate 10, and the projection of the sixth dam base 303 on the substrate 10 can be located within the projection of the fourth dam base 213 on the substrate 10. The fifth dam base 302 and the sixth dam base 303 can be arranged in the same layer as the isolation column 601 of the display area 100.

[0093] FIG. 10 is a cross-sectional view of AA in FIG. 1 in another exemplary embodiment, omitting the structure of the display panel. FIG. 10 differs from FIG. 5 in that a third dam 430 is added, and the second power line 220 is directly extended right below the third dam 430. The rest of the structure can be referred to the description of FIG. 5 above, and will not be repeated here.

[0094] As shown in FIG. 10, the display panel can further include a third dam 430, which can be located on the side of the second dam 420 away from the display area 100, and surround the second dam 420. By directly extending the second power line 220 right below the third dam 430, not only the design of the second power line 220 is not limited by the position of the second dam 420, increasing the flexibility of the design of the display panel, but also the width of the second power line at the frame can be increased, reducing the impedance of the second power line, improving the display quality, especially the display quality of the display panel in high brightness display.

[0095] As shown in FIG. 10, the third dam 430 can include a seventh dam base 162, an eighth dam base 182, and a ninth dam base 204. The orthographic projection of the eighth dam base 182 on the substrate 10 can cover the orthographic projection of the seventh dam base 162 on the substrate 10, and the orthographic projection of the ninth dam base 204 on the substrate 10 can be located within the orthographic projection of the eighth dam base 182 on the substrate 10. The seventh dam base 162 can be located on the first flat layer 16, and the orthographic projection of the first flat portion 161 of the first flat layer 16 on the substrate 10 can cover the orthographic projections of the first conductive portion 151 and the second conductive portion 152 on the substrate 10. The eighth dam base 182 can be located on the second flat layer 18, and the orthographic projection of the second flat portion 181 of the second flat layer 18 on the substrate 10 can cover the orthographic projections of the third conductive portion 171 and the fourth conductive portion 172 on the substrate 10. The ninth dam base 201 can be located on the third flat layer 20.

[0096] In an exemplary embodiment, the third dam 430 can further include a tenth dam base 214, and the orthographic projection of the tenth dam base 214 on the substrate 10 can be located within the orthographic projection of the ninth dam base 201 on the substrate 10. The tenth dam base 214 can be located on the pixel definition layer 21.

[0097] As shown in FIG. 10, the distance between the second dam 420 and the third dam 430 in the direction away from the display area 100 can be an eighth distance Z8, and the eighth distance Z8 can be the minimum distance between the opposite side surfaces of the fourth dam base 213 and the eighth dam base 182. In an exemplary embodiment, the eighth distance Z8 can be greater than or equal to 36 microns and less than or equal to 44 microns, for example, the eighth distance Z8 can be about 40 microns. The distance between the eighth dam base 182 and the seventh dam base 162 in the direction away from the display area 100 can be a ninth distance Z9, and the ninth distance Z9 can be greater than or equal to 18 microns and less than or equal to 22 microns, for example, the ninth distance Z9 can be about 20 microns. The distance between the eighth dam base 182 and the ninth dam base 204 in the direction away from the display area 100 can be a tenth distance Z10, and the tenth distance Z10 can be greater than or equal to 9 microns and less than or equal to 11 microns, for example, the tenth distance Z10 can be about 10 microns. The distance between the ninth dam base 204 and the tenth dam base 214 in the direction away from the display area 100 can be an eleventh distance Z11, and the eleventh distance Z11 can be greater than or equal to 9 microns and less than or equal to 11 microns, for example, the eleventh distance Z11 can be about 10 microns. The distance between the second dam 420 and the third dam 430, and the distance between the dam bases of the third dam 430 itself can be set as needed to control the profile and degree of inclination of the third dam 430 on the side close to the second dam 420, and the present disclosure does not limit this.

[0098] FIG. 11 is a diagram of the positional relationship of the first dam, the second dam, the third dam, and the second power line boundary at the right bezel in an exemplary embodiment, and the film layer structure of the display panel is omitted. The positional relationship of the first dam, the second dam, the third dam, and the second power line boundary at the upper bezel and the left bezel of the display panel can be the same as at the right bezel, and will not be described again here. As shown in FIG. 11, the orthographic projection of the boundary T1 of the second power line 220 on the substrate 10 away from the display area 100 can be located within the orthographic projection of the third dam 430 on the substrate 10. The second power line 220 can be a single-layer structure or a stacked structure, for example, the second power line 220 can be located on the fourth conductive layer 15, or the second power line 220 can be located on the fourth conductive layer 15 and the fifth conductive layer 17, or the second power line 220 can be located on the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19, and the present disclosure does not limit this.

[0099] FIG. 12 is a schematic view of the stacking of the first dam, the second dam and the third dam at the right side frame in an exemplary embodiment, and the film layer structure of the display panel is omitted. The stacking of the first dam, the second dam and the third dam at the upper side frame and the left side frame of the display panel can be the same as that at the right side frame, and will not be described herein again. The difference between FIG. 12 and FIG. 9 is that a third dam 430 is newly added, and the remaining structures can be referred to the description of FIG. 9 above, and will not be described herein again.

[0100] As shown in FIG. 12, at the right side frame, the fourth conductive layer 15, the fifth conductive layer 17 and the third conductive layer 19 are in contact with each other and all extend to directly below the third dam 430. The orthographic projection of the edge of the fourth conductive layer 15 on the substrate 10 is located within the orthographic projection of the seventh dam base 162 on the substrate 10, so that the edge of the fourth conductive layer 15 can be protected. The orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10 is located within the orthographic projection of the eighth dam base 182 on the substrate 10, so that the edge of the fifth conductive layer 17 can be protected. The orthographic projection of the edge of the third conductive layer 19 on the substrate 10 is located within the orthographic projection of the ninth dam base 204 on the substrate 10, so that the edge of the third conductive layer 19 can be protected.

[0101] In an exemplary embodiment, the orthographic projection of the ninth dam base 204 on the substrate 10 can cover the orthographic projections of the seventh dam base 162 and the eighth dam base 182 on the substrate 10. At the right side frame, the distance between the second dam 420 and the third dam 430 can be a twelfth distance Z12, and the twelfth distance Z12 can be the minimum distance between the opposite side surfaces of the fourth dam base 213 and the ninth dam base 204. In an exemplary embodiment, the twelfth distance Z12 can be greater than or equal to 18 microns, for example, the twelfth distance Z12 can be greater than or equal to 20 microns, which is not limited in the present disclosure. By setting the twelfth distance Z12 to be greater than or equal to 18 microns, it can be ensured that the inorganic film layer between the second dam 420 and the third dam 430 will not be connected through, so that the water vapor intrusion path can be eliminated, which is helpful to improve the display effect and service life of the display panel.

[0102] In an exemplary embodiment, the orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10 covers the orthographic projection of the edge of the fourth conductive layer 15 on the substrate 10, and the orthographic projection of the edge of the third conductive layer 19 on the substrate 10 covers the orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10. By setting the edge of the upper conductive layer covering the edge of the lower conductive layer, it can be ensured that the lower conductive layer will not be damaged when the upper conductive layer is formed, which is helpful to avoid cracks in the display panel.

[0103] FIG. 13 is a schematic view of the stack of the first dam, the second dam and the third dam at the right side frame in another exemplary embodiment, and the film layer structure of the display panel is omitted. The stack of the first dam, the second dam and the third dam at the upper side frame and the left side frame of the display panel can be the same as that at the right side frame, and thus is not described herein. The difference between FIG. 13 and FIG. 12 is that, in the direction perpendicular to the substrate 10, the edge of the fifth conductive layer 17 and the edge of the third conductive layer 19 located in the third dam 430 are flush, and the remaining structures can be referred to the description of FIG. 12, and thus is not described herein. By setting the edge of the fifth conductive layer 17 and the edge of the third conductive layer 19 flush, and both covering the edge of the fourth conductive layer 15, the fourth conductive layer 15 is not damaged when the fifth conductive layer 17 and the third conductive layer 19 located above are formed, which helps to avoid cracks in the display panel.

[0104] The display device can be an OLED display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure are not limited thereto.

[0105] Although the embodiments of the present disclosure are described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the present disclosure, and the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display panel, comprising a display area, a binding area located at one side of the display area, and a first peripheral area located at a side of the binding area close to the display area; the display panel comprises a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a cover plate arranged in sequence on the substrate, and an ink layer is arranged on a side of the cover plate close to the substrate; in the first peripheral area, the first conductive layer comprises a plurality of first signal lines, the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and have the same extension direction; a projection of the ink layer on the substrate at least partially overlaps the first peripheral area; a projection of the third conductive layer on the substrate covers a projection of the plurality of first signal lines and the plurality of second signal lines on the substrate, and a projection of the third conductive layer on the substrate at least partially overlaps a projection of the ink layer on the substrate. An overlapping size of the third conductive layer and the ink layer in a direction away from the display area in the first peripheral area is a first overlapping size, and the first overlapping size is greater than or equal to 18 microns.

2. The display panel of claim 1, wherein, The display panel further comprises a second peripheral area located at a periphery of the display area and away from a side of the binding area, and the first peripheral area and the second peripheral area communicate to surround the display area.

3. The display panel of claim 1, wherein, The display panel further comprises a first dam and a second dam, and the first dam and the second dam surround the display area respectively, and the second dam is located at a side of the first dam away from the display area. The display panel further comprises a fourth conductive layer, a first planar layer, a fifth conductive layer, a second planar layer, a third planar layer and a pixel definition layer arranged in sequence on a side of the second conductive layer away from the substrate; the third conductive layer is located between the second planar layer and the third planar layer, and the pixel definition layer is located on a side of the third planar layer away from the substrate.

4. The display panel of claim 3, wherein, The first dam comprises a first dam base and a third dam base arranged in sequence, and the third dam base is located at a side of the first dam base away from the substrate; the second dam comprises a second dam base and a fourth dam base arranged in sequence, and the fourth dam base is located at a side of the second dam base away from the substrate; the first dam base and the second dam base are located on the third planar layer; and the third dam base and the fourth dam base are located on the pixel definition layer. The display panel further comprises a second power line; in the first peripheral area and the second peripheral area, the second power line extends to below a side of the second dam close to the substrate.

5. The display panel of claim 4, wherein, The second power line is located on the fourth conductive layer; or the second power line is located on the fourth conductive layer and the fifth conductive layer, and the second power line between different conductive layers is connected through a via.

6. The display panel of claim 5, wherein, ​ 7. The display panel of claim 5, wherein, The second power line includes a second conductive part and a fourth conductive part, the second conductive part is located in the fourth conductive layer, and the fourth conductive part is located in the fifth conductive layer; the second conductive part, the fourth conductive part and the second power line located in the third conductive layer are sequentially connected through a via, and the second power line located in the third conductive layer extends to below the second dam near a side of the substrate.

8. The display panel of claim 7, wherein, In the first peripheral area, an edge of the second conductive part on the substrate is located within a projection range of the first flat layer on the substrate in a direction away from the display area; and an edge of the fourth conductive part on the substrate is located within a projection range of the second flat layer on the substrate in the direction away from the display area.

9. The display panel of claim 8, wherein, In the first peripheral area, an edge of the fourth conductive part on the substrate covers an edge of the second conductive part on the substrate in the direction away from the display area.

10. The display panel of claim 8, wherein, The third flat layer includes a third flat part, and an edge of the third flat part on the substrate covers an edge of the second flat layer on the substrate in the direction away from the display area in the first peripheral area.

11. The display panel of claim 10, wherein, In the first peripheral area, a size between the edge of the third flat part and the edge of the second flat layer in the direction away from the display area is a fifth overlap size, and the fifth overlap size is greater than or equal to 18 microns.

12. The display panel of claim 10, wherein, A height of the third flat part in a direction perpendicular to the substrate is greater than a height of the first dam base in the direction perpendicular to the substrate.

13. The display panel of claim 5, wherein, In the second peripheral area, the display panel further includes a connecting electrode, the connecting electrode is located on a side of the third flat layer away from the substrate, and the connecting electrode is connected with the second power line; in the second peripheral area, the connecting electrode extends to below the second dam near a side of the substrate.

14. The display panel of claim 13, wherein, In the second peripheral area, an edge of the fourth conductive layer on the substrate is located within a projection range of the first flat layer on the substrate in a direction away from the display area; An edge of the fourth conductive layer on the substrate, an edge of the first flat layer on the substrate, an edge of the fifth conductive layer on the substrate and an edge of the third conductive layer on the substrate are located within a projection range of the third dam base on the substrate.

15. The display panel of claim 14, wherein, In the second peripheral area, the third conductive layer on the substrate covers an edge of the fifth conductive layer on the substrate in the direction away from the display area.

16. The display panel of claim 13, wherein, In the second peripheral area, the first dam further includes a fifth dam base, and the second dam further includes a sixth dam base; the fifth dam base is located on a side of the third dam base away from the substrate, and the sixth dam base is located on a side of the fourth dam base away from the substrate.

17. The display panel of claim 4, wherein, The display panel further includes a third barrier surrounding the display area and located on a side of the second barrier away from the display area; the display panel further includes a second power line; in the first peripheral area and in the second peripheral area, the second power line extends to below a side of the third barrier close to the base after passing through the first barrier and the second barrier.

18. The display panel of claim 17, wherein, The third barrier includes a seventh dam base, an eighth dam base, and a ninth dam base, the seventh dam base is located on the first planar layer, the eighth dam base is located on the second planar layer, and the ninth dam base is located on the third planar layer.

19. The display panel of claim 17, wherein, In a direction away from the display area, a distance between the second barrier and the third barrier is an eighth distance, the eighth distance is a minimum distance between opposite side surfaces of the second barrier and the third barrier, and the eighth distance is greater than or equal to 36 microns and less than or equal to 44 microns.

20. A display device comprising the display panel of any one of claims 1 to 19.

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