Computing device performance improvement method and related apparatus

Abstract

Embodiments of the present application provide a computing device performance improvement method and a related apparatus. A process management optimization function is offloaded to a processing device, and the processing device and a computing device running a thread are independent of each other. The method is applied to the processing device, and the processing device is connected to the computing device. The method comprises: acquiring a first total access performance value of a plurality of service processes, which run on a plurality of processors in a computing device, accessing a plurality of memories in the computing device; if the first total access performance value exceeds a preset value, on the basis of access performance values of the service processes, determining a first service process requiring access performance adjustment; determining an access performance adjustment strategy of the first service process; and sending the adjustment strategy to the computing device to instruct the computing device to adjust the running of the first service process according to the adjustment strategy. The computing device performance improvement method executed by the processing device can effectively reduce the computing load of the processors in the computing device, thereby saving computing resources of the computing device, and reducing a noise floor of the computing device.

Description

A method for improving computing device performance and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 5, 2024, with application number CN202410254444.1 and invention name “A method for improving the performance of a computing device and related devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computers, and in particular to a method for improving the performance of computing devices and related devices. Background Art

[0003] The non-uniform memory access (NUMA) architecture is a memory architecture designed for multi-processor computers. Computers using the NUMA architecture configure each processor and each memory as multiple different NUMA nodes. Different processors take different amounts of time to access (or call) different memories. The time required for the processor in each NUMA node to access the memory within the node is less than the time required to access the memory on other NUMA nodes. For ease of description, the memory in the same node as the processor is called local memory, and the memory located on other nodes is called remote memory (or off-site memory).

[0004] In computers using the NUMA architecture, the performance of a processor accessing local memory is better than that of a processor accessing remote memory. Therefore, when a program running on the processor frequently accesses remote memory, computing performance is affected. Summary of the Invention

[0005] The embodiments of the present application propose a method for improving the performance of a computing device and a related apparatus, which offload the process management optimization function to a processing device. The processing device is independent of the computing device that runs the business process, thereby reducing the computing burden of the computing device and the background noise of the computing device, thereby improving the computing performance of the computing device while optimizing the business process.

[0006] In a first aspect, embodiments of the present application provide a method for improving the performance of a computing device. The method is applied to a processing device connected to a computing device, which is a non-uniform memory access (NUMA) computing device including multiple processors and multiple memories. The method includes:

[0007] First, the processing device obtains a first total access performance value of multiple business processes running through multiple processors in the computing device to multiple memories in the computing device. Furthermore, the first total access performance value includes the total access performance value of multiple threads in the multiple business processes running by the multiple processors to multiple memories in the computing device. Then, when the first total access performance value exceeds a preset value, the processing device determines the first business process whose access performance needs to be adjusted based on the access performance value of each business process. The first business process may include one or more business processes. After the processing device determines the access performance adjustment policy for the first business process, the processing device sends the adjustment policy to the computing device, instructing the computing device to adjust the operation of the first business process according to the adjustment policy.

[0008] It should be noted that the business process in the embodiment of the present application refers to a process task triggered by running an application in a computing device.

[0009] In the above technical solution, the processing device and the computing device's processor are independent of each other. Therefore, having the processing device execute the computing device performance improvement method effectively reduces the computational load on the computing device's processor, conserves computing resources, and lowers the computing device's noise floor. Furthermore, by having the processing device execute the computing device performance improvement method, continuous optimization can be achieved without manual analysis, reducing labor costs.

[0010] In conjunction with the first aspect, in one possible implementation of the first aspect, a processing device is connected to a performance monitoring unit (PMU) in multiple processors in a computing device. Specifically, the processing device obtains, through the PMU, the amount of access to at least one memory device by each processor when running a business process. The processing device then determines an access performance value for the business process based on the access amount. Finally, the processing device determines a first total access performance value based on the access performance value of each business process. For example, the first total access performance value is obtained by summing the access performance values ​​of each business process.

[0011] Exemplarily, the processing device can obtain the amount of memory accesses by the processor when scheduling threads by running multiple tools, for example, by using the "perf stat" tool to obtain the number of memory accesses by the processor in the same NUMA node and the number of memory accesses by the processor across NUMA nodes.

[0012] It should be noted that the amount of memory accessed by the processor in the process of running (or scheduling) a business process includes but is not limited to: the total amount of data accessed by the processor in the process of scheduling the business process within a certain period of time; or, the number of memory accesses by the processor in the process of scheduling the business process within a certain period of time; or, the amount of memory bandwidth occupied by the processor in the process of scheduling the business process within a certain period of time.

[0013] In the above technical solution, the processing device obtains the access volume of the processor to the memory from the PMU in the processor, which improves the timeliness and accuracy of the obtained access volume, further improves the efficiency of the processing device in determining the access performance adjustment strategy, and effectively reduces the computing load of the processor in the computing device.

[0014] In conjunction with the first aspect, in a possible implementation of the first aspect, determining the access performance value of the business process based on the access volume includes: a processing device determining the access volume and performance value of memory accessed by a processor running the business process when executing the business process; and then determining the access performance value of each business process based on the access volume and the performance value. For example, the access performance value is obtained by multiplying the access volume by the performance value.

[0015] Optionally, the performance value includes: access latency of the processor to at least one memory, access speed of the processor to at least one memory, or distance between the processor and at least one memory.

[0016] In the above technical solution, the performance value of a processor accessing memory while running a business process can be represented by multiple indicators. In addition, the performance value can also be expressed as a relative value. For example, the performance value of processor #1 accessing memory #1 on the same NUMA node is 1. Since the performance value of a processor accessing memory on the same NUMA node (e.g., NUMA node #1) is usually optimal, the optimal performance value of processor #1 when accessing memory is 1. The performance value of processor #1 accessing memory on other NUMA nodes can be expressed as a relative value compared to the optimal performance value. For example, the performance value of processor #1 accessing memory #2 on NUMA node #2 is 1.2.

[0017] In the above technical solution, the access performance value is obtained by amplifying the access volume using the performance value, thereby improving the accuracy of the access performance value, so that the processing device can accurately obtain the first total access performance value of the computing device. This ensures that the processing device can promptly and accurately determine the first business process that requires adjustment and optimization, thereby improving the computing performance of the computing device.

[0018] In combination with the first aspect, in a possible implementation of the first aspect, determining the first business process whose access performance needs to be adjusted based on the access performance value of each business process includes: comparing the access performance value of each business process with the theoretical value; and selecting the business process whose access performance value differs the most from the theoretical value as the first business process.

[0019] The theoretical value can also be called the theoretical access performance value. The theoretical value of a business process is calculated based on the amount of memory access actually scheduled by the computing device while running the business process, as well as the performance of the computing device when accessing memory with the optimal performance value. For example, the theoretical value of a business process can be calculated based on the amount of memory access scheduled by the processor while running the business process, as well as the performance of the processor when accessing the memory of the local node.

[0020] The theoretical performance of each business process includes the theoretical performance of each thread within that business process. Each thread's theoretical performance is calculated by combining the amount of memory accesses made by the processor during thread scheduling and the processor's optimal performance for memory access. The optimal performance of a computing device for memory access is a theoretically optimal value that depends on the hardware implementation of the computing system.

[0021] In the above technical solution, by determining the access performance value and theoretical value of a business process, the first business process requiring access performance adjustment can be accurately identified. This avoids over-optimization, reduces data migration, conserves computing resources, and improves computing performance. The processing device prioritizes optimizing business processes with a large difference between their theoretical value and access performance value, achieving the fastest and most significant improvement in computing performance.

[0022] In another possible implementation, after obtaining the access performance value and theoretical value of each of one or more business processes running on the computing device, the processing device selects one or more business processes as first business processes based on the difference between the access performance value and the theoretical value. For example, if the difference is greater than a certain threshold, the business process is selected as the first business process to be optimized.

[0023] Optionally, the processing device may further determine each business process running on the computing device as a first business process to be optimized, and then sequentially optimize the first business processes based on the difference between the access performance value of the first business process and the theoretical value of the first business process. For example, each business process may be optimized sequentially based on the difference from largest to smallest.

[0024] After the first business process is determined, a first thread to be optimized is determined from one or more threads included in the first business process. In one possible implementation, the processing device may also determine which threads in the one or more threads included in the first business process are threads to be optimized based on the access performance values ​​and theoretical values ​​of each thread in the first business process. For ease of description, the thread to be optimized is referred to as the first thread. Similarly, based on the access performance value of the thread and the theoretical value of the thread, the thread with the largest difference between the access performance value and the theoretical value is determined as the first thread to be optimized.

[0025] In another possible implementation, the processing device determines all threads included in a first business process as first threads to be optimized, and then optimizes the threads included in the first business process sequentially based on the difference between each thread's access performance value and a theoretical value. For example, each thread included in the first business process is optimized sequentially based on the difference from largest to smallest.

[0026] In the above technical solution, the processing device can also determine the first business process that needs to adjust the access performance in a variety of ways, thereby improving the implementation flexibility of the solution.

[0027] In conjunction with the first aspect, in one possible implementation of the first aspect, the processing device determines an access performance adjustment policy for a first business process, including: first, the processing device determines that, before access performance adjustment, the processor processing the first business process is the first processor, and determines that the memory storing the first business process is the first memory. Then, the processing device determines, from the computing device, a second memory, where the performance value of the first processor accessing the second memory is better than the performance value of the first processor accessing the first memory. Finally, the processing device determines an access performance adjustment policy for the first business process, where the adjustment policy indicates migrating the first business process to the second memory.

[0028] Optionally, the second memory also needs to meet the following conditions: the second memory is free memory, where free memory refers to memory with available storage space (or available cache amount, or available storage space ratio) greater than or equal to a first threshold. For example, if the first threshold is set to 50%, the available storage space of the second memory is greater than or equal to 50%.

[0029] In conjunction with the first aspect, in one possible implementation of the first aspect, the processing device determines an access performance adjustment policy for a first business process, including: first, the processing device determines that, before access performance adjustment, the processor processing the first business process is the first processor, and determines that the memory storing the first business process is the first memory. Then, the processing device determines a second processor from a computing device, where the performance value of the second processor accessing the first memory is better than the performance value of the first processor accessing the first memory. Finally, the processing device determines an access performance adjustment policy for the first business process, where the adjustment policy indicates migrating the first business process to the second processor.

[0030] Optionally, the second processor also needs to meet the following condition: the second processor is an idle processor, which refers to a processor whose available computing resources (or the percentage of available computing resources) are greater than or equal to a second threshold. For example, if the second threshold is set to 50%, the available computing resources of the second processor are greater than or equal to 50%.

[0031] In conjunction with the first aspect, in one possible implementation of the first aspect, after the adjustment policy is sent to the computing device, the method further includes: the processing device determining a second total access performance value of multiple business processes running on multiple processors in the computing device to multiple memories in the computing device after the computing device adjusts the operation of the first business process according to the adjustment policy. When the second total access performance value is less than or equal to a preset value, the processing device stops optimization. Stopping optimization specifically means that the processing device stops determining which business processes require access performance adjustment.

[0032] In another possible implementation, the optimization stopping condition includes detecting whether multiple NUMA nodes of the computing system include free memory and / or free processors. Optimization is stopped when the multiple NUMA nodes do not include free memory; and optimization is stopped when the multiple NUMA nodes do not include free processors (referring to computing devices).

[0033] Through the above method, the processing device executes the above computing device performance improvement method to optimize the business process only when optimization is required, avoiding unnecessary optimization, reducing the computing burden of the processing device, reducing the data transfer volume on the computing device side, and improving computing performance.

[0034] In combination with the first aspect, in a possible implementation of the first aspect, the processing device is a data processing unit DPU externally connected to the computing device, or a graphics processor GPU, a neural network processor NPU, or a chip-level system SOC built into the computing device.

[0035] In combination with the first aspect, in a possible implementation of the first aspect, the access performance adjustment strategy of the first business process includes: instructing the second processor to schedule the first thread to access a first memory address, where the first memory address is the physical address of the first memory; or, instructing the first processor to schedule the first thread to access a second memory address, where the second memory address is the physical address of the second memory; or, instructing the second processor to schedule the first thread to access the second memory address, where the first thread belongs to the first business process.

[0036] In the embodiments of the present application, the access performance adjustment policy for the first business process can be implemented in a variety of ways, increasing the flexibility of the solution. The operating system on the computing device can modify the processor and / or memory bound to the first thread based on the access performance adjustment policy for the first business process. This modification reduces the access performance value during the execution of the first thread, thereby improving computing performance.

[0037] In conjunction with the first aspect, in a possible implementation of the first aspect, the method further includes: the processing device obtaining memory access data of one or more threads running in the computing device, the memory access data being relevant data of the threads during operation, and then the processing device caching the memory access data in a memory of the processing device. The processing device then obtains configuration information indicating that the memory access data needs to be exported. Based on the configuration information, the processing device obtains the memory access data from the memory of the processing device and then sends the memory access data to an export destination for the memory access data.

[0038] The processing device is only responsible for collecting access data, and the analysis of access data can be performed by other devices, realizing the decoupling of data collection and data analysis. It can be applied to scenarios that require centralized data analysis, improving the implementation flexibility of the solution and reducing the difficulty of implementing the processing device.

[0039] In combination with the first aspect, in a possible implementation manner of the first aspect, the configuration information includes: a network address of the destination, or an input / output (IO) address of the destination.

[0040] In combination with the first aspect, in a possible implementation of the first aspect, the method further includes: the processing device caches the memory access data of the one or more threads in the memory corresponding to the processing device; and then the processing device formats the memory access data of the one or more threads cached in the memory corresponding to the processing device according to the configuration information. Specific formatting processing includes but is not limited to: data checking, data conversion, data filling, data filtering, data normalization, or data scaling, etc., which is not limited in the embodiments of the present application. The processing device can also format the memory access data, thereby improving the accuracy of thread optimization analysis and further reducing the access performance value of the processor to the memory.

[0041] In a second aspect, an embodiment of the present application proposes a computing device, which includes a processing unit and a transceiver unit, and is used to execute the method described in the first aspect and any one of the above-mentioned aspects.

[0042] A third aspect of an embodiment of the present application provides a chip, which includes an interface circuit and a processing circuit, the interface circuit and the processing circuit are interconnected through lines, and the processing circuit is used to run computer programs or instructions to perform the method of the first aspect.

[0043] Optionally, the chip includes at least one processor and a communication interface, the communication interface and the at least one processor are interconnected via a line, and the at least one processor is used to run a computer program or instruction to perform the method of the first aspect.

[0044] Optionally, the communication interface of the chip may be an input / output interface, a pin or a circuit, etc.

[0045] In conjunction with the third aspect, in one implementation of the third aspect of the embodiments of the present application, the chip described above in the present application further includes at least one memory, wherein the at least one memory stores instructions. The memory can be a storage unit within the chip, such as a register, a cache, etc., or a storage unit of the chip (such as a read-only memory, a random access memory, etc.).

[0046] A fourth aspect of an embodiment of the present application provides a computing device, comprising at least one processor coupled to a memory; the memory is used to store programs or instructions; and the at least one processor is used to execute the program or instructions so that the device implements any possible implementation method of the aforementioned first aspect.

[0047] The fifth aspect of an embodiment of the present application provides a computing device, including a communication interface for inputting and / or outputting signaling or data; and a processor for executing a computer-executable program so that the device can implement any possible implementation method of the aforementioned first aspect.

[0048] In a sixth aspect, an embodiment of the present application provides a computing device comprising at least one logic circuit and an input / output interface; the input / output interface is used to input or output information; and the logic circuit is used to execute any possible implementation method as described in the first aspect above.

[0049] A seventh aspect of the present application provides a computing system, comprising a computing device as described in any implementation of the sixth aspect above.

[0050] In an eighth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect.

[0051] In a ninth aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method described in the first aspect.

[0052] A tenth aspect of the present application provides a computing system, which includes a computing device, wherein the computing device is used to execute the method as described in any one of the first aspects above.

[0053] In combination with the tenth aspect, in an implementation of the tenth aspect of the embodiment of the present application, the computing system includes multiple NUMA computing devices and processing devices, and the processors included in the multiple NUMA computing devices are independent of the processing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a schematic diagram of a NUMA architecture;

[0055] FIG2 is a schematic diagram of the structure of a computing system according to an embodiment of the present application;

[0056] FIG3 is another structural diagram of a computing system according to an embodiment of the present application;

[0057] FIG4 is another structural diagram of a computing system according to an embodiment of the present application;

[0058] FIG5 is a schematic diagram of a flow chart of a method for improving performance of a computing device according to an embodiment of the present application;

[0059] FIG6 is a flow chart of another embodiment of a method for improving computing device performance according to an embodiment of the present application;

[0060] FIG7 is a schematic diagram of a process for determining the sum of access performance values ​​of a computing system according to an embodiment of the present application;

[0061] FIG8 is a flow chart of another embodiment of a method for improving computing device performance according to an embodiment of the present application;

[0062] FIG9 is a flow chart of another embodiment of a method for improving computing device performance according to an embodiment of the present application;

[0063] FIG10 is a schematic diagram of memory access by a processor according to an embodiment of the present application;

[0064] FIG11 is a schematic diagram of attribute information in an embodiment of the present application;

[0065] FIG12 is a schematic diagram of the sum of access performance values ​​of a computing system according to an embodiment of the present application;

[0066] FIG13 is a schematic diagram of an optimization solution in an embodiment of the present application;

[0067] FIG14 is a schematic diagram of an optimized access performance value in an embodiment of the present application;

[0068] FIG15 is a schematic diagram of an optimization solution in an embodiment of the present application;

[0069] FIG16 is a schematic diagram of access performance values ​​after optimization according to an embodiment of the present application;

[0070] FIG17 is a schematic structural diagram of a processing device 1700 provided in an embodiment of the present application;

[0071] FIG18 is a schematic structural diagram of a processing device 1800 provided in an embodiment of the present application;

[0072] FIG19 is a schematic structural diagram of a processing device 1900 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. The terms "first", "second" and corresponding terminology labels in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same properties when describing the embodiments of the present application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, so that a process, method, system, product or device that includes a series of units is not necessarily limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or devices.

[0074] In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of this application, "at least one" refers to one or more items, and "multiple items" refers to two or more items. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0075] The following are some technical concepts involved in this application:

[0076] 1. Non-uniform memory access (NUMA) architecture.

[0077] For ease of understanding, please refer to an example of a NUMA architecture. A NUMA computing device (or NUMA node, or simply a node) may include at least one processor. The processor of a NUMA node may include one or more cores. Please refer to Figure 1, which is another schematic diagram of a NUMA architecture. As shown in Figure 1, the NUMA architecture includes four NUMA nodes, namely NUMA node 0, NUMA node 1, NUMA node 2, and NUMA node 3. As shown in Figure 1, each NUMA node may contain 32 cores. NUMA node 0 includes CPU0, which includes 32 cores such as core 0, core 1, ..., core 31. NUMA node 2 includes CPU2, which includes 32 cores such as core 64, core 65, ..., core 95. It should be noted that a NUMA node may include one or more processors, and each processor includes one or more cores.

[0078] At the same time, each NUMA node can also be configured with corresponding memory. For example, NUMA node 0 can be configured with memory 0, whose size can be 4*32 gigabytes (GB). It should be noted that the memory configured for a NUMA node is independent of the NUMA node and can also be set in the NUMA node, and this embodiment of the application does not limit this.

[0079] In the NUMA architecture shown in Figure 1, taking NUMA node 0 as the benchmark, NUMA node 0 can be called the local node (local node), then NUMA node 1 and NUMA node 2 adjacent to NUMA node 0 can be called the neighbor nodes (neighbor node) of NUMA node 0, and NUMA node 3, which is neither a local node nor a neighbor node, can be called the remote node (remote node). Among them, the speed at which the processor of the local node accesses the memory corresponding to different NUMA nodes is usually different. Specifically, the processor of the local node has the fastest access speed when accessing memory 0 of its own node; the slowest access speed when accessing memory 3 of the remote node; and the access speed when accessing memory 1 or memory 2 of the neighbor node is slower than the speed of accessing memory 0, but faster than the speed of accessing memory 3. For a processor, the memory of its node is called local memory, and the memory in other nodes is called off-site memory or remote memory.

[0080] Measuring the performance of a processor accessing memory can be called the memory performance value (characteristics of memory accessing) or simply the performance value. The performance value can be indicated by a variety of performance indicators. For example, the performance value includes but is not limited to: access latency, access speed, or node distance (node ​​distance). The following is a specific explanation. Access latency refers to the access latency value when the processor accesses a certain memory; access speed refers to the access speed (or access rate or data read and write rate) when the processor accesses a certain memory; node distance refers to the distance between the processor and the accessed memory. The node distance can be used to measure the speed or latency of the processor accessing the memory. Among them, the size of the node distance can reflect the speed of the processor accessing the memory. Specifically: the larger the node distance, the slower the speed of the processor accessing the memory; the smaller the node distance, the faster the speed of the processor accessing the memory.

[0081] As shown in Figure 1, the node distance for the processor on NUMA node 0 to access memory 0 on its own node (NUMA node 0) is 10. The node distance for the processor on NUMA node 0 to access memory 0 is 10, and the node distance for the processor on NUMA node 0 to access memory 1 corresponding to NUMA node 1 is 16. The node distance for the processor on NUMA node 0 to access memory 0 is 10, and the node distance for the processor on NUMA node 0 to access memory 2 corresponding to NUMA node 2 is 32. The node distance for the processor on NUMA node 0 to access memory 0 is 10, and the node distance for the processor on NUMA node 0 to access memory 3 corresponding to NUMA node 3 is 33. In summary, the node distance for the processor on NUMA node 0 to access memory 0 on its own node is the smallest, and the memory access speed is the fastest; the node distance for the processor on NUMA node 0 to access memory 3 on NUMA node 3 is the largest, and the memory access speed is the slowest.

[0082] Based on the above description, in the NUMA architecture, the performance value of the processor accessing memory depends on the location of the memory relative to the processor. The performance value of the processor accessing its local memory (local memory refers to the memory in the same NUMA node as the processor) is better than the performance value of accessing remote memory (remote memory refers to the memory in a different NUMA node from the processor). Therefore, when the program running in the processor frequently accesses remote memory, it affects computing performance. In addition, current performance optimization tools often require manual analysis, and there are problems such as difficult configuration, slow optimization response, and poor optimization effect. When the processor runs the performance optimization tool, in addition to occupying the processor's computing resources, it also increases the processor's background noise, affecting the normal operation of the business.

[0083] To address the above technical problems, embodiments of the present application provide a method for improving computing device performance. The method is applied to a processing device connected to a computing device, which is a NUMA computing device and includes multiple processors and multiple memories. First, the processing device obtains a first total access performance value for multiple business processes running on the multiple processors in the computing device to the multiple memories in the computing device. Then, based on the first total access performance value, the processing device determines whether to optimize the business processes running on the computing device. When the first total access performance value exceeds a preset value, the processing device determines a first business process requiring access performance adjustment based on the access performance value of each business process. Then, the processing device determines an access performance adjustment policy for the first business process. Finally, the processing device sends the adjustment policy to the computing device, instructing the computing device to adjust the operation of the first business process according to the adjustment policy. Because the processing device and the computing device are independent of each other, executing the above method for improving computing device performance on the processing device can effectively reduce the computing load on the computing device, conserve computing resources on the computing device, and lower the noise floor of the computing device. By executing the above method on the processing device, continuous optimization can be achieved without manual analysis, reducing labor costs. The operation of the first business process is adjusted by adjusting the strategy, so that the access performance value of the processor accessing the memory is reduced during the computer running the first business process, thereby improving the computing performance.

[0084] First, the computing system involved in the embodiments of the present application is introduced. The computing system includes a computing device and a processing device. For one possible example, please refer to Figure 2, which is a schematic diagram of the structure of a computing system in the embodiments of the present application. For example, the computing system proposed in the embodiments of the present application includes: a computing device and a processing device independent of the computing device. The computing device includes: node 0 (or NUMA node 0), node 1 (or NUMA node 1), node 2 (or NUMA node 2), and node 3 (or NUMA node 3). The computing device is a NUMA computing device. Taking node 0 as an example, node 0 includes CPU 0-0 and CPU 0-1. The memory configured for CPU 0-0 is memory 0-0, and the memory configured for CPU 0-1 is memory 0-1. In node 0, each CPU includes a performance monitoring unit (PMU), which allows user programs to configure the content to be monitored. Node 0 also includes other components, such as L3 cache, etc., which are not limited in the embodiments of the present application. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. The computing device may also be a terminal device such as a desktop computer, a laptop computer, or a smart phone, and this embodiment of the present application does not limit this.

[0085] The following describes the composition of the computing system: In one possible implementation, the processing device and the computing device are independent of each other. In another possible implementation, the processing device is integrated into the computing device, and the processing device is independent of the processors included in the NUMA node.

[0086] In one example, please refer to Figure 3, which is another structural diagram of the computing system in the embodiment of the present application. The computing system of the embodiment of the present application specifically includes: a processing device and a computing device, wherein the processing device and the computing device are independent of each other, the processing device may also include a memory of the processing device, such as a cache of the processing device, the computing device includes a plurality of processors such as processor 0, ..., processor X, X is a positive integer greater than 0, and the memory includes a plurality of memories such as memory 0, ..., memory Y, and Y is a positive integer greater than 0. Each processor can be configured with a memory. A connection is established between the above-mentioned processing device and the computing device. For example, the processing device includes a data processing unit (DPU), and the processing device (DPU) establishes a connection with the CPU and memory of the computing device through a peripheral component interconnect express (PCIe) bus.

[0087] In another example, please refer to Figure 4, which is another structural diagram of the computing system in the embodiment of the present application. The computing system of the embodiment of the present application specifically includes: a computing device, a computing device with a built-in processing device. The processing device may also include a memory of the processing device, such as a cache of the processing device, the computing device includes multiple processors such as processor 0,..., processor X, where X is a positive integer greater than 0, and the memory includes multiple memories such as memory 0,..., memory Y, where Y is a positive integer greater than 0. Each processor can be configured with a memory. A connection is established between the above-mentioned processing device and the computing device. For example, the processing device includes a graphics processing unit (GPU), a neural network processing unit (NPU), an auxiliary processor on a chip-level system (SOC), an intelligent management unit (IMU), a management engine (ME), or any one of a single-chip microcomputer. The processing device establishes a connection with the processor and memory included in the computing device via an advanced extensible interface (AXI) bus or a hyper transport (HT) bus.

[0088] As some examples, the processor included in the computing device may be a central processing unit. Specifically, the processor includes a processor based on an advanced reduced instruction set computer machine (ARM) architecture (such as ARMv8, ARMv9, etc.), an X86 processor based on a complex instruction set architecture (such as Skylake, etc.), or the computing device may be implemented through an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above-mentioned PLD may be a complex programmable logical device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0089] The bus between the computing device and the processing device can be, for example, an advanced extensible interface (AXI) bus, a hyper transport (HT) bus, a quick path interconnect (QPI) bus, a unified bus (UB), a compute express link (CXL), or a peripheral component interconnect express (PCIe) bus, or can be other signal lines that can be used for information exchange, such as shared address lines, data lines, etc., which are not limited in this embodiment.

[0090] The following describes a method for improving computing device performance according to an embodiment of the present application, with reference to the accompanying drawings. Please refer to FIG5 , which is a flow chart illustrating an embodiment of a method for improving computing device performance according to an embodiment of the present application. The method for improving computing device performance according to an embodiment of the present application includes:

[0091] S1. A processing device obtains a first total access performance value of multiple business processes running through multiple processors in a computing device to multiple memories in the computing device.

[0092] In step S1, the processing device determines whether to optimize a business process (also referred to as a business process) running on the computing device by detecting the total access performance value of the computing device. For ease of explanation, the total access performance value of the computing device before optimization is referred to as a first total access performance value.

[0093] In one possible implementation, a processing device is connected to a performance monitoring unit (PMU) of a plurality of processors in a computing device. The processing device obtains, through the PMU, the amount of access to at least one memory accessed by each processor when running a business process. Then, the processing device determines the performance value of the memory accessed by the processor executing the business process when executing the business process. The processing device determines the access performance value of each business process based on the amount of access and the performance value. Then, the access performance values ​​of one or more processors when accessing one or more memories during the running of the business process are summed to obtain the access performance value of the business process. Finally, the access performance value of each business process running in the computing device is summed to determine a first total access performance value.

[0094] It should be noted that the amount of memory accessed by the processor in the process of running (or scheduling) a business process includes but is not limited to: the total amount of data accessed by the processor in the process of scheduling the business process within a certain period of time; or, the number of memory accesses by the processor in the process of scheduling the business process within a certain period of time; or, the amount of memory bandwidth occupied by the processor in the process of scheduling the business process within a certain period of time.

[0095] The performance value of the memory accessed by the processor executing the business process when executing the business process includes, but is not limited to: the access latency when the processor accesses the memory, the access speed when the processor accesses the memory, or the distance between the processor and the memory. The performance value can also be expressed as a relative value. For example, the performance value of processor #1 accessing memory #1 on the same NUMA node is 1. Since the performance value of processors accessing memory on the same NUMA node (such as NUMA node #1) is usually optimal, the optimal performance value of processor #1 when accessing memory is 1. The performance value of processor #1 accessing memory on other NUMA nodes can be expressed as a relative value compared to the optimal performance value. For example, the performance value of processor #1 accessing memory #2 on NUMA node #2 is 1.2.

[0096] In one example, please refer to Figure 7, which is a flow chart of determining the total access performance value of a computing device in an embodiment of the present application. The total access performance value of a computing device can be determined using the following method.

[0097] F1. Obtain access volume of one or more memories by one or more processors during a process in which a computing device runs a business process through one or more processors.

[0098] In step F1, a business process includes one or more threads. Each thread is scheduled by at least one processor and accesses at least one corresponding memory. Therefore, to obtain the memory access volume of a processor during the operation of a business process, it is necessary to first obtain the memory access volume of each thread in the business process during the operation of the processor.

[0099] Exemplarily, the processing device can obtain the amount of memory accesses by the processor when scheduling threads by running multiple tools, for example, by using the "perf stat" tool to obtain the number of memory accesses by the processor in the same NUMA node and the number of memory accesses by the processor across NUMA nodes.

[0100] For ease of understanding, please refer to Figure 10, which is a schematic diagram of the amount of memory accessed by a processor in an embodiment of the present application. Taking a computing device including four NUMA nodes as an example, the computing device includes: processor 0 (processor 0 is the processor included in NUMA node 0), processor 1 (processor 1 is the processor included in NUMA node 1), processor 2 (processor 2 is the processor included in NUMA node 2) and processor 3 (processor 3 is the processor included in NUMA node 3). The memory of the computing device includes memory 0 (memory 0 is the memory configured by NUMA node 0), memory 1 (memory 1 is the memory configured by NUMA node 1), memory 2 (memory 2 is the memory configured by NUMA node 2) and memory 3 (memory 3 is the memory configured by NUMA node 3). Processor 0 configures memory 0, and memory 0 can be regarded as the local memory of processor 0; processor 1 configures memory 1, and memory 1 can be regarded as the local memory of processor 1; processor 2 configures memory 2, and memory 2 can be regarded as the local memory of processor 2; processor 3 configures memory 3, and memory 3 can be regarded as the local memory of processor 3. The computing device runs business process 0, business process 1, business process 2, and business process 3.

[0101] Business process 0 includes thread 0-0 and thread 0-1, and the processor that schedules business process 0 includes processor 0. During the process of scheduling business process 0, processor 0 stores data of thread 0-0 to memory 0 and stores data of thread 0-1 to memory 1.

[0102] The processor bound to thread 0-0 is processor 0, and the memory bound to thread 0-0 is memory 0. The number of times processor 0 accesses memory 0 during the process of scheduling thread 0-0 is 1.

[0103] The processor bound to thread 0-1 is processor 0, and the memory bound to thread 0-1 is memory 1. The number of times processor 0 accesses memory 1 during the process of scheduling thread 0-1 is 1.

[0104] Business process 1 includes thread 1-0, thread 1-1 and thread 1-2. The processor that schedules business process 1 includes processor 1. During the process of scheduling business process 1, processor 1 stores the data of thread 1-0 to memory 0, the data of thread 1-1 to memory 1, and the data of thread 1-2 to memory 2.

[0105] The processor bound to thread 1-0 is processor 1, and the memory bound to thread 1-0 is memory 0. The number of times processor 1 accesses memory 0 during the process of scheduling thread 1-0 is 1.

[0106] The processor bound to thread 1-1 is processor 1, and the memory bound to thread 1-1 is memory 1. The number of times processor 1 accesses memory 1 during the process of scheduling thread 1-1 is 2.

[0107] The processor bound to thread 1-2 is processor 1, and the memory bound to thread 1-2 is memory 2. The number of times processor 1 accesses memory 2 during the process of scheduling thread 1-2 is 2.

[0108] Business process 2 includes threads 2-0, 2-1, 2-2, 2-3, and 2-4. The processors that schedule business process 2 include processors 1, 2, and 3. While scheduling business process 2, processor 1 stores the data of thread 2-0 to memory 0, the data of thread 2-1 to memory 1, and the data of thread 2-2 to memory 2. While scheduling business process 2, processor 2 stores the data of thread 2-3 to memory 0. While scheduling business process 2, processor 3 stores the data of thread 2-4 to memory 0.

[0109] The processor bound to thread 2-0 is processor 1, and the memory bound to thread 2-0 is memory 0. The number of accesses to memory 0 by processor 1 during the process of scheduling thread 2-0 is 1.

[0110] The processor bound to thread 2-1 is processor 1, and the memory bound to thread 2-1 is memory 1. The number of times processor 1 accesses memory 1 during the process of scheduling thread 2-1 is 1.

[0111] The processor bound to thread 2-2 is processor 1, and the memory bound to thread 2-2 is memory 2. The number of times processor 1 accesses memory 2 during the process of scheduling thread 2-2 is 2.

[0112] The processor bound to thread 2-3 is processor 2, and the memory bound to thread 2-3 is memory 0. The number of times processor 2 accesses memory 0 during the process of scheduling thread 2-3 is 1.

[0113] The processor bound to thread 2-4 is processor 3, and the memory bound to thread 2-4 is memory 0. The number of times processor 3 accesses memory 0 during the process of scheduling thread 2-4 is 3.

[0114] Business process 3 includes threads 3-0, 3-1, 3-2, and 3-3. The processors that schedule business process 3 include processor 0, processor 1, processor 2, and processor 3. When scheduling business process 3, processor 0 stores the data of thread 3-0 in memory 3. When scheduling business process 3, processor 1 stores the data of thread 3-1 in memory 3. When scheduling business process 3, processor 2 stores the data of thread 3-2 in memory 3. When scheduling business process 3, processor 3 stores the data of thread 3-3 in memory 3.

[0115] The processor bound to thread 3-0 is processor 0, and the memory bound to thread 3-0 is memory 3. The number of times processor 0 accesses memory 3 during the process of scheduling thread 3-0 is 2.

[0116] The processor bound to thread 3-1 is processor 1, and the memory bound to thread 3-1 is memory 3. The number of times processor 1 accesses memory 3 during the process of scheduling thread 3-1 is 2.

[0117] The processor bound to thread 3-2 is processor 2, and the memory bound to thread 3-2 is memory 3. The number of times processor 2 accesses memory 3 during the process of scheduling thread 3-2 is 1.

[0118] The processor bound to thread 3-3 is processor 3, and the memory bound to thread 3-3 is memory 3. The number of times processor 3 accesses memory 3 during the process of scheduling thread 3-3 is 2.

[0119] Then, the access volume of all threads included in the business process is summed up to obtain the access volume of one or more processors accessing one or more memories during the scheduling process of the business process.

[0120] F2. Obtain attribute information, and determine, based on the attribute information, a performance value of the memory accessed by the processor that schedules the business process.

[0121] In step F2, the processing device obtains attribute information of the computing device, where the attribute information includes a performance value of any processor in the computing device accessing any memory.

[0122] For ease of understanding, in conjunction with the computing device of the example in Figure 10, please refer to Figure 11, which is a schematic diagram of attribute information in an embodiment of the present application. Taking processor 0 as an example, the performance value of processor 0 accessing local memory (i.e., memory 0) is optimal, and this performance value is set to 1. This performance value can be regarded as the optimal performance value of processor 0 accessing the memory in the computing device. The performance value of processor 0 accessing memory 1 is a relative value relative to the optimal performance value, which is 1.2. By analogy, the performance value of processor 0 accessing memory 2 is 1.3, and the performance value of processor 0 accessing memory 3 is 1.4. The performance value of processor 1 accessing local memory (i.e., memory 1) is optimal, and this performance value is 1. Relative to the optimal performance value, the performance value of processor 1 accessing memory 0 is 1.2, the performance value of processor 1 accessing memory 2 is 1.2, and the performance value of processor 1 accessing memory 3 is 1.3. The performance value of processor 2 accessing local memory (i.e., memory 2) is optimal, and this performance value is 1. Relative to the optimal performance, the performance value of processor 2 accessing memory 0 is 1.3, the performance value of processor 2 accessing memory 2 is 1.2, and the performance value of processor 2 accessing memory 3 is 1.2. Processor 3's performance value for accessing local memory (that is, memory 3) is optimal, with a performance value of 1. Relative to the optimal performance, the performance value of processor 3 accessing memory 0 is 14, the performance value of processor 3 accessing memory 1 is 1.3, and the performance value of processor 3 accessing memory 2 is 1.2.

[0123] It should be noted that the execution order of step F1 and step F2 is not limited in this embodiment of the application. After step F1 and step F2, step F3 is executed.

[0124] F3. Determine the access performance value of the business process based on the access volume and the performance value.

[0125] When a computing device is running a business process, one or more processors included in the computing device may access different memories. When different processors access different memories, the performance values ​​are often different. For example, the performance value of a processor accessing the memory of the same node (such as memory access latency) is significantly better than the performance value of the processor accessing the memory of a remote node. Therefore, it is necessary to use the performance value of the processor in accessing the memory to amplify the amount of access the processor has to the memory to reflect the difference in performance value. In an embodiment of the present application, the amount of access after the performance value is amplified is referred to as the access performance value (also referred to as memory access overhead).

[0126] The access performance value of each business process includes the access performance value of each thread in the business process. The access performance value of each thread is calculated by the amount of memory accesses made by the computing device when scheduling the thread and the performance value of the computing device when accessing memory. It should be noted that there are many possible ways to implement the access performance, which is not limited in the embodiments of this application.

[0127] In one example, business process 1 includes threads 1-0, 1-1, and 1-3. The access performance value of business process 1 = 1.2 (the access performance value of thread 1-0) + 2 (the access performance value of thread 1-1) + 2.4 (the access performance value of thread 1-2) = 5.6. For example, the access performance value of thread 1-0 can be calculated as follows: within 10 seconds, processor 1, which schedules thread 1-0, accesses memory 2 (memory 2 stores data related to thread 1) once, and the performance value of processor 1 accessing memory 2 is 1.2. Therefore, the access performance value of thread 1 is 1*1.2=1.2.

[0128] Business process 2 includes thread 2-0, thread 2-1, thread 2-2, thread 2-3 and thread 2-4. The access performance value of business process 2 = 1.2 (access performance value of thread 2-0) + 1 (access performance value of thread 2-1) + 2.4 (access performance value of thread 2-2) + 1.2 (access performance value of thread 2-3) + 5.2 (access performance value of thread 2-4) = 11.1.

[0129] The access performance value of each business process includes the access performance value of each thread in the business process. The access performance value of each thread is obtained by the amount of memory access by the processor when scheduling the thread and the performance value of the processor when accessing the memory.

[0130] F4. Sum the access performance values ​​of one or more business processes running on the computing device to obtain a first total access performance value of the computing device.

[0131] After obtaining the access performance value of each of one or more business processes running on the computing device, the sum of the access performance values ​​of the one or more business processes is calculated. This sum of the access performance values ​​of the one or more business processes can also be referred to as the first total access performance value of the computing device. When the first total access performance value is greater than or equal to a preset value, step S1 is performed to determine which business processes, from among the multiple business processes running on the computing device, are to be optimized. For ease of description, the business processes to be optimized are referred to as first business processes. The first business process includes one or more business processes.

[0132] In conjunction with Figures 10 and 11, the first total access performance value of the computing device in an example is shown in Figure 12. Figure 12 is a schematic diagram of the first total access performance value of a computing device in an embodiment of the present application. According to the amount of memory access by the processor in the process of scheduling threads and the performance value of the processor accessing the memory, the access performance value of each thread is solved. Then, the access performance value of each thread included in the business process is summed to obtain the access performance value of the business process. The access performance value of each business process included in the computing device is summed to obtain the first total access performance value of the computing device. As shown in Figure 12, the first total access performance value of the computing device = 2.2 (access performance value of business process 0) + 5.6 (access performance value of business process 1) + 11.1 (access performance value of business process 2) + 8.6 (access performance value of business process 3) = 27.5.

[0133] S2. When the first total access performance value exceeds a preset value, the processing device determines, based on the access performance value of each service process, a first service process whose access performance needs to be adjusted.

[0134] In step S2, when the first total access performance value exceeds a preset value, the processing device is triggered to determine which business processes require access performance adjustment. Specifically, the processing device determines the first business process from among the multiple business processes running on the computing device. Specifically, the processing device determines the sum of the access performance values ​​of the multiple business processes and, based on the access performance value of each business process, determines the first business process requiring access performance adjustment.

[0135] In one possible implementation, the processing device obtains the access performance value and theoretical value of each of one or more business processes running on the computing device, and then selects the business process with the largest difference between the access performance value and the theoretical value as the first business process.

[0136] In another possible implementation, after obtaining the access performance value and theoretical value of each of one or more business processes running on the computing device, the processing device selects one or more business processes as first business processes based on the difference between the access performance value and the theoretical value. For example, if the difference is greater than a certain threshold, the business process is selected as the first business process to be optimized.

[0137] Optionally, the processing device may further determine each business process running on the computing device as a first business process to be optimized, and then sequentially optimize the first business processes based on the difference between the access performance value of the first business process and the theoretical value of the first business process. For example, each business process may be optimized sequentially based on the difference from largest to smallest.

[0138] After the first business process is determined, a first thread to be optimized is determined from one or more threads included in the first business process. In one possible implementation, the processing device may also determine which threads in the one or more threads included in the first business process are threads to be optimized based on the access performance values ​​and theoretical values ​​of each thread in the first business process. For ease of description, the thread to be optimized is referred to as the first thread. Similarly, based on the access performance value of the thread and the theoretical value of the thread, the thread with the largest difference between the access performance value and the theoretical value is determined as the first thread to be optimized.

[0139] In another possible implementation, the processing device determines all threads included in a first business process as first threads to be optimized, and then optimizes the threads included in the first business process sequentially based on the difference between each thread's access performance value and a theoretical value. For example, each thread included in the first business process is optimized sequentially based on the difference from largest to smallest.

[0140] The following describes the theoretical value of an embodiment of the present application. The theoretical value can also be referred to as the theoretical access performance value. The theoretical value of a business process is obtained based on the amount of memory access actually scheduled by the computing device during the execution of the business process, and the performance value of the computing device when accessing the memory with the best performance value. For example, the theoretical value of a business process can be obtained by the amount of memory access scheduled by the processor during the execution of the business process, and the performance value of the processor when accessing the memory of the local node.

[0141] Specifically, the theoretical value of each business process includes the theoretical value of each thread within that business process. The theoretical value of each thread is calculated by calculating the amount of memory accesses made by the processor during thread scheduling and the optimal performance of the processor when accessing memory. The optimal performance of a computing device when accessing memory is a theoretical optimal value that depends on the hardware implementation of the computing system.

[0142] In conjunction with Figures 10 and 11, in one example, the performance values ​​of processor 1 scheduling thread 1-0 accessing multiple memories in the computing system are as follows: the performance value of processor 1 accessing memory 0 is 1.2, the performance value of processor 1 accessing memory 1 is 1, the performance value of processor 1 accessing memory 2 is 1.2, and the performance value of processor 1 accessing memory 3 is 1.3. Based on these multiple performance values, the optimal performance value is 1, meaning that the performance value of processor 1 accessing memory 1 is the optimal performance value. Based on the fact that processor 1 scheduling thread 1-0 accesses memory 0 1 times during the scheduling of thread 1-0 and the optimal performance value of 1, the theoretical performance value of thread 1-0 is determined to be 1*1=1. Based on the fact that processor 1 scheduling thread 1-1 accesses memory 1 2 times during the scheduling of thread 1-1 and the optimal performance value of 1, the theoretical performance value of thread 1-1 is determined to be 2*1=2. Based on the fact that processor 1 scheduling thread 1-2 accesses memory 2 2 times during the scheduling of thread 1-2 and the optimal performance value of 1, the theoretical performance value of thread 1-2 is determined to be 2*1=2. In summary, the theoretical value of business process 1 is calculated to be 1+2+2=5. Similarly, the theoretical value of business process 0 is 2; the theoretical value of business process 2 is 8; and the theoretical value of business process 3 is 7.

[0143] In one example, among the above-mentioned business processes 0, 1, 2, and 3, the business process 2 has the largest difference between its access performance value and its theoretical value, so business process 2 can be selected as the first business process to be optimized. First, business process 2 is optimized, and then business process 3, business process 1, and business process 0 are selected in turn according to the difference between their access performance value and their theoretical value as the first business process to be optimized, and so on. Taking business process 2 as the first business process as an example, the difference between the access performance value and the theoretical value of threads 2-4 in business process 2 is the largest, so threads 2-4 can be optimized first, and threads 2-4 can be used as the first thread for subsequent optimization processing. Then, according to the difference between their access performance value and their theoretical value, the other threads of business process 2 are optimized as the first thread in turn.

[0144] S3. The processing device determines an access performance adjustment policy for the first service process.

[0145] In step S3, after the processing device determines the first business process that needs to be optimized, it further determines an access performance adjustment strategy for the first business process.

[0146] First, the processing device determines that the processor that schedules the first business process is the first processor, and the memory accessed by the first processor during scheduling the first business process is the first memory. It should be noted that the first processor may include one or more processors, and the first memory may also include one or more memories. Then, the processing device determines a second processor and / or second memory from the multiple processors and multiple memories included in the computing device. The second processor satisfies the following condition: the performance value of the second processor accessing the first memory is better than the performance value of the first processor accessing the first memory. For example, the performance value of the first processor accessing the first memory is 1.4, and the performance value of the second processor accessing the first memory is 1.2. The second memory satisfies the following condition: the performance value of the first processor accessing the second memory is better than the performance value of the first processor accessing the first memory. For example, the performance value of the first processor accessing the first memory is 1.4, and the performance value of the first processor accessing the second memory is 1.2. Finally, the processing device determines an access performance adjustment policy for the first business process based on the determined second processor and / or second memory.

[0147] The following describes how to determine the second memory:

[0148] In one possible implementation, after obtaining attribute information of the computing device, the processing device determines, based on the attribute information, a candidate memory set from multiple memories included in multiple NUMA nodes. The candidate memory set includes one or more memories in the multiple NUMA nodes, and the performance value of the first processor accessing the memory in the candidate memory set is better than the performance value of the first processor accessing the first memory. A second memory is then determined from the candidate memory set. For example, the memory with the best performance value in the candidate memory set is selected as the second memory.

[0149] Optionally, the second memory also needs to meet the following conditions: the second memory is free memory, where free memory refers to memory with available storage space (or available cache amount, or available storage space ratio) greater than or equal to a first threshold. For example, if the first threshold is set to 50%, the available storage space of the second memory is greater than or equal to 50%.

[0150] The following describes how to determine the second processor:

[0151] In one possible implementation, after the processing device obtains attribute information of the computing device, it determines an alternative processor set from multiple processors included in multiple NUMA nodes based on the attribute information. The alternative processor set includes one or more processors in the multiple NUMA nodes, and the performance value of the processors included in the alternative processor set accessing the first memory is better than the performance value of the first processor accessing the first memory.

[0152] Optionally, the second processor also needs to meet the following condition: the second processor is an idle processor, which refers to a processor whose available computing resources (or the percentage of available computing resources) are greater than or equal to a second threshold. For example, if the second threshold is set to 50%, the available computing resources of the second processor are greater than or equal to 50%.

[0153] Furthermore, the processing device may also determine an access performance adjustment policy for a first thread included in the first service process, which is described below with reference to the accompanying drawings.

[0154] Optimization plan A:

[0155] In conjunction with the example of Figure 12, an optimization solution is shown in Figure 13, which is a schematic diagram of an optimization solution in an embodiment of the present application. The optimization direction for the thread is horizontal optimization. Under the premise that the memory storing the thread data remains unchanged, the optimization is achieved by changing the processor of the scheduling thread (i.e., rebinding the processor of the thread). The goal of the optimization is that the processor and memory bound to the thread are the processor and memory in the diagonal direction in Figure 13. The reason is that the performance value of the processor and memory in the diagonal direction is optimal, which can effectively reduce access across NUMA nodes. For example, before optimization, the processor that schedules thread 1-1 is processor 0, and processor 0 stores the data of thread 1-1 in memory 1 during the process of scheduling thread 1-1. The processor with the best performance value among processors 0 to 3 in the process of accessing memory 1 is processor 1. Therefore, the processor that schedules thread 1-1 is changed from processor 0 to processor 1, and processor 1 is determined as the second processor of thread 1-1 (i.e., processor 1 is determined to be the optimization target of thread 1-1). After optimization, the access performance value of thread 1-1 is 1*1=1, which is less than the access performance value of thread 1-1 before optimization, which was 1.2. In other words, when thread 1-1 is the first thread, the first processor scheduled for the first thread before optimization is processor 0, while the second processor scheduled for the first thread after optimization is processor 1, changing the processor bound to thread 1-1 from processor 0 to processor 1.

[0156] Similarly, while maintaining the memory used to store each thread, we optimize by changing the processors bound to each thread. The optimization goal is to bind each thread to processors and memory along the diagonal line in Figure 13. This provides the best performance and effectively reduces cross-NUMA node accesses. Optionally, the order in which optimization is performed on multiple threads can be determined by the difference between the thread's access performance and the theoretical value, with optimization performed in descending order.

[0157] Optimization plan B:

[0158] In conjunction with the example of Figure 13, an optimization scheme is shown in Figure 15, which is a schematic diagram of an optimization scheme in an embodiment of the present application. The optimization direction for the thread is vertical optimization. Under the premise that the processor scheduling the thread remains unchanged, the optimization is achieved by changing the memory storing the thread (i.e., rebinding the thread to the memory). The goal of the optimization is that the processor and memory bound to the thread are the processors and memories in the diagonal direction in Figure 15. The reason is that the performance value of the processors and memories in the diagonal direction is optimal, which can effectively reduce access across NUMA nodes. It should be noted that the scheme illustrated in Figure 15 is to first perform horizontal optimization (first optimize the processor to which the thread is bound) and then perform vertical optimization (then optimize the memory to which the thread is bound). In another possible implementation method, vertical optimization can also be performed first (first optimize the memory to which the thread is bound) and then perform horizontal optimization (then optimize the processor to which the thread is bound). This application does not limit the order of the optimization scheme.

[0159] As shown in Figure 15, the processor that schedules thread 1-0 is processor 1, and the data of thread 1-0 is migrated from memory 0 to memory 1. The memory with the best performance value when processor 1 accesses memory 0 to memory 3 is memory 1. Therefore, the memory storing the data of thread 1-0 is changed from memory 0 to memory 1, and memory 1 is used as the second memory of thread 1-0 (that is, memory 1 is determined to be the optimization target of thread 1-0). Processor 1 that schedules thread 1-0 migrates the data of thread 1-0 from memory 0 to memory 1, and subsequently processor 1 stores the data of thread 1-0 in memory 1 during the process of scheduling thread 1-0. In other words, when thread 1-0 is the first thread, the first memory storing the data of the first thread before optimization is memory 0, and the second memory storing the data of the first thread after optimization is memory 1. The memory bound to thread 1-0 is changed from memory 0 to memory 1.

[0160] Similarly, while the processor that schedules the thread remains unchanged, the thread's memory bindings are modified to achieve optimization. The optimization goal is to bind the thread to processors and memory along the diagonal line in Figure 15. This provides the best performance and effectively reduces cross-NUMA node accesses. Optionally, the order of optimizing multiple threads can be determined by the difference between the thread's access performance and the theoretical value, with optimization performed in descending order.

[0161] It should be noted that the above-mentioned optimization plan B is optimized based on the results of optimization plan A. That is, the processor of the first thread is optimized first, and the memory of the first thread is optimized secondly. In another possible implementation, optimization plan B can be executed first, and optimization plan A can be executed based on the results of optimization plan B. That is, the memory of the first thread is optimized first, and the processor of the first thread is optimized secondly. The embodiments of this application do not limit the execution order of the optimization plans.

[0162] S4. The processing device sends the adjustment policy to the computing device.

[0163] In step S4, after the processing device determines the access performance adjustment policy of the first business process, the processing device sends the adjustment policy to the computing device, and the adjustment policy is used to instruct the computing device to adjust the operation of the first business process according to the adjustment policy. Specifically, the adjustment policy is used to instruct the migration of the first business process to the second processor, or it can also be called: the scheduling policy is used to instruct the processor that schedules the first business process to change from the first processor to the second processor. The adjustment policy is used to instruct the migration of the first business process to the second memory, or it can also be called: the scheduling policy is used to instruct the memory that stores the first business process (referring to the relevant data of the first business process) to change from the first memory to the second memory.

[0164] In a possible implementation, the adjustment policy instructs the second processor to schedule the first service process to access a first memory address, where the first memory address is a physical address of the first memory.

[0165] In another possible implementation, the adjustment policy instructs the first processor to schedule the first service process to access the second memory address, where the second memory address is a physical address of the second memory.

[0166] In another possible implementation, the adjustment policy instructs the second processor to schedule the first service process to access the second memory address.

[0167] Furthermore, the adjustment policy can also be used to instruct the computing device to adjust the execution of the first thread according to the adjustment policy. Referring to the example of FIG13 , where the first thread is thread 2-4, the adjustment policy instructs processor 0 to schedule thread 2-4 to access the physical address of memory 0. Referring to the example of FIG15 , where the first thread is thread 1-0, the adjustment policy instructs processor 1 to schedule thread 1-0 to access the physical address of memory 1.

[0168] Optionally, for ease of explanation, the adjustment policy whose adjustment object is the first thread is referred to as the first adjustment policy. After the processing device sends the first adjustment policy to the computing device to optimize and adjust the first thread, the first thread after scheduling optimization is the second processor, and / or the memory that stores the data of the first thread after optimization is the second memory. Therefore, after the optimization and adjustment, the load of the second processor and / or the second memory increases, which may affect the normal operation of the second thread. The second thread refers to the thread scheduled by the second processor, and the second processor stores the data of the second thread in the second memory during the process of scheduling the second thread. In order to further optimize the computing device, in step S4, the processing device may also send a second adjustment policy to the computing device. The second adjustment policy is used to instruct the computing device to adjust the operation of the second thread according to the second adjustment policy.

[0169] For ease of understanding, please refer to Figure 13, taking the example of the first thread being thread 2-4. Before optimization, the processor (i.e., the first processor) that schedules thread 2-4 (the first thread) is processor 3, and the memory (i.e., the first memory) that stores thread 2-4 before optimization is memory 0. After optimization, the processor (i.e., the second processor) that schedules thread 2-4 (the first thread) is processor 0, and the memory (i.e., the first memory) that stores thread 2-4 after optimization is memory 0. Among the threads scheduled by processor 0 (the second processor), it is found that the access performance value of thread 3-0 is smaller after the processor bound to the thread is changed from processor 0 to processor 3. Therefore, thread 3-0 is determined as the second thread, and the processor that schedules thread 3-0 is changed from processor 0 (i.e., the second processor) to processor 3 (i.e., the first processor), while the data of thread 3-0 is still stored in memory 3. In conjunction with the example of Figure 13, the second adjustment strategy is illustrated by taking thread 3-0 as the second thread as an example. The second adjustment strategy instructs processor 3 to schedule thread 3-0 to access the physical address of memory 0.

[0170] After determining the second thread, the processing device sends a second adjustment policy to the computing device. The first adjustment policy is used to instruct the processor that schedules the second thread to change from the second processor to the first processor. Alternatively, the second adjustment policy is used to instruct the memory that stores the second thread (referring to the relevant data of the second thread) to change from the second memory to the first memory. Alternatively, the second adjustment policy is used to instruct the processor that schedules the second thread to change from the second processor to the first processor, and the memory that stores the second thread to change from the second memory to the first memory.

[0171] In a possible implementation, the second adjustment policy instructs the first processor to schedule the second thread to access a second memory address, where the second memory address is a physical address of the second memory.

[0172] In another possible implementation, the second adjustment policy instructs the second processor to schedule the second thread to access the first memory address, where the first memory address is a physical address of the first memory.

[0173] In another possible implementation, the second adjustment policy instructs the first processor to schedule the second thread to access the first memory address.

[0174] S5. The computing device adjusts the operation of the first business process according to the adjustment policy.

[0175] In step S5, after receiving the adjustment policy, the operating system (OS) on the computing device reallocates the processor and / or memory to the first business process according to the adjustment policy. Alternatively, the computing device rebinds the processor and / or memory to the first business process according to the adjustment policy.

[0176] After reallocation, the processor that schedules the first business process is changed to the second processor, the data of the first business process is still stored in the first memory, and the second processor accesses the first memory during the process of scheduling the first business process. Alternatively, after reallocation, the processor that schedules the first business process is still the first processor, the relevant data of the first business process is stored in the second memory, and the first processor accesses the second memory during the process of scheduling the first business process. Alternatively, after reallocation, the processor that schedules the first business process is changed to the second processor, the relevant data of the first business process is stored in the second memory, and the second processor accesses the second memory during the process of scheduling the first business process.

[0177] Furthermore, when the adjustment policy is used to instruct the computing device to adjust the execution of the first thread according to the adjustment policy, the computing device reallocates the processor and / or memory to the first thread (or rebinds the processor and / or memory to the first thread) according to the adjustment policy.

[0178] The following is an example:

[0179] In conjunction with Figure 13, the sum of the access performance values ​​of each business process after optimization is shown in Figure 14, which is a schematic diagram of the access performance values ​​after optimization in an embodiment of the present application. The processor of the scheduling thread 1-2 is changed from processor 1 to processor 2, and the memory storing the data of thread 1-2 remains unchanged. The processor of the scheduling thread 2-2 is changed from processor 1 to processor 2, and the memory storing the data of thread 2-2 remains unchanged. The processor of the scheduling thread 2-4 is changed from processor 3 to processor 0, and the memory storing the data of thread 2-4 remains unchanged. The processor of the scheduling thread 3-0 is changed from processor 0 to processor 3, and the memory storing the data of thread 3-0 remains unchanged. The sum of the access performance values ​​after optimization: 2 (access performance value of business process 0) + 5.2 (access performance value of business process 1) + 8.5 (access performance value of business process 2) + 7.8 (access performance value of business process 3) = 23.5.

[0180] In conjunction with Figure 15, the sum of the access performance values ​​of each business process after optimization is shown in Figure 16, which is a schematic diagram of the access performance values ​​after optimization in an embodiment of the present application. The memory for storing thread 1-0 data is changed from memory 0 to memory 1, and the processor for scheduling thread 1-0 remains unchanged. The memory for storing thread 2-0 data is changed from memory 0 to memory 1, and the processor for scheduling thread 2-0 remains unchanged. The memory for storing thread 2-3 data is changed from memory 0 to memory 3, and the processor for scheduling thread 2-3 remains unchanged. The memory for storing thread 3-1 data is changed from memory 3 to memory 2, and the processor for scheduling thread 3-1 remains unchanged. The sum of the optimized access performance values: 2 (access performance value of business process 0) + 5 (access performance value of business process 1) + 8.2 (access performance value of business process 2) + 7.6 (access performance value of business process 3) = 22.8.

[0181] After step S5, the processing device may optionally determine whether to terminate the adjustment optimization of the service process according to the optimization termination condition. The manner of terminating the adjustment optimization includes stopping sending the adjustment policy.

[0182] In one possible implementation, the optimization stopping condition includes detecting whether multiple NUMA nodes of the computing system include free memory and / or free processors. Optimization is stopped when the multiple NUMA nodes do not include free memory; and optimization is stopped when the multiple NUMA nodes do not include free processors (referring to computing devices).

[0183] In another possible implementation, the optimization stop condition includes: the second total access performance value is less than or equal to a preset value, and the second total access performance value is the sum of the access performance values ​​of multiple business processes running through multiple processors in the computing device to multiple memories in the computing device.

[0184] The above method can avoid over-optimization, reduce the amount of data migration, save computing resources, and improve computing performance.

[0185] In the embodiment of the present application, the processors of the processing device and the computing device are independent of each other. Therefore, the processing device running the computing device performance improvement method can effectively reduce the computing load of the processor in the computing device, save the computing resources of the computing device, and reduce the background noise of the computing device. In addition, by running the computing device performance improvement method on the processing device, continuous optimization can be achieved without manual analysis, reducing labor costs. By adjusting the strategy to reallocate a second processor and / or second memory with a higher performance value to the first business process, the computer reduces the access performance value of the computing device to the memory during the execution of the first business process, thereby improving computing performance.

[0186] In combination with the above-mentioned embodiments, the computing device performance improvement method proposed in the embodiments of the present application can also export the memory access data of the thread. The processing device is only responsible for collecting the memory access data, and the analysis of the memory access data can be performed by other devices, thereby realizing the decoupling of data collection and data analysis. It can be applied to scenarios that require centralized data analysis, thereby improving the implementation flexibility of the solution and reducing the implementation difficulty of the processing device.

[0187] Please refer to Figure 6, which is a flow chart of another embodiment of the method for improving computing device performance proposed in the embodiment of the present application. The method for improving computing device performance proposed in the embodiment of the present application further includes:

[0188] D1. Obtain memory access data of one or more threads running in the computing device. The memory access data is relevant data of the threads during their execution, and then the processing device caches the memory access data in a memory of the processing device.

[0189] D2. Save the memory access data of one or more threads.

[0190] Optionally, the processing device formats the memory access data of one or more threads cached in the memory corresponding to the processing device based on the configuration information. Specific formatting processing includes, but is not limited to, data inspection, data conversion, data padding, data filtering, data normalization, or data scaling, etc., which are not limited in the embodiments of the present application. The processing device can also format the memory access data, thereby improving the accuracy of thread optimization analysis and further reducing the access performance value of the processor to memory.

[0191] D3. Obtain configuration information, which is used to indicate that the accessed data needs to be exported. For example, the configuration information includes: the network address of the destination, or the input / output (IO) address of the destination.

[0192] D4. Send the accessed data to the export destination of the accessed data according to the configuration information.

[0193] In combination with the above embodiments, the computing device performance improvement method proposed in the embodiments of the present application can also continuously optimize the threads running on the computing device to further improve computing performance. Please refer to Figure 8, which is a flow chart of another embodiment of the computing device performance improvement method proposed in the embodiments of the present application. The computing device performance improvement method proposed in the embodiments of the present application also includes:

[0194] G1. Detect whether the total access performance value of the computing device is greater than a preset value.

[0195] If the total access performance value of the computing device is greater than or equal to the preset value, then proceed to step G2 to step G5; if the total access performance value of the computing device is less than the preset value, then proceed to step G6.

[0196] G2. Get the access performance value of one or more threads.

[0197] G3. Get the theoretical value of one or more threads.

[0198] It should be noted that the execution order of step G2 and step G3 is not limited in the embodiment of the present application.

[0199] G4. Determine a first thread to be optimized based on the access performance values ​​of one or more threads and the theoretical values ​​of the one or more threads, where the first service thread includes the first thread.

[0200] In one example, the access performance value of a thread run by a computing device and the theoretical value of the thread are shown in Table 1.

[0201] Table 1

[0202] In summary, the thread with the largest difference is thread 2, so thread 2 is selected as the first service thread for optimization. Then, thread 3, thread 1, and thread 0 are selected as the first threads for optimization in sequence.

[0203] G5. Reallocate the processor and / or memory to the first thread.

[0204] After step G5 is completed, step G1 is executed.

[0205] G6. End optimization.

[0206] In the embodiment of the present application, by running the above-mentioned computing device performance improvement method, continuous optimization can be achieved without manual analysis, thereby effectively improving computing performance.

[0207] In conjunction with the aforementioned embodiments, when executing the aforementioned method for improving computing device performance, the processing device may further split the method into multiple threads for execution to improve the processing efficiency of the processing device. For ease of distinction, the threads running on the processing device are referred to as processing device threads. For example, please refer to FIG9 , which is a flow chart of another embodiment of the method for improving computing device performance proposed in the embodiment of the present application. The method for improving computing device performance proposed in the embodiment of the present application further includes:

[0208] H1. The processing device starts processing device thread 1, obtains memory access data through the PMU of the computing device, and stores the memory access data in the memory of the processing device.

[0209] The memory access data obtained in step H1 refers to relevant data of the thread during its operation, such as a monitoring report (Profile). Exemplarily, the memory access data includes the access volume of the computing device when scheduling the thread. For an introduction to the access volume, please refer to the aforementioned embodiment and will not be repeated here.

[0210] When the processing device is running the processing device thread 1, the processing device may obtain memory access data from the performance monitoring unit PMU of the computing device and store the memory access data in a memory associated with the processing device. The memory associated with the processing device may be a cache within the processing device.

[0211] After the processing device stores the accessed data in the memory of the processing device, the process proceeds to step H2.

[0212] H2. Terminate processing device thread 1, start processing device thread 2, and format the access data cached in the memory of the processing device.

[0213] In step H2, processing device thread 1 is terminated, and the processing device then starts processing device thread 2. Processing device thread 2 is used to format the access data collected by processing device thread 1. Formatting the access data can also be referred to as preprocessing the access data. Formatting includes, but is not limited to, deduplication, merging, and / or filtering.

[0214] Before the processing device thread 2 formats the accessed data, step H3 may be entered.

[0215] H3. Check whether the export destination of accessed data is configured.

[0216] In step H3, the processing device obtains configuration information and then detects whether the configuration information configures an export destination for accessed data. The configuration information includes but is not limited to: a network address of the destination, or an input / output (IO) address of the destination.

[0217] If the export destination of the accessed data is configured in the configuration information, then the process proceeds to step H4; if the export destination of the accessed data is not configured, then the process proceeds to step H5.

[0218] H4. If the export destination of the accessed data is configured, then the processing device thread 2 is terminated and the processing device thread 3 is started to export the accessed data according to the configuration information.

[0219] In step H4, when the configuration information configures the export destination of the accessed data, the processing device terminates processing device 2 and starts processing device thread 3. Specifically, processing device thread 3 executes the configuration information to send the accessed data to the export destination, and then enters step H5.

[0220] Optionally, the processing device may export the original memory access data, or the processing device may export the memory access data after formatting, which is not limited in the embodiment of the present application.

[0221] H5. End processing device thread 2 or 3, start processing device thread 4, determine the access performance value of each business process running in the computing system, and then determine the total access performance value of the computing device.

[0222] In step H5, after the processing device terminates processing device thread 2 or processing device thread 3, it starts processing device thread 4. Processing device thread 4 determines the total access performance value of the computing device. The specific method for determining the total access performance value is described in the previous embodiment and is not described here in detail.

[0223] H6. Detect whether the total access performance value of the computing device is greater than a preset value.

[0224] In step H6, after determining the total access performance value of the computing device, the processing device checks whether the total access performance value of the computing device is greater than a preset value. If the total access performance value of the computing system is greater than the preset value, optimization is determined to be necessary, and the process proceeds to step H7. If the total access performance value of the computing system is less than or equal to the preset value, optimization is determined not to be necessary, and the process proceeds to step H1 to continue acquiring memory access data.

[0225] H7. End processing device thread 4, start processing device thread 5, determine the first business process whose access performance value differs the most from the theoretical value, and then reallocate the processor to the first thread of the first business process.

[0226] In step H7, the processing device terminates processing device thread 4 and starts processing device thread 5. Processing device thread 5 determines the business process with the largest difference between the access performance value and the theoretical value as the first business process, and then reallocates a processor to the first thread of the first business process. The first thread refers to one or more threads in the first business process that require optimization. After the processing device determines the second processor to be reallocated to the first thread, the processing device proceeds to step H8, where it sends an adjustment policy to the computing device. The adjustment policy instructs the operating system on the computing device to change the processor of the first thread from the first processor to the second processor.

[0227] H8. Send the adjustment policy to the computing device.

[0228] After step H8, execute step H9.

[0229] H9. Check whether the optimization stop conditions are met.

[0230] In step H9, the processing device detects whether the computing system meets the optimization stop condition after the optimization in step H7. If the optimization stop condition is met, the process proceeds to step H1; if not, the process proceeds to step H10 to continue optimizing the memory allocated by the first thread.

[0231] H10. End processing device thread 5, start processing device thread 6, and reallocate memory for the first thread of the first business process.

[0232] In step H10, the processing device terminates processing device thread 5 and initiates processing device thread 6, which then reallocates memory for the first thread of the first business process. After the processing device determines the second memory to be reallocated for the first thread, the process proceeds to step H11, where the processing device sends an adjustment policy to the computing device. The adjustment policy instructs the operating system on the computing device to change the memory of the first thread from the first memory to the second memory.

[0233] H11. Send the adjustment policy to the computing device.

[0234] After step H11, step H9 is executed.

[0235] In an embodiment of the present application, by running multiple processing device threads on a processing device, the computing device performance improvement method is offloaded to the processing device for execution. While utilizing the high concurrency characteristics of the processing device, the background noise of the computing device is effectively reduced, thereby improving computing efficiency. The processing device can also export the collected memory access data to other devices or services. The processing device focuses on executing business process management, while other devices or services further analyze the memory access data, which reduces the implementation difficulty of the processing device and improves the implementation flexibility.

[0236] On the basis of the embodiments corresponding to FIG. 1 to FIG. 16 , in order to better implement the above-mentioned solutions of the embodiments of the present application, relevant devices for implementing the above-mentioned solutions are also provided below.

[0237] Please refer to Figure 17, which is a schematic diagram of the structure of a processing device 1700 provided in an embodiment of the present application. This embodiment of the present application provides a processing device 1700, which includes a transceiver unit 1701 and a processing unit 1702. The processing device 1700 can specifically be the processing device in the above embodiment.

[0238] The processing device 1700 includes: a transceiver unit 1701, configured to obtain a first total access performance value of the multiple business processes running through the multiple processors in the computing device to the multiple memories in the computing device;

[0239] Processing unit 1702 is configured to determine, when the first total access performance value exceeds a preset value, a first business process requiring access performance adjustment based on the access performance value of each business process;

[0240] The processing unit 1702 is further configured to determine an access performance adjustment policy for the first business process;

[0241] The transceiver unit 1701 is further configured to send the adjustment policy to the computing device, instructing the computing device to adjust the operation of the first business process according to the adjustment policy.

[0242] In one possible implementation, the processing device is connected to a performance monitoring unit PMU in a plurality of processors in the computing device;

[0243] The obtaining of access performance values ​​of the multiple processes running on the multiple processors in the computing device to the multiple memories in the computing device includes:

[0244] The transceiver unit 1701 is further configured to obtain, through the PMU, the amount of access to at least one memory accessed by each processor when running a service process;

[0245] The processing unit 1702 is further configured to determine an access performance value of the business process according to the access volume;

[0246] The processing unit 1702 is further configured to determine the first total access performance value according to the access performance value of each of the business processes.

[0247] In a possible implementation, the processing unit 1702 is further configured to determine the amount of access and performance value of the memory accessed by the processor running the business process when executing the business process;

[0248] The processing unit 1702 is further configured to determine the access performance value of each business process according to the access volume and the performance value.

[0249] In one possible implementation,

[0250] The processing unit 1702 is further configured to compare the access performance value of each business process with a theoretical value;

[0251] The processing unit 1702 is further configured to select the business process having the largest difference between the access performance value and the theoretical value as the first business process.

[0252] In one possible implementation,

[0253] The processing unit 1702 is further configured to determine that the processor processing the first service process is a first processor;

[0254] The processing unit 1702 is further configured to determine that the memory storing the first business process is a first memory;

[0255] The processing unit 1702 is further configured to determine a second processor from the computing device, wherein a performance value of the second processor accessing the first memory is better than a performance value of the first processor accessing the first memory;

[0256] The processing unit 1702 is further configured to determine an access performance adjustment policy for the first business process, where the adjustment policy indicates migrating the first business process to the second processor.

[0257] In one possible implementation,

[0258] The processing unit 1702 is further configured to determine that the processor processing the first service process is a first processor;

[0259] The processing unit 1702 is further configured to determine that the memory storing the first business process is a first memory;

[0260] The processing unit 1702 is further configured to determine a second memory from the computing device, wherein a performance value of the first processor accessing the second memory is better than a performance value of the first processor accessing the first memory;

[0261] The processing unit 1702 is further configured to determine an access performance adjustment policy for the first business process, where the adjustment policy indicates migrating the first business process to the second memory.

[0262] In one possible implementation,

[0263] The processing unit 1702 is further configured to determine a second total access performance value of the multiple business processes running on the multiple processors in the computing device to the multiple memories in the computing device;

[0264] The processing unit 1702 is further configured to stop the optimization when the second total access performance value is less than or equal to the preset value.

[0265] In one possible implementation, the processing device 1700 is a data processing unit DPU externally connected to the computing device, or a graphics processing unit GPU, a neural network processor NPU, or a chip-level system SOC built into the computing device.

[0266] In another example, the transceiver unit 1701 is used to execute step S1 and / or step S4 of the aforementioned embodiment, and the processing unit 1702 is used to execute step S2 and / or step S3 of the aforementioned embodiment.

[0267] In another example, the transceiver unit 1701 is used to execute step D1, step D3 and / or step D4 of the aforementioned embodiment, and the processing unit 1702 is used to execute step D2 of the aforementioned embodiment.

[0268] In another example, the processing unit 1702 is configured to execute step F1, step F2, step F3 and / or step F4 of the aforementioned embodiment.

[0269] In another example, the processing unit 1702 is configured to execute step G1, step G2, step G3, step G4, step G5 and / or step G6 of the aforementioned embodiment.

[0270] In another example, the transceiver unit 1701 is used to execute step H4, step H8 and / or step H11 of the aforementioned embodiment, and the processing unit 1702 is used to execute step H1, step H2, step H3, step H5, step H6, step H7, step H9 and / or step H10 of the aforementioned embodiment.

[0271] It should be noted that the execution process of the units of the above-mentioned processing device 1700 and the corresponding technical effects, etc., can be specifically referred to the description in the method embodiment shown above in this application, and will not be repeated here.

[0272] Please refer to Figure 18, which is a schematic diagram of the structure of a processing device 1800 provided in this application. The processing device 1800 at least includes an input and output interface 1802. The processing device 1800 can be a chip or an integrated circuit.

[0273] Optionally, the device further includes a logic circuit 1801 .

[0274] The transceiver unit 1701 shown in FIG17 may be a communication interface, which may be the input / output interface 1802 in FIG18 , which may include an input interface and an output interface. Alternatively, the communication interface may be a transceiver circuit, which may include an input interface circuit and an output interface circuit.

[0275] Among them, the logic circuit 1801 and the input and output interface 1802 can execute the method executed by the processing device in the aforementioned method embodiment and achieve corresponding beneficial effects, which will not be repeated here.

[0276] Optionally, the logic circuit 1801 may include a memory and a processor, wherein the memory is used to store computer programs, and the processor reads and executes the computer programs stored in the memory to perform corresponding processing and / or steps in any method embodiment.

[0277] Alternatively, logic circuit 1801 may include only a processor. A memory for storing computer programs is located outside the processing device, and the processor is connected to the memory via circuits / wires to read and execute the computer programs stored in the memory. The memory and processor may be integrated or physically separate.

[0278] Alternatively, the logic circuit 1801 may be one or more chips, or one or more integrated circuits. For example, the logic circuit 1801 may be one or more data processing units, field programmable gate arrays, application-specific integrated circuits, system-on-chips, central processing units, network processors, digital signal processing circuits, microcontrollers, programmable controllers, or other integrated circuits, or any combination of the above chips or processors.

[0279] Please refer to Figure 19, which is a schematic diagram of the structure of a processing device 1900 provided in this application. The processing device 1900 can specifically be the processing device in the above embodiment.

[0280] Herein, a possible logical structure diagram of the processing device 1900 is shown. The processing device 1900 may include but is not limited to at least one processor 1901 and a communication port 1902 .

[0281] Further optionally, the processing device 1900 may also include at least one of a memory 1903 and a bus 1904 . In an embodiment of the present application, the at least one processor 1901 is used to control the actions of the processing device 1900 .

[0282] In addition, processor 1901 can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0283] It should be noted that the processing device 1900 shown in Figure 19 can be specifically used to implement the steps implemented by the processing device in the aforementioned method embodiment and to achieve the corresponding technical effects of the processing device. The specific implementation methods of the device shown in Figure 19 can refer to the description in the aforementioned method embodiment and will not be repeated here.

[0284] An embodiment of the present application also provides a computer program product, which, when run on a computer, enables the computer to execute the steps executed by the aforementioned computing device, or enables the computer to execute the steps executed by the aforementioned computing device.

[0285] A computer-readable storage medium is also provided in an embodiment of the present application. The computer-readable storage medium stores a program for signal processing. When the program is run on a computer, the computer executes the steps executed by the aforementioned computing device, or the computer executes the steps executed by the aforementioned computing device or computing device.

[0286] The computing device or computing device provided in the embodiment of the present application can specifically be a chip, and the chip includes: a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, a pin or a circuit. The processing unit can execute the computer execution instructions stored in the storage unit so that the chip in the computing device executes the compilation method described in the above embodiment. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit can also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static computing devices that can store static information and instructions, a random access memory (RAM), etc.

[0287] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0288] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0289] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0290] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0291] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

Claims

1. A method for improving computing device performance, characterized in that: The method is applied to a processing device connected to the computing device, the computing device being a non-uniform memory access (NUMA) computing device including multiple processors and multiple memories, and the method includes: Obtaining a first total access performance value of a plurality of business processes running in the computing device through the plurality of processors to the plurality of memories in the computing device; When the first total access performance value exceeds a preset value, determining a first business process whose access performance needs to be adjusted according to the access performance value of each business process; Determining an access performance adjustment strategy for the first business process; The adjustment policy is sent to the computing device, instructing the computing device to adjust the operation of the first business process according to the adjustment policy.

2. The method according to claim 1, characterized in that The processing device is connected to a performance monitoring unit PMU in a plurality of processors in the computing device; The obtaining of access performance values ​​of the multiple processes running on the multiple processors in the computing device to the multiple memories in the computing device includes: Obtaining, through the PMU, the amount of access to at least one memory accessed by each processor when running a service process; Determining an access performance value of the business process according to the access volume; The first total access performance value is determined according to the access performance value of each of the business processes.

3. The method according to claim 2, characterized in that Determining the access performance value of the business process according to the access volume includes: Determining the amount of access and performance value of the memory accessed by the processor running the business process when executing the business process; The access performance value of each business process is determined according to the access volume and the performance value.

4. The method according to any one of claims 1 to 3, characterized in that The determining, according to the access performance value of each business process, the first business process requiring access performance adjustment includes: Compare the access performance value of each business process with the theoretical value; The business process having the largest difference between the access performance value and the theoretical value is selected as the first business process.

5. The method according to any one of claims 1 to 4, characterized in that Determining the access performance adjustment strategy for the first business process includes: Determining that a processor processing the first service process is a first processor; Determining that a memory storing the first business process is a first memory; determining a second processor from the computing device, wherein a performance value of the second processor accessing the first memory is better than a performance value of the first processor accessing the first memory; An access performance adjustment policy for the first business process is determined, where the adjustment policy indicates migrating the first business process to the second processor.

6. The method according to any one of claims 1 to 4, characterized in that Determining the access performance adjustment strategy for the first business process includes: Determining that a processor processing the first service process is a first processor; Determining that a memory storing the first business process is a first memory; determining a second memory from the computing device, wherein a performance value of the first processor accessing the second memory is better than a performance value of the first processor accessing the first memory; An access performance adjustment policy for the first business process is determined, where the adjustment policy indicates migrating the first business process to the second memory.

7. The method according to any one of claims 1 to 6, characterized in that After sending the adjustment policy to the computing device, the method further includes: Determine a second total access performance value of the plurality of business processes running in the computing device through the plurality of processors to the plurality of memories in the computing device; When the second total access performance value is less than or equal to the preset value, the optimization is stopped.

8. The method according to any one of claims 1 to 7, characterized in that The processing device is a data processing unit DPU externally connected to the computing device, or a graphics processor GPU, a neural network processor NPU, or a chip-level system SOC built into the computing device.

9. A processing device, characterized in that The processor device includes a communication interface and a processor: The communication interface is used to input and / or output signaling or data; The processor is configured to execute a computer-executable program so that the method according to any one of claims 1 to 8 is executed.

10. A computing system, characterized in that The computing system includes: a computing device and a processing device, The processing device is connected to the computing device, the computing device is a non-uniform memory access (NUMA) computing device, and the computing device includes multiple processors and multiple memories; The processing device executes the method according to any one of claims 1 to 8.

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