Scalable parameter allocation of fluxoniums in a cross-resonance architecture with static capacitive couplings

Abstract

A superconducting qubit processor includes a plurality of fluxonium superconducting loop-based qubit devices, the fluxonium qubit devices arranged and connected in a lattice with a capacitive coupling between neighbour fluxonium qubit devices in the lattice; the fluxonium-based qubit devices divided in a first group of first type fluxonium qubits as control qubits and a second group of second type fluxonium qubits as target qubits, such that in the lattice each first type fluxonium qubit is neighboured by a second type fluxonium qubit and vice versa; the first type fluxonium qubits having a first qubit frequency and the second type fluxonium qubits having a second qubit frequency; the first and second qubit frequency being defined by structural parameters of the first and the second type fluxonium qubit, respectively; the first qubit frequency having a value between about 30% and about 50% of the value of the second qubit frequency.

Description

[0001]Scalable parameter allocation of fluxoniums in a cross-resonance architecture with static capacitive couplings Field of the invention The present invention relates to a superconducting qubit processor comprising a plurality of fluxonium superconducting loop-based qubit devices, and to a method for manufacturing such a superconducting qubit processor. Background An implementation of a superconducting qubit processor is known from prior art “Topological and Subsystem Codes on Low-Degree Graphs with Flag Qubits” by Chamberland et al, Physical Review X 10, 011022 (2020). The implementation comprises a lattice of fixed-frequency transmon-type qubit devices with static capacitive coupler architecture. The lattice is designed in a heavy hexagon code or square code arrangement. It is known that transmon-type qubit devices (transmons) are prone to frequency collisions which have the effect to adversely increase the error rate of the superconducting qubit processor and thus reduce its efficiency. A transmon-based design of such qubit processor is expected already to require laser annealing to fabricate a distance 3 heavy- hexagon processor with about twenty qubits. It is an object of the present invention to overcome or mitigate one or more of the disadvantages from the prior art. Summary of the invention The object is achieved by a superconducting qubit processor in accordance with claim 1. By implementing the superconducting qubit processor comprising a plurality of fluxonium superconducting loop-based qubit devices, arranged and connected in a lattice with a capacitive coupling between neighbour fluxonium qubit devices in the lattice, the fabrication demands become more simplified compared to the fabrication of a qubit processor based on transmons. Also, the operation characteristics of the processor are relatively enhanced. By arranging the plurality of fluxonium-based qubit devices in a first group of first type fluxonium qubits with a function of control qubits and a second group of second type fluxonium qubits with a function of target qubits, such that in the lattice each first type fluxonium qubit is neighboured by a second type fluxonium qubit and vice versa, the first type fluxonium qubits having a first qubit frequency and the second type fluxonium qubits having a second qubit frequency; the first qubit frequency being defined by structural parameters of the first type fluxonium qubit; the second qubit frequency being defined by structural parameters of the second type fluxonium qubit, a cross-resonance (CR) scheme is used to facilitate two qubit interactions between connected qubits of the first and second type. The CR scheme involves driving the first type fluxonium with electromagnetic fields oscillating at the connected second type fluxonium's qubit frequency. The CR scheme is possible between qubits connected either capacitively or inductively, but this application focuses on couplings provided by primarily capacitive means since strong capacitive coupling is easier to engineer compared to inductive coupling. In the above scheme, one of the pair, is called the control qubit, driven at the frequency of the other, called the target qubit. The cross-resonance scheme has the effect that the target qubit rotates around an axis with a Rabi frequency and direction conditional on the state of the control qubit. This microwave activated interaction naturally generates a CNOT gate up to additional phase gates and target qubit rotations. Moreover, the feature of the first qubit frequency having a value between about 30% and about 50% of the value of the second qubit frequency, improves individual qubit addressability when performing arbitrary sequences of single and two qubit gates which reduces unintended crosstalk to neighbouring qubits not involved in a particular gate operation. The target qubit should have a frequency higher than the control qubit, otherwise the CNOT gate speed (i.e., the inverse of gate duration time) appears to linearly decrease to zero as the target qubit frequency goes to zero. Also the target qubit frequency should be detuned from one third of its own |1^ → |2^ quantum state transition frequency because of harmonics generated by the control qubit. To avoid collisions the first (control) qubit frequency is set within the predetermined range of 30% to 50% of the second (target) qubit frequency. Brief description of drawings Embodiments of a superconducting qubit processor will by way of non-limiting example be described in detail with reference to the accompanying drawings. In the drawings: Figure 1 schematically shows a diagram of an arrangement of a pair of fluxonium qubit devices, coupled capacitively; Figure 2 schematically shows a heavy-hexagon arrangement of a superconducting qubit processor according to an embodiment; Figure 3 schematically shows a diagram of a CNOT speed enhancement factor for different driving frequency and control qubit EJ parameter frequency; Figure 4 schematically shows a diagram for erroneous transitional probability for varying target / spectator parameters and predetermined ECparameter frequency; Figure 5 schematically shows a diagram for collision-free probability as a function of junction resistance variation, in accordance with a superconducting qubit processor according to an embodiment. The superconducting qubit processor and features thereof are shown schematically and not drawn to scale. The figures are for illustrative purposes only, and do not serve as restriction of the scope as laid down by the claims. Detailed description of embodiments Figure 1 schematically shows a diagram of an arrangement of a pair of fluxonium qubit devices, coupled capacitively. A first type fluxonium qubit device and a second type fluxonium qubit device are arranged adjacent and coupled capacitively by a capacitor. Each fluxonium qubit device comprises a loop constructed from linear elements of superconducting material, in which a Josephson junction is arranged in parallel with an inductance and a capacitance. The Josephson junction consists of a thin insulator layer in the superconducting material. The fluxonium qubit devices each have individual structural parameters ^^^^, ^^^^, and ^^^^, relating to charging energy ^^^^, Josephson energy ^^^^ and inductive energy ^^^^ , as will be described below in more detail. The diagram shows the first type fluxonium qubit device or control qubit being driven by an electromagnetic pulse modulated at the second type fluxonium qubit device or target qubit frequency with peak amplitude Ω at frequency ωd. To facilitate a cross-resonance scheme, the control and target qubits are coupled via their charge operators ^̂^c, ^̂^t with coupling strength ^^. Preferably, the control and target qubits are fixed at their respective half flux (Φ / 2) bias point to improve the coherence time. By varying the duration of the pulse, the target qubit rotates around the ^^-axis at different rates depending on the initial control qubit eigenstate. A difference in rotation angle of ^^ realizes a CNOT gate (with an additional target qubit rotation) between the control and target qubit. According to the invention, a quantum processor architecture composed of all fluxonium qubits fixed at half-flux bias with qubit frequencies below 1 GHz is proposed. The qubits can be arranged with either heavy-hexagon or regular hexagon or square lattice connectivity, with either direct capacitive coupling between neighbours or capacitive coupling mediated by a bus resonator. More generally, the qubits can be arranged with any connectivity having a planar graph. Two-qubit CNOT gates are implemented using the cross-resonance (CR) effect by coupling adjacent fluxoniums via their charge operators. The fluxoniums are divided into two parameter groups, “control” and “target”. No two qubits of the same group or type (control and control, or target and target) are directly coupled to one another. During the CNOT gate, the control qubit is strongly irradiated by a CR drive at the target qubit’s frequency. Figure 2 schematically shows a heavy-hexagon arrangement of a superconducting qubit processor 100 according to an embodiment. According to an embodiment, the superconducting qubit processor 100 comprises a plurality of fluxonium superconducting loop-based qubit devices (fluxonium qubit devices) 2, 4, 6. The fluxonium qubit devices are arranged and connected in a lattice with a capacitive coupling between each pair of neighbour fluxonium qubit devices in the lattice. The plurality of fluxonium qubit devices are divided in a first group of first type fluxonium qubits 2, 4 with a function of control qubits and a second group of second type fluxonium qubits 6 with a function of target qubits. The arrangement of the two groups of fluxonium qubits in the lattice is such that each first type fluxonium qubit 2; 4 is neighboured by a second type fluxonium qubit 6 and vice versa. According to an embodiment, the lattice of the superconducting qubit processor 100 has a layout of a heavy hexagon lattice or a layout of a square lattice. By the arrangement that each first type fluxonium qubit is neighboured by a second type fluxonium qubit and vice versa, in the lattice a first type fluxonium qubit and a neighbour second type fluxonium qubit form a CNOT gate. As known to the skilled in the art, a fluxonium qubit device has 3 structural parameters conventionally expressed in units of frequency, which parameters can be adapted during design and manufacturing, ^^^^, ^^^^, and ^^^^, relating to charging energy ^^^^, Josephson energy ^^^^and inductive energy ^^^^. To correlate the parameters with the structure of the fluxonium qubit device: the charging energy ECof a fluxonium qubit is inversely proportional to the capacitance of the fluxonium qubit device. The inductive energy EL is inversely proportional to the inductance of the fluxonium qubit device. The Josephson energy EJis proportional to the Josephson junction critical current. To distinguish, the first type fluxonium qubits have a first qubit frequency and the second type fluxonium qubits have a second qubit frequency that are defined by the above structural parameters of the fluxonium qubit devices according to the respective group. The first qubit frequency is defined by structural parameters of the first type fluxonium qubit, and the second qubit frequency is defined by structural parameters of the second type fluxonium qubit. According to the embodiment, the first qubit frequency has a value between about 30% and about 50% of the value of the second qubit frequency. In an example, the first qubit frequency is designed to be between 250 and 350 MHz and the second qubit frequency is between 600 and about 1000 Mhz. For the control qubit (i.e, the first type fluxonium qubit device), an ^^^^c / ^^^^cratio is chosen and fixed to be as small as possible while still having an ^^^^c that can be reliably fabricated. For ^^^^ca value is chosen large enough so that the control qubit has “sufficient” anharmonicity, as will be explained with reference to Figure 3. Figure 3 schematically shows a diagram of a CNOT speed enhancement factor for different driving frequency and control qubit EJcparameter frequency. The CNOT speed enhancement is defined as the relative speedup over a two level truncation of the two fluxonium systems. As an example, the diagram is shown as a function of the driving frequency and the control qubit parameter EJrelated frequency, with ELc / EJc= 0.2 and ECc=1GHz. Figure 3 is qualitatively similar for different choices of ^^^^c / ^^^^cratio. The dotted lines indicate resonance frequencies of the control qubit where the CR drive will induce leakage transitions if the target qubit frequency is too close. The two lowest frequency dotted lines correspond to ^^^^,02 / 4 and ^^^^,21 / 3 where ^^^^,^^^^ is the control qubit’s |^^^ → |^^^ quantum state transition frequency. It is intended that the dotted lines be beyond a designated qubit frequency interval of 0 – 1 GHz, so that the target qubit frequency is not at risk to collide with these resonances. It will be appreciated that fluxonium qubit devices can be reliably fabricated with ^^^^ no lower than ∼ 0.3 GHz. Based on this, control qubit parameters can be chosen (E in GHz): ^^^^c= 4.0, ^^^^c = 1.2, ^^^^c = 0.4; and ^^^^c / ^^^^c of 0.1 (i.e. <0.2). To achieve fast CNOT gates, the CR drive needs to be large enough to saturate the entangling interaction. The charge line of the control qubits should thus be placed closer to the fluxonium’s capacitive pads to increase its sensitivity to the drive signals. For the target qubit (i.e., the second type fluxonium qubit device), a lower ^^^^t results in faster CNOT gates. But fabrication constraints limits ^^^^tto be at least ∼ 2 GHz. Further, a low ^^^^t reduces anharmonicity and makes frequency collisions more likely. In the following we provide design rules for choosing target fluxonium parameters. The target qubits should have a frequency higher than the control qubits, otherwise the CNOT gate speed appears to linearly decrease to zero as the target qubit frequency goes to zero. Due to a harmful transition between a control and spectator qubit, the target qubit frequency should be greater than (^^^^,01 + 1 GHz) / 2 (where 1 GHz is selected as upper limit of target qubit frequencies). The target qubit frequency also should be detuned from ^^^^,12 / 3 (one-third of its |1^ → |2^ quantum state transition frequency). This is because the control qubit is driven strongly and hence higher harmonics of the driving frequency are also generated by the dressed control qubit (e.g. ^^^^,01, 2^^^^,01, 3^^^^,01, etc.). To abate this collision it is determined that either ^^^^,12 / 3 is beyond the upper bound of target qubit frequencies (1 GHz), or below the lower frequency bound ((^^^^,01 + 1 GHz) / 2 ≈ 650 MHz). The latter case leads to slightly faster CNOT gates, but also increased relaxation rates through dielectric loss and quasiparticle tunneling. In the former case, the anharmonicity also should not be too large as this slows down the CNOT gate. Based on the above as target fluxonium parameters are selected (E in GHz): ^^^^t= 2.8, ^^^^t= 1.2, ^^^^t= 0.5 − 0.8; and ^^^^t / ^^^^tratio of about 0.23. In an embodiment, the ^^^^t / ^^^^t ratio of the target qubits and ^^^^c / ^^^^c ratio of the control qubits should each less than 0.3. In a further embodiment, the control qubit type has a first barrier height ratio of 5 <= EBc / ECc <= 10, where EBc is a difference between the local maxima and minima of the function: V1c(φ) = 0.5*ELc*φ2+ EJc*cos(φ), which defines the potential energy V1c of the control type fluxonium qubit as a function of phase φ, and the target type fluxonium qubit has a second barrier height ratio of 1.5 <= EBt / ECt <= 5, where EBt is a difference between the local maxima and minima of the function V2t(φ) = 0.5*ELt*φ2+ EJt*cos(φ), which defines the potential energy V2t of the target type fluxonium qubit as a function of phase φ. In comparison, the control qubit has a higher anharmonicity, and the target qubits have a lower anharmonicity. Control qubit–target qubit and control qubit–spectator qubit collisions were analysed numerically and visualized using a heatmap as shown in fig.4 to inform on the severity of harmful transitions and regions of parameter space far from harmful transitions. Figure 4 schematically shows a diagram for erroneous transitional probability for varying target / spectator parameters and predetermined ECparameter frequency. In the set-up as shown ECc= 1.2 GHz. Control qubit parameters are fixed at EJ,c= 4.0 GHz, EC,c= 1.2 GHz, and EL,c= 0.4 GHz. The drive amplitude is Ω=2.0 and coupling strength is J=0.1. The driving frequency is fixed at 0.6 GHz in the Control--Spectator graph. The points X1 – X6 relate to the quantum state transitions as indicated in table 1: Control-Target Control-Spectator Condition Bounds [MHz] Condition Bounds [MHz] X1 fc,01 − ft,01 ±100 X5 fs,01 − ft,01 ±30 X2 fc,01+ ft,12− 4ft,01±5 X6 fs,01+ fc,01− 2ft,01−90, +35 X3 ft,12− 3ft,01±20 fs,12− fc,01− 2ft,01−15, +40 X4 fc,02 − 4ft,01 −80, +20 fs,12 − 3ft,01 ±10 fs.02− 4ft,01±5 Table 1: quantum state transitions for control qubit - target qubit and control qubit – spectator qubit. (indices: control qubit: c, target qubit: t, spectator qubit: s) The allocation of structural parameters for each of control and target qubits allows to obtain relatively high collision-free yields (i.e. avoiding harmful transitions) in the superconducting qubit processor by detuning the target qubits relative to the control qubits. Figure 5 schematically shows a diagram for calculated collision-free yield probability as a function of junction resistance variation, in accordance with an superconducting qubit processor according to an embodiment. The solid lines S1, S2 indicate the probability for 300 and 1000 fluxonium based qubits respectively. The dotted lines D3, D5, D7 indicate the collision-free yield probability for so-called distance 3 (23 qubits), distance 5 (65 qubits) and distance 7 (127 qubits) respectively.. D3, D5, D7 are Monte Carlo sampled collision-free probabilities for fluxoniums using the proposed example parameter allocation: EJ,c=4.0 EC,c=1.2 EL,c=0.4, and EJ,t=2.8, EC,t=1.2, EL,t=0.5-0.8. S1 and S2 are curves based on extrapolation of the Monte Carlo sampled probabilities. The same extrapolation technique is used as in: https: / / www.nature.com / articles / s41534- 021-00464-5 Variation of in particular the structural parameters EJ and EL of the fluxonium qubit devices can be achieved according to state-of-the-art by means of process technology related Josephson junction manufacturing variations or alternatively by laser annealing the manufactured Josephson junctions in which Josephson junctions are selectively exposed to energy from laser beam(s). The lattice of the superconducting qubit processor can be manufactured by creating a plurality of fluxonium superconducting loop-based qubit devices that are arranged and connected in a lattice with a capacitive coupling between neighbour fluxonium qubit devices in the lattice. According to the method, the creation of the plurality of fluxonium-based qubit devices is configured to form a first group of first type fluxonium qubits with, in a cross-resonance gate operation, a function of control qubits and a second group of second type fluxonium qubits with a function of target qubits, such that in the lattice each first type fluxonium qubit is neighboured by a second type fluxonium qubit and vice versa. The method comprises creating on a substrate the fluxonium qubit devices according to a pattern corresponding to the lattice, where each fluxonium qubit device comprises a loop constructed from linear elements of superconducting material, in which a Josephson junction is arranged in parallel with an inductance, the Josephson junction consisting of a thin insulator layer in the superconducting material and the inductance possibly provided by an array of Josephson junctions or by a line consisting of aluminium granular particles. The first type fluxonium qubits are created with a first width and thickness of the linear elements and a first thickness and width of the thin insulator layer according to a first device layout for the first type fluxonium qubits and the second type fluxonium qubits are created with a second width and thickness of the linear elements and a second thickness and width of the thin insulator layer according to a second device layout for the second type fluxonium qubits, with the first device layout being different from the second device layout, in a manner that the first device layout defines a first qubit frequency for the first type fluxonium qubits and the second device layout defines a second qubit frequency for the second type fluxonium qubits. The first qubit frequency is configured to have a value between about 30% and about 50% of the value of the second qubit frequency. The capacitance of the first and second fluxonium devices can be adjusted by lithography of their respective layout during the manufacturing of the qubit processor. Embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. However, the embodiments of the present disclosure are not limited to the specific embodiments and should be construed as including all modifications, changes, equivalent devices and methods, and / or alternative embodiments of the present disclosure. The terms “have”, “may have”, “include” and “may include” as used herein indicate the presence of corresponding features (for example, elements such as numerical values, functions, operations, or parts), and do not preclude the presence of additional features. The terms “A or B”, “at least one of A or / and B” or “one or more of A or / and B” as used herein include all possible combinations of items enumerated with them. For example, “A or B”, “at least one of A and B”, or “at least one of A or B” means (1) including at least one A, (2) including at least one B, or (3) including both at least one A and at least one B. The terms such as “first” and “second” as used herein may modify various elements regardless of an order and / or importance of the corresponding elements, and do not limit the corresponding elements. These terms may be used for the purpose of distinguishing one element from another element. For example, a first element may be referred to as a second element without departing from the scope the present invention, and similarly, a second element may be referred to as a first element. It will be understood that, when an element (for example, a first element) is “(operatively or communicatively) coupled with / to” or “connected to” another element (for example, a second element), the element may be directly coupled with / to another element, and there may be an intervening element (for example, a third element) between the element and another element. To the contrary, it will be understood that, when an element (for example, a first element) is “directly coupled with / to” or “directly connected to” another element (for example, a second element), there is no intervening element (for example, a third element) between the element and another element. The expression “configured to (or set to)” as used herein may be used interchangeably With “suitable for” “having the capacity to” “designed to” “adapted to”, “made to”, or “capable of” according to a context. The term “configured to (set to)” does not necessarily mean “specifically designed to” in a hardware level. Instead, the expression “apparatus configured to…” may mean that the apparatus is “capable of…” along with other devices or parts in a certain context. The terms used in describing the various embodiments of the present disclosure are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. All of the terms used herein including technical or scientific terms have the same meanings as those generally understood by an ordinary skilled person in the related art unless they are defined otherwise. The terms defined in a generally used dictionary should be interpreted as having the same or similar meanings as the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings unless they are clearly defined herein. According to circumstances, even the terms defined in this disclosure should not be interpreted as excluding the embodiments of the present disclosure. The person skilled in the art will understand that the features described above and / or below may be combined in any way deemed useful. The drawings of the present disclosure show examples / embodiments of the invention, which will be described in detail hereinafter. It is to be understood that one or more of elements / components shown and / or described in one or more of these examples / embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples / embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another. The invention has been described with reference to embodiments. Obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims.

Claims

Claims 1. A superconducting qubit processor comprising a plurality of fluxonium superconducting loop-based qubit devices, the fluxonium qubit devices arranged and connected in a lattice with a capacitive coupling between neighbour fluxonium qubit devices in the lattice; according to a cross-resonance scheme, the plurality of fluxonium-based qubit devices divided in a first group of first type fluxonium qubit devices with a function of control qubits and a second group of second type fluxonium qubit devices with a function of target qubits, such that in the lattice each first type fluxonium qubit device is neighboured by a second type fluxonium qubit device and vice versa; the first type fluxonium qubit devices having a first qubit frequency and the second type fluxonium qubit devices having a second qubit frequency; the first qubit frequency being defined by structural parameters of the first type fluxonium qubit device; the second qubit frequency being defined by structural parameters of the second type fluxonium qubit device; wherein the first qubit frequency has a value between about 30% and about 50% of the value of the second qubit frequency.

2. The superconducting qubit processor according to claim 1, wherein a first type fluxonium qubit device serving as the control qubit and a second type fluxonium qubit serving as the target qubit form a CNOT gate.

3. The superconducting qubit processor according to claim 1 or 2, wherein the first qubit frequency is between 250 and 350 MHz and the second qubit frequency is between 600 and about 1000 Mhz.

4. The superconducting qubit processor according to any one of claims 1 – 3, wherein the structural parameters of the first type fluxonium qubit comprise a first capacitance based parameter EC1, a first inductance based parameter EL1 and a first Josephson energy EJ1 of the Josephson junction of the first type fluxonium qubit device, and the structural parameters of the second type fluxonium qubit comprise a second capacitance based parameter EC2, a second inductance based parameter EL2 and a second Josephson energy EJ2 of a Josephson junction of the second type fluxonium qubit device.

5. The superconducting qubit processor according to claim 4, wherein: EC1 has a value of about 1.2 GHz, EL1 has a value of about 0.4 GHz and EJ1 has a valueof about 4.0 GHz; EC2 has a value of about 1.2 GHz, EL2 has a value of about 0.5 – 0.8 GHz and EJ2 has a value of about 2.8 GHz.

6. The superconducting qubit processor according to claim 4 or 5, wherein the first type fluxonium qubit device has a ratio of the first inductance based parameter EL1 and the first Josephson energy EJ1, EL1 / EJ1 <= 0.3, and the second type fluxonium qubit device has a ratio of the second inductance based parameter EL2 and the second Josephson energy EJ2, EL2 / EJ2 <= 0.

3.

7. The superconducting qubit processor according to claim 6, wherein the first type fluxonium qubit device has a first barrier height ratio of 5 <= EB1 / EC1 <= 10, where EB1 is a difference between the local maxima and minima of the function: V1(φ) = 0.5*EL1*φ2+ EJ1*cos(φ) which defines the potential energy V1 of the first type fluxonium qubit device as a function of phase φ, and the second type fluxonium qubit device has a second barrier height ratio of 1.5 <= EB2 / EC2 <= 5, where EB2 is a difference between the local maxima and minima of the function: V2(φ) = 0.5*EL2*φ2+ EJ2*cos(φ) which defines the potential energy V2 of the second type fluxonium qubit device as a function of phase φ.

8. The superconducting qubit processor according to any one of claims 4 – 7, wherein the first and second capacitance based parameter EC1, EC2 are inversely proportional to the capacitance of the first fluxonium qubit device and the second fluxonium qubit device, respectively; the first and second inductance based parameter EL1, EL2 are inversely proportional to the inductance of the first fluxonium qubit device and the second fluxonium qubit device, respectively.

9. The superconducting qubit processor according to any one of the preceding claims, wherein the lattice has either a heavy hexagon lattice layout or a square lattice layout or a connectivity having a planar graph.

10. The superconducting qubit processor according to any one of the preceding claims, wherein the capacitive coupling between neighbour fluxonium qubit devices is either a direct capacitive coupling between the neighbour fluxonium qubit devices or a capacitive couplingmediated by a bus resonator extending between said neighbour fluxonium qubit devices.

11. A method for manufacturing a superconducting qubit processor comprising a plurality of fluxonium superconducting loop-based qubit devices, the fluxonium qubit devices arranged and connected in a lattice with a capacitive coupling between neighbour fluxonium qubit devices in the lattice; the plurality of fluxonium-based qubit devices divided in a first group of first type fluxonium qubit devices with a function of control qubits and a second group of second type fluxonium qubit devices with a function of target qubits, such that in the lattice each first type fluxonium qubit device is neighboured by a second type fluxonium qubit device and vice versa, the method comprising: -- creating on a substrate the fluxonium qubit devices according to a pattern corresponding to the lattice, each fluxonium qubit device comprising a loop constructed from linear elements of superconducting material, in which a Josephson junction is arranged in parallel with an inductance, the Josephson junction consisting of a thin insulator layer in the superconducting material; -- creating the first type fluxonium qubit devices with a first width and thickness of the linear elements and a first thickness and width of the thin insulator layer according to a first device layout for the first type fluxonium qubit devices and -- creating the second type fluxonium qubit devices with a second width and thickness of the linear elements and a second thickness and width of the thin insulator layer according to a second device layout for the second type fluxonium qubit devices, with the first device layout being different from the second device layout, in a manner that the first device layout defines a first qubit frequency for the first type fluxonium qubit devices and the second device layout defines a second qubit frequency for the second type fluxonium qubit devices, wherein the first qubit frequency has a value between about 30% and about 50% of the value of the second qubit frequency.

12. The method according to claim 11, further comprising annealing the first type fluxonium qubits individually and / or the second type fluxonium qubits individually by means of a laser beam so as to modify structural parameters of the qubits, the structural parameters comprising first and second inductance based parameter EL1, EL2 inversely proportional to the inductance of the first fluxonium qubit device and the second fluxonium qubit device, respectively, and first and second Josephson Junction energyparameters EJ1, EJ2 of the first fluxonium qubit device and the second fluxonium qubit device, respectively.

13. The method according to claim 12, further comprising lithographically adjusting the capacitance of the first fluxonium qubit device and the capacitance of the second fluxonium qubit device, respectively, the capacitance of the first fluxonium qubit device and the second fluxonium qubit device being inversely proportional to the first and second capacitance based parameter EC1, EC2 respectively.