Electrical junction structure

Abstract

According to an example aspect of the present invention, there is provided a junction structure comprising a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating electrode material and having a native oxide or native nitride layer, a second patterned layer being of a first electrode material and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one self-passivating electrode material being between the first patterned layer and the third patterned layer.

Description

ELECTRICAL JUNCTION STRUCTUREFIELD

[0100] The present disclosure relates to the field of electrical junctions, such as tunnel junctions and superconducting tunnel junctions.BACKGROUND

[0200] Electrical junctions between different and similar metallic, semiconducting and superconducting materials and combinations of these are utilized in many applications from logic devices to sensing. Here, superconducting junction devices form the basis of many applications in the field of low-temperature sensors and electronics. Several different variations of superconducting junctions have been described in past decades, optimized for different applications. In superconducting junction devices superconducting tunnel junctions for an important devices sub-set. Broadly speaking, the approaches can be divided into those combining angle-evaporation and lift-off and those combining superconductor-insulator- superconductor trilayers and subtractive patterning. Superconducting qubits use the former almost exclusively because so far approaches based on lift-off have produced more ideal junctions in the sense of introducing less material in the vicinity of the junction that is capable of absorbing energy at the qubit frequency, which is typically in the range of a few gigahertz, and because so far superconducting quantum processing units have contained relatively few junctions, such that the limited reproducibility of lift-off has been acceptable. The trilayer-based approach is prevalent in more classical applications of superconducting junctions, such as magnetometers, current amplifiers, travelling-wave parametric amplifiers and single-flux quantum, SFQ, circuits. These circuits may contain a very large number of junctions, for example ten thousand, and therefore the superior yield and reproducibility of the approach based on trilayers and subtractive patterning is more important than microwave loss. Superconducting quantum processors are expected to eventually reach a similar scale in terms of number of junctions, therefore making it an interesting problem to develop trilayer-based junctions with low microwave loss.SUMMARY

[0300] According to some aspects, there is provided the subject-matter of the independent claims. Some embodiments are defined in the dependent claims.

[0400] According to a first aspect of the present disclosure, there is provided a junction structure comprising a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating electrode material and having a native oxide or native nitride layer on all faces of the first patterned layer adjacent to a face facing the substrate, a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first electrode material and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a second electrode material, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one self-passivating electrode material being between the first patterned layer and the third patterned layer.

[0500] According to a second aspect of the present disclosure, there is provided a method of manufacturing a structure, comprising obtaining a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating electrode material and having a native oxide or native nitride layer on all faces of the first patterned layer adjacent to a face facing the substrate, obtaining a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first electrode material and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and obtaining a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a second electrode material, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one selfpassivating electrode material being between the first patterned layer and the third patterned layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0600] FIGURE 1A illustrates an example structure in accordance with at least some embodiments of the present invention;

[0700] FIGURE IB is a top view of the structure of FIGURE 1 A;

[0800] FIGURES 2A - 2E illustrate phases of a manufacturing method in accordance with at least some embodiments of the present invention;

[0900] FIGURE 3A illustrates a variant of the herein described structure;

[1000] FIGURE 3B illustrates a variant of the herein described structure, and

[1100] FIGURE 4 is a flow graph of a method in accordance with at least some embodiments of the present invention.EMBODIMENTS

[1200] Junction structures, such as tunnel junctions, are herein described, where a native oxide layer or a native nitride layer passivates the sides of a bottom electrode in a junction. To enable this, in the case of native oxide layer the bottom electrode is of an electrode material, such as a metal or semiconductor, which has a self-passivating character in that it grows a self-terminating native oxide layer to a certain thickness in an atmosphere that comprises oxygen. Once the native oxide layer reaches this thickness its growth essentially stops. Native oxide of aluminium is an example, where a native oxide of approximately 2 nanometres, nm, forms under typical ambient conditions through the Cabrera-Mott process that self-terminates. The bottom electrode may comprise a single material with a self-terminating native oxide, or a multilayer of several materials with selfterminating oxides. Thus the bottom electrode is of at least one self-passivating material. Thus, in general electrode materials may be metals or semiconductors, for example. In particular, each electrode material used in a structure as herein disclosed may be a metal, for example. The native oxide or native nitride may be on all faces of the bottom electrode adjacent to a face facing the counter electrode. In some embodiments, the native oxide or native nitride is further also on a face of the bottom electrode which faces the counter electrode.

[1300] Using the native oxide to passivate the sides of the bottom electrode provides an improvement over existing trilayer-based junctions in that p tan 8 is smaller, thus allowing longer energy relaxation time of a qubit which comprises the junction structure, as well as an improvement over lift-off-based approaches in that the junction structure may beproduced using wafer-scale methods with a high yield and improved parameter control. Here, tan 8 is the loss tangent of the passivation material and the participation ratio p of the passivation material is the fraction of energy stored in electromagnetic fields within the passivation material, relative to the total electromagnetic energy stored in the qubit, defined analogously to Eq. 1 in document ArXiv:2104.01544vl. Furthermore, in a trilayer architecture, advanced deposition techniques, such as molecular beam epitaxy, pulsed laser deposition or atomic layer deposition, may be more readily used for the most sensitive part, namely the tunnel junction barrier between the bottom and counter electrodes, which may be as thin as a 0.3 nanometres, 1 nanometre or 2 nanometres. As mentioned above, in some embodiments a native nitride is used to passivate the bottom electrode instead of the native oxide.

[1400] In the trilayer-based approach to making tunnel junctions, an unpatterned metal-insulator-metal stack, called the trilayer, is deposited, where the insulator in this stack ultimately forms the tunnel barrier in the tunnel junction. In this document, as is common in the field of physics, the term metal does not refer exclusively to elemental metals in the periodic table, but additionally means any solid that has free charge carriers, implying that electrically the material behaves like a metal, as opposed to an insulator. Besides elemental metals such as aluminium, niobium, tantalum, titanium, tungsten, molybdenum and indium, this broader definition also includes their compounds as well as their nitrides and oxides, such as niobium nitride and titanium nitride, that have a composition that results in metallic electrical behaviour. Similarly, doped semiconducting materials fall within this broader definition of a metal. In other embodiments, metal comprises merely elemental metals. The insulator is thin enough to allow significant quantum mechanical tunnelling of charge carriers through the tunnel barrier, the insulator being typically 0.1 to 10 nm thick, depending on the exact combination of materials in the trilayer and the target specific resistivity for the barrier. In case of semiconductors the barrier can incorporate or consist solely of depletion regions or Schottky barriers.

[1500] At the intended operation temperature, each metal in the trilayer can be either a superconducting metal or a non- superconducting metal, also called a normal metal. If both metals are superconductors at the operation temperature, the resulting junction is called a superconductor-insulator-superconductor, SIS, junction, which is a type of Josephson junction, JJ. If one metal is superconducting and the other is a normal metal at the operation temperature, the resulting junction is called a normal-metal — insulator — superconductor,NIS, junction. If both metals are normal at the operation temperature, the resulting junction is called a normal-metal — insulator — normal-metal, NIN, junction. A given structure that is an SIS junction at low operating temperatures becomes an SIN junction at intermediate temperatures above the transition temperature, Tc, of one of the metals, and eventually an NIN junction when operation temperature exceeds the Tc of the second metal, which may or may not be the same metal as the first one. For example, an aluminium — aluminiumoxide — niobium stack is a SIS junction below approximately 1 K, a NIN junction above approximately 9 K, and a NIS junction at operation temperatures in between.

[1600] In realistic devices, the insulator is not ideal and its admittance also contains a real part. Assuming that the real part is small, the ratio of the real part to the imaginary part can be called the loss tangent, tan 8. This nonideality can often be modelled by a large parallel resistance shunting an ideal junction. Each of the metals in the SIS, SIN or NIN junctions may also consist of a stack of multiple materials that are galvanically connected to each other. For example, it is common to form a SIS junction where the bottom metal, in other words the bottom layer or a first patterned layer, consists of a bilayer of roughly 100 nm of niobium and roughly 10 nm of aluminium. Here, a galvanic connection refers to an electrical connection that allows direct current flow that is well described by Ohm’ s law, in the range of currents relevant for operation.

[1700] After an unpattemed trilayer is deposited, a junction with finite lateral area needs to be defined, and a second electrode formed that makes contact to the top of the patterned trilayer. The lateral junction size can vary from junction to junction on the same device. In superconducting qubits, typical junction sizes are from (100 nm)A2 to (900 nm)A2 but smaller sizes down to (10 nm)A2 may be relevant. In detector applications, very large junctions may be useful, for example (1 um)A2, (10 um)A2, (100 um)A2, (1 mm)A2 or even (1 cm)A2. In a conventional pillar-junction approach, the main processing steps include patterning of the trilayer, deposition of a passivation layer, definition of the junction area by etching a hole into the passivation layer, and deposition and patterning of the top electrode. The purpose of the passivation layer is to prevent short circuiting of the top contact electrode to the base of the trilayer, which would shunt current around the tunnel barrier in the trilayer. The pillar-junction approach results in a large volume of passivation material in the vicinity of the junction and the materials conventionally used for the passivation are deposited amorphous insulators, which are generally far from ideal insulators. For example, silicon dioxide, SiO2, deposited by plasma-enhanced chemical vapor deposition, PECVD, has a tan8 no better than 10A-3 at few-gigahertz frequencies, especially when deposited at low enough temperatures to not damage aluminium oxide tunnel barriers, for example at 150 C. This implies that no reasonable superconducting qubits can be fabricated with the conventional pillar-junction approach. A more recent approach, the side-wall spacer passivated sub-pm Josephson junction fabrication process, SWAPS, differs from the pilar-junction approach in that the passivation layer is etched away almost completely and only remains on the sidewalls of the patterned trilayer. SWAPS is described in document DOI: 10.1088 / 1361- 6668 / aa9411. Nevertheless, because the remaining sliver of passivation on the sidewalls is located at the point of high electric field and is made of a deposited amorphous insulator with poor tan 8, the microwave loss introduced by the spacer in the SWAPS solution is still too large to build state-of-the-art superconducting qubits.

[1800] Therefore, in building trilayer-type superconducting tunnel junctions for qubit applications, a key challenge is to passivate the bottom metal in the trilayer such that a top contact can be reliably formed, while simultaneously minimizing the volume of material with poor loss tangent in areas of high electric fields. More quantitatively, in order for the passivation to not limit the overall qubit performance, the product p tan 8 should be small in comparison to the inverse of the effective qubit quality factor 2pi f_q Tl, where f_q is qubit frequency and Tl is the energy relaxation time of the qubit. For state-of-the-art superconducting qubits, l / (2pi f_q Tl) is of order 10A-7. For the SWAPS process and typical transmon qubit parameters, p is of order 10A-4 or greater and tan 8 is 10A-2 or greater, and therefore p tan 8 is limited to roughly 10A-6 or worse.

[1900] FIGURE 1A illustrates an example structure in accordance with at least some embodiments of the present invention. A substrate 110 may comprise silicon, for example, or sapphire. In applications that require extremely low microwave losses, such as in superconducting qubits, a silicon substrate may be high-resistivity silicon, wherein high- resistivity silicon may have a resistivity of at least 5 kOhm cm, 10 kOhm cm or 20 kOhm cm, for example. The substrate may also be of silicon-on-insulator, SOI, type, or may contain other features, such as signal lines or through silicon vias that the junction may be connected to in order to form a more complex device, such as a superconducting qubit or a full quantum processor. In non-qubit applications, such as in amplifiers, isolators, filters or detectors, the substrate may also be an oxidized silicon wafer, for example. Further examples of non-qubit applications of the junction structure include memories, thermometers, electron coolers, rectifiers and photodetectors. Depending on the choice of substrate, the choice of electrodes,and the choice of etch recipes during fabrication, the surface of substrate 110 may also become patterned as a by-product of etching steps of the metal layers. This topography of substrate 110 does not fundamentally impact the functionalities of the junction structure, and thus topography of substrate 110 is not illustrated in the figures, for the sake of clarity.

[2000] A base electrode 120 is disposed directly on substrate 110, by which it is meant that no functional layer is between substrate 110 and base electrode 120. Base electrode 120 is of a self-passivating metal, such as, for example, aluminium, tantalum, titanium or indium. The self-passivating metal may be a self-passivating superconducting metal. Base electrode 120 forms a first patterned layer of the illustrated structure. Base electrode 120 may be between 10 and 500 nm thick, for example between 100 and 110 nm thick. By superconducting metal it is meant a metal which acts as a superconductor when under a specific transition temperature, which is 1.2 Kelvin for bulk aluminium and 3.4 Kelvin for bulk indium, for example.

[2100] Counter electrode 130 forms a second patterned layer of the structure of FIGURE 1A. Counter electrode 130 is also of a metal, which may be the same one as base electrode 120, or a different one. The counter electrode may be of a superconducting metal, for example. For example, counter electrode may be of niobium, tantalum, tungsten, titanium or their metallic oxides or nitrides. The counter electrode 130 may be, like base electrode 120, between 10 and 500 nm thick, for example between 100 and 110 nm thick. In other words, base electrode 120 and counter electrode 130 may have the same thickness or they may have different thicknesses. Counter electrode 130 has an oxide layer 132 on a face 130a of the second patterned layer not facing the first patterned layer, for example on a face 130a opposite to a face of counter electrode 130 facing the first patterned layer. Oxide layer 132 need not be of self-terminating nature and its thickness or quality does not have a strong impact on the behaviour of the complete junction structure shown in FIGURE 1. An example of a junction structure is a tunnel junction structure.

[2200] Between base electrode 120 and counter electrode 130 is a tunnel junction barrier 125. This barrier is a thin layer forming a weak link between base 120 and counter 130 electrodes. Depending on the effective height of the energy barrier that the insulating material presents to the tunnelling charge carriers, the thickness of the tunnel barrier may be between 0.1 nm and 10 nm, for example. As one example, the barrier may be a 0.5 nm, 1 nm 2 nm, or 3 nm layer of aluminium oxide, which may be formed by exposing a base electrode120 with an aluminium top surface to a certain partial pressure of oxygen for a certain time before depositing counter electrode 130 thereon. Depending on the target tunnel barrier resistivity, typical aluminium oxidation time can vary from 1 minute to 1 hour and typical partial pressure from 10 mTorr to 500 Torr and process temperature may be, for example, 300 K, 77 K or 400 K. More advanced methods, such as molecular beam epitaxy, pulsed laser deposition or atomic layer deposition may also or alternatively be used to form tunnel barrier 125, as well as electrode 120 and 130. Alternatively, the tunnel barrier may be of tantalum oxide. A tunnel barrier can be made from ferroelectric material to enable memory functionality. In at least some embodiments, the structure of FIGURE 1 forms a JJ, such that tunnel junction barrier 125 acts as the weak link of the JJ. For transmon qubits and using Al, Ta or Nb as metals in a SIS junction, the specific resistivity of the tunnel barrier is typically in the range of 0.1 kOhm umA2 to 100 kOhm umA2, such that the Josephson inductance of the junction is some tens of nanohenries. A wide range of specific resistivities is relevant because the Josephson inductance scales inversely with the lateral junction area, and also depends on the energy gaps of the superconductors. In detector applications, very low absolute leakage currents may be important and thus very opaque tunnel junctions may be desirable, and thus target specific resistivity may be between 1 kOhm umA2 and 100 MOhm umA2, for example. In electronic cooler applications employing SIN junctions, very transparent tunnel junctions may be desirable for achieving large cooling power, and thus specific resistivity may be between 1 Ohm umA2 and 1 kOhm umA2, for example. Here, specific resistivity is defined as the inverse of tunnel conductance per area. We note that this is common in the context of tunnel junctions but may differ from other uses of the term specific resistivity.

[2300] The base electrode 120, tunnel junction barrier 125 and the counter electrode 130 together form a trilayer structure.

[2400] A third patterned layer of the illustrated structure is lower wiring layer 140, which may be of niobium, for example, or another suitable superconducting metal, such as aluminium, indium, tantalum, tungsten, titanium or their metallic oxides or nitrides. The lower wiring layer may be between 10 and 500 nm thick. For example, the lower wiring layer may comprise a 100 nm niobium or tantalum layer. The lower wiring layer 140 may be used to electrically convey information to the tunnel junction, for example. The lower wiring layer 140 is also in part on substrate 110 and against at least one side of bottom electrode 120, a native oxide 122 or a nitride of the self-passivating superconducting metalof the bottom electrode 120 being between the first layer and the third layer and acting as a passivation layer. In at least some embodiments, the native oxide or the nitride is the only passivation layer of bottom electrode 120, there being no spacer element in addition to the native oxide or the nitride. This leaves lower wiring layer 140 at most 4 nanometres from the superconducting material of bottom electrode 120, where lower wiring layer 140 is against bottom electrode 120, as illustrated in FIGURE 1A. In other words, the smallest distance between lower wiring layer 140 and bottom electrode 120 is at most 4nm, this being the thickness of the passivation layer.

[2500] On the lower wiring layer 140 is upper wiring layer 150, which forms a fourth patterned layer and may be of a suitable superconducting metal, such as niobium, tantalum or indium, for example. Upper wiring layer 150 may have a thickness between 10 and 500 nm thick. For example, the upper wiring layer may comprise a 100 nm niobium or tantalum layer with 10 nm of aluminium on top, such that the aluminium layer may be used as a hard mask during patterning of the upper and lower wiring layers. Fourth patterned layer 150 may thus be of a third metal, in case the counter electrode 130 is of a first metal and third patterned layer 140 is of a second metal, the first, second and third metals being different from each other.

[2600] A via 160 is provided to enable galvanic electrical access to counter electrode 130 from wiring layers 140 and 150. This via 160 penetrates lower wiring layer 140 and oxide layer 132 of counter electrode 130. Via 160 may penetrate into counter electrode 130 but does not reach tunnel junction barrier 125. Upper wiring layer 150 coats the inner surface of via 160.

[2700] Of note in FIGURE 1A, is that a native oxide layer 122 of the bottom electrode passivates the sides of bottom electrode 120. Native oxide layer 122 may have a thickness of 2 to 4 nm in the case of aluminium, about 3 nm for tantalum and up to 4 nm for indium. In case of titanium, the self-termination effect is not as ideal but the oxide growth rate nevertheless slows down dramatically after the initial nanometres of oxide have formed, and therefore titanium can be meaningfully considered self-passivating for the purposes of the herein described structure. Titanium oxidization has been studied in the context of medical implants. A typical value reported for the native oxide thickness of titanium is approximately 3 nm when measured within hours or days of being exposed to atmospheric conditions, and in the range of 5 to 10 nm when several months have passed and the sample has been exposedto air or a solution mimicking conditions inside a human body. For all of the materials, the exact thicknesses can be modified by exposing the sample to temperatures or oxygen partial pressures that differ significantly from regular ambient conditions.

[2800] Using the native oxide layer to passivate bottom electrode 120, instead of a separate passivation spacer structure, provides the significant benefit that higher-coherence- time superconducting qubits can be constructed than with other trilayer-type junctions, such as SWAPS or pillar-type junctions, as discussed below. In more exact terms, p tan 5 can be reduced by more than one order of magnitude, despite the tendency of p to increase with decreasing thickness of the passivation structure between base electrode 120 and wiring layer 140. This is because self-termination of oxide growth occurs thanks to high quality of the oxide that grows. In the case of aluminium, for example, the Cabrera-Mott process through which the native oxide forms self-terminates because the native aluminium oxide that grows is of high enough quality to inhibit electron tunnelling as well as aluminium ion migration through it. Thus materials with self-terminating native oxides that are thin, for example between 0.5 nm and 10 nm, are good candidates for sidewall passivation with a low tan 8, since many aspects of oxide quality that are important for self-termination in the Cabrera-Mott process are also important for low tan 8. In the case of aluminium oxide, for example, tan 8 of approximately 2 x 10A-6 is possible.

[2900] Next, a limit on p tan 8 and qubit coherence time for the case of aluminium oxide and a typical transmon qubit will be discussed. The participation ratio p can remain well below 10A-2 for typical transmon qubit parameters and reasonable junction dimensions. For example, using the parallel-plate capacitor approximation for passivation native oxide 122 sandwiched between base electrode 120 and lower wiring layer 140 on two sides of the junction, the capacitance can be estimated as roughly 220 attofarads for a lateral junction size of 100 nm, 50 nm height of base electrode 120, 2 nm thickness of native oxide 122, and a relative dielectric constant of 10. Therefore, p can be estimated as 0.006 if one assumes a total qubit capacitance of 70 femtofarads. Together with assuming 2 x 10A-6 for tan 8, this implies p tan 8 of approximately 10A-8. If lateral junction size is reduced to 50 nm and height of base electrode 120 is reduced to 20 nm, p is reduced further to approximately 10A-3 and p tan 8 approximately 3 x 10A-9. Assuming a qubit frequency of 4 GHz, p tan 8 of 3 x 10A- 9 would limit T1 to 13 milliseconds, which is far beyond state of the art, implying that losses in the passivation oxide would not limit performance, and far better than what can be achieved with SWAPS or pillar-type junctions, for example.

[3000] One can also argue that, generally, the native oxide of any material suitable for forming high-quality tunnel barriers is likely to work well as a junction side-wall passivation layer. This is because, if the loss tangents are similar for passivation native oxide 122 and tunnel barrier 125, microwave losses in the passivation will always be smaller than in the tunnel barrier itself because the participation ratio of the tunnel barrier is much larger than the participation ratio of the passivation, as long as the lateral dimensions of the tunnel junction are larger than the thickness of bottom electrode 120. This can be seen by using the parallel-plate approximation to estimate the capacitance of the structure formed by tunnel barrier 125 sandwiched between metals 120 and 130, as well as for the native oxide passivation 122 sandwiched between metals 120 and 140. The ratio of the participation ratios corresponds directly to the ratio of the capacitances, since the voltage drop across both structures can be approximated as equal.

[3100] The thickness of native oxide 122 on other faces of bottom electrode 120 than the one facing counter electrode 130 may be larger than the thickness of tunnel barrier 125, which is between bottom electrode 120 and counter electrode 130. If tunnel barrier 125 is also formed of the same material as the native oxide 122, this implies that current tunnelling through native oxide 122 can often be neglected in comparison to the current tunnelling through tunnel barrier 125. However, this need not be the case. For example, if native oxide 122 is formed under reduced-oxygen-partial-pressure conditions similar to oxidization conditions used for the tunnel barrier 125, and the lateral junction area is small, for example 50 nm x 50 nm, then significant tunnel current may flow through the sidewall passivation.

[3200] The presence of via 160, as well as splitting the wiring layer into a lower wiring layer 140 and an upper wiring layer 150, are beneficial for protecting native oxide 122 during aggressive fabrication processes that could lead to lowering of tan 8. In particular, the combination of the via and the split wiring layer makes it possible to omit a step of removing oxide from counter electrode 130 while native oxide layer 122 is also exposed to the same oxide removal process. This is in contrast to e.g. conventional SWAPS, where the oxide from the top surface of the counter electrode is removed by ion milling before deposition of the counter electrode, which is likely to damage the sidewall passivation exposed to the same ion milling step. The structure presented in FIGURE 1A can instead be created without any oxide removal steps until after lower wiring layer 140 has been deposited, permanently protecting native oxide passivation 122 from aggressive fabrication steps that follow. In particular, native oxide layer 122 is protected during the removal of oxides from lowerwiring layer 140 and the bottom of via 160, carried out prior to deposition of upper wiring layer 150. Nevertheless, this combination provides galvanic electrical connectivity from wiring layers 140 and 150 to counter electrode 130.

[3300] In some embodiments, a native nitride is used to passivate the bottom electrode instead of the native oxide, described above. Here, a native nitride or oxide means any nitride or oxide that consists of nitrogen or oxygen and the material or materials used for base electrode 120. Here, we use the term broadly to also include oxides and nitrides for which the exact thickness or composition differs from that that forms at regular ambient conditions. For example, the native nitride or oxide may be formed under reduced or increased partial pressure of oxygen or nitrogen, relative to the partial pressures in regular ambient conditions (approximately 21 kPa of oxygen and 79 kPa of nitrogen). The increase or decrease may be by a factor of two or ten, for example. The temperature may also be increased or decreased from approximately 300K to, for example, 77 K, 200K, 400K, or 500 K. Here, native oxides and nitrides that are insulating native oxides or insulating native nitrides are most relevant, with the term insulating referring to electrical behaviour.

[3400] By lateral directions it is herein meant directions parallel to the surface of substrate 110. By lateral area it is herein meant an area projected onto the surface of substrate 110. By vertical direction it is herein meant the direction perpendicular to the surface of substrate 110. By patterned layer it is herein meant a layer which partly, but not completely, covers the surface upon which the patterned layer is located. For example, a patterned layer may be a layer that does not cover the entire lateral area of the substrate. By outer face it is meant a face defining an outer boundary of a layer, that is, not a face internal to the layer, such as between sub-layers of a multilayer when the multilayer is built of plural sub-layers. By at least partially covering it is meant, e.g. that the second patterned layer may be completely on the first patterned layer, and the second patterned layer may cover the first patterned layer completely or merely in part. Further in general and not only relating to FIGURE 1A, the native oxide or native nitride may be an insulating native oxide or insulating native nitride, respectively.

[3500] FIGURE IB is a top view of the structure of FIGURE 1A. This may be referred to as a full overlap implementation of the herein described tunnel junction structure. We refer to the dimensions in the plane of FIGURE IB as the lateral dimensions.

[3600] In this embodiment, bottom electrode 120 has been patterned into a rectangular shape and is oriented vertically in the illustration , while the lower wiring layer 140 and upper wiring layer 150 have been patterned into a rectangle that is oriented horizontally. Counter electrode 130 has been patterned such that it exists in the area where bottom electrode 120 and wiring layers 140 and 150 overlap. We refer to this overlap area as the tunnel junction area, since it is the area where charge carriers tunnel through tunnel barrier 125. We refer to other parts of bottom electrode 120 as the bottom lead and to the other parts of wiring layers 140 and 150 as the top lead. Via 160 is also visible in the top view of FIGURE IB. Via 160 illustrates the option where the via is fully contained within counter electrode 130, that is, fully within the tunnel junction area. Via 160b illustrates an alternative lateral geometry for the via, where the via extends beyond the tunnel barrier area in such a manner that it stays within bottom electrode 120. This is acceptable, since sidewall passivation of bottom electrode 120 is only required in areas where lower wiring layer 140 crosses the edge of bottom electrode 120. In the example embodiment of FIGURE IB, this corresponds to a via extending outside the tunnel junction area in the two vertical directions.

[3700] The rectangular shapes and the full-overlap geometry illustrated in FIGURE IB are beneficial in that the size of the tunnel junction area is insensitive to small errors in lateral alignment of the lithography mask used to pattern wiring layers 140 and 150, relative to the bottom electrode 120. However, the lateral geometry of the tunnel junction area or the bottom or top leads may be freely chosen and any other shape could be used, such as a circle, oval or rectangle with different aspect ratios. The bottom and top leads, used to make electrical contact to other circuitry on the substrate, also need not be perpendicular to each other as illustrated in the example of FIGURE IB. They can point in arbitrary directions, and can even extend in multiple directions. For example, bottom electrode 120 could extend both up and down to connect to two different parts of surrounding circuitry, instead of extending just up as illustrated in FIGURE IB.

[3800] For counter-electrode materials with a high-quality native oxide 132, such as aluminium, it is also possible to have wiring layers 140 and 150 cross over bottom electrode 120 without forming a galvanic connection between the bottom electrode and the wiring layers, by simply omitting via 160. In that case, oxide 132 provides galvanic isolation and a parallel-plate capacitor is instead formed by oxide 132 sandwiched between counter electrode 130 and lower wiring layer 140. This capacitor is electrically in series with tunnel junction, thus blocking direct current. Such crossings may be beneficial for signal routingand come without any additional processing steps, assuming that tunnel junctions of the type illustrated in FIGURE 1A are in any case fabricated in other areas of the same substrate. This is in contrast to the SWAPS process, where a tunnel junction is formed in all areas where the bottom electrode layer and the wiring layer overlap, and thus an additional insulator layer and an additional metal layer are needed if a signal needs to be routed over the bottom lead or the top lead of a SWAPS junctions.

[3900] FIGURE 2A illustrates a phase of a manufacturing method in accordance with at least some embodiments of the present invention. Here, a trilayer comprising bottom electrode 120, counter electrode 130 and the tunnel junction barrier 125, described above, has been obtained on substrate 110. For example, the bottom electrode 120 may be of aluminium, or another self-passivating superconducting metal such as tantalum, titanium or indium. Counter electrode 130 may be of niobium or tantalum, for example. Barrier layer 125 may be oxidized aluminium, for example. Barrier layer 125 may be between 0.5 and 2.5 nm thick, for example. The trilayer may be patterned in a manner to suit the application at hand, for example by optical or electro-beam lithography followed by plasma etching using fluorine or chlorine chemistry. This etch step may also penetrate into substrate 110, which is not illustrated in the figures for the sake of clarity. In particular, bottom electrode 120 may be of aluminium, tunnel junction barrier 125 may be of aluminium oxide and counter electrode 130 may be of niobium. In another embodiment, bottom electrode 120 may be of aluminium, tunnel junction barrier 125 may be of aluminium oxide and counter electrode 130 may be of tantalum. In another embodiment, bottom electrode 120 may be of aluminium, tunnel junction barrier 125 may be of aluminium oxide and counter electrode 130 may be of aluminium. In another embodiment, bottom electrode 120 may be of tantalum, tunnel junction barrier 125 may be of tantalum oxide and counter electrode 130 may be of niobium. In another embodiment, bottom electrode 120 may be of tantalum, tunnel junction barrier 125 may be of tantalum oxide and counter electrode 130 may be of tantalum. The thickness of bottom electrode 120 may be 50 nm and the thickness of the counter electrode 130 may be 100 nm, for example.

[4000] Processing advances from FIGURE 2A to FIGURE 2B, where the bottom 120 and counter 130 electrodes have been allowed to oxidize in an atmosphere which comprises oxygen. Thus native oxide 122 has formed on exposed faces of base electrode 120 and oxide layer 132 has formed on exposed faces of counter electrode 130. Alternatively, bottom 120 and counter 130 electrodes may be allowed to nitridize in an atmosphere which comprisesnitrogen. The thicknesses of oxide layers 120 and 132 may be approximately 3 nm, for example.

[4100] Processing advances from FIGURE 2B to FIGURE 2C, where lower wiring layer 140 has been deposited on the oxidized trilayer structure of FIGURE 2B. As noted above, lower wiring layer 140 may be a niobium layer. The thickness of lower wiring layer 140 may be approximately 100 nm, for example.

[4200] Processing advances from FIGURE 2C to FIGURE 2D, where a contact hole has been etched through lower wiring layer 140 to reach counter electrode 130. The contact hole, which will form part of via 160, penetrates the oxide 132 layer of the counter electrode 130. The contact hole may penetrate into the bulk of counter electrode 130 in addition to penetrating oxide layer 132. The contact hole does not, however, reach tunnel junction barrier 125. In the direction drawn as horizontal in FIGURE 2D, the length of via 160 may be made smaller than the length of counter electrode 130, such that the via etching step does not risk damaging native oxide 122 used for sidewall passivation. In the perpendicular lateral direction, out-of-plane in FIGURE 2D, in some embodiments the via may or may not extend outside counter electrode 130 since there is no corresponding sidewall-passivation oxide. For SIS junctions and typical qubit dimensions, the exact lateral shape and size of via 160 may vary, as long as the critical current through the via is larger than the critical current through the tunnel barrier. Via 160 may be, for example, circular with a diameter of 50 nm or 500 nm, or it may be rectangular with similar lateral area.

[4300] Processing advances from FIGURE 2D to FIGURE 2E, where upper wiring layer 150 has been deposited over lower wiring layer 140, which is not yet patterned, and via 160. Upper wiring layer 150 may be deposited after removal of oxides from exposed surfaces of lower wiring layer 140 and via 160. For example, this oxide removal can be performed by ion milling in-situ in the same vacuum as the deposition of upper wiring layer 150, for example using a cluster tool that has a deposition chamber for the metal deposition and an etch chamber for the ion milling as well as capability of transferring a wafer between the chambers without breaking vacuum. After deposition of upper wiring layer 150, the upper wiring layer 150, lower wiring layer 140 and areas of counter electrode 130 outside the tunnel junction are patterned by etching. If all of these are niobium or tantalum while base electrode 120 is aluminium, using plasma etching with fluoride chemistry is a beneficial approach since fluoride-based plasma etch recipes can etch niobium and tantalum forexample one hundred or one thousand times faster than they etch aluminium. Therefore, in that case, base electrode 120 acts as a natural etch stop. This etch step may also penetrate into substrate 110, which is not illustrated in the figures for the sake of clarity. This results in the structure illustrated also in FIGURE 1A. As noted above, upper wiring layer 150 coats inner faces of the contact hole etched through lower wiring layer 140. As also noted above, upper wiring layer 150 may be a niobium layer, or a compound layer comprising niobium with a thin aluminium layer on top, such that the aluminium may be used as a hard mask when patterning the niobium of lower wiring layer 140 and upper wiring layer 150.

[4400] Overall, the herein described tunnel junction architecture enables improved performance in superconducting quantum computers, when used therein in qubits. It further enhances the scalability of quantum computers. The herein described tunnel junction architecture may also be used to create high-yield and high-quality tunnel junctions for travelling wave parametric amplifiers, TWPAs, single-flux-quantum circuits, SQUID magnetometers, SQUID current amplifiers, as well as solid-state coolers based on SIN junctions. Compared to conventional SWAPS, the tunnel junctions described here may result in higher yield, as the step of creating a separately-deposited and separately-etched sidewall spacer is omitted and replaced with a simpler process of growing a native oxide and etching a via, and the passivation structure is not exposed to ion milling during fabrication. As discussed above, the junctions may be of higher quality in the sense of providing low microwave losses, but for the same reasons they may also provide less charge noise or magnetic flux noise at low frequencies, i.e. better 1 / f characteristics. Furthermore, as described above, the tunnel junction architecture described herein may provide additional possibilities for signal routing, by allowing bottom and top leads to cross each other without making a galvanic connection, which may allow removal of an additional wiring layer in the above-mentioned devices.

[4500] FIGURE 3A illustrates a variant of the herein described structure. In detail, this is a corner overlap variant of the herein described tunnel junction structure, where the bottom electrode 120 is in the vertical orientation and the wiring layers 140 and 150 extend from the left edge of the figure to cover, in part, the bottom electrode. In this variant, a comer of the rectangular bottom electrode is overlapped by a comer of the rectangular counter electrode, and the electrodes overlap only in these corners. The location and shape of via 160 is outlined in the figure using a black rectangle.

[4600] FIGURE 3B illustrates a variant of the herein described structure. This is a partial overlap variant, where a tip of a rectangularly shaped and vertically oriented wiring layers 140 and 150 partially overlaps a side the rectangularly shaped and horizontally oriented bottom electrode 120, and the electrodes do not otherwise overlap. The location and shape of via 160 is outlined in the figure using a black rectangle.

[4700] A main advantage of the variants of FIGURES 3A and 3B is that it is possible to produce tunnel junctions where one or both of the lateral tunnel junction dimensions are below the minimum line width of the lithography system used for fabrication of the device. In the comer overlap variant illustrated in FIGURE 3A, minima for both dimensions of the tunnel junction are determined by relative alignment of the layers. The alignment may be controlled more precisely than the minimum line width in common optical lithography systems. In the partial overlap variant illustrated in FIGURE 3B, the tunnel junction dimension illustrated vertically in the image may be smaller than the linewidth of the lithography system. In both FIGURE 3 A and 3B, via 160 can be larger than the tunnel junction, in both dimensions. In contrast, in the full overlap solution of FIGURE IB, via 160 has to be narrower than base electrode 120, limiting the minimum width of base electrode 120 to values that are larger than the minimum via width that the lithography system is capable of producing. These variants may also have an advantage from a microwave loss perspective in that some more of the native oxide on the counter electrode 130 is removed in these approaches, as compared to the full overlap variant. Disadvantages of these variants include worse parameter control in that the junction size is sensitive to misalignment between layers, and likewise the precise junction size is sensitive to rounding of the corners in realistic patterned layers.

[4800] FIGURE 4 is a flow graph of a method in accordance with at least some embodiments of the present invention.

[4900] Phase 410 comprises obtaining a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating metal and having a native oxide or native nitride layer on all outer faces of the first patterned layer other than a face facing the substrate. Phase 420 comprises obtaining a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first metal and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer. Finally, phase 430 comprises obtaining a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a secondmetal, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one selfpassivating metal being between the first patterned layer and the third patterned layer.

[5000] It is to be understood that the embodiments of the invention disclosed are not limited to the particular structures, process steps, or materials disclosed herein, but are extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting.

[5100] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Where reference is made to a numerical value using a term such as, for example, about or substantially, the exact numerical value is also disclosed.

[5200] As used herein, a plurality of items, structural elements, compositional elements, and / or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition, various embodiments and example of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of the present invention.

[5300] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the preceding description, numerous specific details are provided, such as examples of lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[5400] While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the invention. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below.

[5500] The verbs “to comprise” and “to include” are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. The features recited in depending claims are mutually freely combinable unless otherwise explicitly stated. Furthermore, it is to be understood that the use of "a" or "an", that is, a singular form, throughout this document does not exclude a plurality.

[5600] As used herein, “at least one of the following: ” and “at least one of ” and similar wording, where the list of two or more elements are joined by “and” or “or”, mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.TECHNICAL EXAMPLEIn a specific technical example, there is provided a superconducting qubit comprising a structure having a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating metal and having a native oxide or native nitride layer on all outer faces of the first patterned layer other than a face facing the substrate, a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first metal and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a second metal, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one self-passivating metal being between the first patterned layer and the third patterned layer, wherein an area of the native oxide or native nitride layer between the first patterned layer and the second patterned layer is between (10 nm)A2 and (900 nm)A2, the native oxide or native nitride layer forming a tunnel barrier between the first patterned layer and the second patterned layer, a specific resistivity of the tunnel barrier is in the range of 0.1 kOhm umA2 to 100 kOhm umA2, and a Josephson inductance of the junction is between 20 and 70 nanohenries.INDUSTRIAL APPLICABILITY

[5700] At least some embodiments of the present invention find industrial application in superconducting tunnel junctions.ACRONYMS LIST JJ Josephson junction nm nanometreSFQ single flux quantumSQUID superconducting quantum interference deviceTWPA travelling wave parametric amplifiersREFERENCE SIGNS LIST

Claims

CLAIMS:

1. A junction structure comprising:- a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating electrode material and having a native oxide or native nitride layer on all faces of the first patterned layer adjacent to a face facing the substrate;- a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first electrode material and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and- a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a second electrode material, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one self-passivating electrode material being between the first patterned layer and the third patterned layer.

2. The junction structure according to claim 1, wherein the junction structure is a tunnel junction structure, a thickness of a tunnel barrier between the first patterned layer and the second patterned layer is between 0.1 nanometres and 10 nanometres, the tunnel barrier having a specific resistivity between 1 pmA2 and 100 MQ pmA2.

3. The junction structure according to claim 1 or 2, further comprising a via galvanically connecting the third patterned layer and the second patterned layer, the via traversing the oxide layer on the face of the second patterned layer, and surfaces of the via and at least part of the third patterned layer are covered by a fourth patterned layer , the fourth patterned layer being of the first, the second or a third electrode material.

4. The junction structure according to any of claims 1 - 3, wherein at least one of the at least one self-passivating electrode material is aluminium, tantalum, titanium or indium.

5. The junction structure according to any of claims 1 - 4, wherein the first electrode material is niobium.

6. The junction structure according to any of claims 1 - 5, wherein the third patterned layer is niobium.

7. The junction structure according to any of claims 1 - 5, wherein the third patterned layer is tantalum.

8. The junction structure according to any of claims 1 - 5, wherein the third patterned layer is aluminium.

9. The junction structure according to any of claims 3 or 4 - 8 as dependent on claim 3, wherein the fourth patterned layer is of niobium, tantalum or aluminium.

10. The junction structure according to any of claims 1 - 9, wherein a smallest distance between the first patterned layer and the third patterned layer is at most 4 nanometres.

11. The junction structure according to any of claims 2 or 3 - 10 as dependent on claim 2, wherein an area of the tunnel barrier between the first patterned layer and the second patterned layer is between (10 nm)A2 and (1 cm)A2.

12. A superconducting qubit that comprises a junction structure according to one or more of claims 1 - 11.

13. The superconducting qubit according to claim 12 as dependent on claims 11 and 2, wherein the area of the tunnel barrier between the first patterned layer and the second patterned layer is between (10 nm)A2 and (900 nm)A2.

14. A quantum computing device comprising at least one qubit, wherein one or more than one of the at least one qubit comprises a junction structure according to one or more of claims 1 - 11 or the at least one qubit comprises a superconducting qubit according to claim 12 or 13.

15. A method of manufacturing a structure, comprising:- obtaining a first patterned layer directly on a substrate, the first patterned layer being of at least one self-passivating electrode material and having a native oxide or nativenitride layer on all faces of the first patterned layer adjacent to a face facing the substrate;- obtaining a second patterned layer at least partially covering the first patterned layer, the second patterned layer being of a first electrode material and having an oxide layer on a face of the second patterned layer other than a face facing the first patterned layer, and- obtaining a third patterned layer on the oxide layer of the second patterned layer, the third patterned layer being of the first or a second electrode material, the third patterned layer being further on the substrate and against at least one side of the first patterned layer, the native oxide or nitride of at least one of the at least one selfpassivating electrode material being between the first patterned layer and the third patterned layer.

16. The method according to claim 15, further comprising building a via to the second patterned layer, the via traversing the third patterned layer and the oxide layer.

17. The method according to claim 15 or 16, wherein at least one of the self-passivating electrode material is aluminium, tantalum or indium.

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