Electronic circuit and computing device

Abstract

Provided are an electronic circuit and a computing device which are capable of achieving improved characteristics. According to an embodiment, this electronic circuit includes a first structure. The first structure includes a first Josephson junction including a first end and a first other end, a second Josephson junction including a second end and a second other end, a third Josephson junction including a third end and a third other end, a first conductive part coupled to the first other end and the third end, a second conductive part coupled to the second and third other ends, and a third conductive part coupled to the first and second ends. One half of the sum of second and third frequencies is smaller than a first frequency. The second frequency corresponds to a first excited state of the first structure when a magnetic flux passing through a space surrounded by a loop including the first to third Josephson junctions and the first to third conductive parts is zero. The third frequency corresponds to a second excited state of the first structure when the magnetic flux is zero. The first frequency corresponds to the second excited state when the magnetic flux is 0.5 times a magnetic flux quantum.

Description

Electronic circuits and computing devices

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to electronic circuits and computing devices.

[0002] For example, electronic circuits including a plurality of nonlinear elements are used in computing devices, and improved performance is desired in electronic circuits and computing devices.

[0003] JP 2023-20041 A

[0004] Embodiments of the present invention provide electronic circuits and computing devices that can have improved performance.

[0005] According to an embodiment of the present invention, an electronic circuit includes a first structure. The first structure includes a first Josephson junction including a first end and a first other end, a second Josephson junction including a second end and a second other end, a third Josephson junction including a third end and a third other end, a first conductive portion configured to couple with the first other end and the third end, a second conductive portion configured to couple with the second other end and the third other end, and a third conductive portion configured to couple with the first end and the second end. Half the sum of the second frequency and the third frequency is less than the first frequency. The second frequency corresponds to a first excited state of the first structure when a magnetic flux passing through a space surrounded by a loop including the first Josephson junction, the second Josephson junction, the third Josephson junction, the first conductive portion, the second conductive portion, and the third conductive portion is zero. The third frequency corresponds to a second excited state of the first structure when the magnetic flux is zero. The first frequency corresponds to the second excited state when the magnetic flux is 0.5 times a magnetic flux quantum.

[0006] FIG. 1 is a schematic diagram illustrating an electronic circuit according to the first embodiment. FIG. 2 is a graph illustrating characteristics of the electronic circuit according to the first embodiment. FIG. 3 is a graph illustrating characteristics of an electronic circuit according to a reference example. FIGS. 4(a) and 4(b) are graphs illustrating characteristics of the electronic circuit according to the first embodiment. FIG. 5 is a graph illustrating characteristics of the electronic circuit. FIG. 6 is a graph illustrating the operation of the electronic circuit according to the first embodiment. FIG. 7 is a graph illustrating the operation of the electronic circuit according to the first embodiment. FIG. 8 is a graph illustrating characteristics of the electronic circuit according to the first embodiment. FIG. 9 is a graph illustrating characteristics of a computing device according to a second embodiment. FIG. 10 is a schematic diagram illustrating a computing device according to the second embodiment. FIG. 11 is a schematic plan view illustrating an electronic circuit and a computing device according to an embodiment. FIGS. 12(a) and 12(b) are schematic diagrams illustrating an electronic circuit and a computing device according to an embodiment. FIGS. 13(a) and 13(b) are schematic diagrams illustrating an electronic circuit and a computing device according to an embodiment. FIG. 14 is a schematic plan view illustrating an electronic circuit according to an embodiment. FIG. 15 is a schematic view illustrating an electronic circuit according to a third embodiment. FIG. 16 is a schematic view illustrating an electronic circuit according to the third embodiment. FIG. 17 is a schematic plan view illustrating an electronic circuit according to a fourth embodiment. FIGS. 18( a) and 18(b) are schematic views illustrating an electronic circuit according to the fourth embodiment. FIGS. 19( a) to 19(c) are schematic views illustrating an electronic circuit according to a fifth embodiment. FIGS. 20( a) to 20(c) are schematic views illustrating an electronic circuit according to the fifth embodiment. FIG. 21 is a schematic cross-sectional view illustrating an electronic circuit according to the fifth embodiment. FIGS. 22( a) to 22(i) are schematic cross-sectional views illustrating a method for manufacturing the electronic circuit according to the fifth embodiment. FIGS. 23( a) to 23(i) are schematic cross-sectional views illustrating a method for manufacturing the fifth electronic circuit. FIG. 24 is a schematic view illustrating an electronic circuit according to a sixth embodiment. Fig. 25 is a circuit diagram illustrating an electronic circuit according to a sixth embodiment. Fig. 26 is a schematic plan view illustrating an electronic circuit according to the sixth embodiment. Fig. 27 is a schematic view illustrating an electronic circuit according to the sixth embodiment. Fig. 28 is a schematic plan view illustrating an electronic circuit according to a seventh embodiment.Figures 29(a) and 29(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. Figures 30(a) and 30(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. Figures 31(a) and 31(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. Figures 32(a) and 32(b) are schematic diagrams illustrating a computing device according to the eighth embodiment.

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions will be omitted as appropriate.

[0008] First Embodiment Fig. 1 is a schematic diagram illustrating an electronic circuit according to a first embodiment. Fig. 2 is a graph illustrating characteristics of the electronic circuit according to the first embodiment. As shown in Fig. 1, an electronic circuit 110 according to the embodiment includes a first structure 50C.

[0009] The first structure 50C includes a first Josephson junction 21, a second Josephson junction 22, a third Josephson junction 23, a first conductive portion 11c, a second conductive portion 12c, and a third conductive portion 13c. The first Josephson junction 21 includes a first end 21a and a first other end 21b. The second Josephson junction 22 includes a second end 22a and a second other end 22b. The third Josephson junction 23 includes a third end 23a and a third other end 23b.

[0010] The first conductive portion 11c is configured to be coupled to the first other end 21b and the third other end 23a. The second conductive portion 12c is configured to be coupled to the second other end 22b and the third other end 23b. The third conductive portion 13c is configured to be coupled to the first end 21a and the second end 22a.

[0011] For example, the first structure 50C is coupled to the first quantum bit 50A and the second quantum bit 50B. The electronic circuit 110 is, for example, a variable coupler. The electronic circuit 110 is, for example, a double transmon coupler.

[0012] For example, a magnetic flux Φ passing through a space SP surrounded by a loop 50r including the first Josephson junction 21, the second Josephson junction 22, the third Josephson junction 23, the first conductive portion 11c, the second conductive portion 12c, and the third conductive portion 13c is controlled. For example, a signal Sg1 is supplied to the first conductive member 61. The signal Sg1 is a current pulse or the like. A magnetic field based on the signal Sg1 is applied to the space SP within the loop 50r. The magnetic flux Φ is controlled by the magnetic field.

[0013] The horizontal axis of Fig. 2 is the magnetic flux ratio ER1. The magnetic flux ratio ER1 is the magnetic flux quantum Φ of the magnetic flux Φ. ０ 2 is the frequency F0. The frequency F0 corresponds to the energy level of the excited state.

[0014] 2, the first structure 50C has a plurality of excited states, including a first excited state E1 and a second excited state E2, which can be controlled by a magnetic flux Φ.

[0015] 2, the first structure 50C has a first frequency f1, a second frequency f2, and a third frequency f3. The second frequency f2 corresponds to the energy level of a first excited state E1 of the first structure 50C when the magnetic flux Φ passing through the space SP surrounded by the loop 50r is zero. The third frequency f3 corresponds to the energy level of a second excited state E2 of the first structure 50C when the magnetic flux Φ is zero. The first frequency f1 corresponds to the energy level of a second excited state E2 of the first structure 50C when the magnetic flux Φ is zero. ０ This corresponds to the energy level of the second excited state E2 when the magnetic flux ratio ER1 is 0.5 times that of the first excited state E2 (when the magnetic flux ratio ER1 is 0.5).

[0016] 2, for example, half the sum of the second frequency f2 and the third frequency f3 is smaller than the first frequency f1, and half the sum of the second frequency f2 and the third frequency f3 corresponds to the average of the second frequency f2 and the third frequency f3.

[0017] As will be described later, in this embodiment, even when the magnetic flux Φ is close to zero, a sufficiently small residual ZZ coupling strength can be obtained. For example, the residual ZZ coupling strength can be suppressed to 10 kHz or less. This makes it possible to control the ZZ coupling strength, for example, by using an AC signal Sg1 with a substantially zero DC component.

[0018] For example, a two-qubit gate operation can be performed using a signal Sg1 that does not include a DC component. This two-qubit gate operation corresponds to a CZ gate. For example, the influence of noise such as external heat can be suppressed. This enables highly accurate control. According to the embodiment, an electronic circuit capable of improving characteristics can be provided.

[0019] For example, the difference between the first frequency f1 and half the sum of the second frequency f2 and the third frequency f3 is defined as the frequency difference Δf. The frequency difference Δf is {(f2+f3) / 2}-f1. In this embodiment, the frequency difference Δf is negative.

[0020] The characteristics illustrated in FIG. 2 can be obtained by optimizing the configuration of the electronic circuit 110, for example.

[0021] 1, a first capacitance C1 is formed between the first conductive portion 11c and the third conductive portion 13c, a second capacitance C2 is formed between the second conductive portion 12c and the third conductive portion 13c, and a third capacitance C3 is formed between the first conductive portion 11c and the second conductive portion 12c.

[0022] In this embodiment, for example, the third capacitance C3 is greater than 0.2 times the first capacitance C1, or the third capacitance C3 is greater than 0.2 times the second capacitance C2, which makes it easier for the frequency difference Δf to become negative.

[0023] 3 is a graph illustrating the characteristics of an electronic circuit according to a reference example. FIG. 3 illustrates the characteristics of an electronic circuit 119 according to a reference example. In the electronic circuit 119, the third capacitance C3 is 0.2 times or less the first capacitance C1 and 0.2 times or less the second capacitance C2. As shown in FIG. 3, in the electronic circuit 119 according to the reference example, the frequency difference Δf is positive.

[0024] In the reference example, the residual ZZ coupling strength is sufficiently reduced by DC-shifting the magnetic flux ratio ER1 to about 0.35. In the reference example, for example, an external coil and a DC power supply are provided to shift the magnetic flux ratio ER1 to about 0.35. This makes the device susceptible to noise such as external heat.

[0025] In contrast, in the embodiment, even when the magnetic flux Φ is close to zero, a sufficiently small residual ZZ coupling strength can be obtained. For example, the residual ZZ coupling strength can be suppressed to 10 kHz or less. The external coil and DC power supply used in the reference example are no longer necessary, making it less susceptible to noise such as external heat. As a result, for example, the ZZ coupling strength between two quantum bits coupled to the electronic circuit 110 according to the embodiment can be controlled by an AC signal Sg1 with a substantially zero DC component.

[0026] 4A and 4B are graphs illustrating the characteristics of the electronic circuit according to the first embodiment. The horizontal axis of each graph represents the magnetic flux ratio ER1, and the vertical axis represents the ZZ coupling strength ζ. ｚｚ 4(b) is an enlarged view of a part of FIG. 4(a). As shown in FIGS. 4(a) and 4(b), at a low magnetic flux ratio ER1, the ZZ coupling strength ζ is sufficiently small. ｚｚ At a low magnetic flux ratio ER1, the coupled quantum bits can be manipulated. As shown in FIGS. 4(a) and 4(b), the ZZ coupling strength ζ when the magnetic flux Φ is zero ｚｚ The residual ZZ bond strength ζ ０ In this example, the residual ZZ bond strength ζ ０ The absolute value of / 2π is 7 kHz or less. "π" is the constant of the circumference of a circle.

[0027] 5 is a graph illustrating the characteristics of an electronic circuit. The horizontal axis of FIG. 5 represents the frequency difference Δf. As already explained, the frequency difference Δf is {(f2+f3) / 2}-f1. The vertical axis represents the residual ZZ coupling strength ζ ０ As already explained, the residual ZZ bond strength ζ ０ is the ZZ coupling strength ζ when the magnetic flux Φ is zero ｚｚAs shown in FIG. 5, when the frequency difference Δf is negative, the residual ZZ coupling strength ζ ０ In an embodiment, the frequency difference Δf is negative, so that when the magnetic flux Φ is zero, the residual ZZ coupling strength ζ ０ Since the frequency difference Δf is negative, the ZZ coupling strength between quantum bits can be controlled even by the signal Sg1 that does not contain a DC component.

[0028] In an embodiment, when the frequency difference Δf is negative and the absolute value of the frequency difference Δf increases, the residual ZZ coupling strength ζ ０ The absolute value of the frequency difference Δf is negative and may be 0.5 GHz or more. The residual ZZ coupling strength ζ is small. ０ In an embodiment, the absolute value of the frequency difference Δf may be, for example, 20 GHz or less.

[0029] 6 and 7 are graphs illustrating the operation of the electronic circuit according to the first embodiment. These figures illustrate the signal Sg1. The horizontal axis represents time tm. The vertical axis represents the intensity PS of the signal Sg1. As shown in FIG. 6, the signal Sg1 includes a positive pulse and a negative pulse. The absolute value of the intensity PS of the positive pulse may be substantially the same as the absolute value of the intensity PS of the negative pulse. As shown in FIG. 7, the signal Sg1 may be an AC signal. The DC component of the signal Sg1 may be substantially zero.

[0030] In the embodiment, the first frequency f1 may be, for example, 1 GHz or more and 20 GHz or less, the second frequency f2 may be, for example, 1 GHz or more and 20 GHz or less, and the third frequency f3 may be, for example, 1 GHz or more and 20 GHz or less.

[0031] 8 is a graph illustrating the characteristics of the electronic circuit according to the first embodiment. The horizontal axis of FIG. 8 represents the first capacitance ratio C3 / C1. The vertical axis represents the frequency difference Δf. As can be seen from FIG. 8, as the first capacitance ratio C3 / C1 increases, the frequency difference Δf becomes negative and the absolute value of the frequency difference Δf increases. When the first capacitance ratio C3 / C1 is 0.2 or greater, the frequency difference Δf becomes less than 0.

[0032] In this embodiment, for example, the third capacitance C3 is preferably 0.2 times or more the first capacitance C1. For example, the third capacitance C3 is preferably 0.2 times or more the second capacitance C2. For example, the third capacitance C3 is more preferably 0.3 times or more the first capacitance C1. For example, the third capacitance C3 is more preferably 0.3 times or more the second capacitance C2. For example, the third capacitance C3 may be 10 times or less the first capacitance C1. For example, the third capacitance C3 may be 10 times or less the second capacitance C2. For example, if the third capacitance C3 is excessively large, the circuit size is likely to become large.

[0033] In the embodiment, for example, the electronic circuit 110 is a double transmon coupler. In the electronic circuit 110, when the externally applied magnetic flux Φ is zero, the residual ZZ coupling strength ζ ０ For example, the ZZ coupling strength can be controlled by the signal Sg1 that is substantially free of DC components. Since no DC components are required, for example, the influence of heat can be suppressed. For example, power can be reduced. For example, the influence of pulse distortion in the signal Sg1 can be suppressed.

[0034] For example, as shown in Fig. 2, when the magnetic flux Φ is near zero, the change in energy (frequency F0) is small. For example, the coherence time becomes long.

[0035] 1, a computing device 210 according to the second embodiment includes the electronic circuit 110 according to the first embodiment, a first quantum bit 50A, and a second quantum bit 50B. The first quantum bit 50A is configured to couple to the first conductive portion 11c. The second quantum bit 50B is configured to couple to the second conductive portion 12c.

[0036] 1, a fourth capacitance C4 is formed between the first conductive portion 11c and the first quantum bit 50A. A fifth capacitance C5 is formed between the second conductive portion 12c and the second quantum bit 50B.

[0037] In the embodiment, the third capacitance C3 between the first conductive portion 11c and the second conductive portion 12c is preferably greater than three times the fourth capacitance C4 and greater than three times the fifth capacitance C5. This makes it easier to obtain, for example, a negative frequency difference Δf.

[0038] 9 is a graph illustrating the characteristics of the electronic circuit according to the second embodiment. The horizontal axis of FIG. 9 represents the second capacitance ratio C3 / C4. The vertical axis represents the frequency difference Δf. As can be seen from FIG. 9, as the second capacitance ratio C3 / C4 increases, the frequency difference Δf decreases. In the region where the second capacitance ratio C3 / C4 is greater than 3, the frequency difference Δf becomes less than 0.

[0039] In this embodiment, the third capacitance C3 is preferably three times or more than the fourth capacitance C4. The third capacitance C3 is preferably three times or more than the fifth capacitance C5. For example, the third capacitance C3 is preferably 50 times or less than the fourth capacitance C4. For example, the third capacitance C3 is preferably 50 times or less than the fifth capacitance C5. It is more preferable that the third capacitance C3 is 4.6 times or more than the fourth capacitance C4. It is even more preferable that the third capacitance C3 is 4.6 times or more than the fifth capacitance C5.

[0040] 1 , the computing device 210 according to the embodiment may further include a control unit 70. The first structure 50C may further include a first conductive member 61. The control unit 70 is configured to supply a signal Sg1 to the first conductive member 61 to control the magnetic flux Φ passing through the space SP.

[0041] 6 and 7 , the signal Sg1 includes, for example, a positive polarity signal and a negative polarity signal. The control unit 70 may be configured to execute a two-qubit gate on the first quantum bit 50A and the second quantum bit 50B by supplying such signal Sg1 to the first conductive member 61.

[0042] As shown in FIG. 1 , the first quantum bit 50A includes, for example, a fourth Josephson junction 24 including a fourth end 24a and a fourth other end 24b. The fourth other end 24b is configured to be coupled to the first conductive portion 11c. The fourth end 24a may be configured to be coupled to the third conductive portion 13c. The third conductive portion 13c may function as, for example, a ground layer 50g (GND). The first quantum bit 50A may further include, for example, a fourth conductive portion 24c. The fourth other end 24b is electrically connected to the fourth conductive portion 24c. A fourth capacitance C4 is formed between the fourth conductive portion 24c and the first conductive portion 11c. The fourth conductive portion 24c may be configured to be coupled to the first conductive portion 11c.

[0043] 1 , the second quantum bit 50B includes, for example, a fifth Josephson junction 25 including a fifth end 25a and a fifth other end 25b. The fifth other end 25b is configured to couple to the second conductive portion 12c. The fifth end 25a may be configured to couple to the third conductive portion 13c. The second quantum bit 50B may further include, for example, a fifth conductive portion 25c. The fifth other end 25b is electrically connected to the fifth conductive portion 25c. A fifth capacitance C5 is formed between the fifth conductive portion 25c and the second conductive portion 12c. The fifth conductive portion 25c may be configured to couple to the second conductive portion 12c.

[0044] 1, a sixth capacitance C6 may be formed between the fourth end 24a and the fourth other end 24b, and a seventh capacitance C7 may be formed between the fifth end 25a and the fifth other end 25b.

[0045] FIG. 10 is a schematic diagram illustrating a computing device according to the second embodiment. As shown in FIG. 10, the computing device 211 according to the embodiment further includes a high-pass filter 75. The remaining configuration of the computing device 211 may be similar to that of the computing device 210. The high-pass filter 75 is provided between the control unit 70 and the first conductive member 61. The high-pass filter 75 removes DC components. For example, a magnetic flux Φ based on the AC component of the signal Sg1 is effectively applied to the space SP. Higher accuracy of operation can be achieved.

[0046] Below, several examples of the structures of electronic circuits and computing devices according to the embodiments will be described. FIG. 11 is a schematic plan view illustrating an electronic circuit and a computing device according to the embodiment. As shown in FIG. 11 , in an electronic circuit 112 according to the embodiment, the first Josephson junction 21, the second Josephson junction 22, the third Josephson junction 23, the first conductive portion 11c, the second conductive portion 12c, and the third conductive portion 13c are provided on a first surface 80F of a base 80. In this example, in a computing device 212 including the electronic circuit 112, the first quantum bit 50A and the second quantum bit 50B are also provided on the first surface 80F. The first conductive portion 11c, the second conductive portion 12c, and the third conductive portion 13c are based on a first conductive layer 80L provided on the first surface 80F.

[0047] As shown in FIG. 11 , in this example, the first conductive portion 11c includes a first opposing portion 11p and a first other opposing portion 11q. The first opposing portion 11p faces the second conductive portion 12c. The first other opposing portion 11q faces the fourth conductive portion 24c. The first opposing portion 11p and the first other opposing portion 11q may satisfy at least one of a first condition and a second condition. In the first condition, the area of ​​the first opposing portion 11p is larger than the area of ​​the first other opposing portion 11q. In the second condition, the first distance between the first opposing portion 11p and the second conductive portion 12c is shorter than the second distance between the first other opposing portion 11q and the fourth conductive portion 24c. With this configuration, for example, the third capacitance C3 is larger than the fourth capacitance C4.

[0048] The second conductive portion 12c includes a second opposing portion 12p and a second other opposing portion 12q. The second opposing portion 12p faces the first conductive portion 11c. The second other opposing portion 12q faces the fifth conductive portion 25c. The second opposing portion 12p and the second other opposing portion 12q may satisfy at least one of a third condition and a fourth condition. In the third condition, the area of ​​the second opposing portion 12p is larger than the area of ​​the second other opposing portion 12q. In the fourth condition, the third distance between the second opposing portion 12p and the first conductive portion 11c is shorter than the fourth distance between the second other opposing portion 12q and the fifth conductive portion 25c. With this configuration, for example, the third capacitance C3 is larger than the fifth capacitance C5.

[0049] 12(a) and 12(b) are schematic diagrams illustrating an electronic circuit and a computing device according to an embodiment. FIG. 12(a) is a plan view. FIG. 12(b) is a cross-sectional view taken along line A1-A2 in FIG. 12(a). As shown in FIGS. 12(a) and 12(b), in an electronic circuit 113 according to an embodiment and a computing device 213 including the electronic circuit 113, a first structure 50C further includes a base 80. The base 80 includes a first surface 80F and a first side surface 81. The first side surface 81 intersects with a plane PL1 including the first surface 80F. The plane PL1 is, for example, along the X-Y plane. The first side surface 81 intersects with the X-Y plane. A third Josephson junction 23 is provided on the first surface 80F. At least a portion of the first conductive portion 11c is provided on the first side surface 81. The configuration of the electronic circuit 110 (and the computing device 210) may be applied to the configuration of the electronic circuit 113 (and the computing device 213) other than this.

[0050] By providing at least a portion of the first conductive portion 11c on the first side surface 81, the area of ​​the electronic circuit 113 and the computing device 213 can be reduced, making miniaturization easier. By utilizing the side surface of the base 80, a large capacitance can be obtained on a small surface. The first side surface 81 may be the side surface of a hole that penetrates the base 80 in the Z-axis direction.

[0051] In the electronic circuit 113 and the computing device 213, the base 80 may further include a second side surface 82. The second side surface 82 intersects with a plane PL1 that includes the first surface 80F. At least a portion of the second conductive portion 12c is provided on the second side surface 82.

[0052] 13(a) and 13(b) are schematic diagrams illustrating an electronic circuit and a computing device according to an embodiment. FIG. 13(a) is a plan view. FIG. 13(b) is a cross-sectional view taken along line A1-A2 in FIG. 13(a). As shown in FIGS. 13(a) and 13(b), in the electronic circuit 114 according to the embodiment and the computing device 214 including the electronic circuit 114, the base 80 of the first structure 50C includes a first surface 80F, a first side surface 81, and a second side surface 82. In this example, the first side surface 81 and the second side surface 82 are side surfaces of a recess provided in the base 80. The electronic circuit 114 and the computing device 214 can also be reduced in area. Miniaturization is easy. By utilizing the side surfaces of the base 80, a large capacitance can be obtained in a small area.

[0053] The embodiments may include the following technical solutions: (Technical Solution 1) A first structure including: a first Josephson junction including a first end and a first other end; a second Josephson junction including a second end and a second other end; a third Josephson junction including a third end and a third other end; a first conductive portion configured to couple with the first other end and the third end; a second conductive portion configured to couple with the second other end and the third other end; and a third conductive portion configured to couple with the first end and the second end, wherein half of the sum of the second frequency and the third frequency is smaller than the first frequency, the second frequency corresponds to a first excited state of the first structure when a magnetic flux passing through a space surrounded by a loop including the first Josephson junction, the second Josephson junction, the third Josephson junction, the first conductive portion, the second conductive portion, and the third conductive portion is zero, and the third frequency corresponds to a second excited state of the first structure when the magnetic flux is zero. the first frequency corresponds to the second excited state when the magnetic flux is 0.5 times a magnetic flux quantum.

[0054] (Technical Solution 2) The electronic circuit described in Technical Solution 1, wherein the first structure further includes a base, the base includes a first surface and a first side surface intersecting a plane including the first surface, the third Josephson junction is provided on the first surface, and at least a portion of the first conductive portion is provided on the first side surface.

[0055] (Technical Solution 3) An electronic circuit described in Technical Solution 1 or 2, wherein a third capacitance between the first conductive portion and the second conductive portion is greater than 0.2 times the first capacitance between the first conductive portion and the third conductive portion, and the third capacitance is greater than 0.2 times the second capacitance between the second conductive portion and the third conductive portion.

[0056] (Technical Solution 4) The electronic circuit according to Technical Solution 3, wherein the third capacitance is 0.3 times or more the first capacitance, and the third capacitance is 0.3 times or more the second capacitance.

[0057] (Technical Solution 5) An electronic circuit described in any one of Technical Solutions 1 to 4, wherein the first frequency is 1 GHz or more and 20 GHz or less, the second frequency is 1 GHz or more and 20 GHz or less, and the third frequency is 1 GHz or more and 20 GHz or less.

[0058] (Technical Solution 6) The electronic circuit according to any one of Technical Solutions 1 to 5, wherein the absolute value of the difference between ½ of the sum and the first frequency is 0.5 GHz or more.

[0059] (Technical Solution 7) A computing device further comprising: the electronic circuit according to Technical Solution 1 or 2; a first quantum bit configured to couple with the first conductive portion; and a second quantum bit configured to couple with the second conductive portion.

[0060] (Technical Solution 8) A computing device described in Technical Solution 7, wherein a third capacitance between the first conductive portion and the second conductive portion is greater than three times a fourth capacitance between the first conductive portion and the first quantum bit, and the third capacitance is greater than three times a fifth capacitance between the second conductive portion and the second quantum bit.

[0061] (Technical Solution 9) The computing device according to Technical Solution 8, wherein the third capacitance is greater than 4.6 times the fourth capacitance, and the third capacitance is greater than 4.6 times the fifth capacitance.

[0062] (Technical Solution 10) A computing device described in any one of Technical Solutions 7 to 9, further comprising a control unit, wherein the first structure further includes a first conductive member, and the control unit is configured to supply a signal to the first conductive member to control the magnetic flux in the space.

[0063] (Technical Solution 11) The computing device according to Technical Solution 10, wherein the signal includes a positive polarity signal and a negative polarity signal, and the control unit is configured to perform a two-qubit gate on the first quantum bit and the second quantum bit.

[0064] (Technical Solution 12) The computing device according to Technical Solution 10 or 11, further comprising a high-pass filter provided between the control unit and the first conductive member.

[0065] (Technical Solution 13) The computing device described in any one of Technical Solutions 7 to 12, wherein the first quantum bit includes a fourth Josephson junction including a fourth end and a fourth other end, the fourth other end is configured to be coupled to the first conductive portion, and the fourth end is configured to be coupled to the third conductive portion.

[0066] (Technical Solution 14) The computing device described in Technical Solution 13, wherein the first quantum bit further includes a fourth conductive portion, the fourth other end is electrically connected to the fourth conductive portion, and the fourth conductive portion is configured to be coupled to the first conductive portion.

[0067] (Technical proposal 15) The first conductive portion includes a first opposing portion opposing the second conductive portion and a first other opposing portion opposing the fourth conductive portion, wherein the first opposing portion and the first other opposing portion satisfy at least one of a first condition and a second condition, wherein, in the first condition, an area of ​​the first opposing portion is larger than an area of ​​the first other opposing portion, and, in the second condition, a first distance between the first opposing portion and the second conductive portion is shorter than a second distance between the first other opposing portion and the fourth conductive portion, a computing device as described in Technical proposal 14.

[0068] (Technical Proposal 16) The computing device described in any one of Technical Proposals 7 to 12, wherein the first quantum bit includes a fourth Josephson junction including a fourth end and a fourth other end, wherein the fourth other end is configured to be coupled to the first conductive portion, and the fourth end is configured to be coupled to the third conductive portion, the first quantum bit further includes a fourth conductive portion, wherein the fourth other end is electrically connected to the fourth conductive portion, and the fourth conductive portion is configured to be coupled to the first conductive portion, the first conductive portion includes: a first opposing portion that faces the second conductive portion, and a first other opposing portion that faces the fourth conductive portion, the first opposing portion and the first other opposing portion satisfy at least one of a first condition and a second condition, wherein under the first condition, an area of ​​the first opposing portion is larger than an area of ​​the first other opposing portion, and under the second condition, a first distance between the first opposing portion and the second conductive portion is shorter than a second distance between the first other opposing portion and the fourth conductive portion.

[0069] (Technical Solution 17) The computing device described in any one of Technical Solutions 7 to 16, wherein the second quantum bit includes a fifth Josephson junction including a fifth end and a fifth other end, the fifth other end is configured to be coupled to the second conductive portion, and the fifth end is configured to be coupled to the third conductive portion.

[0070] (Technical Solution 18) The computing device described in Technical Solution 17, wherein the second quantum bit further includes a fifth conductive portion, the fifth other end is electrically connected to the fifth conductive portion, and the fifth conductive portion is configured to be coupled to the second conductive portion.

[0071] (Technical proposal 19) The second conductive portion includes a second opposing portion opposing the first conductive portion and a second other opposing portion opposing the fifth conductive portion, wherein the second opposing portion and the second other opposing portion satisfy at least one of a third condition and a fourth condition, wherein in the third condition, an area of ​​the second opposing portion is larger than an area of ​​the second other opposing portion, and in the fourth condition, a third distance between the second opposing portion and the fifth conductive portion is shorter than a fourth distance between the second other opposing portion and the third conductive portion, a computing device as described in Technical proposal 18.

[0072] (Technical Solution 20) The computing device described in any one of Technical Solutions 7 to 16, wherein the second quantum bit includes a fifth Josephson junction including a fifth end and a fifth other end, the fifth other end configured to be coupled to the second conductive portion, and the fifth end configured to be coupled to the third conductive portion, the second quantum bit further includes a fifth conductive portion, the fifth other end being electrically connected to the fifth conductive portion, and the fifth conductive portion being configured to be coupled to the second conductive portion, the second conductive portion including: a second opposing portion that faces the first conductive portion, and a second other opposing portion that faces the fifth conductive portion, the second opposing portion and the second other opposing portion satisfy at least one of a third condition and a fourth condition, wherein under the third condition, an area of ​​the second opposing portion is larger than an area of ​​the second other opposing portion, and under the fourth condition, a third distance between the second opposing portion and the fifth conductive portion is shorter than a fourth distance between the second other opposing portion and the third conductive portion.

[0073] The third capacitance C3 between the first conductive portion 11c and the second conductive portion 12c is preferably greater than 1.5 times the fourth capacitance C4 between the first conductive portion 11c and the first quantum bit 50A. The third capacitance C3 is preferably greater than 1.5 times the fifth capacitance C5 between the second conductive portion 12c and the second quantum bit 50B.

[0074] 14 is a schematic plan view illustrating an electronic circuit according to the embodiment. As shown in FIG. 14 , in the electronic circuit 114 a according to the embodiment and in a computing device 214 a including the electronic circuit 114 a, a first structure 50C is provided on a base 80.

[0075] 15 is a schematic diagram illustrating an electronic circuit according to a third embodiment. As shown in FIG. 15 , in an electronic circuit 115 and a computing device 215 according to the embodiment, a first structure 50C includes a first inductor 21L, a second inductor 22L, and an intermediate Josephson junction 23x instead of the first Josephson junction 21, the second Josephson junction 22, and the third Josephson junction 23. Except for this, the configuration of the electronic circuit 115 may be similar to the configuration of the electronic circuit 110.

[0076] In the electronic circuit 115, the first structure 50C includes: a first inductor 21L including a first end 21a and a first other end 21b; a second inductor 22L including a second end 22a and a second other end 22b; an intermediate Josephson junction 23x including a third end 23a and a third other end 23b; a first conductive portion 11c configured to be coupled to the first other end 21b and the third end 23a; a second conductive portion 12c configured to be coupled to the second other end 22b and the third other end 23b; and a third conductive portion 13c configured to be coupled to the first end 21a and the second end 22a.

[0077] In the electronic circuit 115, half the sum of the second frequency f2 and the third frequency f3 is also smaller than the first frequency f1. The second frequency f2 corresponds to a first excited state E1 of the first structure 50C when the magnetic flux Φ passing through a space SP surrounded by a loop 50r including the first inductor 21L, the second inductor 22L, the middle Josephson junction 23x, the first conductive portion 11c, the second conductive portion 12c, and the third conductive portion 13c is zero. The third frequency f3 corresponds to a second excited state E2 of the first structure 50C when the magnetic flux Φ is zero. The first frequency f1 corresponds to the second excited state E2 when the magnetic flux Φ is 0.5 times the magnetic flux quantum.

[0078] The first inductor 21L may include one or more Josephson junctions, the multiple Josephson junctions included in the first inductor 21L being connected in series. The second inductor 22L may include one or more Josephson junctions, the multiple Josephson junctions included in the second inductor 22L being connected in series.

[0079] 16 is a schematic diagram illustrating an electronic circuit according to the third embodiment. As shown in FIG. 16, in an electronic circuit 115a and a computing device 215a according to the embodiment, a first structure 50C includes a plurality of intermediate Josephson junctions 23x. Except for this, the configuration of the electronic circuit 115a may be similar to the configuration of the electronic circuit 115. The plurality of intermediate Josephson junctions 23x are connected in series.

[0080] 17 is a schematic plan view illustrating an electronic circuit according to a fourth embodiment. As shown in FIG. 17 , in an electronic circuit 115 b and a computing device 215 b according to the fourth embodiment, a first conductive member 61 is provided on a base 80.

[0081] 18(a) and 18(b) are schematic diagrams illustrating an electronic circuit according to the fourth embodiment. Fig. 18(a) is a plan view. Fig. 18(b) is a perspective view. As shown in Fig. 18(a) and 18(b), in an electronic circuit 115c and a computing device 215c according to the embodiment, the first conductive member 61 is provided apart from the base 80.

[0082] Fifth Embodiment FIGS. 19( a) to 19(c) are schematic diagrams illustrating an electronic circuit according to a fifth embodiment. FIG. 19(a) is a plan view. FIG. 19(b) is a transparent plan view. FIG. 19(c) is a cross-sectional view. As shown in FIGS. 19(a) to 19(c), in an electronic circuit 115d and a computing device 215d according to the embodiment, a fourth Josephson junction 24 and a fifth Josephson junction 25 are provided on a first surface 80F of a base body 80. A first Josephson junction 21, a second Josephson junction 22, and a third Josephson junction 23 are provided on a second surface 80G of the base body 80. The direction from the second surface 80G to the first surface 80F is along a first direction D1.

[0083] In this example, a conductive layer is provided on the first side surface 81 of the base 80, and a first through electrode 81v is formed by this conductive layer. A conductive layer is provided on the second side surface 82 of the base 80, and a second through electrode 82v is formed by this conductive layer. These through electrodes electrically connect the conductive member on the first surface 80F and the conductive member on the second surface 80G. The through electrodes may be, for example, TSVs.

[0084] 20(a) to 20(c) are schematic diagrams illustrating an electronic circuit according to the fifth embodiment. FIG. 20(a) is a plan view. FIG. 20(b) is a transparent plan view. FIG. 20(c) is a cross-sectional view. As shown in FIGS. 20(a) and 20(b), in an electronic circuit 115e and a computing device 215e according to the embodiment, a first Josephson junction 21, a second Josephson junction 22, and a third Josephson junction 23 are provided on a first surface 80F of a base 80. A fourth Josephson junction 24 and a fifth Josephson junction 25 are provided on a second surface 80G of the base 80.

[0085] In this example, a conductive layer is provided on the first side surface 81 of the base 80, and a first through electrode 81v is formed by this conductive layer. A conductive layer is provided on the second side surface 82 of the base 80, and a second through electrode 82v is formed by this conductive layer. These through electrodes electrically connect the conductive member on the first surface 80F and the conductive member on the second surface 80G.

[0086] 21 is a schematic cross-sectional view illustrating an electronic circuit according to the fifth embodiment. As shown in FIG. 21 , the electronic circuit 116 according to the embodiment includes, in addition to the first base 85A, a second base 85B, a first opposing electrode 51C, and a second opposing electrode 52C. The configuration of the electronic circuit 116 other than these may be similar to the configuration of the electronic circuit 110. The computing device 216 includes the electronic circuit 116.

[0087] In this example, first base 85A includes a first surface F1 and a second surface F2. The direction from second surface F2 to first surface F1 is along first direction D1. First quantum bit 50A and second quantum bit 50B are provided on first surface F1. First structure 50C is provided on second surface F2. First element terminal 51T coupled to first quantum bit 50A is provided on first surface F1. Second element terminal 52T coupled to second quantum bit 50B is provided on first surface F1.

[0088] The second base 85B includes a third surface F3 and a fourth surface F4. The fourth surface F4 faces the first surface F1 of the first base 85A. The fourth surface F4 is located between the first surface F1 and the third surface F3. The fourth surface F4 is, for example, a lower surface. The third surface F3 is, for example, a upper surface. The direction from the fourth surface F4 to the third surface F3 is along the first direction D1.

[0089] The first opposing electrode 51C is provided on the fourth face F4. The second opposing electrode 52C is provided on the fourth face F4. The first opposing electrode 51C can be coupled (e.g., capacitively coupled) to the first element terminal 51T. The second opposing electrode 52C can be coupled (e.g., capacitively coupled) to the second element terminal 52T.

[0090] A first readout electrode 51R, a first readout conductive portion 51Rv, a second readout electrode 52R, and a second readout conductive portion 52Rv may be provided. The first readout electrode 51R and the second readout conductive portion 52Rv are provided on the third face F3. The first readout conductive portion 51Rv extends in the second base 85B along the first direction D1. The first readout conductive portion 51Rv electrically connects the first opposing electrode 51C to the first readout electrode 51R. The second readout conductive portion 52Rv extends in the second base 85B along the first direction D1. The second readout conductive portion 52Rv electrically connects the second opposing electrode 52C to the second readout electrode 52R.

[0091] For example, the first readout electrode 51R and the second readout electrode 52R may be connected to the control unit 70. The control unit 70 (see FIG. 1) can obtain a signal corresponding to the state of the first quantum bit 50A and a signal corresponding to the state of the second quantum bit 50B via these electrodes.

[0092] 21 , the electronic circuit 116 may include a third base 85C. The third base 85C includes a fifth surface F5 and a sixth surface F6. The fifth surface F5 faces the second surface F2. The fifth surface F5 is located between the sixth surface F6 and the second surface F2. The fifth surface F5 is, for example, the upper surface. The sixth surface F6 is, for example, the lower surface. The direction from the sixth surface F6 to the fifth surface F5 is along the first direction D1.

[0093] The electronic circuit 116 includes a magnetic flux control unit 60. The magnetic flux control unit 60 is provided on the fifth face F5. The magnetic flux control unit 60 is capable of controlling the magnetic flux Φ in the space SP within the loop 50r (see FIG. 1 ). For example, a control unit 70 is provided. The control unit 70 controls the magnetic flux control unit 60 to control the magnetic flux Φ.

[0094] In this example, the magnetic flux control unit 60 includes a first conductive member 61. In this example, the electronic circuit 116 includes a first control conductive unit 61u and a second control conductive unit 61v.

[0095] 21 , the first conductive member 61 is provided on the fifth surface F5. The first control conductive portion 61u extends in the third base 85C along the first direction D1. The first control conductive portion 61u is electrically connected to a portion of the first conductive member 61. The second control conductive portion 61v extends in the third base 85C along the first direction D1. The second control conductive portion 61v is electrically connected to another portion of the first conductive member 61.

[0096] The control unit 70 is connected to the first conductive member 61 via the first control conductive unit 61u and the second control conductive unit 61v. A magnetic field is generated by a signal (current) supplied from the control unit 70 to the first conductive member 61. The generated magnetic field is applied to a space SP within the loop 50r (see FIG. 1 ). The magnetic flux Φ in the space SP is controlled.

[0097] 21 , the conductive layer for ground potential GND provided on the first face F1 and the conductive layer for ground potential GND provided on the fourth face F4 may be electrically connected by a connection portion 58 a, and the conductive layer for ground potential GND provided on the second face F2 and the conductive layer for ground potential GND provided on the fifth face F5 may be electrically connected by a connection portion 58 b.

[0098] A conductive layer provided on the fifth surface F5 and set to a fixed potential (e.g., ground potential GND) and a conductive layer provided on the sixth surface F6 and set to a fixed potential (e.g., ground potential GND) may be electrically connected by a conductive member extending through the third base 85C along the first direction D1.

[0099] The electronic circuit 116 may include a first element conductive portion 51v and a second element conductive portion 52v. The first element conductive portion 51v extends in the first direction D1 through the first base body 85A. The first element conductive portion 51v is electrically connected to the first quantum bit 50A. Alternatively, the first element conductive portion 51v can be coupled (e.g., capacitively coupled) to the first quantum bit 50A.

[0100] The second element conductive portion 52v extends in the first direction D1 through the first base 85A. The second element conductive portion 52v is electrically connected to the second quantum bit 50B. Alternatively, the second element conductive portion 52v can be coupled (e.g., capacitively coupled) to the second quantum bit 50B.

[0101] 22A to 22I are schematic cross-sectional views illustrating a method for manufacturing an electronic circuit according to the fifth embodiment. As shown in FIG. 22A, a first base 85A is prepared. The first base 85A includes a first surface F1 and a second surface F2.

[0102] 22B, a conductive portion 85 is formed on a first base 85A. The conductive portion 85 extends along a first direction D1 from the second surface F2 to the first surface F1. The conductive portion 85 may be a TSV or the like. The conductive portion 85 may be a first element conductive portion 51v and a second element conductive portion 52v or the like.

[0103] 22( c), a conductive member 86a is formed on the first surface F1. The conductive member 86a may be at least a part of a capacitor included in the first quantum bit 50A, the second quantum bit 50B, etc. At least a part of the conductive member 86a is electrically connected to the conductive portion 85.

[0104] 22( d ), a fourth Josephson junction 24 and a fifth Josephson junction 25 are formed on the first surface F1. In this manner, a first quantum bit 50A and a second quantum bit 50B are formed on the first surface F1 of the first substrate 85A. The first quantum bit 50A includes the fourth Josephson junction 24. The second quantum bit 50B includes the fifth Josephson junction 25.

[0105] As shown in Fig. 22(e), a first member 88 including a recess 88d is prepared. As shown in Fig. 22(f), a first member 88 is provided. The first quantum bit 50A and the second quantum bit 50B are located between the first base 85A and the recess 88d. A support member 88s may be provided between the first surface F1 and the recess 88d. The support member 88s stabilizes the distance between the first surface F1 and the recess 88d.

[0106] 22G, a conductive member 86b is formed on the second surface F2. The conductive member 86b may be at least a part of a capacitor included in the first structure 50C, etc. At least a part of the conductive member 86b is electrically connected to the conductive portion 85.

[0107] 22(h), the first Josephson junction 21, the second Josephson junction 22, and the third Josephson junction 23 are formed on the second surface F2. These Josephson junctions are included in the first structure 50C. In this manner, in this manufacturing method, the first structure 50C is formed on the second surface F2 of the first base 85A. The first surface F1 is located between the second surface F2 and the first member 88.

[0108] 22I, the first member 88 is removed, thereby obtaining, for example, the electronic circuit according to the embodiment.

[0109] 23(a) to 23(i) are schematic cross-sectional views illustrating a method for manufacturing an electronic circuit according to the fifth embodiment. As shown in FIG. 23(a), a substrate that will become a first base 85A is prepared. As shown in FIG. 23(b), a recess 81d is formed on a first surface F1 of the first base 85A. The first base 85A includes a second surface F2. The first base 85A includes a protrusion 81p around the recess 81d.

[0110] 23(c), a conductive portion 85 is formed on a first base 85A. The conductive portion 85 extends along a first direction D1 from the second surface F2 to the first surface F1. The conductive portion 85 may be a TSV or the like. The conductive portion 85 may be a first element conductive portion 51v and a second element conductive portion 52v or the like.

[0111] 23(d), a conductive member 86a is formed on the first surface F1. The conductive member 86a may be at least a part of a capacitor included in the first quantum bit 50A, the second quantum bit 50B, etc. At least a part of the conductive member 86a is electrically connected to the conductive portion 85.

[0112] 23( e), a fourth Josephson junction 24 and a fifth Josephson junction 25 are formed on the first surface F1. In this manner, a first quantum bit 50A and a second quantum bit 50B are formed on the first surface F1 of the first substrate 85A. The first quantum bit 50A includes the fourth Josephson junction 24. The second quantum bit 50B includes the fifth Josephson junction 25.

[0113] 23( f), a first member 88 is provided. The first quantum bit 50A and the second quantum bit 50B are located between the first base 85A and the first member 88. A support portion 88s may be provided between the recess 81d on the first surface F1 and the first member 88. The support portion 88s stabilizes the distance between the recess 81d and the first member 88.

[0114] 23G, a conductive member 86b is formed on the second surface F2. The conductive member 86b may be at least a part of a capacitor included in the first structure 50C, etc. At least a part of the conductive member 86b is electrically connected to the conductive portion 85.

[0115] 23(h), the first Josephson junction 21, the second Josephson junction 22, and the third Josephson junction 23 are formed on the second surface F2. In this manner, in this manufacturing method, the first structure 50C is formed on the second surface F2 of the first base 85A. The first surface F1 is located between the second surface F2 and the first member 88.

[0116] 23I, the first member 88 is removed. Furthermore, the protrusion 81p of the first base 85A is removed. In this way, for example, the electronic circuit according to the embodiment is obtained.

[0117] Sixth Embodiment Fig. 24 is a schematic diagram illustrating an electronic circuit according to a sixth embodiment. As shown in Fig. 24, an electronic circuit 117 according to the embodiment includes a first quantum bit 50A, a second quantum bit 50B, a first structure 50C (first coupler 10A), a first readout conductive member 48a, and a first filter 31F. The first coupler 10A may correspond to the first structure 50C. A computing device 217 includes the electronic circuit 117.

[0118] The first coupler 10A includes a first resonator 11R and a second resonator 12R. The first resonator 11R is capable of coupling to the first quantum bit 50A. The second resonator 12R is capable of coupling to the second quantum bit 50B. For example, the first resonator 11R is capable of electromagnetically coupling to the first quantum bit 50A. For example, the second resonator 12R is capable of electromagnetically coupling to the second quantum bit 50B. The electromagnetic coupling includes, for example, capacitive coupling. The electromagnetic coupling includes, for example, inductive coupling. The first coupler 10A is, for example, a tunable coupler.

[0119] The first filter 31F includes a first filter portion 31P, a first other filter portion 31Q, and a first readout portion 31R. The first filter portion 31P is capable of being coupled to the first resonator 11R. The first other filter portion 31Q is capable of being coupled to the second resonator 12R. The first readout portion 31R is capable of being coupled to the first readout conductive member 48a. The first filter 31F may be, for example, a Purcell filter.

[0120] In this embodiment, the state of the quantum bit is read out by the first readout conductive member 48a via the first filter 31F, which allows, for example, quantum bits and couplers to be provided at a high density.

[0121] In the embodiment, the resonator included in the first coupler 10A is coupled to the first filter 31F. The state of the quantum bit is read out via the coupler and the first filter 31F. In the embodiment, the readout resonator can be omitted. Space can be saved. High density quantum bits can be obtained. According to the embodiment, an electronic circuit capable of improving characteristics can be provided.

[0122] 24 , in this example, the first filter 31F includes a first conductive component 41 and a second conductive component 42. The first conductive component 41 includes a first conductive portion 41p and a first other conductive portion 41q. The second conductive component 42 includes a second conductive portion 42p and a second other conductive portion 42q. The first conductive portion 41p is capable of coupling to the first resonator 11R. The second conductive portion 42p is capable of coupling to the second resonator 12R. The first other conductive portion 41q is capable of coupling to the first readout conductive member 48a. The second other conductive portion 42q is capable of coupling to the first readout conductive member 48a.

[0123] The first conductive portion 41p corresponds to the first filter portion 31P. The second conductive portion 42p corresponds to the first other filter portion 31Q. At least one of the first other conductive portion 41q and the second other conductive portion 42q corresponds to the first readout portion 31R.

[0124] The first quantum bit 50A, the second quantum bit 50B, the first coupler 10A, the first readout conductive member 48a and the first filter 31F may be formed, for example, by a conductive portion 85 (e.g., a conductive layer) provided on the first surface F1 of the base 80.

[0125] 24, the first coupler 10A includes a third Josephson junction 23 (for example, a first coupler Josephson junction 11K). One end of the third Josephson junction 23 (first coupler Josephson junction 11K) is connected to the first resonator 11R. The other end of the third Josephson junction 23 (first coupler Josephson junction 11K) is connected to the second resonator 12R.

[0126] The first resonator 11R includes a first Josephson junction 21. The second resonator 12R includes a second Josephson junction 22. The first Josephson junction 21 may be the first inductor 21L already described, and the second Josephson junction 22 may be the second inductor 22L already described.

[0127] The first resonator 11R is, for example, a first transmon resonator, the second resonator 12R is, for example, a second transmon resonator, and the first coupler 10A is, for example, a double transmon coupler.

[0128] A conductive portion is provided that is connected to the first Josephson junction 21 (for example, the first inductor 21L) and a conductive portion is provided that is connected to the second Josephson junction 22 (for example, the second inductor 22L).

[0129] The first filter portion 31P of the first filter 31F is couplable to the conductive portion connected to the first Josephson junction 21. The first other filter portion 31Q of the first filter 31F is couplable to the conductive portion connected to the second Josephson junction 22. The conductive portion connected to the first Josephson junction 21 and the first Josephson junction 21 are included in the first resonator 11R. The conductive portion connected to the second Josephson junction 22 and the second Josephson junction 22 are included in the second resonator 12R.

[0130] As shown in FIG. 24, a first qubit 50A includes a fourth Josephson junction 24 and a second qubit 50B includes a fifth Josephson junction 25.

[0131] The conductive portion connected to the fourth Josephson junction 24 can be coupled to a conductive portion connected to the first Josephson junction 21 (e.g., the first inductor 21L). The conductive portion connected to the fourth Josephson junction 24 can be coupled to a conductive portion connected to the second Josephson junction 22 (e.g., the second inductor 22L).

[0132] A portion of the conductive portion 85 (conductive layer) provided on the first surface F1 of the base 80 may function as a ground layer 50g. The ground layer 50g is set to the ground potential GND (e.g., a reference potential). For example, the ground layer 50g may be provided around the conductive portion 85 (conductive layer) that constitutes the first quantum bit 50A, the second quantum bit 50B, the first coupler 10A, the first readout conductive member 48a, and the first filter 31F.

[0133] As shown in FIG. 24 , a readout circuit 70R may be provided. For example, the readout circuit 70R may be included in the electronic circuit 117. The readout circuit 70R may be provided separately from the electronic circuit 117. The readout circuit 70R is electrically connected to the first readout conductive member 48a. The readout circuit 70R can detect the state of the first quantum bit 50A and the state of the second quantum bit 50B based on a signal obtained from the first readout conductive member 48a. For example, the readout circuit 70R detects an output signal based on an input signal input to the first readout conductive member 48a. This makes it possible to detect the state of the first quantum bit 50A and the state of the second quantum bit 50B. The readout circuit 70R outputs an output signal Sig1 including the detection result.

[0134] 25 is a circuit diagram illustrating an electronic circuit according to the sixth embodiment. As shown in FIG. 25, the first resonator 11R includes a first Josephson junction 21 (e.g., a first inductor 21L) and a first capacitor (a first capacitance C1). The first capacitance C1 is connected in parallel with the first Josephson junction 21 (e.g., the first inductor 21L).

[0135] The second resonator 12R includes a second Josephson junction 22 (e.g., a second inductor 22L) and a second capacitor (a second capacitance C2). The second capacitance C2 is connected in parallel with the second Josephson junction 22 (e.g., the second inductor 22L).

[0136] The first coupler 10A further includes a third Josephson junction 23 (e.g., the first coupler Josephson junction 11K). One end of the third Josephson junction 23 (e.g., the first coupler Josephson junction 11K) is connected to one end of the first Josephson junction 21 and one end of a first capacitor (first capacitance C1). The other end of the third Josephson junction 23 (e.g., the first coupler Josephson junction 11K) is connected to one end of the second Josephson junction 22 and one end of a second capacitor (second capacitance C2).

[0137] The other end of the first Josephson junction 21 and the other end of the first capacitor (first capacitance C1) are set to the ground potential GND. The other end of the second Josephson junction 22 and the other end of the second capacitor (second capacitance C2) are set to the ground potential GND.

[0138] The first quantum bit 50A includes a fourth Josephson junction 24 and a sixth capacitor (sixth capacitance C6). The sixth capacitance C6 is connected in parallel with the fourth Josephson junction 24. One end of the fourth Josephson junction 24 and one end of the sixth capacitor (sixth capacitance C6) can be coupled to the first conductive portion 11c. The other end of the fourth Josephson junction 24 and the other end of the sixth capacitor (sixth capacitance C6) are set to the ground potential GND.

[0139] The second quantum bit 50B includes a fifth Josephson junction 25 and a seventh capacitor (seventh capacitance C7). The seventh capacitance C7 is connected in parallel with the fifth Josephson junction 25. One end of the fifth Josephson junction 25 and one end of the seventh capacitor (seventh capacitance C7) can be coupled to the second conductive portion 12c. The other end of the fifth Josephson junction 25 and the other end of the seventh capacitor (seventh capacitance C7) are set to the ground potential GND.

[0140] The first conductive component 41 can be considered, for example, as an LC circuit connected in parallel. The first conductive component 41 corresponds, for example, to the first filter resonator 41f. The second conductive component 42 can be considered, for example, as an LC circuit connected in parallel. The second conductive component 42 corresponds, for example, to the second filter resonator 42f. These LC circuits are waveguide resonators.

[0141] In one example, the resonant frequency of the first quantum bit 50A is approximately 8.3 GHz. The resonant frequency of the second quantum bit 50B is approximately 9.0 GHz. The resonant frequency of the first resonator 11R is approximately 11.0 GHz. The resonant frequency of the second resonator 12R is approximately 11.7 GHz. The frequency of the first resonator 11R is different from the resonant frequency of the second resonator 12R. The resonant frequencies of the first resonator 11R and the second resonator 12R are read out via the first filter 31F. The resonant frequencies of the first quantum bit 50A and the second quantum bit 50B are substantially blocked by the first filter 31F.

[0142] In the embodiment, for example, the resonant frequency of the first resonator 11R is higher than the resonant frequency of the first quantum bit 50A, and the resonant frequency of the second resonator 12R is higher than the resonant frequency of the second quantum bit 50B.

[0143] 25 , a loop 50r is provided in a first coupler 10A. The loop 50r includes a conductive path including a first Josephson junction 21, a conductive path including a second Josephson junction 22, and a conductive path including a third Josephson junction 23. For example, by controlling the magnetic flux Φ in the loop 50r, the coupling strength between a first quantum bit 50A and a second quantum bit 50B can be controlled.

[0144] For example, the coupling between the first quantum bit 50A and the second quantum bit 50B can be substantially turned off. This state is, for example, an idle state. In the idle state, the first resonator 11R can be considered as a resonator strongly coupled to the first quantum bit 50A. The first resonator 11R can function as a readout resonator. In this embodiment, a separately formed readout resonator is not required. A space-saving electronic circuit can be obtained.

[0145] For example, transmons are used as the first filter resonator 41f and the second filter resonator 42f instead of linear resonators. In this case, the transmon input is sufficiently weakened. Strong coupling between the first resonator 11R and the first quantum bit 50A results in a large state-dependent frequency shift. For example, with strong coupling, the state-dependent frequency shift is approximately 30 MHz, making it possible to read out the quantum bit state.

[0146] For example, if there is a loss of around 50% in the output signal, a read error probability of less than 1% is obtained for a read period of 200 ns.

[0147] FIG. 26 is a schematic plan view illustrating an electronic circuit according to the sixth embodiment. FIG. 27 is a schematic view illustrating an electronic circuit according to the sixth embodiment. As shown in FIGS. 26 and 27 , an electronic circuit 117a according to the embodiment includes a first conductive member 61. In the electronic circuit 117a, the first conductive member 61 is configured to be coupled to the control unit 70 via a coupling capacitor (coupling capacitance Cx1). Except for this, the configuration of the electronic circuit 117a may be similar to the configuration of the electronic circuit 110. The computing device 217a includes the electronic circuit 117a.

[0148] Seventh Embodiment FIG. 28 is a schematic plan view illustrating an electronic circuit according to a seventh embodiment. As shown in FIG. 28 , an electronic circuit 117b according to the embodiment includes a plurality of quantum bits 50b and a plurality of first structures 50C. The plurality of first structures 50C correspond to couplers. The plurality of quantum bits 50b are arranged, for example, in a matrix on the XY plane. One of the plurality of quantum bits 50b is arranged between another of the plurality of quantum bits 50b. One of the plurality of quantum bits 50b corresponds, for example, to the first quantum bit 50A. Another of the plurality of quantum bits 50b corresponds, for example, to the second quantum bit 50B. One of the plurality of first structures 50C can be coupled (e.g., capacitively coupled) to one of the plurality of quantum bits 50b. One of the plurality of first structures 50C can be coupled (e.g., capacitively coupled) to another of the plurality of quantum bits 50b.

[0149] A computing device 217b according to the embodiment includes an electronic circuit 117b. Any of the above-described electronic circuit configurations can be applied to the computing device 217b. For example, Josephson junctions included in the plurality of quantum bits 50b are provided on the first face F1. Josephson junctions included in each of the plurality of first structures 50C may be provided on another face (such as the second face F2).

[0150] Eighth Embodiment Figures 29(a) and 29(b) are schematic diagrams illustrating a computing device according to an eighth embodiment. Figure 29(b) is a cross-sectional view taken along line A1-A2 in Figure 29(a). As shown in Figures 29(a) and 29(b), an electronic circuit 130 according to the embodiment includes a first base 85A and a second base 85B. A computing device 230 includes the electronic circuit 130.

[0151] In the electronic circuit 130, the first quantum bit 50A and the first structure 50C are provided on a first base 85A. The second quantum bit 50B is provided on a second base 85B. The first structure 50C is coupled to the second quantum bit 50B via a first connection member 15a.

[0152] A first substrate conductive layer 85AL is provided on the first substrate 85A. A second substrate conductive layer 85BL is provided on the second substrate 85B. The first substrate conductive layer 85AL may form at least a portion of the first quantum bit 50A. The first substrate conductive layer 85AL may form at least a portion of the first structure 50C. The second substrate conductive layer 85BL may form at least a portion of the second quantum bit 50B.

[0153] 30(a) and 30(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. FIG. 30(b) is a cross-sectional view taken along line A1-A2 in FIG. 30(a). As shown in FIGS. 30(a) and 30(b), in an electronic circuit 131 according to the embodiment, a first structure 50C is provided on a third base 85C. Except for this, the configuration of the electronic circuit 131 may be similar to the configuration of the electronic circuit 130. A computing device 231 includes the electronic circuit 131.

[0154] In electronic circuit 131, first quantum bit 50A is provided on first base 85A. Second quantum bit 50B is provided on second base 85B. First structure 50C is coupled to first quantum bit 50A via first connection member 15a. First structure 50C is coupled to second quantum bit 50B via second connection member 15b.

[0155] 31(a) and 31(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. FIG. 31(b) is a cross-sectional view taken along line A1-A2 in FIG. 31(a). As shown in FIGS. 31(a) and 31(b), in the electronic circuit 132 according to the embodiment, the third base 85C overlaps the first base 85A and the second base 85B. Except for this, the configuration of the electronic circuit 132 may be the same as the configuration of the electronic circuit 131. The computing device 232 includes the electronic circuit 132.

[0156] In the electronic circuit 132, the position in the first direction D1 of the conductive member included in the third base 85C is between the position in the first direction D1 of the first base 85A and the position in the first direction D1 of the third base 85C. The position in the first direction D1 of the conductive member included in the third base 85C is between the position in the first direction D1 of the second base 85B and the position in the first direction D1 of the third base 85C.

[0157] In electronic circuit 132, first structure 50C is coupled to first quantum bit 50A provided on first base 85A via first connecting member 15a, and to second quantum bit 50B provided on second base 85B via second connecting member 15b.

[0158] 32(a) and 32(b) are schematic diagrams illustrating a computing device according to the eighth embodiment. FIG. 32(b) is a cross-sectional view taken along line A1-A2 in FIG. 32(a). As shown in FIGS. 32(a) and 32(b), in the electronic circuit 133 according to the embodiment, the connecting members are omitted from the configuration of the electronic circuit 132. The configuration of the electronic circuit 133 other than this may be the same as the configuration of the electronic circuit 132. The computing device 233 includes the electronic circuit 133.

[0159] In electronic circuit 133, first structure 50C provided on third base 85C is coupled to first quantum bit 50A provided on first base 85A. First structure 50C provided on third base 85C is coupled to second quantum bit 50B provided on second base 85B. The coupling may be, for example, capacitive coupling.

[0160] According to the embodiment, it is possible to provide an electronic circuit and a computing device that can improve the performance.

[0161] The embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configurations of the elements included in the electronic circuit or computing device, such as the structure, Josephson junction, substrate, conductive portion, and control portion, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0162] Any combination of two or more elements of each example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0163] All electronic circuits and computing devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the electronic circuits and computing devices described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0164] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention.

[0165] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0166] 10A: first coupler, 11K: first coupler Josephson junction, 11R, 12R: first and second resonators, 11c to 13c: first to third conductive portions, 11p, 12p: first and second opposing portions, 11q, 12q: first and second other opposing portions, 15a, 15b: first and second connecting members, 21 to 25: first to fifth Josephson junctions, 21L, 22L: first and second inductors, 21a to 25a: first to fifth ends, 21b to 25b: first to fifth other ends, 23x: intermediate Josephson junction, 24c, 25c: fourth and fifth conductive portions, 31F: first filter, 31P: first filter portion, 31Q: first other filter portion, 31R: first readout portion, 41, 42: first and second conductive parts; 41f, 42f: first and second filter resonators; 41p, 42p: first and second conductive portions; 41q, 42q: first and second other conductive portions; 48a: first readout conductive member; 50A, 50B: first and second quantum bits; 50C: first structure; 50b: quantum bit; 50g: ground layer; 50r: loop; 51C, 52C: first and second opposing electrodes; 51R, 52R: first and second opposing readout electrodes; 51Rv, 52Rv: first and second opposing readout conductive portions; 51T, 52T: first and second element terminals; 51v, 52v: first and second element conductive portions; 58a, 58b: connection portion; 60: magnetic flux control portion; 61: First conductive member, 61u, 61v: First and second control conductive portions, 70: Control portion, 75: High-pass filter, 80: Base, 80F: First surface, 80G: Second surface, 80L: First conductive layer, 81, 82: First and second side surfaces, 81d: Recess, 81p: Protrusion, 81v, 82v: First and second through electrodes, 85: Conductive portion, 85A to 85C: First to third bases, 85AL, 85BL: First and second base conductive layers, 86a, 86b: Conductive member, 88d: Recess, 88s: Support portion, 110, 112 to 114, 114a, 115, 115a to 115e, 117a, 117b, 119, 130 to 133: electronic circuits; 210 to 214, 214a, 215a to 215e, 217a, 217b, 230 to 233: computing devices; C1 to C7: first to seventh capacitances; Cx1: coupling capacitance; D1;First direction, E1, E2: first and second excitation states, ER1: magnetic flux ratio, F0: frequency, F1 to F6: first to sixth planes, GND: ground potential, PL1: plane, PS: intensity, Δf: frequency difference, SP: space, Sg1: signal, Sig1: output signal, f1 to f3: first to third frequencies, tm: time, Φ: magnetic flux, Φ; ０ : magnetic flux quantum, ζ ０ : Residual ZZ bond strength, ζ ｚｚ :ZZ bond strength

Claims

1. A first structure including: a first Josephson junction including a first end and a first other end; a second Josephson junction including a second end and a second other end; a third Josephson junction including a third end and a third other end; a first conductive portion configured to couple with the first other end and the third end; a second conductive portion configured to couple with the second other end and the third other end; and a third conductive portion configured to couple with the first end and the second end; wherein half of the sum of the second frequency and the third frequency is smaller than the first frequency; the second frequency corresponds to a first excited state of the first structure when a magnetic flux passing through a space surrounded by a loop including the first Josephson junction, the second Josephson junction, the third Josephson junction, the first conductive portion, the second conductive portion, and the third conductive portion is zero; and the third frequency corresponds to a second excited state of the first structure when the magnetic flux is zero. the first frequency corresponds to the second excited state when the magnetic flux is 0.5 times a magnetic flux quantum.

2. The electronic circuit according to claim 1, wherein the first structure further includes a substrate, the substrate including a first surface and a first side surface intersecting a plane including the first surface, the third Josephson junction being provided on the first surface, and at least a portion of the first conductive portion being provided on the first side surface.

3. An electronic circuit according to claim 1 or 2, wherein a third capacitance between the first conductive portion and the second conductive portion is greater than 0.2 times the first capacitance between the first conductive portion and the third conductive portion, and the third capacitance is greater than 0.2 times the second capacitance between the second conductive portion and the third conductive portion.

4. A computing device further comprising: the electronic circuit of claim 1 or 2; a first quantum bit configured to couple with the first conductive portion; and a second quantum bit configured to couple with the second conductive portion.

5. The computing device of claim 4, wherein a third capacitance between the first conductive portion and the second conductive portion is greater than 1.5 times a fourth capacitance between the first conductive portion and the first quantum bit, and the third capacitance is greater than 1.5 times a fifth capacitance between the second conductive portion and the second quantum bit.

6. The computing device of claim 4, further comprising a control unit, wherein the first structure further comprises a first conductive member, and the control unit is configured to supply a signal to the first conductive member to control the magnetic flux in the space.

7. The computing device of claim 6, wherein the signal includes a positive polarity signal and a negative polarity signal, and the control unit is configured to perform a two-qubit gate on the first quantum bit and the second quantum bit.

8. The computing device of claim 6, further comprising a high-pass filter disposed between said control unit and said first conductive member.

9. The computing device of claim 4, wherein the first quantum bit includes a fourth Josephson junction including a fourth end and a fourth other end, the fourth other end configured to couple with the first conductive portion, and the fourth end configured to couple with the third conductive portion, the first quantum bit further includes a fourth conductive portion, the fourth other end electrically connected to the fourth conductive portion, and the fourth conductive portion configured to couple with the first conductive portion, the first conductive portion including: a first opposing portion opposing the second conductive portion; and a first other opposing portion opposing the fourth conductive portion, the first opposing portion and the first other opposing portion satisfy at least one of a first condition and a second condition, wherein under the first condition, an area of ​​the first opposing portion is larger than an area of ​​the first other opposing portion, and under the second condition, a first distance between the first opposing portion and the second conductive portion is shorter than a second distance between the first other opposing portion and the fourth conductive portion.

10. The computing device of claim 4, wherein the second quantum bit includes a fifth Josephson junction including a fifth end and a fifth other end, the fifth other end configured to couple with the second conductive portion, and the fifth end configured to couple with the third conductive portion, the second quantum bit further includes a fifth conductive portion, the fifth other end electrically connected to the fifth conductive portion, and the fifth conductive portion configured to couple with the second conductive portion, the second conductive portion including: a second opposing portion opposing the first conductive portion; and a second other opposing portion opposing the fifth conductive portion, the second opposing portion and the second other opposing portion satisfying at least one of a third condition and a fourth condition, wherein under the third condition, an area of ​​the second opposing portion is larger than an area of ​​the second other opposing portion, and under the fourth condition, a third distance between the second opposing portion and the fifth conductive portion is shorter than a fourth distance between the second other opposing portion and the third conductive portion.

11. An electronic circuit comprising: a first structure including: a first inductor including a first end and a first other end; a second inductor including a second end and a second other end; an intermediate Josephson junction including a third end and a third other end; a first conductive portion configured to couple with the first other end and the third end; a second conductive portion configured to couple with the second other end and the third other end; and a third conductive portion configured to couple with the first end and the second end; wherein half of the sum of the second frequency and the third frequency is less than the first frequency; the second frequency corresponds to a first excited state of the first structure when a magnetic flux passing through a space surrounded by a loop including the first inductor, the second inductor, the intermediate Josephson junction, the first conductive portion, the second conductive portion, and the third conductive portion is zero; the third frequency corresponds to a second excited state of the first structure when the magnetic flux is zero; and the first frequency corresponds to the second excited state when the magnetic flux is 0.5 times a magnetic flux quantum.

12. A computing device comprising: a first quantum bit; a second quantum bit; a first coupler including a first resonator and a second resonator, wherein the first resonator is couplable with the first quantum bit and the second resonator is couplable with the second quantum bit; a first conductive readout member; and a first filter including a first filter portion, a first other filter portion, and a first readout portion, wherein the first filter portion is couplable with the first resonator, the first other filter portion is couplable with the second resonator, and the first readout portion is couplable with the first conductive readout member.

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