Interposer

Abstract

The present invention addresses the problem of improving mounting reliability. An interposer (1) is provided with a dielectric substrate (2), a through wiring portion (3), a pad electrode (4), and a protective layer (5). The through wiring portion (3) penetrates the dielectric substrate (2). The pad electrode (4) is positioned across a first main surface (21) of the dielectric substrate (2) and the through wiring portion (3). The pad electrode (4) is connected to the through wiring portion (3). The protective layer (5) is disposed on the first main surface (21) of the dielectric substrate (2). The pad electrode (4) includes a first portion (41) that is in contact with the first main surface (21) of the dielectric substrate (2), and a second portion (42) that overlaps the first portion (41). In the pad electrode (4), the outer edge of the first portion (41) is located inside the outer edge of the second portion (42). A part of the protective layer (5) is interposed between the first main surface (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4).

Description

Interposer

[0001] The present disclosure relates to interposers, and more particularly to interposers comprising dielectric substrates.

[0002] 2. Description of the Related Art Conventionally, a wiring board on which electronic components such as semiconductor chips are mounted is known as an interposer (see Patent Document 1).

[0003] Interposers are sometimes required to have improved mounting reliability.

[0004] JP 2012-94734 A

[0005] An object of the present disclosure is to provide an interposer that can improve mounting reliability.

[0006] An interposer according to one aspect of the present disclosure includes a dielectric substrate, a through wiring portion, a pad electrode, and a protective layer. The dielectric substrate has a first main surface and a second main surface opposite the first main surface. The through wiring portion penetrates the dielectric substrate. The pad electrode is located across the first main surface of the dielectric substrate and the through wiring portion. The pad electrode is connected to the through wiring portion. The protective layer is disposed on the first main surface of the dielectric substrate. The pad electrode includes a first portion in contact with the first main surface of the dielectric substrate and a second portion overlapping the first portion. In the pad electrode, the outer edge of the first portion is located inside the outer edge of the second portion. A portion of the protective layer is interposed between the first main surface of the dielectric substrate and the second portion of the pad electrode.

[0007] FIG. 1 is a cross-sectional view of an interposer according to a first embodiment. FIGS. 2A and 2B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 3A and 3B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 4A and 4B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 5A and 5B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 6A and 6B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 7A and 7B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 8A and 8B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 9A and 9B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIG. 10 is a cross-sectional view of an interposer according to a second embodiment. FIG. 11 is a cross-sectional view of an interposer according to a third embodiment. FIG. 12 is a cross-sectional view of an electronic component module according to a fourth embodiment including the interposer according to the first embodiment. FIGS. 13A and 13B are cross-sectional views illustrating steps in a method for manufacturing the electronic component module according to the first embodiment.

[0008] Hereinafter, embodiments 1 to 4 will be described with reference to the drawings. The drawings referred to in the following embodiments 1 to 4 are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.

[0009] (Embodiment 1) (1) Interposer As shown in FIG. 1 , an interposer 1 according to embodiment 1 includes a dielectric substrate 2, a plurality of through wiring portions 3, a plurality of pad electrodes 4, and a protective layer 5. The dielectric substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The plurality of through wiring portions 3 penetrate the dielectric substrate 2. The plurality of pad electrodes 4 are located across the first main surface 21 of the dielectric substrate 2 and the through wiring portions 3. The plurality of pad electrodes 4 are connected to the plurality of through wiring portions 3, respectively. The protective layer 5 is disposed on the first main surface 21 of the dielectric substrate 2. Each of the plurality of pad electrodes 4 includes a first portion 41 in contact with the first main surface 21 of the dielectric substrate 2 and a second portion 42 overlapping the first portion 41. In a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge of each of the plurality of pad electrodes 4 is located inside the outer edge of the second portion 42. In the interposer 1 , a portion of the protective layer 5 is interposed between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of pad electrodes 4 .

[0010] According to the interposer 1 of the first embodiment, it is possible to improve the mounting reliability.

[0011] The interposer 1 according to the first embodiment further includes a plurality of wiring portions 6 and a plurality of second pad electrodes 7 different from the plurality of pad electrodes 4 (hereinafter also referred to as first pad electrodes 4). The plurality of second pad electrodes 7 correspond one-to-one to the plurality of through wiring portions 3 and one-to-one to the plurality of first pad electrodes 4. The plurality of second pad electrodes 7 are connected to corresponding through wiring portions 3 among the plurality of through wiring portions 3. Furthermore, each of the plurality of second pad electrodes 7 is connected to a corresponding first pad electrode 4 among the plurality of first pad electrodes 4 via the through wiring portion 3.

[0012] The interposer 1 according to the first embodiment is disposed, for example, between a semiconductor chip and a package substrate of a SiP (System in Package). The semiconductor chip includes, for example, a processor, a logic IC (Integrated Circuit), a memory (for example, a High Bandwidth Memory (HBM)), etc.

[0013] (2) Components of the Interposer Each component of the interposer 1 according to the first embodiment will be described below with reference to FIG.

[0014] The dielectric substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. When viewed in a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge shape of the dielectric substrate 2 is rectangular, but may be a shape other than rectangular.

[0015] The dielectric substrate 2 has a first dielectric layer 201 and a second dielectric layer 202. The first dielectric layer 201 is laminated on the second dielectric layer 202. The first dielectric layer 201 has a first main surface 211 and a second main surface 212 opposite the first main surface 211. The second dielectric layer 202 has a first main surface 221 and a second main surface 222 opposite the first main surface 221. In the dielectric substrate 2, the second main surface 212 of the first dielectric layer 201 is in contact with the first main surface 221 of the second dielectric layer 202. The first main surface 21 of the dielectric substrate 2 is formed by the first main surface 211 of the first dielectric layer 201. The second main surface 22 of the dielectric substrate 2 is formed by the second main surface 222 of the second dielectric layer 202.

[0016] The first main surface 21 of the dielectric substrate 2 has an uneven shape over the entire area of ​​the first main surface 21. In other words, the first main surface 21 of the dielectric substrate 2 is a rough surface.

[0017] The material of the first dielectric layer 201 includes an organic material. More specifically, the material of the first dielectric layer 201 includes, as a main component, for example, an imide resin (e.g., polyimide, bismaleimide, etc.) or a fluorine resin (e.g., polytetrafluoroethylene, etc.). From the viewpoint of improving the high-frequency characteristics of the interposer 1, the material of the first dielectric layer 201 preferably has a low dielectric constant and a low dielectric loss tangent. "Improving the high-frequency characteristics" means reducing the transmission loss of signals transmitted through the through wiring portion 3.

[0018] The material of the second dielectric layer 202 includes an organic material. More specifically, the material of the second dielectric layer 202 includes, as a main component, for example, an imide-based resin (e.g., polyimide, bismaleimide, etc.), a fluorine-based resin (e.g., polytetrafluoroethylene, etc.), or an epoxy-based resin. The material of the second dielectric layer 202 may be the same as or different from the material of the first dielectric layer 201.

[0019] Each of the plurality of through wiring portions 3 includes, for example, a first via conductor portion 31, a connection electrode 32, and a second via conductor portion 33. The first via conductor portion 31 is composed of a first portion 311 seamlessly connected to the first portion 41 of the first pad electrode 4, and a second portion 312 seamlessly connected to the second portion 42 of the first pad electrode 4. In each through wiring portion 3, the first via conductor portion 31, the connection electrode 32, and the second via conductor portion 33 are arranged in this order from the first main surface 21 side of the dielectric substrate 2. In each through wiring portion 3, the first via conductor portion 31 and the connection electrode 32 are directly connected, and the connection electrode 32 and the second via conductor portion 33 are directly connected, so that the first via conductor portion 31, the connection electrode 32, and the second via conductor portion 33 are electrically connected. In each through wiring portion 3, a first via conductor portion 31 penetrates the first dielectric layer 201. In each through wiring portion 3, a connection electrode 32 and a second via conductor portion 33 are embedded in the second dielectric layer 202. The multiple connection electrodes 32 are embedded in the second dielectric layer 202 and exposed from a first main surface 221 of the second dielectric layer 202. The main surface 321 of each of the multiple connection electrodes 32 is covered by the first via conductor portion 31 and a part of the first dielectric layer 201.

[0020] In a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge shape of each of the plurality of first via conductors 31 is circular. Each of the plurality of first via conductors 31 is shaped like a truncated cone. The outer diameter of each of the plurality of first via conductors 31 gradually decreases as it moves away from the first pad electrode 4 and closer to the connection electrode 32 in the thickness direction D1 of the dielectric substrate 2. At the interface between the first via conductor 31 and the connection electrode 32, the outer diameter of the first via conductor 31 is smaller than the outer diameter of the connection electrode 32.

[0021] In a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge shape of each of the plurality of connection electrodes 32 is circular. Each of the plurality of connection electrodes 32 has a truncated cone shape. The outer diameter of each of the plurality of connection electrodes 32 gradually decreases with increasing distance from the first via conductor portion 31 in the thickness direction D1 of the dielectric substrate 2.

[0022] In a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge shape of each of the multiple second via conductors 33 is circular. Each of the multiple second via conductors 33 is shaped like a truncated cone. The outer diameter of each of the multiple second via conductors 33 gradually decreases as it moves away from the second pad electrode 7 and closer to the connection electrode 32 in the thickness direction D1 of the dielectric substrate 2. At the interface between the second via conductor 33 and the connection electrode 32, the outer diameter of the second via conductor 33 is smaller than the outer diameter of the connection electrode 32.

[0023] The material of each of the plurality of through wiring portions 3 includes, for example, copper. The material of each of the plurality of through wiring portions 3 is not limited to copper, but may be, for example, a copper alloy, aluminum, or titanium.

[0024] Each of the plurality of first pad electrodes 4 is located across a corresponding one of the plurality of through wiring portions 3 and the first main surface 21 of the dielectric substrate 2. More specifically, each of the plurality of first pad electrodes 4 is located across a first via conductor portion 31 of a corresponding one of the plurality of through wiring portions 3 and a part of the first main surface 21 of the dielectric substrate 2.

[0025] In a plan view from the thickness direction D1 of the dielectric substrate 2, each of the multiple first pad electrodes 4 has a circular shape. In a plan view from the thickness direction D1 of the dielectric substrate 2, each of the multiple first pad electrodes 4 is larger than each of the through wiring portion 3 and the second pad electrode 7. In a plan view from the thickness direction D1 of the dielectric substrate 2, an outer edge 402 of each of the multiple first pad electrodes 4 encompasses an outer edge of a first via conductor 31 connected to the first pad electrode 4. In addition, in a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge 402 of each of the multiple first pad electrodes 4 encompasses an outer edge 322 of a connection electrode 32 overlapping the first pad electrode 4. In addition, in a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge 402 of each of the multiple first pad electrodes 4 encompasses an outer edge 702 of a second pad electrode 7 overlapping the first pad electrode 4. The multiple first pad electrodes 4 protrude from the first main surface 21 of the dielectric substrate 2. Each of the plurality of first pad electrodes 4 has a main surface 401 opposite to the dielectric substrate 2. In each of the plurality of first pad electrodes 4, the second portion 42 has an outer peripheral surface 421 that is connected to the main surface 401 of the first pad electrode 4.

[0026] The material of each of the plurality of first pad electrodes 4 includes, for example, copper. The material of each of the plurality of first pad electrodes 4 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium.

[0027] The thickness of each of the plurality of first pad electrodes 4 is, for example, 10 μm, but is not limited to 10 μm. The thickness of each of the plurality of first pad electrodes 4 is the thickness of the portion in contact with the first main surface 21 of the dielectric substrate 2.

[0028] Each of the multiple first pad electrodes 4 includes a first portion 41 in contact with the first main surface 21 of the dielectric substrate 2 and a second portion 42 overlapping the first portion 41. In a plan view from the thickness direction D1 of the dielectric substrate 2, the first portion 41 of each of the multiple first pad electrodes 4 is circular, and the second portion 42 of each of the multiple first pad electrodes 4 is also circular. In each of the multiple first pad electrodes 4, an outer edge of the first portion 41 is located more inward than an outer edge of the second portion 42 in a plan view from the thickness direction D1 of the dielectric substrate 2. In each of the multiple first pad electrodes 4, a step is present between an outer peripheral surface 411 of the first portion 41 and an outer peripheral surface 421 of the second portion 42.

[0029] Each of the plurality of second pad electrodes 7 is located across a corresponding one of the plurality of through wiring portions 3 and the second main surface 22 of the dielectric substrate 2. More specifically, each of the plurality of second pad electrodes 7 is located across a second via conductor portion 33 of a corresponding one of the plurality of through wiring portions 3 and a part of the second main surface 22 of the dielectric substrate 2.

[0030] In a plan view from the thickness direction D1 of the dielectric substrate 2, each of the multiple second pad electrodes 7 has a circular shape. In a plan view from the thickness direction D1 of the dielectric substrate 2, each of the multiple second pad electrodes 7 is smaller than each of the first pad electrodes 4. In a plan view from the thickness direction D1 of the dielectric substrate 2, an outer edge 702 of each of the multiple second pad electrodes 7 includes an outer edge of the second via conductor 33 connected to the second pad electrode 7. In addition, in a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge 702 of each of the multiple second pad electrodes 7 is included within an outer edge 322 of the connection electrode 32 connected to the second pad electrode 7. In addition, in a plan view from the thickness direction D1 of the dielectric substrate 2, the outer edge 702 of each of the multiple second pad electrodes 7 is included within an outer edge 402 of the first pad electrode 4 connected to the second pad electrode 7. The multiple second pad electrodes 7 protrude from the second main surface 22 of the dielectric substrate 2. Each of the plurality of second pad electrodes 7 has a main surface 701 opposite to the dielectric substrate 2 .

[0031] The material of each of the second pad electrodes 7 includes, for example, copper. The material of each of the second pad electrodes 7 is not limited to copper, but may be, for example, a copper alloy, aluminum, or titanium.

[0032] The thickness of each of the second pad electrodes 7 is, for example, 5 μm, but is not limited to 5 μm. The thickness of each of the second pad electrodes 7 is the thickness of the portion in contact with the second main surface 22 of the dielectric substrate 2.

[0033] The protective layer 5 is laminated directly on the first main surface 21 of the dielectric substrate 2 and covers the first main surface 21 of the dielectric substrate 2. The protective layer 5 is a passivation layer. The protective layer 5 includes a first portion 501 that does not overlap the multiple pad electrodes 4, and multiple second portions 502 that are interposed between the first main surface 21 of the dielectric substrate 2 and the second portions 42 of each of the multiple pad electrodes 4.

[0034] The material of the protective layer 5 includes an organic material. More specifically, the material of the protective layer 5 includes, as a main component, for example, an imide resin (e.g., polyimide, bismaleimide, etc.) or a fluorine resin (e.g., polytetrafluoroethylene, etc.). From the viewpoint of improving the high-frequency characteristics of the interposer 1, the material of the protective layer 5 preferably has a low dielectric constant and a low dielectric loss tangent.

[0035] The thickness of the protective layer 5 is greater than the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the multiple first pad electrodes 4, but is thinner than the thickness of the first pad electrodes 4. The protective layer 5 covers a portion of the outer circumferential surface 421 of the second portion 42 of the first pad electrode 4, but does not reach the main surface 401 of the first pad electrode 4. In this embodiment, as an example, the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the multiple first pad electrodes 4 is 100 nm, and the thickness of the pad electrode 4 is 10 μm. In this case, the thickness of the protective layer 5 is preferably 100 nm or greater and less than 10 μm.

[0036] In this embodiment, the surface roughness of the main surface 51 of the protective layer 5 is smaller than the surface roughness of the first main surface 21 of the dielectric substrate 2. The surface roughness of the main surface 51 of the protective layer 5 is the surface roughness of the first portion 501 of the protective layer 5. In this disclosure, the "surface roughness" refers to the arithmetic mean roughness Ra. The arithmetic mean roughness Ra is defined, for example, in JIS B 0601-2001 (ISO 4287-1997). In this disclosure, the arithmetic mean roughness Ra is a value measured from a cross-sectional scanning electron microscope (SEM) image.

[0037] From the viewpoint of making the surface roughness of the main surface 51 of the protective layer 5 smaller than the surface roughness of the first main surface 21 of the dielectric substrate 2, the thickness of the protective layer 5 is more preferably 500 nm or more and less than 10 μm. Furthermore, from the viewpoint of preventing the protective layer 5 from reaching the main surfaces 401 of the plurality of first pad electrodes 4, the thickness of the protective layer 5 is more preferably 80% or less of the thickness of the first pad electrodes 4 (8 μm) or less.

[0038] The plurality of wiring portions 6 are embedded in the dielectric substrate 2. More specifically, the plurality of wiring portions 6 are embedded in the second dielectric layer 202, exposed from the first main surface 221 of the second dielectric layer 202, and covered with the first dielectric layer 201. The plurality of wiring portions 6 are connected to at least one of the plurality of connection electrodes 32. The thickness of each of the plurality of wiring portions 6 is the same as the thickness of each of the plurality of connection electrodes 32.

[0039] (3) Method for Manufacturing Interposer A method for manufacturing the interposer 1 according to the first embodiment will be described with reference to FIGS. 2A to 9B.

[0040] In the method for manufacturing the interposer 1, after preparing a laminate 10 in which a second dielectric layer 202 is disposed on a first carrier substrate 9 as shown in FIG. 2A, steps 1 to 15 are carried out in sequence.

[0041] The first carrier substrate 9 includes, for example, a metal substrate 91, a metal foil 92 (hereinafter also referred to as the first metal foil 92), a release layer 93, and a second metal foil 94, which are arranged in this order. In this embodiment, the metal substrate 91 is made of stainless steel, but may be made of a material other than stainless steel. In this embodiment, the first metal foil 92 is made of copper foil. The first metal foil 92 is made of copper, but may be made of a material other than copper. The second metal foil 94 is made of copper, but may be made of a material other than copper. The release layer 93 is made of an acrylic resin, but is not limited to an acrylic resin and may be made of a silicone resin. The second metal foil 94 is thinner than the first metal foil 92. The first carrier substrate 9 may include, for example, an organic substrate, a silicon substrate, or a glass substrate instead of the metal substrate 91. As the organic substrate, for example, an LCP (Liquid Crystal Polymer) substrate, a PET (Polyethylene terephthalate) substrate, a PTFE (Polytetrafluoroethylene) substrate, or the like can be used.

[0042] In the first step, as shown in FIG. 2B, a plurality of connection electrodes 32 and a plurality of wiring portions 6 are formed on the second dielectric layer 202 of the laminate 10.

[0043] 3A , in the second step, a first dielectric layer 201 is formed to cover the first main surface 221 of the second dielectric layer 202, the plurality of connection electrodes 32, and the plurality of wiring portions 6. In the second step, a solution containing an organic material for the first dielectric layer 201 is applied onto the laminate 10 using a coater (e.g., a spin coater) or a dispenser, and pre-baked to form the first dielectric layer 201. Note that in the second step, the first dielectric layer 201 may also be formed by laminating a resin film that will become the first dielectric layer 201 onto the laminate 10.

[0044] 3B , in the third step, a plurality of first via holes 213 are formed in the first dielectric layer 201 by laser processing, and a desmearing process is performed to remove resin residue generated by the laser processing, thereby forming an uneven shape on the first main surface 21 of the dielectric substrate 2. In the third step, the plurality of first via holes 213 are formed in regions in the dielectric substrate 2 where the plurality of first via conductors 31 are to be formed, respectively. The plurality of first via holes 213 correspond one-to-one to the plurality of first via conductors 31.

[0045] In the manufacturing method of the interposer 1 of this embodiment, multiple first via conductor portions 31 are formed by performing steps 4 to 6, and multiple first pad electrodes 4 are formed by performing steps 4 to 7.

[0046] 4A , in the fourth step, a seed layer 11 is formed by, for example, electroless plating, to cover the first main surface 21 of the dielectric substrate 2, the inner surfaces of the plurality of first via holes 213, and the exposed portions of the main surfaces 321 of the plurality of connection electrodes 32. The material of the seed layer 11 is the same as the material of the first portions 41 of each first pad electrode 4. The material of the seed layer 11 is, for example, copper, but is not limited to this and may be, for example, a copper alloy. The method of forming the seed layer 11 is not limited to electroless plating and may also be a sputtering method.

[0047] 4B , in the fifth step, a resist layer 13 having a predetermined pattern is formed on the seed layer 11. The predetermined pattern of the resist layer 13 is a pattern that exposes regions in the seed layer 11 where the plurality of first via conductors 31 and the plurality of first pad electrodes 4 are to be formed.

[0048] 5A , in the sixth step, a plurality of first via conductors 31 and a plurality of first pad electrodes 4 are formed. In the sixth step, the plurality of first via conductors 31 and a plurality of first pad electrodes 4 are formed by, for example, electrolytic plating, and then the resist layer 13 is removed. The material of each of the plurality of plating layers 12 grown on the seed layer 11 in the sixth step is the same as the material of the second portion 42 of the first pad electrode 4. The material of the plating layer 12 is, for example, copper, but is not limited to this and may be, for example, a copper alloy.

[0049] In the seventh step, as shown in Fig. 5B , a portion of the seed layer 11 is removed to expose the first main surface 21 of the dielectric substrate 2. In the seventh step, the seed layer 11 exposed in the state of Fig. 5A is removed by wet etching. In the seventh step, a portion of each of the plurality of first pad electrodes 4 that is formed by a part of the seed layer 11 is side-etched, so that a first portion 41 having a smaller outer diameter than the second portion 42 is formed in each of the plurality of first pad electrodes 4. Therefore, in the seventh step, a gap 14 is formed between the second portion 42 of each of the plurality of first pad electrodes 4 and the first main surface 21 of the dielectric substrate 2. In this embodiment, the material of the multiple plating layers 12 is the same as the material of the seed layer 11, but each plating layer 12 is formed by electrolytic plating, while the seed layer 11 is formed by electroless plating. Therefore, the film quality of each plating layer 12 is different from the film quality of the seed layer 11, and the etching rate of the plating layer 12 is slower than the etching rate of the seed layer 11 with respect to an etching solution that etches copper. As a result, the exposed portion of the seed layer 11 can be selectively etched in a maskless state (the state shown in Figure 5A).

[0050] 6A , the protective layer 5 is formed to cover the first main surface 21 of the dielectric substrate 2. In the eighth step, a solution containing the organic material of the protective layer 5 is applied by a coater (e.g., a spin coater) and baked to form the protective layer 5. From the viewpoint of forming the protective layer 5 so as to eliminate the gap 14 between the second portion 42 of the first pad electrode 4 and the first main surface 21 of the dielectric substrate 2, the viscosity of the solution containing the organic material of the protective layer 5 is preferably less than 50 mPa s.

[0051] 6B , a temporary adhesive layer 15 is formed to cover the plurality of first pad electrodes 4 and the protective layer 5. In the ninth step, the temporary adhesive layer 15 is formed by applying a varnish containing an organic material (e.g., acrylic resin) for the temporary adhesive layer 15 and drying it. The thickness of the temporary adhesive layer 15 is, for example, 20 μm. The thickness of the temporary adhesive layer 15 is the thickness of the portion that contacts the protective layer 5.

[0052] 7A , in the tenth step, a second carrier substrate 16 is bonded to the temporary adhesive layer 15. The second carrier substrate 16 includes, for example, a glass substrate 161 and a release layer 162 laminated on the glass substrate 161. In the tenth step, the release layer 162 of the second carrier substrate 16 is bonded to the temporary adhesive layer 15.

[0053] 7B , the first carrier substrate 9 is removed from the dielectric substrate 2. In the 11th step, the structure including the metal substrate 91, the first metal foil 92, and the release layer 93 of the first carrier substrate 9 is peeled off from the second metal foil 94, and then the second metal foil 94 is removed by etching.

[0054] 8A, in the twelfth step, a plurality of second via holes 223 are formed in the dielectric substrate 2. In the twelfth step, the plurality of second via holes 223 are formed in the region of the dielectric substrate 2 where the second via conductor portion 33 is to be formed.

[0055] In the thirteenth step, as shown in FIG. 8B, a plurality of second via conductors 33 and a plurality of second pad electrodes 7 are formed.

[0056] In a fourteenth step, as shown in FIG. 9A, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15 .

[0057] 9B , in the fifteenth step, the temporary adhesive layer 15 is mechanically peeled off to obtain the interposer 1. In the fifteenth step, instead of mechanically peeling off the temporary adhesive layer 15, the temporary adhesive layer 15 may be removed by dry etching.

[0058] In the method for manufacturing the interposer 1 according to the first embodiment, the interposer 1 is formed by performing the first to fifteenth steps.

[0059] (4) Advantages In the interposer 1 according to the first embodiment, the pad electrode 4 includes a first portion 41 that is in contact with the first main surface 21 of the dielectric substrate 2 and a second portion 42 that overlaps the first portion 41. In the pad electrode 4, the outer edge of the first portion 41 is located inside the outer edge of the second portion 42. In the interposer 1, a part of the protective layer 5 is interposed between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4.

[0060] The above configuration makes it possible to improve mounting reliability. More specifically, the above configuration makes it possible to improve impact resistance compared to a case where there is a gap 14 between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4, thereby improving mounting reliability to a circuit board (e.g., a printed wiring board) that has a land electrode to which the pad electrode 4 is connected.

[0061] Furthermore, in the interposer 1 according to the first embodiment, the thickness of the protective layer 5 is greater than the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4, and is thinner than the thickness of the pad electrode 4. The protective layer 5 covers a part of the outer peripheral surface 421 of the second portion 42 of the pad electrode 4, and does not reach the main surface 401 of the pad electrode 4.

[0062] According to the above configuration, it is possible to further improve the impact resistance and the mounting reliability.

[0063] In the interposer 1 according to the first embodiment, the material of the protective layer 5 is an organic material.

[0064] According to the above configuration, the dielectric constant and dielectric loss tangent of the protective layer 5 can be reduced compared to when the protective layer 5 is made of an inorganic material, thereby improving the high-frequency characteristics of the interposer 1.

[0065] Furthermore, in the interposer 1 according to the first embodiment, the first main surface 21 of the dielectric substrate 2 has an uneven shape over the entire area of ​​the first main surface 21 .

[0066] According to the above configuration, it is possible to improve the adhesion of the protective layer 5 to the first main surface 21 of the dielectric substrate 2 .

[0067] Furthermore, in the interposer 1 according to embodiment 1, the surface roughness of the main surface 51 of the protective layer 5 opposite the first main surface 21 of the dielectric substrate 2 is smaller than the surface roughness of the first main surface 21 of the dielectric substrate 2.

[0068] According to the above configuration, for example, when a manufacturing method for the interposer 1 is adopted that includes a step of attaching the second carrier substrate 16 to the protective layer 5 via a temporary adhesive layer 15, it becomes easier to remove the temporary adhesive layer 15 from the protective layer 5.

[0069] An interposer 1A according to a second embodiment will be described with reference to Fig. 10. Regarding the interposer 1A according to the second embodiment, the same components as those of the interposer 1 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals and the description thereof will be omitted.

[0070] (1) Configuration The interposer 1A of the second embodiment differs from the interposer 1 of the first embodiment in that each of the multiple through wiring portions 3 of the interposer 1 of the first embodiment is composed only of a first via conductor portion 31, and multiple connection electrodes 32 constitute multiple second pad electrodes 7A.

[0071] In the interposer 1A according to the second embodiment, the second pad electrodes 7A are connected to the first pad electrodes 4 in a one-to-one relationship.

[0072] (2) Method of Manufacturing Interposer With regard to the method of manufacturing the interposer 1A according to the second embodiment, the same steps as those in the method of manufacturing the interposer 1 according to the first embodiment will not be described as appropriate.

[0073] In the manufacturing method of the interposer 1A of embodiment 2, the structure shown in FIG. 7B is obtained by performing steps 1 to 11 of the manufacturing method of the interposer 1 of embodiment 1, and then the second dielectric layer 202 is subjected to CMP (Chemical Mechanical Polishing) to expose the multiple second pad electrodes 7A and the multiple wiring portions 6.

[0074] Thereafter, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15 in the same manner as in step 14 of the manufacturing method of the interposer 1 of embodiment 1, and then the temporary adhesive layer 15 is mechanically peeled off in the same manner as in step 15, thereby obtaining the interposer 1A.

[0075] (3) Advantages Like the interposer 1 according to the first embodiment, the interposer 1A according to the second embodiment can improve the mounting reliability.

[0076] Third Embodiment An interposer 1B according to a third embodiment will be described with reference to Fig. 11. Regarding the interposer 1B according to the third embodiment, the same components as those of the interposer 1 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals and the description thereof will be omitted.

[0077] (1) Configuration The interposer 1B according to the third embodiment differs from the interposer 1 according to the first embodiment in that it includes a protective layer 5B instead of the protective layer 5 of the interposer 1 according to the first embodiment.

[0078] Like the protective layer 5, the protective layer 5B covers the first main surface 21 of the dielectric substrate 2. In the interposer 1B, a portion of the protective layer 5B is interposed between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4.

[0079] In the interposer 1B, the protective layer 5B is located across the first main surface 21 of the dielectric substrate 2, the outer peripheral surface 421 of the second portion 42 of each of the plurality of first pad electrodes 4, and the main surface 401 of each of the plurality of first pad electrodes 4. The protective layer 5B is a solder resist layer, but also functions as a passivation layer. The protective layer 5B includes a first portion 511 that does not overlap the plurality of pad electrodes 4, and a plurality of second portions 512 that are interposed between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of pad electrodes 4. The protective layer 5B has a plurality of openings 53B that expose a portion of each of the main surfaces 401 of the plurality of first pad electrodes 4.

[0080] The opening width of the opening 53B in the protective layer 5B increases with increasing distance from the main surface 401 of the first pad electrode 4.

[0081] The surface roughness of the main surface 51B of the protective layer 5B opposite to the first main surface 21 of the dielectric substrate 2 is smaller than the surface roughness of the first main surface 21 of the dielectric substrate 2.

[0082] (2) Method for Manufacturing Interposer The method for manufacturing the interposer 1B according to the third embodiment is substantially the same as the method for manufacturing the interposer 1 according to the first embodiment, but differs from the method for manufacturing the interposer 1 according to the first embodiment in that a protective layer 5B is formed instead of the protective layer 5. With regard to the method for manufacturing the interposer 1B according to the third embodiment, the description of the same steps as those in the method for manufacturing the interposer 1 according to the first embodiment will be omitted as appropriate.

[0083] The method for manufacturing the interposer 1B differs from the method for manufacturing the interposer 1 in the eighth step among the first to fifteenth steps.

[0084] In the method for manufacturing the interposer 1B, after the structure shown in FIG. 5B is obtained by performing steps 1 to 7 in the method for manufacturing the interposer 1, a protective layer 5B is formed in step 8. In step 8, a plurality of openings 53B are formed in the protective layer 5B using photolithography. In step 8, a solution containing the organic material for the protective layer 5B is applied using a coater (e.g., a spin coater), and after pre-baking, a protective layer 5B having a plurality of openings 53B is formed using photolithography. A positive photosensitive resist material is used as the organic material for the protective layer 5B.

[0085] In the method for manufacturing the interposer 1B, after the eighth step, steps similar to the ninth to fifteenth steps in the method for manufacturing the interposer 1 are carried out, thereby obtaining the interposer 1B according to the third embodiment.

[0086] (3) Advantages Like the interposer 1 according to the first embodiment, the interposer 1B according to the third embodiment can improve the mounting reliability.

[0087] Fourth Embodiment An electronic component module 100 according to a fourth embodiment will be described with reference to Fig. 12. The electronic component module 100 according to the fourth embodiment includes the interposer 1 according to the first embodiment (see Fig. 1).

[0088] (1) Configuration The electronic component module 100 according to the fourth embodiment includes an interposer 1 , an IC chip 19 which is an electronic component, and a resin layer 20 .

[0089] The IC chip 19 is mounted on the interposer 1. More specifically, the IC chip 19 is flip-chip mounted on the interposer 1. The IC chip 19 has a plurality of external connection electrodes (not shown), which are connected to the plurality of second pad electrodes 7 of the interposer 1, respectively, via solder bumps 18.

[0090] The resin layer 20 is disposed on the second main surface 22 side of the dielectric substrate 2 of the interposer 1 so as to cover the IC chip 19. The resin layer 20 includes, for example, a resin (e.g., an epoxy resin). The resin layer 20 may further include a filler.

[0091] (2) Manufacturing method of electronic component module The manufacturing method of electronic component module 100 is substantially the same as the manufacturing method of interposer 1 of embodiment 1, but differs from the manufacturing method of interposer 1 of embodiment 1 in that it includes a component mounting process and a molding process between the 13th and 14th processes in the manufacturing method of interposer 1 of embodiment 1.

[0092] 8B by performing the first to thirteenth steps in the manufacturing method of the interposer 1 according to the first embodiment, in the component mounting step, an IC chip 19, which is an electronic component, is mounted on the interposer 1, as shown in Fig. 13A. Note that in this embodiment, prior to the component mounting step, solder bumps 18 are formed on each of the plurality of second pad electrodes 7 via a barrier layer 17, but it is not essential to form the barrier layer 17 and the solder bumps 18.

[0093] In the molding process, as shown in Fig. 13A, a resin layer 20 is formed on the second main surface 22 of the dielectric substrate 2 of the interposer 1 so as to cover the IC chip 19. In a fourteenth process, as shown in Fig. 13B, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15.

[0094] In a fifteenth step, the temporary adhesive layer 15 is removed to obtain the electronic component module 100 including the interposer 1 .

[0095] (3) Advantages The electronic component module 100 according to the fourth embodiment includes the interposer 1, which makes it possible to improve the mounting reliability.

[0096] (Other) In interposers 1, 1A, and 1B, the organic material that is the material of each of the first dielectric layer 201 and the second dielectric layer 202 is an insulator, and the first dielectric layer 201, the second dielectric layer 202, and the dielectric substrate 2 are, respectively, a first insulator layer, a second insulator layer, and an insulator substrate.

[0097] (Modifications) The above-described first to fourth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fourth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0098] For example, in the interposers 1, 1A, and 1B, the material of each of the first dielectric layer 201 and the second dielectric layer 202 is not limited to an organic material, and may be, for example, an inorganic material (e.g., ceramic, etc.). In the interposers 1, 1A, and 1B, when the material of each of the first dielectric layer 201 and the second dielectric layer 202 is an inorganic material, the inorganic material is an insulator, and the first dielectric layer 201, the second dielectric layer 202, and the dielectric substrate 2 are a first insulator layer, a second insulator layer, and an insulator substrate, respectively.

[0099] In the interposers 1, 1A, and 1B, the dielectric substrate 2 may have one or more dielectric layers in addition to the first dielectric layer 201 and the second dielectric layer 202.

[0100] Furthermore, in the interposers 1 and 1A, the material of the protective layer 5 is not limited to an organic material, but may be, for example, an inorganic material.

[0101] Furthermore, although the interposers 1, 1A, and 1B are provided with a plurality of through wiring portions 3 and a plurality of pad electrodes 4, the number of each of the through wiring portion 3 and the pad electrode 4 may be one.

[0102] (Aspects) The following aspects are disclosed in this specification.

[0103] An interposer (1; 1A; 1B) according to a first aspect includes a dielectric substrate (2), a through wiring portion (3), a pad electrode (4), and a protective layer (5; 5B). The dielectric substrate (2) has a first main surface (21) and a second main surface (22) opposite the first main surface (21). The through wiring portion (3) penetrates the dielectric substrate (2). The pad electrode (4) is located across the first main surface (21) of the dielectric substrate (2) and the through wiring portion (3). The pad electrode (4) is connected to the through wiring portion (3). The protective layer (5; 5B) is disposed on the first main surface (21) of the dielectric substrate (2). The pad electrode (4) includes a first portion (41) in contact with the first main surface (21) of the dielectric substrate (2) and a second portion (42) overlapping the first portion (41). In the pad electrode (4), the outer edge of the first portion (41) is located inside the outer edge of the second portion (42). A part of the protective layer (5; 5B) is interposed between the first main surface (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4).

[0104] According to this aspect, it is possible to improve the mounting reliability.

[0105] In the interposer (1; 1A) according to the second aspect, in the first aspect, the thickness of the protective layer (5) is greater than the distance between the first main surface (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4) and is thinner than the thickness of the pad electrode (4). The protective layer (5) covers a portion of the outer peripheral surface (421) of the second portion (42) of the pad electrode (4) and does not reach the main surface (401) of the pad electrode (4).

[0106] According to this aspect, it is possible to further improve the impact resistance and the mounting reliability.

[0107] In the interposer (1; 1A) according to the third aspect, in the first or second aspect, the material of the protective layer (5) is an organic material.

[0108] According to this aspect, it is possible to improve high frequency characteristics.

[0109] The interposer (1; 1A) according to a fourth aspect is based on any one of the first to third aspects. The first main surface (21) of the dielectric substrate (2) has an uneven shape over the entire area of ​​the first main surface (21).

[0110] According to this embodiment, it is possible to improve the adhesion of the protective layer (5) to the first main surface (21) of the dielectric substrate (2).

[0111] The interposer (1; 1A) according to the fifth aspect is based on the fourth aspect. The surface roughness of the main surface (51) of the protective layer (5) opposite to the first main surface (21) of the dielectric substrate (2) is smaller than the surface roughness of the first main surface (21) of the dielectric substrate (2).

[0112] According to this aspect, for example, when a manufacturing process is adopted in which a second carrier substrate (16) is attached to the protective layer (5) via a temporary adhesive layer (15), it becomes easier to remove the temporary adhesive layer (15) from the protective layer (5).

[0113] In the interposer (1B) according to the sixth aspect, in the first aspect, the protective layer (5B) is located across the first main surface (21) of the dielectric substrate (2), the outer peripheral surface (421) of the second portion (42) of the pad electrode (4), and the main surface (401) of the pad electrode (4). The protective layer (5B) has an opening (53B) that exposes a portion of the main surface (401) of the pad electrode (4).

[0114] According to this aspect, it is possible to further improve the impact resistance and the mounting reliability.

[0115] In the interposer (1B) according to the seventh aspect, in the sixth aspect, the opening width of the opening (53B) in the protective layer (5B) increases with increasing distance from the main surface (401) of the pad electrode (4).

[0116] According to this aspect, when a manufacturing process is adopted in which a second carrier substrate (16) is attached to the protective layer (5B) via a temporary adhesive layer (15), it becomes easier to remove the temporary adhesive layer (15) from the protective layer (5B).

[0117] In an interposer (1B) according to an eighth aspect, in the sixth or seventh aspect, the protective layer (5B) is a solder resist layer.

[0118] According to this aspect, it is possible to improve the positional accuracy during mounting.

[0119] In the interposer (1; 1A; 1B) according to the ninth aspect, in any one of the first to eighth aspects, the material of the dielectric substrate (2) includes an organic material.

[0120] According to this aspect, it is possible to improve high frequency characteristics.

[0121] An interposer (1; 1A; 1B) according to a tenth aspect is based on any one of the first to ninth aspects. In the pad electrode (4), the material of the first portion (41) contains Cu, and the material of the second portion (42) contains Cu.

[0122] REFERENCE SIGNS LIST 1, 1A, 1B interposer 2 dielectric substrate 21 first main surface 22 second main surface 3 through wiring portion 4 pad electrode (first pad electrode) 41 first portion 42 second portion 421 outer peripheral surface 401 main surface 5, 5B protective layer 51, 51B main surface 53B opening 6 wiring portion 7, 7A second pad electrode 19 IC chip 20 resin layer 100 electronic component module D1 thickness direction

Claims

1. An interposer comprising: a dielectric substrate having a first main surface and a second main surface opposite to the first main surface; a through wiring portion penetrating the dielectric substrate; a pad electrode located across the first main surface of the dielectric substrate and the through wiring portion and connected to the through wiring portion; and a protective layer located on the first main surface of the dielectric substrate, wherein the pad electrode includes a first portion in contact with the first main surface of the dielectric substrate and a second portion overlapping the first portion, and the outer edge of the first portion of the pad electrode is located inside the outer edge of the second portion, and a part of the protective layer is interposed between the first main surface of the dielectric substrate and the second portion of the pad electrode.

2. An interposer as described in claim 1, wherein the thickness of the protective layer is greater than the distance between the first main surface of the dielectric substrate and the second portion of the pad electrode and is thinner than the thickness of the pad electrode, and the protective layer covers a portion of the outer circumferential surface of the second portion of the pad electrode and does not extend to the main surface of the pad electrode.

3. The interposer according to claim 1 or 2, wherein the material of the protective layer is an organic material.

4. The interposer according to claim 1 or 2, wherein the first main surface of the dielectric substrate has an uneven shape over the entire area of ​​the first main surface.

5. The interposer according to claim 4, wherein the surface roughness of the main surface of the protective layer opposite to the first main surface of the dielectric substrate is smaller than the surface roughness of the first main surface of the dielectric substrate.

6. The interposer according to claim 1, wherein the protective layer is located across the first main surface of the dielectric substrate, the outer peripheral surface of the second portion of the pad electrode, and the main surface of the pad electrode, and the protective layer has an opening that exposes a portion of the main surface of the pad electrode.

7. The interposer according to claim 6, wherein the opening width of the opening in the protective layer increases with increasing distance from the main surface of the pad electrode.

8. The interposer according to claim 6 or 7, wherein the protective layer is a solder resist layer.

9. The interposer according to claim 1 or 2, wherein the material of the dielectric substrate includes an organic material.

10. An interposer according to claim 1 or 2, wherein in the pad electrode, the material of the first portion includes Cu, and the material of the second portion includes Cu.

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