Clock and data recovery circuitry for sampling a burst serial data signal

Abstract

Example embodiments describe a CDR, circuitry (400) for sampling a burst serial data signal (401) characterized by a data symbol period; the burst serial data signal containing at least a preamble and data portion (401b); the CDR circuitry is configurable in a first mode (403a) for detecting (440) a sampling position when receiving the preamble portion, and in a second mode (403b) for sampling (410) the data portion. The CDR comprises i) a sampling circuitry (410) to sample the signal by at least one sampling clock (404); ii) a sampling clock generator (450) to generate from a reference clock signal (405) with a configurable phase shift (408) one first and one second sampling clock (404a, 404b) for sampling the burst serial data signal by the sampling circuitry when in the respective first and second mode, and to generate the second sampling clock (404b) for sampling times per data symbol period, and to generate the first sampling clock (404a) such that the sampling circuitry samples different sampling positions within an equivalent data symbol period during data symbol periods by adjusting the sampling period of the at least one first sampling clock signal by a sampling offset,, during the sampling of the data symbol periods; and iii) an edge detection circuitry (440) configured to, in the first mode, determine a sampling position from the sampled predefined pattern, and configured to derive the configurable phase shift from the determined sampling position and the applied sampling offset.

Description

[0001] CLOCK AND DATA RECOVERY CIRCUITRY FOR SAMPLING A BURST SERIAL DATA SIGNAL Technical Field

[0001] Various example embodiments relate, amongst others, to a clock and datarecovery, CDR, circuitry for sampling a burst serial data signal. Background

[0002] In serial data communication, a serial data signal is transmitted over acommunication medium in the form of a series of data symbols at a certain symbolrate, also referred to as baud rate. The data symbols respectively represent one or more bits of data. At the receiving end, the data symbols are sampled at least onceper data symbol period. The sampled value is then converted back into the one ormore bits of data that is encoded by the value. Clock and data recovery relates to therecovery of timing information at the receiving end from such a received serial datasignal and the use of this timing information for identifying an optimal sampling positionwithin the data symbol period.

[0003] In a time-division multiplexing communication system, such as a passive opticalnetwork, or an optically switched network, the data is transmitted and received in bursts. Both the transmitting and receiving ends have a local reference clock.Achieving a successful reception with an acceptable Bit Error Rate, BER, requiressynchronization between these clocks. Furthermore, the phase of the receiving clock must align with the incoming data before it starts sampling the actual data within the burst stream. To synchronize the clock, it is imperative to closely match the frequency of the clock at the receiving end with that of the transmitting end. Additionally, the phase of the receiving clock should be aligned with the incoming data. To facilitate this alignment, a preamble may be incorporated at the beginning of the burst. The preamble comprises a predefined pattern with the same symbol rate as the data. This predefinedpattern may periodically repeat in the preamble, for example as a sequence ofalternating zeros and ones when a data symbol encodes a single bit of data.

[0004] As the preamble does not carry actual data, aligning the receiving clock phasewith the incoming data should be achieved as fast and accurately as possible. Byminimizing this so-called locking time, the preamble duration is minimized whichincreases the time the communication channel can be used to transmit actual data. One approach to realize this goal involves employing a large oversampling ratio duringpreamble sampling, such as 8 times oversampling, as disclosed in EP1061691A2. InEP1061691A2, it is disclosed to sample the preamble 8 times per unit interval, UI, i.e.per duration of one data symbol. The clock phase that is furthest away from a datatransition is then selected as the most optimal sampling position. However, whilereducing locking time, this oversampling requires a higher power consumption and acomplex hardware architecture. An alternative solution may be provided by searchingthe optimal sampling clock phase by dynamically changing the clock phase from acoarse step to a finer one to obtain the optimal sampling position. Although this solutionposes less hardware requirements, the locking time is constrained by the sequentialoperation during the detection process. Such a solution is for example disclosed in A.Rylyakov et al., "22.1 A 25Gb / s burst-mode receiver for rapidly reconfigurable optical networks," 2015 ISSCC. Summary

[0005] The scope of protection sought for various embodiments of the invention is setout by the independent claims.

[0006] The embodiments and features described in this specification that do not fallwithin the scope of the independent claims, if any, are to be interpreted as examples useful for understanding various embodiments of the invention.

[0007] Amongst others, it is an object of the present disclosure to provide a clock anddata recovery circuitry for sampling a burst serial data signal with a fast locking time.

[0008] This object is achieved, according to a first example aspect, by a clock and datarecovery, CDR, circuitry for sampling a burst serial data signal characterized by a datasymbol period. The burst serial data signal contains at least a preamble portion havinga predefined pattern that defines a sampling position within the data symbol period,and contains a data portion. The CDR circuitry is configurable in a first mode fordetecting the sampling position when receiving the preamble portion, and in a second mode for sampling the data portion at the detected sampling position when receiving the data portion. The CDR circuitry comprises a sampling circuitry configured to sample the burst serial data signal by at least one sampling clock signal. The CDRcircuitry further comprises a sampling clock generation circuitry configured to generatefrom a reference clock signal with a configurable phase shift at least one first and at least one second sampling clock signal for sampling the burst serial data signal by the sampling circuitry when in the respective first and second mode. The sampling clockgeneration circuitry is further configured to generate the at least one second samplingclock from the reference clock signal such that the sampling circuitry performs thesampling ^ times per data symbol period, and to generate the at least first samplingclock signal from the reference clock signal such that the sampling circuitry samples ^different sampling positions within an equivalent data symbol period during ^ datasymbol periods containing the predefined pattern by adjusting the sampling period ofthe at least one first sampling clock signal by a sampling offset, ^^^, during the samplingof the ^ data symbol periods. The CDR circuitry further comprises an edge detectioncircuitry configured to, in the first mode, determine the sampling position from the sampled predefined pattern, and configured to derive the configurable phase shift for the at least one second sampling clock signal during the second mode from the determined sampling position and the applied sampling offset.

[0009] The data portion of the burst serial data signal encodes data in the data portionas a series of consecutive data symbols at the symbol rate, sometimes also referredto as baud rate. The length of such a data symbol is referred to as the data symbolperiod or unit interval, ^^. To decode the data, the data signal is sampled by thesampling circuitry by at least one sampling clock signal. The term ‘at least one’ refersto the known principle that the sampling itself is not limited to performing the samplingby one single clock signal but may also be achieved by different sampling signals such as a pair of complementary clock signals and / or interleaved clock signals. Thesampling may then be done at each rising and / or falling edge of such a clock signalthereby obtaining a series of samples at the different sampling positions.

[0010] The sampling clock generation circuitry generates the at least one samplingclock signal for the sampling circuitry from a reference clock signal wherein the phaseof the reference clock signal is configurable, i.e. the reference clock signal has a configurable phase shift. Applying this phase shift to the reference clock signal will thusresult in a phase shift of the resulting at least one sampling clock signal. During thedifferent modes, the at least one sampling clock signal is slightly different as definedby the sampling offset, ^^^ but the operation of the sampling circuitry itself remainsunaltered. In both modes, the at least one sampling clock signal is still derived fromthe same reference clock signal and, hence, the timing relation or alignment betweenthem is predefined. In other words, the specific relative position between samplingpositions in the first mode and second mode is deterministic. Because of the samplingoffset ^^^, ^ different sampling positions within the ^^ will be sampled during ^subsequent data symbol periods until the sequence of ^ different sampling positionsis repeated. For a certain selected ^ and ^, the offset can be defined as a fraction ofthe sampling period, i.e. as ((^ × ^ ÷ ^) − ^) wherein ^ and ^ are coprimes, ^ isgreater than ^, and ^ is greater than ^. This allows determining the configurable phaseshift directly from the ^ different sampling positions. In other words, each positionwithin the sampled predefined pattern can be mapped onto a certain value of the configurable phase shift.

[0011] It is an advantageous that the CDR circuitry does not require a dedicatedoversampling circuitry for the edge detection, i.e. the same reference clock signal andsampling circuitry can be used without further alteration. Also, there is no need foradditional clocks or clock generators as the same sampling clock generation circuitryand sampling circuitry is used during the first and second mode. The edge detectionitself is also fast because determining a clock edge from the ^ samples does notrequire complex calculation. The resulting locking time is therefore fast and power efficient.

[0012] According to example embodiments, the predefined pattern occurs periodicallyin the preamble portion and the ^ data symbol periods contain at least twooccurrences of the predefined pattern.

[0013] When the pattern occurs periodically, a large number of sampling positionsmay be obtained because the pattern is repeated over the ^ data symbol periods. Asa result all the ^ sampling positions can be mapped onto a single occurrence of thepattern. Based on the length of the pattern, ^ and ^ may be selected from which thesampling offset tsp can be derived.

[0014] According to example embodiments, the sampling clock generation circuitry isfurther configured to generate the at least one first sampling clock signal with anincrementally increasing phase offset with respect to the at least one second samplingclock signal.

[0015] An incrementally increasing phase offset will result in an increased overallsampling frequency. As the sampling signal is still derived from the reference clock,the signals in the first and second mode will still have a predefined alignment allowing determining the configurable phase shift for the second mode by the edge detection circuitry.

[0016] According to a further embodiment, the sampling clock generation circuitry isfurther configured to generate at least one sampling clock signal from the referenceclock signal for performing the sampling by the ^ times per data symbol period, andto generate the at least one first sampling clock signal by incrementally increasing the configurable phase shift of the reference clock signal, and to generate the at least one second sampling clock signal by applying the configurable phase shift derived by the edge detection circuitry to the reference clock signal.

[0017] In other words, the increased overall sampling frequency is obtained bymanipulating the configurable phase shift itself. There is thus no need for further clock manipulation circuitry.

[0018] According to example embodiments, the sampling circuitry comprises aplurality of ^ sampling instances operated in an interleaved manner and samplingthe serial burst signal by ^ respective sampling signals (671-674). The samplingclock generation circuitry is further configured to generate, in the second mode, the^ sampling signals with a 360 ÷ ^ phase difference and, in the first mode, with adifferent phase difference.

[0019] In other words, in the second mode, there is an equal phase difference betweenthe M sampling signals resulting in an even sampling of the data signal. In the firstmode there will be an oversampling in sets of M consecutive samples but with a gapbetween each of these sets. The M consecutive samples may then be used to samplethe predefined pattern in the preamble and, by the edge detection circuitry, to determine the sampling position. It is an advantage that there is no increase in the sampling rate of each of the sampling instances. Instead, an oversampling of the predefined pattern is achieved by concentrating the sampling positions of the differentsampling instances within the overall sampling period of the M sampling instances.

[0020] The M respective sampling signals may be ^ ^ pairs of complementaryclock signals having, in the second mode, a 50% duty cycle and a 360 ÷ ^ phasespacing, and having, in the first mode, a duty cycle different from 50% and a different phase spacing between the different pairs.

[0021] When having pairs of complementary signals, a duty cycle of X% for the ^ ÷ ^first signals of the respective pairs will result in a duty cycle of 100-X% for the other^ ÷ ^ second signal of the respective pairs. When combining this change in duty cyclewith a smaller phase spacing between the different pairs, an even concentration of the^ samples within the overall sampling period of the ^ sampling instances can beobtained.

[0022] According to further example embodiments, the sampling clock generationcircuitry comprises i) a phase shifting circuitry configured to apply the configurablephase shift to the reference clock; ii) a clock generation circuitry configured to furthershift the phase of the reference clock by 360 ÷ ^ increments thereby obtaining the Msampling signals with a 50% duty cycle and 360 ÷ ^ phase spacing; iii) a phasecorrecting circuitry comprising at least one injection locking ring oscillator having ^ ÷^ delay cell circuits connected in series with a single edge feedback delay providing aconfigurable feedback delay for the rising and falling edge of the ^ ÷ ^ pairs ofcomplementary clock signals. In the first mode, a different feedback delay is thenprovided for the rising and falling edge thereby obtaining the duty cycle smaller than 50% and the smaller phase spacing.

[0023] According to further example embodiments, the sampling circuitry comprises^ = ^ sampling instances.Brief Description of the Drawings

[0024] Some example embodiments will now be described with reference to theaccompanying drawings.

[0025] Fig. 1 shows an example embodiment of a system comprising a transmitter andreceiver for communicating burst serial communication signals;

[0026] Fig. 2 shows signals occurring in the system of Fig. 1;

[0027] Fig. 3 shows an example burst serial communication signal having a preambleportion and a data portion;

[0028] Fig. 4A shows a CDR circuitry according to example embodiments;

[0029] Fig. 4B shows the CDR circuitry of Fig. 4A when operating according to a firstmode of operation;

[0030] Fig. 4C shows the CDR circuitry of Fig. 4A when operating according to asecond mode of operation;

[0031] Fig. 5A illustrates the sampling of a preamble portion of a burst serialcommunication signal according to example embodiments;

[0032] Fig. 5B illustrates a plot of sampling points obtained from the sampling asillustrated in Fig.5A;

[0033] Fig.6 illustrates sampling of a preamble portion and data portion of a burst serialcommunication signal according to example embodiments;

[0034] Fig. 7 shows a CDR circuitry according to an example embodiment;

[0035] Fig. 8 shows a sampling clock generation circuitry according to an exampleembodiment;

[0036] Fig. 9 illustrates an output phase corrector circuitry according to an exampleembodiment;

[0037] Fig. 10 illustrates an injection locking ring oscillator according to an exampleembodiment;

[0038] Fig. 11 illustrates a delay cell of the injection locking ring oscillator as shown inFig.10;

[0039] Fig. 12 shows a lookup table for determining a phase offset from a sampledpreamble portion of a burst serial communication signal

[0040] Fig. 13 shows a testing set-up for determining a performance of a CDR circuitryaccording to example embodiments;

[0041] Fig. 14 shows testing results illustrating a performance of a CDR circuitryaccording to the prior art;

[0042] Fig. 15 shows testing results illustrating a performance of a CDR circuitryaccording to example embodiments compared to a performance of a CDR circuitryaccording to example embodiments with an edge position detector disabled; and

[0043] Fig. 16 shows testing results illustrating a performance of a CDR circuitryaccording to example embodiments compared to a performance of a CDR circuitry according to example embodiments with an edge position detector disabled.Detailed Description of Embodiment(s)

[0044] The present disclosure relates to clock and data recovery, CDR, circuitry forsampling a burst serial data signal. Fig.1 illustrates an example communication system100 as known in the art. Fig. 2 illustrates different communication signals 114, 116,121, 122, 123 that occur throughout communication system 100. Communicationsystem 100 comprises a transmitter 120 and receiver 110. Transmitter 120 isconfigured to generate a serial data signal 123 and transmit it onto a communicationmedium 130 to the receiver 110. Transmitter 120 comprises a modulation circuitry 124that receives a binary signal 121 and modulates the binary signal onto a series of data symbols at a certain symbol rate. The symbol rate and symbol period is defined by a data clock signal 122 from a clock generator circuitry 125. The communication medium 130 may be an optical fibre wherein the transmitter transmits light pulses at different light intensities. The communication medium may also be an electrical conductor wherein the transmitter generates electrical pulses at different voltages or currents.

[0045] Fig. 2 shows an example of binary signal 121 represented by a series of zeroand one bit values. Modulation circuitry 124 modulates every bit onto a data symbol.In this case a zero bit is represented by a low value 216 of the data signal 123 and aone is represented by a high value of the data signal 123. Low and high may take the form of voltages or light intensities that are transmitted onto the communicationmedium 130. Modulation circuitry 124 generates a data symbol during every period ofthe data clock signal 122. The duration of a data symbol, the data symbol period, isalso referred to as a unit interval, ^^. For example, transmitter 120 may change and hold the next bit value of the binary input signal 121 during every rising edge of data clock signal 122. Due to non-idealities, the data clock signal may suffer from jittershowing as phase shifts in the data clock signal and in the generated burst serial datasignal 123. The data clock signal may also suffer from drifting shown as a frequency change in the data clock signal and a change in symbol frequency in the serial data signal 123.

[0046] Transmitter 120 transmits the data signals in bursts onto communicationmedium 130, i.e. the data signals are limited in time and have a beginning and end. This allows time-division multiplexing wherein the communication medium 130 is shared with other transmitters and / or receivers, each transmitting their data signal in different time slots.

[0047] In communication system 100, a receiver 110 can receive data signals 123.Receiver 110 may comprise circuitry 111 to compensate the received data signal 123 for unwanted distortion from the communication medium 130, e.g. interference between different data symbols, also referred to as inter-symbolic interference or,shortly, ISI. Such compensation is also referred to as equalization and the circuitry 111as an equalizer. Receiver 110 also comprises a sampling circuitry 113 that samplesthe received signal 112 according to a sampling clock signal 116. The sampling clocksignal 116 is generated by a clock recovery circuitry 115 that synchronizes an internallygenerated reference clock signal 114 to the received signal 112, and thus to the dataclock signal 122 of the transmitter. If the frequency of the reference clock signal 114closely matches the frequency of the data clock signal 122, the clock recovery may generate the sampling clock signal by adjusting the phase shift of the reference clock signal 114.

[0048] A burst serial data signal 123 as used in the present disclosure comprises atleast a preamble or preamble portion 213 and a data portion 215. The preamble portioncontains a predefined pattern 214 that defines the optimal sampling position within adata symbol period, i.e. within a ^^. In the example of figure 2, the preamble portion213 contains an alternating sequence 214 of zeroes and ones. The predefined pattern214 is a single alteration between a zero and one and spans over two data symbolperiods 216, The predefined pattern is thus two ^^. The clock recovery circuitry 115may then adjust the phase of the reference clock signal 114 until the rising edges ofthe sampling clock signal 116 align with the rising and falling edges of the preamblesignal 213. During this synchronization, the phase error 217 between the samplingclock signal 116 and the unknown data clock signal is minimized. At the end of thepreamble period 213, the sampling clock signal should be synchronized such that itallow correct sampling of the received signal in sampling circuitry 113 resulting output bit stream 117.

[0049] Fig. 3 shows an example of a burst serial data signal 331 as known in the art.Burst signal 331 may be transmitted by a transmitter 120 as signal 123 and receivedby receiver 110. Burst signal 331 that is received by a receiver may be fed into a clockand data recovery circuits according to example embodiments of the presentdisclosure. When a signal 331 is transmitted the communication channel is idle 311 as represented by the sequence of zeros 301. The signal starts with an initializationportion 312 containing a sequence of ones 302. This initialization portion 312 may beused by a receiver to detect the start of an incoming burst signal. During initializationportion 312, a receiver may activate sub circuitries for the receival of data signal 331,e.g. turn them from a low power or sleeping mode into an active or operational mode. The signal 331 then continues with the preamble portion 313, in this case as a sequence of alternating ones and zeros. This preamble portion may be used by the receiver to synchronize its sampling clock with the received signal 331. After the preamble portion 313, the signal may continue with a silent portion 314, e.g. a sequence of trailing ones or zeroes 304. This portion 314 may signal the end of the preamble and start of the coming data portion 315. The data portion 305 contains the actual payload data of the burst signal, i.e. the binary sequency the receiver has to demodulate from the signal by sampling its values by the generated sampling clock. At the end of the signal 331, the transmitter goes back into an idle state 316 as represented by the sequence of zeros 306.

[0050] Fig. 4A illustrates a clock and data recovery circuitry, CDR, 400 according to anexample embodiment. CDR 400 comprises a sampling clock generator circuitry 450,shortly sampling clock generator, that generates a sampling clock signal 404 from areference clock 405 according to a configurable phase shift 408. CDR 400 alsocomprises a sampling circuitry 410 that samples a received burst serial data signal 401 by the sampling clock 404. To this end, sampling circuitry 410 performs the samefunction as sampling circuitry 113, and clock generator circuitry performs the samefunction as clock recovery circuitry 115. CDR 400 is configured to receive data signalswith at least a preamble portion and a data portion, e.g. signals as described with reference to Fig.1, 2, and 3.

[0051] CDR 400 further comprises a mode control circuitry 420 that can configure theCDR 400 in at least two different modes 403, a first mode and a second mode. Fig. 4Billustrates CDR 400 when it is configured by mode control circuitry 420 into the firstmode 403a. Fig. 4C shows CDR 400 when it is configured by mode control circuitry 420 into the second mode 403b. Mode control circuitry 420 puts the CDR into firstmode 403a during receival of the preamble portion 401a of the signal 401. Modecontrol circuitry 420 puts the CDR into second mode 403b during receival of the data portion 401b of the signal 401. Mode control circuitry 420 may be configured in the first mode when waiting for arrival of a data signal 401, upon detection of an incoming data signal 401, during the initialization portion 312 of the incoming data signal 401, or at the beginning of the preamble portion 313. Mode control circuitry 420 may be configured into the second mode at the end of the preamble portion, during a silent portion 314 between the preamble portion and data portion, at the beginning of thedata portion, or during the preamble portion when the synchronization is complete. Inthis disclosure, the first mode is also referred to as the preamble mode, and the second is also referred to as the data mode.

[0052] The received signal 401 is characterized by a data symbol period or ^^. Theinverse of the data symbol period defines the symbol rate or baud rate of the datasignal 401. The preamble portion of the signal contains a predefined pattern thatdefines the ideal sampling position within the data symbol period as also describedwith reference to Fig. 1, 2, and 3. As will be described in further detail below, duringthe first mode, CDR circuitry 400 detects this sampling position in the preamble portion401a, and, during the second mode, CDR circuitry samples the data portion 401b atthis sampling position.

[0053] In order to detect the sample position and perform the subsequent sampling,CDR 400 contains a sampling clock generator 450 that generates at least one samplingclock signal 404 for the sampling circuitry 410. Sampling circuitry 410 operates the same in both modes, i.e. no reconfiguration is needed between the modes. Samplingcircuitry 410 samples a received data signal 401 according to at least one samplingclock signal 404. The at least one clock signal 404 defines when the sampling circuitry410 samples the signal 401. As a result, sampling circuitry 410 generates a series ofconsecutive samples 402 according to the at least one sampling clock signal 404. Theterm ‘at least one’ refers to different possible embodiments of a sampling circuitry 410as known in the art wherein the sampling circuitry may use one or more sampling clocksignals. When having more than one sampling clock signal 404, the different samplingclocks are interleaved, i.e. each sampling clock triggers the sampling circuitry at adifferent time, i.e. in an interleaved manner. Sampling circuitry 410 may on its turn alsobe interleaved by providing different sampling instances each operating according toone of the respective interleaved sampling clocks. As a result, each sampling instanceproduces a new output sample one after the other. In general, the least one samplingclock signal 404 may be defined as ^ sampling clock signals wherein ^ is a naturalnumber equal to or greater than one, i.e. ^ ≥ ^.

[0054] Sampling clock generator 450 is configured to generate the at least one clocksignal 404 from a reference clock signal 405 with a configurable phase shift 408. Inother words, the at least one sampling clock 404 is directly derived from the reference clock 405. Apart from the configurable phase shift 408, sampling clock generator 450 may perform further operations on the reference clock signal such as for example dividing the reference clock signal, phase shifting the reference clock, shifting the rising and / or falling edges of the reference clock signal, and inverting the reference clock signal. When the configurable phase shift is constant, the relation between thereference clock 405 and at least one sampling clock 404 is fixed. The configurablephase shift 408 allows changing the phase of the reference clock and, as aconsequence, the phase of the generated at least one sampling clock signal 404. The reference clock 405 is selected such that the sampling circuitry 410 samples thereceived data signal 401 at an overall sampling rate of ^ times per data symbol periodwherein ^ is a natural number equal to or greater than one, i.e. ^ ≥ ^. By adjustingthe configurable phase shift 408, the ^ sampling positions within a data symbol periodcan be adjusted, i.e. shifted.

[0055] CDR 400 contains an edge position detector circuitry 440 that is operable duringthe first mode 403a. Edge position detector circuitry 440 is activated by the mode control circuitry 420 during the first mode by control signal 403a. During the first mode, edge position detector circuitry 440 receives the samples from the sampling circuitry 410 during reception of the preamble portion 401a. From these samples, edge detection circuitry derives the sampling position as defined by the preamble’s predefined pattern. This sampling position is then converted into a phase shift for thesampling clock generator circuitry 450 during the second mode, represented as phaseshift 407b in Fig. 4C. Phase shift 407b is thus a fixed phase that is determined by edgeposition detector circuitry 440 during the first mode and applied during the secondmode. In order to determine the sampling position within the preamble pattern, edgeposition detector requires more samples of the predefined pattern than the ^ positionswithin the data symbol period. This is done by producing a different at least one sampling clock signal during the first mode, further referred to as the at least one first sampling clock signal 404a. During the second mode, the at least one sampling clock404b defines the ^ sampling clock positions within the data symbol period asdiscussed above. The at least one sampling clock during the second mode is further referred to as the at least one second sampling clock signal 404b.

[0056] During the first mode, CDR 400 is configured to generate the sampling clock404a such that it samples ^ equivalent sampling positions within ^ data symbol periodswherein ^ is a natural number greater than ^, ^ is a natural number greater than 1,and wherein ^ and ^ are coprime. In other words, over ^ data symbol periods, ^different locations within a data symbol period are sampled. It should be noted that thisdoes not imply that the overall sampling rate is increased from ^ times per ^^ to ^times per ^^. As will be described with reference to the below embodiments, these ^ equivalent sampling positions may be obtained by adjusting the sampling period of the at least one first sampling clock signal by a sampling offset, ^^^, during the sampling ofthe ^ data symbol periods. For a certain selected ^ and ^, the offset can be obtainedas a fraction of the sampling period, i.e. as the fraction ((^ × ^ ÷ ^) − ^) of thesampling period.

[0057] According to further example embodiments, CDR circuitry 400 further comprisesa phase control circuitry 430. Circuitry 430 is operable during the second mode 403band activated by mode control circuitry 420. Phase control circuitry determines fromthe sampled data portion 402b additional phase errors between the reference clock405 and data signal 401b. Such phase error may be caused by clock jitter in thereference clock of the transmitter, by frequency drift in the reference clock of thetransmitter and / or receiver, or by a mismatch between the frequency of the referenceclock and in the transmitter and receiver. When detecting the phase error this error may be corrected by additionally shifting the reference clock 405 by an additional phase error signal 406b. Phase error signal 406b is thus in addition to the phase shift407b as determined by edge position detector 440 during the first mode. As such, during the second mode, the configurable phase shift 408b is the sum of the phase error signal 406b and the fixed phase shit 407b.

[0058] Fig. 5A and Fig. 5B illustrate the operation of CDR circuitry 400 according to afurther example embodiment. Fig. 5A shows the preamble 501a of a received datasignal 401. The preamble contains zero to one alterations. The predefined pattern isthen a single zero and one as shown by accolade 509. The predefined pattern is thustwo symbol periods or two ^^ long. Fig. 5A shows the preamble for six symbol periodsresulting in three subsequent iterations of the predefined pattern. Fig. 5A further showsthe reference clock 405 of the CDR circuitry 400 as the sequence of corresponding sampling positions 505 as defined by the reference clock. Sampling clock generator 450 generates from this reference clock one sampling clock signal 404. Fig.5A shows this sampling clock signal during the first mode as first mode sampling signal 505a and second mode sampling signal 505b. Signals 505, 505a, and 505b are not shown asphysical signals but as the corresponding sampling positions. Reference clock 505shows the sampling positions during both the first and second mode when no configurable phase shift 408 is applied. The frequency of the reference clock isselected to obtain 2 samples per symbol period, i.e. ^ = ^, thereby defining a samplingperiod of ^^ ÷ ^ = ^^⁄ ^ = ^^⁄ ^ .

[0059] During the first mode, the configurable phase shift 408a of the reference clock405 is increased for every sampling period such that the overall sampling period ^^⁄ ^is extended by the sampling offset ^^^. The offset is selected such that ^ differentsampling positions are sampled within an equivalent unit interval ^^. The equivalent^^ is thereby defined as the superposition of the ^ subsequent unit intervals. Becauseof the extended sampling period, during each of these ^ subsequent unit intervals,sampling will occur at different positions within the unit interval. After the ^ subsequentunit intervals, the sampling circuitry will have sampled each of the ^ different samplingpositions at least one time. In order to obtain these ^ different sampling positions withinthe maximum of ^ subsequent unit intervals, the increment ^^^ is selected such thatthe sampling is aligned over the ^ subsequent unit intervals. This is achieved when thefollowing equation is fulfilled: ^× ^^ = ^ × (^^^ ^ + ^^^) (Eq. 1)wherein ^ and ^ are natural numbers; ^ is the default number of samples per unitinterval; ^^ is the length of the unit interval, i.e. the symbol period length; ^^^ is thesampling offset, i.e. a sampling increment, expressed in the same unit as the unitinterval; ^ is greater than ^; and ^ and ^ are coprime numbers. In this case, ^^^ canbe expressed as a fraction ^ of the sampling period by reordering Eq. 1: wherein ^=^×^ ^− ^ (Eq. 3)

[0060] The numbers ^ and ^ may be selected such that ^^^ falls within an acceptablerange. ^^^may be negative such that the sampling period is smaller during the first mode than during the second mode. ^^^may also be positive such that the sampling period is larger during the first mode than during the second mode. Preferably, ^^^is positive such that the sampling circuitry can be designed according to its target sampling frequency during the second mode, i.e. during data sampling. Preferably ^and ^ are selected such that the absolute value of the fraction ^ is smaller than 0.5,more preferably smaller than 0.4, even more preferably smaller than 0.25.

[0061] Fig. 5A depicts an illustrative example where ^ = ^^, ^ = ^, ^ = ^, and thepreamble has a predefined pattern of two unit intervals. In other words, Within anequivalent ^^, the 11 different samples at different sampling positions are obtainedover a total of 6 consecutive unit intervals. By applying Eq. 2 and 3, ^^^=^^^^ ^ ^ × ^^^ ^^ ^ or thus ^ = is obtained, i.e. the sampling period in the first modeis increased by 1 / 11thof the sampling period in the second mode by applying anincreasing phase shift of ^^^^ ^ ^ × ^^^ ^^ ^ for every sampling period. This is alsoshown in Fig. 5A as phase offset ^^^ 517. Fig. 5B shows a plot 540 where the sampledpredefined pattern is reconstructed from the obtained {^^, ^^, … , different samplingpositions {^^, ^^, … , ^^^} starting with ^^ for which the applied phase offset 408a is zero.Within the predefined pattern, the optimal sampling position is defined by the crossing 507 of the preamble signal. From plot 5B it can be determined that this position lays between the sampling points S7and S11. As all the equivalent sampling positions are defined with reference to the initial sampling point ^^for which the phase offset 408ais zero, the phase offset ϕ 544 can be derived, i.e. the offset that is to be applied tothe reference clock during the second mode such that the sampling during the second mode is performed in the optimal sampling positions, i.e. such that the CDR circuitry is synchronized with the received signal 401.

[0062] When ^ and ^ are determined for a certain preamble pattern, edge positiondetector 440 may be configured to apply the increasing phase shift until the ^ samplesare obtained. From these ^ samples, the sampling position is then derived and thecorresponding phase shift 407b is applied during the second mode. Phase shift 407b may for example be determined by edge position detector 440 from a lookup-table. Each possible position of the transition 507 within the sampled pattern then corresponds with a predetermined phase offset 544 that is to be added as phase shift 407b during the second mode.

[0063] Fig. 6 illustrate the operation of CDR circuitry 400 according to a anotherexample embodiment. Fig. 6 shows a representation of different signals 601, 605, 671-678 as a function of time. Signal 601 represents incoming data signal 401 havingpreamble portion 601a and data portion 601b. The preamble has consecutivepredefined patterns 609 that are the same as the predetermined patter 509 as shown in Fig.5A, i.e. an alternating one and zero value with a duration of two unit intervals.

[0064] Fig. 6 further illustrates input reference clock signal 405 after application of theconfigurable phase shift 408 as the phase shifted reference clock 605. During the firstor preamble mode, a constant phase shift 408a is applied, e.g. a zero phase shift.During the second or data mode, the phase shift is increased by the phase shift 644 that is determined by the edge detector 440. The at least one sampling signal 404contains a plurality of eight clock signals 671-678 that define a series of samplingpositions 605c that are sampled by sampling circuitry 410. These eight samplingsignals together are further also referred to as sampling signals 605a during the first mode of operation and as sampling signals 605b during the second mode of operation.Sampling circuitry 410 comprises a plurality of eight sampling instances that areoperated in an interleaved manner, i.e. the sampling instances sample the incomingsignal 601 on a rising edge of the respective clock signals 671-678. During the secondmode 403b, the eight sampling signals are derived from the phase shifted referenceclock signal 605 such that the signals have a 360 / 8 degrees, i.e. 45 degrees, phasedifference. As a result, during the second mode, an equal sampling period of ^^⁄ ^ isobtained. In the example of Fig. 6, ^ = ^, thus the sampling period during the secondmode is ^^⁄ ^ , the same as in the example of Fig. 5A and 5B. The reference clock canbe shifted by the configurable phase shift 408. As such, during the second mode ofoperation, the optimal sampling position as defined by the zero to one transition can be obtained by applying the phase shift 644. This phase shift is determined by the edge detection circuitry during the first mode of operation.

[0065] According to an example embodiment and as shown in Fig.6, the eight samplingsignals are derived from the phase shifted refence clock signal 605, and thus from thereference clock signal 405, as four pairs 681-684 of complementary clock signals. Tothis end, clock generation circuitry may first generate four clock signals with a 360 / 4degrees, i.e. 90 degrees, phase difference represented as clock signals ^^^^, ^^^^,^^^^, and ^^^^. These clock signals are then inverted by the clock generationcircuitry to obtain the other complementary clock signals ^ ^^^^^^^^^^, ^ ^^^^^^^^^^, ^ ^^^^^^^^^^, and^^^^^^^^^^^.

[0066] During the first mode, sampling clock generator 450 generates the clock signalsfrom the reference clock with phase shifts that are less than 45 degrees apart. As aresult, the sampling instances 605 are moved closer together, thereby obtaining eight subsequent samples from the respective clocks that are spaced closer together. Further, as a result, a larger phase shift will be observed between the last interleaved sample, i.e. from clock 678, and the first interleaved sample, i.e. from clock 671.Because of the smaller phase shift, an oversampling of the first predefined pattern 609of the preamble is achieved, i.e. there are five samples 6011 to 6015 obtained over the first two UI 609 instead of the four samples during the second mode as shown in 601b.These five samples are again used by edge position detector 440 during the first modeto determine the ideal sampling position 607. This position 607 then defines the phase shift 644 that is applied as phase shift 407b to the reference clock signal 405 during the second mode.

[0067] The offset ^^^ 617 in the sampling period between the subsequent clock signals671-678 may again be selected according to Eq. 2 above. The number of differentsampling positions will be limited to the interleaving. In general, if there are ^ differentsampling clocks that make up the at least one sampling signal 404, then the numberof ^ different sampling positions can be at most M, i.e. ^ ≤ ^. Also the number of unitintervals over which the ^ positions are obtained is limited by the number of unitintervals that are sampled during one sampling clock period. Returning to the exampleof Fig. 6, the number of sampling clocks is eight, i.e. ^ = ^; the number of equivalentsampling positions is five, i.e. ^ = ^, which is smaller than 8; the number of unitintervals to obtain the 5 samples is two, i.e. ^ = ^, which is smaller than 4; and theCDR is configured to sample twice per unit interval, i.e. ^ = ^. From this, the fraction^ can be derived as ^ = i.e. the phase differencebetween sampling clocks is decreased by one fifth.

[0068] According to further example embodiments, the decreased phase differencebetween the clock signals 671-678 may be obtained by generating the positive clocksignals 671, 673, 675, and 677 with the decreased phase difference and with asmaller duty cycle. The decreased duty cycle is then selected such that the complementary clock signals 672, 674, 676, and 678 follow the positive clock signalswith this same phase difference.

[0069] Fig. 7 shows a CDR circuitry 700 according to an example embodiment. CDRcircuitry 700 may comprise all components of CDR circuitry 400. These components are indicated by the same reference numbers. CDR circuitry 700 further comprises additional frequency adjustment components. CDR 700 comprises a clock generationcircuitry 780 that generates the reference clock 405 with adjustable frequency that isdetermined by a frequency control circuitry 770. This frequency control circuitry 770 may adjust the frequency according to a phase error 406 that is detected between data signal 401 and the sampling clock 404. If the phase error is continuously decreasing or increasing, then there is a frequency mismatch between the data signal 401 and the reference clock 405. This mismatch is detected by frequency control 770 and adjusted by changing the frequency 772 of the reference clock generator 780. The CDR circuitry 700 may also be part of a group of CDR circuitries that sample data signals that were generated at a transmitting end by the same reference clock. In this case, each of the phase errors 706 detected by these CDRs may be added together to obtain an average phase error 771 to adjust the frequency of the reference clock 780.

[0070] Fig. 8 illustrates an example embodiment 850 of sampling clock generationcircuitry 450 that is configured to generate the at least one sampling clock signal 404as eight interleaved sampling clocks from the reference clock 405, i.e. ^ = ^. Circuitry450 may be used for generating the clock signals 671 to 678 according to the exampleembodiment as depicted in Fig.6. Circuitry 850 comprises a phase shifting circuitry860 that applies the configurable phase shift 408 to the reference clock signal 405 asto obtain a phase shifted reference clock signal 861. This signal 861 is represented inFig.6 as the reference signal 605. By applying the phase shift 644 to the referenceclock with a fast settling, the edge of the incoming data signal 601 will be aligned withthe sampling clock in the second mode nearly immediately. The phase shiftedreference clock signal 861 is then supplied to an initial phase generator circuitry 870that is configured to generate eight phase shifted clock signals 871. These eight signalsare shifted with respect to each other by a fixed phase shift, i.e. by the same phase shift during the first and second mode of operation. The initial phase generator may for example comprise a delay locked loop circuitry for producing these signals 871.Signals 871 are then supplied to an output phase corrector circuitry 880 that producesthe actual sampling clocks 404 during the first and second mode 403. This outputphase corrector is configured with a configurable duty-cycle and phase spacing in order to obtain the sampling clock signals 671-678 during both modes of operation.

[0071] Figs. 13-16 illustrate testing of a CDR circuitry according to exampleembodiments.

[0072] Fig. 13 shows a testing set-up 1300 for testing a CDR circuitry according toexample embodiments. In Fig.13, a device under test, DUT, 1320 is shown. The DUT1320 is, for example, a CDR circuitry 400 comprising a sampling clock generator 850,where N=8, M=8, K=2 and S=3. During an example test, the DUT 1320 is providedwith inputs 1301, 1302. The inputs 1301, 1302 are generated by an arbitrary waveformgenerator, AWG, 1310. Input 1301 is a burst serial data signal 1301 to be sampled bythe DUT 1320. Input 1302 is a reference clock 1320, which may for example bereference clock 405, based upon which the DUT 1320 samples the data signal 1301.DUT 1320 is further connected to an oscilloscope 1330 to observe signals 1321, 1322generated by the DUT 1320. Signal 1321 is a sampled data signal 1321 and signal1322 is a sampling clock 1322 recovered by DUT 1320. Further, the AWG 1310 alsoprovides a start signal 1303 to the oscilloscope 1330 to initiate and / or terminate ameasurement. The oscilloscope 1330 is, for example, configured to perform ameasurement for a duration during which start signal 1303 has a value of ‘1’. Theoscilloscope 1330 may be configured to stop performing a measurement whenever thestart signal 1303 has a value of ‘0’. The set-up 1300 may be assumed to comprise afixed loop bandwidth.

[0073] Fig. 14 shows testing results obtained by performing a measurement using theset-up illustrated in Fig. 13, wherein the edge position detector 440 of DUT 1320 isdisabled. By disabling the edge position detector 440, the DUT 1320 behaves as atraditional CDR circuitry. Subsequently, the performance is obtained to provide astarting point against which the DUT 1320 according to example embodiments can becompared. The performance is quantified in terms of locking time. The locking time ismeasured as a phase difference between the sampling clock signal 1322 and thereference clock 1302. Fig.14 shows a y-axis 1410 illustrating a locking time, expressedin nanoseconds, ns as a function of an input phase offset on an x-axis 1420, expressedin radians. Curve 1430 shows the result of performing the measurement with the edgeposition detector 440 disabled. This illustrates that the locking time is proportional tothe initial input phase offset for a set-up wherein a loop bandwidth is fixed. Fig.14 alsoillustrates that the worst locking times occur around an initial phase of + π, i.e. aroundthe edges of curve 1430, where the locking time reaches values close to 500 ns.

[0074] Fig. 15 shows signals obtained during performing of a first test under the set-upof Fig. 13 for both a CDR circuitry according to example embodiments as well as aCDR circuitry according to example embodiments with the edge position detector,EPD, 440 disabled. Fig. 15 shows an x-axis 1501 illustrating the time passing duringthe test expressed in ns. Y-axis 1502 illustrates time expressed in picoseconds, ps.Start signal 1303 is shown over time 1501 at a top subplot 1540 of Fig. 15. Start signal1303 may, for example, be a periodic signal that switches on and off at regular timeintervals. The test starts where the start signal 1303 switches from zero to one at time0 ns. The test may be performed with a burst serial data signal 1301 comprising astream of consecutive packets, e.g. separated by gaps of 32 bits. For example, each packet may comprise 32736 bits of a “1010…” clock pattern, corresponding to a half- rate clock.

[0075] Further, in middle subplot 1550, Fig. 15 shows reference clock signal 1302 andsampling clock signal 1322 over time 1501. Subplot 1340 shows an enlarged view ofsignals 1302, 1322 to show the difference in phase between them. For example, at a certain point in time, around 200 ns into the test, after locking, there is a phasedifference 1511 of 91.13 ps between the signals 1302, 1322. This phase difference of91.13 ps corresponds to half a unit interval phase offset shift. In other words, theexperiment is conducted in a ‘worst case’ situation as identified above in Fig.14, which illustrates that a phase shift of π, i.e. ½ unit interval, takes the longest time toovercome. Around 550 ns, i.e. when the test is concluded and start signal 1303 is off,there is a 107.94 ps phase difference 1512 between the signals 1302, 1322, for a CDRcircuitry according to example embodiments with the EPD 440 enabled. At bottomsubplot 1560, Fig.15 further shows the phase difference of a CDR circuitry with the EPD 440 enabled 1521 alongside the same corresponding phase difference of a CDRcircuitry with the EPD 440 disabled 1520. Bottom subplot 1560 shows that there is a16.81 ps difference 1530 between the phase difference on locking, i.e. 91.13 ps andthe phase difference after the test, i.e. 107.94. This is the difference to be achieved bythe CDR circuitry. Subplot 1560 shows that with the EPD 440 on, the CDR circuitryimmediately, being within 0.8 ns, locks onto the desired phase difference of 91.13 ps.With the EPD off 1520, on the other hand, it takes 467 ns to reach locking.

[0076] Fig. 16 shows signals obtained during performing of a second test under theset-up of Fig.13 for both a CDR circuitry according to example embodiments as well as a CDR circuitry according to example embodiments with the EPD 440 disabled.Similar to time axis 1501, Fig.16 shows x-axis 1601. Fig.16 has a y-axis 1602 showinga voltage, expressed in millivolts, mV, as measured in the oscilloscope 1330. As in Fig.15, Fig. 16 shows the start signal 1303 in subplot 1630. Fig. 16 also shows thesampling clock signal 1322 in subplot 1660. Further, Fig. 16 shows the sampled datasignal 1321 in subplot 1650 compared to the burst serial data signal 1301 in subplot1640. The test may be performed with a burst serial data signal 1301 comprising astream of consecutive packets, e.g. separated by gaps of 32 bits, similar to Fig. 15. Asillustrated in subplot 1640, each packet may comprise a customised data pattern of 32 bits of a “1010…” pattern preamble, followed by 8 zero-bits, 8 one-bits, and 32688 bitsof a pseudo-random binary sequence PRBS-7 pattern in its data portion 315. Such aPRBS-7 pattern 1610 may have a duration of 4.233 ns. Fig. 16 shows that a matchingmay be achieved after 48 unit intervals at a data rate of 30 Gb / s corresponding to a locking time of 1.6 ns.

[0077] Fig. 9 illustrates the output phase corrector circuitry 880 according to anexample embodiment. Circuitry 880 comprises one or more injection locking ringoscillators, ILROs, 910 that are connected in series. The first ILRO 910 takes the clocksignals 871 as obtained from the initial phase generator 870 and generates therefromintermediate clock signals 911 that serve as input for the next ILRO 910. At the output, the sampling clock signals 404 are obtained. An ILRO 910 has a configurable feedback delay that can be configured differently in the first and second mode by mode control signal 403.

[0078] Fig. 10 illustrates an example embodiment of such a single ILRO 910 withconfigurable feedback delay. ILRO 910 is configured as an injection locking ringoscillator with four, i.e. delay circuits 1010 that are connected in series. The ringoscillator has a single edge feedback delay 1020, 1021 that provides a configurablefeedback delay 1030, 1031 for respectively the rising and falling edge of the four pairsof the complementary clock signals during the first mode of operation thereby obtainingthe smaller duty cycle and decreased phase spacing during the first mode of operation.During the second mode of operation the feedback delay is fixed thereby obtaining the50% duty cycle. Fig. 11 illustrates an example embodiment of the delay circuit 1010for use in the ILRO 910.

[0079] To ensure that the first input clock signal 871a of clock signals 871 has a fixedphase offset with respect to the edge of the incoming data, output phase corrector comprises a phase detector 920 that is configured to detect the phase differencebetween the first input clock signal 871a and the first output clock signal 971a. Theoutput 923 of the phase detector 920 is used to generate the control voltage 924 forthe ILROs 910, i.e. vctrl_mode1 and vctrl_mode2 respectively during the first and second mode. The phase difference between input clock 871a and output clock 971amay be tuned to zero individually by applying vctrl_mode1 and vctrl_mode2 in the firstand the second mode respectively. Since the delay between the first output clock 971a and the reference clock 405 is constant, the first output clock 971will have a fixed delayduring the first and second mode so that the phase offset between the first output clock971a and the incoming data before is known before the phase shift 408 is applied. Thegeneration of control voltages 924 may be done as an initializing procedure of CDR400 or during an idle period of input data signal 401. Switching between these twocontrol voltages 924 ensures fast switching to the second mode after the edgedetection during the first mode.

[0080] An unbalanced and balanced duty-cycle control in the ILRO is achieved byswitching on / off the Single Edge Feedback Delay, SEFD, inside of the ILRO. In thefirst mode, the second input of AND gate 971 and OR gate 972 at the input side of thefirst delay cell 1010 are connected to the delayed version 1030, 1031 of the feedbackclock 1020, 1021 from the last delay cell 1010. Only the rising edge will be delayed atthe output of AND gate 971 and only the falling edge will be delayed at the output ofthe OR gate 972. Since only the rising edge or the falling edge experiences a longerdelay in the loop, the duty-cycle in this mode will not be balanced, i.e. will not be 50%. In the second mode, the second input of AND gate 971 and OR gate 972 at the inputside of the first delay cell 1010 are connected to logic high and logic low respectively.As a result, there is no difference between the rising edge and falling edge delay,resulting in the 50% duty-cycle during the first mode. By putting multiple ILROs 910 inseries, the accuracy of the phase spacing of the sampling clock may be furtherimproved.

[0081] Fig. 12 shows a lookup table 1200 that may be used by edge detection circuitry440 during the first mode. Edge detection may be done by using the first eight samplingresults, s<7:0> from the respective eight interleaved clocks. Table 1200 then lists oneach row a possible result when sampling the preamble portion having the knownpredefined pattern. Column X then shows the estimated edge position with respect tothe column Phase1. In this example, since the first phase of the sampling clock has a fixed delay with respect to incoming data, the phase offset estimation, Phase_Est, can be calculated by using the index of Phase1 and X, i.e Phase_Est = (index of Phase1+ X)*Phase Spacing in the first mode. The value of X is obtained based on a duty-cycleof 40% for clocks 671, 673, 675, and 677 and a duty-cycle of 60% for clocks 672, 674,676, and 678.

[0082] As used in this application, the term "circuitry" may refer to one or more or all ofthe following: (a) hardware-only circuit implementations such as implementations in onlyanalog and / or digital circuitry and(b) combinations of hardware circuits and software, such as (as applicable): (i) a combination of analog and / or digital hardware circuit(s) withsoftware / firmware and (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and (c) hardware circuit(s) and / or processor(s), such as microprocessor(s) or aportion of a microprocessor(s), that requires software (e.g. firmware) for operation, butthe software may not be present when it is not needed for operation. This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the termcircuitry also covers an implementation of merely a hardware circuit or processor (ormultiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and / or firmware. The term circuitry also covers, for exampleand if applicable to the particular claim element, a baseband integrated circuit orprocessor integrated circuit for a mobile device or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

[0083] Although the present invention has been illustrated by reference to specificembodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the scope of the claims are therefore intended to be embraced therein.

[0084] It will furthermore be understood by the reader of this patent application that thewords "comprising" or "comprise" do not exclude other elements or steps, that the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms "first", "second", third", "a", "b", "c", and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms "top", "bottom", "over", "under", and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above.

Claims

CLAIMS 1. A clock and data recovery, CDR, circuitry (400) for sampling a burst serial data signal(401, 601) characterized by a data symbol period (216); the burst serial data signalcontaining at least a preamble portion (213, 401a, 501a, 601a) having a predefinedpattern (214, 509, 609) that defines a sampling position (507, 607) within the datasymbol period, and containing a data portion (315, 401b); and wherein the CDRcircuitry is configurable in a first mode (403a) for detecting (440) the sampling position when receiving the preamble portion, and in a second mode (403b) for sampling (410) the data portion at the detected sampling position when receiving the data portion; the CDR circuitry further comprising: a sampling circuitry (410) configured to sample the burst serial data signal by at least one sampling clock signal (404); asampling clock generation circuitry (450) configured to generate from areference clock signal (405, 505, 605) with a configurable phase shift (408) at leastone first and at least one second sampling clock signal (404a, 404b, 505a, 505b, 605a,605b) for sampling the burst serial data signal by the sampling circuitry when in therespective first and second mode, and to generate the at least one second samplingclock signal (404b, 505b, 605b) from the reference clock signal such that the samplingcircuitry performs the sampling ^ times per data symbol period; and to generate the atleast one first sampling clock signal (404a, 505a, 605a) from the reference clock signalsuch that the sampling circuitry samples ^ different sampling positions (5011-50110,6011-6013) within an equivalent data symbol period during ^ data symbol periodscontaining the predefined pattern by adjusting the sampling period of the at least onefirst sampling clock signal by a sampling offset, ^^^ (517, 617), during the sampling ofthe ^ data symbol periods;an edge detection circuitry (440) configured to, in the first mode, determine thesampling position (507, 607) from the sampled predefined pattern, and configured toderive the configurable phase shift (544, 644) for the second sampling clock signalduring the second mode from the determined sampling position and the appliedsampling offset.

2. The CDR circuitry (400) according to claim 1 wherein the sampling offset ^^^isdefined by a fraction of the sampling period as ((^ × ^ ÷ ^) − ^); and wherein ^ and^ are coprime, ^ is greater than ^, and ^ is greater than 1.

3. The CDR circuitry (400) according to claim 1 or 2 wherein the predefined pattern(509) occurs periodically in the preamble portion (501a); and wherein the ^ datasymbol periods contain at least two occurrences of the predefined pattern.

4. The CDR circuitry (400) according to claim 3 wherein the sampling clockgeneration circuitry is further configured to generate the at least one first sampling(505a) clock signal with an incrementally increasing phase offset with respect to theat least one second sampling clock signal (505b).

5. The CDR circuitry (400) according to claim 4 wherein the sampling clockgeneration circuitry is further configured to generate at least one sampling clocksignal from the reference clock signal (505) for performing the sampling by the ^times per data symbol period, and to generate the at least one first sampling clocksignal (505a) by incrementally increasing the configurable phase shift of the reference clock signal, and to generate the at least one second sampling clock signal by applying the configurable phase shift derived by the edge detection circuitry to the reference clock signal.

6. The CDR circuitry (400) according to any one of claims 1 to 3wherein the sampling circuitry (410) comprises a plurality of ^ sampling instancesoperated in an interleaved manner and sampling the serial burst signal by ^respective sampling signals (671-674); and wherein the sampling clock generationcircuitry is further configured to generate, in the second mode, the ^ samplingsignals (671-674) with a ^^^ ÷ ^ phase difference and, in the first mode, with adifferent phase difference.

7. The CDR circuitry (400) according to claim 6 wherein the ^ respective samplingsignals are ^ ÷ ^ pairs of complementary clock signals having, in the second mode,a 50% duty cycle and a ^^^ ÷ ^ phase spacing, and having, in the first mode, a dutycycle different from 50% and a different phase spacing between the different pairs.

8. The CDR circuitry (400) according to claim 7 wherein the sampling clockgeneration circuitry comprises:- a phase shifting circuitry (860) configured to apply the configurable phase shiftto the reference clock (405); -a clock generation circuitry (870) configured to further shift the phase of thereference clock by ^^^ ÷ ^ increments thereby obtaining the ^ samplingsignals with a 50% duty cycle and ^^^ ÷ ^ phase spacing;- a phase correcting circuitry (880) comprising at least one injection locking ringoscillator (910) having ^ ÷ ^ delay cell circuits (1010) connected in series witha single edge feedback delay (1020, 1021) providing a configurable feedbackdelay (1030, 1031) for the rising and falling edge of the ^ ÷ ^ pairs ofcomplementary clock signals;and wherein, in the first mode, a different feedback delay is provided for the risingand falling edge thereby obtaining the duty cycle smaller than 50% and the smallerphase spacing.

9. The CDR circuitry (400) according to claim 7 or 8 wherein the sampling circuitry(410) comprises ^ = ^ sampling instances.

10. The CDR circuitry (400) according to claim 6 and claim 4 or 5.

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