Method for manufacturing at least one optoelectronic device and associated optoelectronic device

Abstract

The invention relates to a method for manufacturing an optoelectronic device (1) and to the associated device (1), the method comprising: from a stack (2) comprising a buffer layer (20), a first layer (21) having a first type of charge carrier, an active region (220) configured to emit or receive light radiation, and a second region (230) having a second type of charge carrier, etching from the first layer (21) until the buffer layer (20) so as to laterally delimit a first region (210) and a first non-etched portion (200) of the buffer layer (20), each having a lateral flank (200a, 210a), and then depositing a layer based on a dielectric material (3), so as to cover the lateral flanks (200a, 210a). The mechanical stresses in the stack (2) are thus reduced.

Description

[0001] Method for manufacturing at least one optoelectronic device and associated optoelectronic device

[0002] TECHNICAL FIELD

[0003] The present invention relates to the field of microelectronics and optoelectronics technologies. It finds particularly advantageous application in the manufacture of optoelectronic devices, and in particular light-emitting diodes (LEDs).

[0004] STATE OF THE ART

[0005] A self-emitting display screen consists of pixels that emit their own light. Each pixel is typically formed by several optoelectronic devices such as LEDs or micro-LEDs (from the English Light Emitting Diode).

[0006] An LED typically comprises charge carrier injection regions (electrons and holes) between which an active region is interposed. The active region is the location where radiative recombinations of electron-hole pairs occur, which allows light emission to be obtained.

[0007] According to one possibility, these LEDs are so-called smart LEDs, typically comprising an optically active structure connected to dedicated driver electronics, or driver substrate, based on transistors. Groups of smart LEDs connected to independent control electronics typically form “smart pixels”.

[0008] LEDs, for example smart LEDs, are typically manufactured from a multilayer stack based on a III-V material. The stack is, for example, formed by full-wafer epitaxy on a carrier substrate and then assembled with a driver substrate. When epitaxy is performed on the driver substrate, for example, based on sapphire or silicon, the lattice mismatch between the driver substrate and the III-V material, for example GaN, leads to mechanical deformation of the driver substrate, and thus to a curvature of the stack. For industrial applications, GaN epitaxy is typically performed on thick silicon substrates (more than 1 mm thick in the standard 8-inch diameter, or about 200 mm), while post-processing takes place on thinner driver substrates in accordance with industrial standards. For example, in the 8-inch format, the standard thickness of the driver substrate in post-processing is 725 μm.

[0009] An example of an optoelectronic device is given by document W02022069506 A1. In this example, the device comprises a stack based on a III-V material comprising:

[0010] - a first layer having a first type of charge carriers,

[0011] - an active region configured to emit or receive light radiation, the active layer surmounting the first layer,

[0012] - a second region having a second type of charge carriers, the second region surmounting the active region.

[0013] The manufacturing of this type of optoelectronic device is based on the transition from a first substrate, typically thicker than 1 mm, to a second substrate, thinner than the first substrate, which can be handled by different tools. The curvature of the stack is further increased during this substrate change. This curvature can exceed the conventional limit of deflection less than or equal to 100 pm for a standard diameter of 8 inches. Handling by post-processing tools can be impacted. The support substrate can also delaminate during the substrate change.

[0014] The manufacture of an optoelectronic device may further comprise bonding a support transparent to the emitted or received radiation, allowing at the end of the process the individual manipulation of the pixels during a step of placing the pixels on a screen. This step of bonding the transparent support may again induce an undesirable curvature of the stack on the second substrate.

[0015] An object of the present invention is therefore to propose a solution improving the manufacture of optoelectronic devices compared to existing solutions. An objective may more particularly be to release the mechanical constraints of the stack during the manufacture of optoelectronic devices.

[0016] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

[0017] SUMMARY

[0018] To achieve this objective, according to a first aspect, a method is provided for manufacturing at least one optoelectronic device comprising: a supply of a stack based on a III-V material and comprising: o a buffer layer, o a first layer having a first type of charge carriers, and surmounting the buffer layer, o at least one active region configured to emit or receive light radiation, and surmounting the first layer, o at least one second region having a second type of charge carriers, and surmounting the active region,

[0019] - at least one etching of the stack comprising an etching from the first layer into the buffer layer, the buffer layer being at least partially etched in a direction normal to its main extension plane, so as to delimit laterally, from the first layer and the buffer layer, at least a first region and a first non-etched portion of the buffer layer surmounted by the active region, the first region and the first portion of the buffer layer each having a lateral flank,

[0020] - following the etching of the stack, a deposition of a layer based on a dielectric material on the stack, so as to cover said lateral sides.

[0021] Etching the first layer and at least part of the buffer layer allows the mechanical stresses in the stack to be released. During the development of the invention, it was further demonstrated that etching only the first layer did not have a satisfactory impact on reducing the curvature.

[0022] The curvature of the stack on the support substrate is thus reduced. The manufacturing of the optoelectronic device is therefore more reliable. It limits the risk of delamination of the support substrate and facilitates the handling of the stack on the control substrate by conventional post-processing tools.

[0023] Due to the etching of the first layer and at least part of the buffer layer, the deposition of the layer based on dielectric material is more substantial. During the development of the invention, it was surprisingly demonstrated that the impact in terms of cost and manufacturing time, linked to the greater deposition of dielectric material, was however offset by the gain in ease of handling and reliability of the manufacturing process.

[0024] A second aspect of the invention relates to an optoelectronic device comprising:

[0025] - a layer based on a dielectric material,

[0026] - a stack based on a III-V material overlying the layer based on a dielectric material, the stack comprising: o a second region having a second type of charge carriers, and overlying the layer based on a dielectric material, o an active region configured to emit or receive light radiation, and overlying the second region, o a first region having a first type of charge carriers, and overlying the active region, o a buffer layer overlying the first region. Advantageously, the first region and at least a first portion of the buffer layer each have a lateral flank, and in that the layer based on a dielectric material covers said lateral flanks.

[0027] The device therefore presents the advantages resulting from the method according to the first aspect. Its manufacture being simplified and made reliable, its cost can be reduced.

[0028] Furthermore, the first region is thus not exposed on the sides of the optoelectronic device. The risk of electrical contact with the first region is therefore reduced, and preferably eliminated. The reliability of the optoelectronic device is thus improved.

[0029] BRIEF DESCRIPTION OF THE FIGURES

[0030] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0031] Figure 1A represents a cross-sectional view of an example of an optoelectronic device obtained without etching the first layer and the buffer layer, for comparison and according to an example not covered by the invention.

[0032] Figures 1B and 1C illustrate a cross-sectional view of an exemplary optoelectronic device according to two exemplary embodiments of the invention.

[0033] Figures 2 to 11 represent cross-sectional views of steps in the method of manufacturing the optoelectronic device, according to an exemplary embodiment of the invention, and more particularly:

[0034] - figures 2 to 4 illustrate an example of formation of the optically active structure and the production of part of the electrical interconnections,

[0035] - figures 5 and 6 illustrate an example of etching of the first layer into the buffer layer and the deposition of the dielectric material layer,

[0036] - figure 7 illustrates an example of transfer of the stack with the dielectric layer, from the donor substrate to a control substrate,

[0037] - Figure 8 illustrates an example of buffer layer texturing,

[0038] - figures 9 and 10A illustrate an example of assembly with a transmission layer and formation of another part of the electrical interconnections,

[0039] - Figures 10B and 11 illustrate an example of cutting to form several optoelectronic devices.

[0040] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, the relative dimensions and thicknesses of the different elements, layers, regions and substrate are not representative of reality. DETAILED DESCRIPTION

[0041] Before commencing a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below.

[0042] According to one example, the stack having a total thickness EO taken along the direction normal to the main extension plane of the stack, the etching of the first layer into the buffer layer is configured so that, at the end of said etching, the buffer layer has a second portion at the level of the etching carried out, the second portion having a non-zero residual thickness E1. Preferably, the residual thickness E1 is between 0.2.E0 and 0.5.E0. Thus, the optoelectronic device retains some of the buffer layer at the level of the etching carried out. This facilitates the post-processing steps after assembly with the control substrate. The specified range facilitates these steps while satisfactorily reducing the mechanical stress in the stack.

[0043] According to one example, the etching of the first layer into the buffer layer is configured so that, at the end of said etching, the buffer layer has a second portion in line with the etching carried out, the second portion having a residual thickness E1 of between 0.8 pm and 2 pm, preferably between 1.2 and 1.8 pm, for example a thickness substantially equal to 1.5 pm.

[0044] In one example, the stack comprises an active layer comprising the at least one active region, and a second layer comprising the at least one second region.

[0045] In one example, the method comprises, prior to etching from the first layer into the buffer layer, etching the second layer and the active layer into the first layer, so as to form at least one active area comprising an active region and a second region.

[0046] According to one example, the method further comprises, preferably before etching from the first layer into the buffer layer, providing electrical interconnections configured to electrically and separately connect the first layer and the at least one second region.

[0047] According to one example, the stack comprises several active zones each comprising a second region and an active region, the etching of the first layer into the buffer layer being configured to form several first regions and several first portions of the buffer layer, each surmounted by an active zone, the method further comprising a cut between the lateral flanks of said first regions and said first portions so as to obtain a plurality of optoelectronic devices each comprising an active zone. The method thus allows the parallel manufacture of several optoelectronic devices. The reduction of the curvature of the stack is all the more advantageous in this case, and in particular for large support substrates.Furthermore, since the first layer is fully etched, electrical contact through the first layer is eliminated between different optically active structures comprising the first region, the active region and the second region. This makes it more advantageous to electrically test the manufactured optoelectronic devices independently, even before they are cut to separate them.

[0048] In one example, the stack is arranged on a support substrate.

[0049] According to one example, the support substrate has, in its main extension plane, at least one dimension greater than or equal to 100 mm, preferably 150 mm, and preferably greater than or equal to 200 mm. According to one example, the support substrate has, in its main extension plane, at least one dimension less than or equal to 300 mm. The curvature effect of the stack will indeed increase all the more with the dimensions of the support substrate. The reduction of the curvature of the stack is therefore all the more advantageous for these dimensions of support substrate, used in industrial production.

[0050] According to one example, the stack is arranged on a support substrate at least for the steps of providing the stack, etching the first layer into the buffer layer and / or depositing the layer based on the dielectric material.

[0051] According to one example, the deposition of the layer based on a dielectric material forms an exposed surface of the stack, opposite the support substrate, and the method further comprises transferring the stack to a second substrate distinct from the support substrate, by the exposed surface of the stack, and for example a CMOS substrate. The reduction of the mechanical stresses in the stack in fact facilitates the transfer of the stack to the second substrate. This transfer in fact usually induces an increase in the curvature of the stack. By the relaxation of the mechanical stresses in the stack, this effect is limited.

[0052] In one example, the method includes texturing the buffer layer to form a plurality of reliefs on an exposed surface of the buffer layer. Texturing the buffer layer improves extraction of light emitted by the active region or, if applicable, improves reception of light received by the active layer. In one example, the texturing is performed after deposition of the dielectric material-based layer. In one example, the texturing is performed after transfer of the stack to the second substrate and removal of the support substrate, so as to expose the buffer layer.

[0053] According to one example, the etching of the first layer into the buffer layer being configured so that, at the end of said etching, the buffer layer has a second portion at the level of the etching carried out, having a residual thickness E1, the texturing is configured so that the plurality of reliefs extends over at least 90% of E1, and preferably over substantially all of E1. The texturing of the buffer layer over this thickness range makes it possible to minimize, and preferably to avoid, any residual electrical contact by the buffer layer, between different optically active structures comprising the first region, the active region and the second region. It is thus possible, before cutting, to independently and reliably test the manufactured optoelectronic devices.When texturing is done on substantially the entirety of E1, this also allows for subsequent cutting to separate different optoelectronic devices, without crossing a layer of III-V material. This example is therefore particularly advantageous for the parallel manufacturing of several optoelectronic devices, as done for example, on an industrial scale. Synergistically, the fact that the optoelectronic device retains the buffer layer at the level of the etching carried out is particularly advantageous with this characteristic. Texturing a single type of material, the buffer layer in this case, is made easier compared to texturing two different materials. This post-processing step is thus made easier.

[0054] According to one example, the method further comprises assembling the layer based on a dielectric material with the second substrate, and more particularly a so-called "drive" substrate configured to electrically drive the optoelectronic device. The reduction of mechanical stresses in the stack facilitates the transfer of the stack onto the second substrate, and in particular from a support substrate to the drive substrate. This transfer usually induces an increase in the curvature of the stack. By relaxing the mechanical stresses in the stack, this effect is limited. The drive substrate can typically be thinner than the support substrate. The curvature of the stack is therefore generally aggravated during the transfer onto the drive substrate, in existing solutions.

[0055] According to one example, the stack being disposed on a support substrate at least when providing the stack, the assembly of the layer based on a dielectric material with the driving substrate further comprises a removal of the support substrate so as to expose a surface of the buffer layer.

[0056] According to one example, where appropriate following the texturing step, the method comprises assembling the buffer layer on an at least partially transparent transmission layer. The method is then particularly advantageous, the assembly of the buffer layer on the transmission layer usually inducing an increase in the curvature of the stack. By relaxing the mechanical constraints in the stack, this effect is further limited.

[0057] According to one example, prior to assembling the buffer layer with a transmission layer, assembling the layer based on a dielectric material with the second substrate, and more particularly the control substrate, further comprises removing the support substrate so as to expose the buffer layer.

[0058] In one example, the support substrate is based on a material distinct from the III-V material of the stack. In one example, the support substrate is based on silicon or sapphire.

[0059] According to one example, the second substrate, and for example the control substrate, is a substrate based on a material distinct from the support substrate. According to one example, the second substrate has a thickness less than or equal to, and preferably strictly less than, the thickness of the support substrate.

[0060] According to one example, the stack having a total thickness EO, the buffer layer has a second portion in contact with the layer based on a dielectric material, the residual thickness E1 of the buffer layer at the level of the second portion being between 0.2.E0 and 0.5.E0. The optoelectronic device therefore results from a manufacturing process that is further simplified and made more reliable, its cost can be further reduced.

[0061] According to one example, the buffer layer is in contact with the first region and the layer based on a dielectric material, in particular according to the portion of the buffer layer considered. According to one example, the buffer layer has a first surface opposite a surface in contact with the first region and the layer based on a dielectric material, said first surface forming a plurality of reliefs. The extraction or reception of light by the optoelectronic device is thus improved.

[0062] According to one example, the buffer layer has a second portion in contact with the layer based on a dielectric material, the second portion having a residual thickness E1, and the plurality of reliefs extends over at least 90% of E1, and preferably over substantially all of E1. The second portion may result from the partial etching of the buffer layer, and be in contact with and surmounting the layer based on a dielectric material.

[0063] According to one example, the device further comprises a so-called "drive" substrate configured to electrically drive the optoelectronic device, the layer based on a dielectric material preferably being arranged on the drive substrate.

[0064] In one example, the device further includes electrical interconnects configured to electrically connect the drive substrate and the stack.

[0065] In one example, the device further includes a transmission layer overlying the buffer layer, the transmission layer being at least partially transparent.

[0066] According to one example, the lll-V material is a lll-N material. According to one example, the lll-V material comprises at least the element Ga and the element N, preferably the lll-V material is selected from the group consisting of GaN, AIGaN.

[0067] According to one example, the at least one etch of the stack defines an etch volume in the stack. The layer based on a dielectric material can be deposited so as to fill, preferably entirely, the etch volume.

[0068] In one example, the dielectric material-based layer is deposited to cover or equivalently surmount the stack to form an exposed surface. This exposed surface is preferably planar. Accordingly, the dielectric material-based layer of the device may include a planar surface opposite the stack.

[0069] Following deposition of the dielectric material-based layer, the method may include planarizing the exposed surface of the dielectric material layer.

[0070] The layer based on a dielectric material is thus deposited so as to fill the etched volume and form a flat surface. The layer of dielectric material can be a non-conformal volume layer. In synergy with at least partial etching of the buffer layer releasing the mechanical constraints, this facilitates manipulation of the optoelectronic device by minimizing the effects of curvature of the stack.

[0071] According to one example, the exposed surface of the layer based on a dielectric material extends along a plane parallel to the main direction of extension of the layers of the stack.

[0072] In one example, the layer based on a dielectric material is continuous.

[0073] In one example, the layer based on a dielectric material is based on or made of oxide.

[0074] According to one example, the layer based on a dielectric material is directly in contact with the sides of the first region and of the at least one first portion of the buffer layer. According to one example, in projection in a main extension plane of the buffer layer, the second portion of the buffer layer is distinct from the first portion of the buffer layer. The second portion of the buffer layer may have a thickness less than the thickness of the first portion of the buffer layer.

[0075] According to one example, the second portion of the buffer layer has at least one side not covered by the layer based on a dielectric material.

[0076] According to one example, the layer based on a dielectric material has a portion, preferably continuous, surmounting the stack and preferably the electrical interconnections. This portion may have a thickness substantially between 0.3 μm and 1.5 μm, preferably substantially equal to 0.5 μm.

[0077] In this patent application, the terms "light-emitting diode", "LED" or simply "diode" are used synonymously. An "LED" can also be understood to mean a "micro-LED" or even a smart LED, where appropriate.

[0078] In a perfectly conventional manner, a structure based on a III-V material is a structure made of, or comprising, a material comprising at least one species from column III of the periodic table and at least one species from column V of this table. Similarly, a structure based on a III-N material is a structure made of, or comprising a material comprising at least one species from column III of the periodic table and nitrogen (N). A III-N material can therefore, for example, be taken from GaN, AIGaN, AllnGaN, InN.

[0079] A substrate, a layer, a device, "based" on a material M, means a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus, a GaN-based diode typically comprises GaN and / or alloys of AIGaN and / or InGaN.

[0080] Similarly, the following abbreviations relating to a material M are possibly used:

[0081] - uM, or equivalently iM, refers to the intrinsic or unintentionally doped material M, according to the terminology usually used in the field of microelectronics for the prefix u- or equivalently i-,

[0082] - nM refers to the material M doped N, N+ or N++, according to the terminology usually used in the field of microelectronics for the prefix n-,

[0083] - pM refers to the material M doped P, P+ or P++, according to the terminology usually used in the field of microelectronics for the prefix p-,

[0084] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant greater than 3.

[0085] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them. Furthermore, the term "step" means the carrying out of a part of the process, and can designate a set of sub-steps.

[0086] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term "step" does not necessarily mean actions that are unitary and inseparable in time and in the sequence of phases of the process.

[0087] It is specified that in the context of the present invention, the thickness of a layer or of the substrate is measured in a direction perpendicular to the surface or to the plane along which this layer or this substrate has its maximum extension. The thickness is thus taken in a direction perpendicular to the main faces of the substrate on which the different layers rest. Thus, a layer typically has a thickness along z, when it extends mainly along an xy plane. The relative terms “on”, “under”, “underlying” preferably refer to positions taken in the z direction.

[0088] Dimensional values ​​are within manufacturing and measurement tolerances.

[0089] A parameter that is "substantially equal to / greater than / less than" a given value means that this parameter is equal to / greater than / less than the given value, within plus or minus 10% of this value. A parameter that is "substantially between" two given values ​​means that this parameter is at least equal to the smallest given value, within plus or minus 10% of this value, and at most equal to the largest given value, within plus or minus 10% of this value.

[0090] It is specified that, in the context of the present invention, the terms "on", "under", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.Unless explicitly stated, it is specified that, in the context of the present invention, the relative arrangement of a third layer interposed between a first layer and a second layer does not necessarily mean that the layers are in direct contact with each other, but means that the third layer is either directly in contact with the first and second layers, or separated from them by at least one other layer or at least one other element. By "in contact" or "in contact with", it is meant that a fine interface may exist, for example caused by manufacturing variability.

[0091] The expression "A and / or B" means (A), (B), or (A and B). The expression "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The optoelectronic device 1 and its manufacturing method are now described according to several particular examples of embodiment with reference to the figures. In the following figures, the notions of "on", "under" or even "high", "low" are to be interpreted according to:

[0092] - for the optoelectronic device, a position in which the radiation emitted or received is from the top of the device 1,

[0093] - for the process steps, the normal orientation of the stack and layers and substrate during the manufacturing process steps.

[0094] The optoelectronic device 1 is illustrated for example by figures 1 B and 1 C. Figure 1A is given for comparison and is described in more detail later.

[0095] The optoelectronic device 1 comprises a stack 2 based on a III-V material. The stack 2 comprises an optically active structure comprising:

[0096] - a first region 210 having a first type of charge carriers,

[0097] - an active region 220 configured to emit or receive light radiation, and more particularly to emit this radiation in the case of an LED,

[0098] - a second region 230 having a second type of charge carriers, distinct from the first type of charge carriers.

[0099] In a known manner, the active region 220 can be configured to combine the first type and the second type of charge carriers to emit the light radiation, symbolized by the arrow in FIGS. 1 B and 1 C. The active region 220 is preferably directly in contact with the first 210 and second 230 regions.

[0100] The method of manufacturing the optoelectronic device 1 is described with reference to figures 2 to 11. Note that the characteristics described below can be applied to the optoelectronic device 1, as is apparent from the description which follows and from figures 1 B and 1 C.

[0101] As illustrated for example by Figure 2, stack 2 may comprise several superimposed layers. Stack 2 may comprise:

[0102] - the buffer layer 20 configured to provide the interface between the support substrate 8 and the subsequent layer, and more particularly the first layer 21,

[0103] - a first layer 21 having a first type of charge carriers, for example electrons, and intended to form at least a first region 210,

[0104] - an active layer 22, interposed between the first layer 21 and the second layer 22, preferably in contact with them, and intended to form at least one active region 220,

[0105] - a second layer 23 having a second type of charge carriers, for example holes, and intended to form at least one second region 230.

[0106] The first layer 21 is preferably in contact with the buffer layer 20.

[0107] The III-V material may be an III-N material. More particularly, the III-V material may be GaN. According to one example, the first layer 21 and the first region 210 are N-doped, for example n-GaN. According to one example, the second layer 23 and the second region 230 are P-doped, for example p-GaN. Note that the type of charge carriers of the first 21 and second 23 layers may be reversed. The buffer layer 20 may not be intentionally doped, for example u-GaN. According to one example, the buffer layer 20 is undoped. In the following, it is considered, without limitation, that the III-V material is GaN. Note that the buffer layer 20 may be based on or made of a material identical to or distinct from the other layers and / or regions of III-V materials. The buffer layer 20 may comprise several sub-layers. For example, the buffer layer 20 may be based on or made of AIGaN or AIN, or a stack of AIN / AIGaN / GaN layers.

[0108] The stack 2 may be formed by full-plate epitaxial growth of the III-V material on a support substrate 8 based on a distinct material, for example based on or made of silicon or sapphire. For this purpose, the stack comprises a buffer layer 20 capable of interfacing between the support substrate 8 and a first layer 21 intended to form the first region 210. Note that the term “layer”, in relation to “region”, does not necessarily imply, unless explicitly stated, that the layer extends in the entire xy plane of the object in question. The method for manufacturing the optoelectronic device 1 aims to release the mechanical stresses present in the stack 2 of III-V material, induced by the lattice shift between the support substrate 8 and the III-V material. When the support substrate 8 is based on or made of silicon, the stack 2 may be described as a structured semiconductor on silicon.

[0109] The stack 2 may further comprise an electrical contact layer 24, based on or made of an electrically conductive material. This material may for example be ITO (abbreviated from the English “indium-tin oxide”).

[0110] The stack 2 may have a total thickness Eo, considering the thickness of the assembly formed by the buffer layer 20, the first layer 21 or the first region 210, the active layer 22 or active region 220 and the second layer 23 or second region 230, and where appropriate the electrical contact layer 24, or the corresponding region 240. This thickness may for example be greater than or equal to 3 pm, preferably greater than or equal to 4 pm, for example substantially equal to 4.5 pm.

[0111] The stack 2 may be arranged on the support substrate 8. The support substrate 8 may have a thickness greater than or equal to 1 mm, as is conventional for full GaN wafer epitaxy. The support substrate 8 may have, in its main extension plane, at least one dimension greater than or equal to 150 mm, preferably greater than or equal to 200 mm, and for example substantially equal to 300 mm, this dimension being for example its diameter. This format of support substrate 8 is for example typically used in industrial production lines.

[0112] The method may comprise a step of shaping the optically active structure, as illustrated for example in Figures 2 and 3. For this, the method may comprise a first etching configured to etch, from an exposed surface 2b of the stack 2, the second layer 23 and the active layer 22, and where appropriate the electrical contact layer 24. This first etching may define a first etching volume or equivalently an etched volume in the stack 2. A structure 2a may thus be obtained, in relief relative to the first layer 21. This structure may for example be obtained by photolithography and / or etching. The relief structure 2a, which may also be designated equivalently by the term active zone 2a, comprises, and preferably consists of, the second region 230, the active region 220, and where appropriate the electrical contact region 240. The active zone 2a may have a thickness substantially equal to 600 nm.According to one example, the first layer 21 has a thickness of between 100 nm and 200 nm.

[0113] Preferably, this first etching is configured to form several structures 2a on the surface of the stack 2, to obtain several optoelectronic devices 1 at the end of the process. In the following, this scenario is considered without limitation.

[0114] As illustrated for example by Figure 4, the method can then comprise the production of electrical interconnections 60 on the surface of the stack 2. These electrical interconnections 60 can be configured to electrically and separately connect the first layer 21 and the second region(s) 230 to a second substrate 4, for example a control substrate 4, (for example assembled to the stack 2 during a subsequent step of the method), and in particular in cooperation with complementary interconnections 61 described later to form electrical connections 6. These electrical interconnections 60 can comprise metal tracks, and insulating portions 63 based on or made of a dielectric material. The second substrate 4 can therefore be electrically connected to the stack 2 in the optoelectronic device 1 obtained.

[0115] The method may then comprise a second etching, from the first layer 21 into the buffer layer 20, as illustrated for example in FIG. 5. The first layer 21 present at this stage of the method is therefore entirely etched during the second etching, as well as at least a portion of the buffer layer 20 to finish forming one or more optically active structures, in addition to the first etching. This second etching may define a second etching volume or equivalently an etched volume in the stack 2.

[0116] As illustrated in Figures 5, 1B and 1C, this etching forms the first region 210 of the optoelectronic device 1, preferably delimiting a first portion 200 of the buffer layer 20, not etched during the second etching step, and a second portion 201 resulting from the partial etching of the buffer layer 20. Due to this second etching, the first region 210 and the first portion 200 each have a lateral flank 210a, 200a respectively. For example, these lateral flanks 200a, 210a are common between the first region 210 and the first portion 200, and are in continuity with each other. It may be provided, even if this is not preferred, that these lateral flanks 200a, 210a are not in continuity with each other, for example resulting from two distinct sub-etchings.

[0117] Several first regions 210 and first portions 200 of the buffer layer 20 may also be delimited in line with the unetched areas. Thus, a first region 210 and a first portion 200 may be delimited for each relief structure 2a, i.e. under each second region 240 and active region 230. In line with the etching, the second portion 201 may be formed, resulting from the partial etching in the z direction of the buffer layer 20. Preferably, the buffer layer 20 is only partially etched in the z direction during this etching. The thickness of the second portion 201 is then non-zero. Alternatively, provision may be made for the buffer layer 20 to be completely etched in line with the etching, and preferably without etching the support substrate 8.This, however, increases the volume of dielectric material to be deposited for the dielectric material layer 3, and may complicate certain subsequent steps, in particular the texturing step as will be discussed later.

[0118] The second etching of the first layer 21 into the buffer layer 20 can be carried out externally to the active zone 2a, in projection in the xy plane. This second etching can in particular be carried out between active zones 2a. This second etching can be carried out from the exposed surface of the stack 2, and therefore through a part of the electrical interconnections 60, and insulating portions 63 previously deposited.

[0119] The etching of the first layer 21 into the buffer layer 20 can be configured so that the second portion 201 has a non-zero residual thickness E1 of between 0.2. EO and 0.5.E0. For example, the second portion 201 has a residual thickness of between 0.8 pm and 2 pm, for example a thickness substantially equal to 1.5 pm. The assembly formed by the active zone 2a and the region 210 and portion 200 after the second etching can therefore have a thickness E2 of between 0.5.E0 and 0.8.E0, as illustrated for example in FIGS. 1 B and 5.

[0120] The residual thickness E1 may be between 30% and 70% of the thickness of the assembly formed by the buffer layer 20, its portion 200 and the corresponding region 210, for example equal to 1.5 pm. The etched depth E3 of the first layer 21 and of the buffer layer 20 may be substantially equal to 2.5 pm.

[0121] The second portion 201 can extend over a distance of between 50 and 100 pm, in a direction taken in the xy plane, between two directly neighboring active zones 2a.

[0122] The second etching may be configured such that, in the main extension plane of the layer 20, the second portion 201 of the buffer layer 20 may represent a surface area of ​​proportion less than or equal to 30%, preferably less than or equal to 25%, of the total surface area of ​​the buffer layer 20, in projection in the xy plane. According to one example, in the main extension plane of the layer 20, the second portion 201 of the buffer layer 20 may represent a surface area of ​​proportion greater than or equal to 5%, of the total surface area of ​​the buffer layer 20, in projection in the xy plane.

[0123] Preferably, the second portion 201 is continuous, that is to say it is not split into several zones resulting from localized etchings of the buffer layer 20. The second portion 201 can surround, preferably completely, the first portion 200 of the buffer layer 20, for example along a plane (x,y) parallel to the main extension plane of the layers of the stack.

[0124] As illustrated in Figure 6 for example, a layer based on or made of dielectric material, designated dielectric material layer 3, can then be deposited so as to cover, preferably entirely, stack 2 and electrical interconnections 60. Dielectric material layer 3 can be deposited so as to fill the first and second etching volumes and form a flat surface 3a surmounting stack 2. Dielectric material layer 3 can therefore be a non-conformal volume layer. Flat surface 3a thus represents the entire surface of dielectric material layer 3, opposite the stack. Dielectric material layer 3 can comprise a portion entirely surmounting stack 2, this portion extending along a plane parallel to the main direction of extension of the layers of stack 2.This portion may have, preferably from the electrical interconnections 6, 60 and where appropriate up to the second substrate 4, a thickness E3 substantially between 0.3 μm and 1.5 μm, preferably substantially equal to 0.5 μm. This makes it possible to have a sufficient thickness to allow assembly on a second substrate 4.

[0125] The dielectric material can be based on or made of silicon oxide. Due to the second etching, it is understood that the volume of dielectric material deposited is increased compared to existing solutions. This therefore lengthens the associated deposition time. The combination of the second etching described above and this deposition of dielectric material is therefore counterintuitive from the point of view of improving a manufacturing process.

[0126] A person skilled in the art is able to identify the appropriate deposition method for depositing the layer of dielectric material 3, in particular among chemical vapor deposition methods. The method may comprise a step of planarizing the exposed surface 3a of the layer of dielectric material 3, for example by chemical and / or mechanical polishing. More particularly, any deposition method making it possible to fill the first and second etching volumes may be envisaged.

[0127] The method may further comprise the formation of vias, and in particular through-silicon-vias (TSVs). These vias may be formed through the layer of deposited dielectric material 3 to establish an electrical connection between the optically active structure and the substrate, and in particular the second substrate 4. In order to simplify the figures, these vias are not shown in the figures. These vias may be configured to connect the interconnections 60 and 61 once formed, to form the electrical connections 6. The formation of these vias is preferably done before the transfer to the second substrate 4.

[0128] The method can then comprise the transfer of the stack 2 and the layer of dielectric material 3 onto a second substrate 4, as illustrated for example by the transition from Figure 6 to Figure 7. The reduction in mechanical stresses in the stack 2 is therefore the reduction in curvature is particularly advantageous for this transfer step. For this, the layer of dielectric material 3 can be assembled to the second substrate 4 at its exposed surface 3a. The support substrate 8 can then be removed, for example by etching, in particular in the case of a silicon substrate. The removal of the substrate 8 can thus expose a surface 20a on the surface of the buffer layer 20. The surface 20a initially in contact with the support substrate 8 can therefore become exposed.

[0129] The second substrate 4 may be a conductive layer or a stack of several conductive layers and insulating layers, this stack allowing for example the formation of an interconnection network and an electronic control circuit. The substrate 4 may further be based on materials such as sapphire, silicon, but also be a “TFT” (“Thin-Film Transistor”, in English or thin-film transistor), a complementary metal oxide semiconductor (CMOS technology, or “Complementary Metal-Oxide-Semiconductor” in English). The substrate 4 may comprise a display support structure, known as “Backplane” in English terminology. This structure may comprise conductive tracks, connectors, and other elements designed to connect light-emitting diodes for example. It is therefore understood that the second substrate 4 may be a control substrate 4 configured to electrically control the LED.The substrate 4 may comprise or preferably be a CMOS substrate. The second substrate 4 may have a thickness greater than or equal to 500 μm and less than or equal to 1 mm, for example substantially equal to 725 μm.

[0130] For the assembly of substrate 4 with surface 3a, the technique known as “hybrid bonding” can be used, particularly in the case of a CMOS type substrate 4.

[0131] Due to the transfer by reversal on the substrate 4, the layer of dielectric material 3 is underlying the active zones 2a in the optoelectronic device obtained, and covers the lateral flanks 200a, 210a of the first portion 200 of the buffer layer 20 and of the first region 210, as illustrated in FIGS. 1 B and C. Equivalently, the first region 210 and the second portion 200 of the buffer layer extend along its main plane of extension only over a portion of the optoelectronic device 1, without being exposed at the level of the lateral flanks 1a of the optoelectronic device 1. It is therefore understood that, in the same xy plane, the layer of dielectric material 3 can be juxtaposed with the buffer layer 20, and more particularly a part of the first portion 200 of the buffer layer at the level of its lateral flank 200a.In another xy plane, the layer of dielectric material 3 can be juxtaposed with the first region 210, at its lateral flank 210a.

[0132] For comparison, and as illustrated by FIG. 1A, without this second etching step, the first layer 21 is not etched. This first layer 21 can extend along its main extension plane throughout the formed optoelectronic device 1. The first layer 21 is then flush or exposed on the sides 1a of the device 1, and is not juxtaposed with the layer of dielectric material 3 along an xy plane.

[0133] According to one embodiment, the method may comprise a step of texturing the surface that becomes exposed following the removal of the support substrate 8. This step is for example illustrated by FIG. 8. For this step in particular, it is particularly advantageous that the buffer layer 20 is not completely etched during the etching from the first layer 21 into the buffer layer 20. If the buffer layer 20 were completely etched during the etching of the first layer 21 into the buffer layer 20, then the exposed surface 20a would be formed of two distinct types of materials, with dielectric filling material 3 deposited following this etching. Indeed, it is simpler to texture a layer formed of a single type of material. This makes it possible in particular to avoid alignment problems during the lithography and etching sub-steps that can be implemented during this step.The etching of a single type of material is simplified compared to the etching of two different materials. A plurality of reliefs 203 can be produced on this exposed surface, and more particularly the exposed surface 20a of the buffer layer 20.

[0134] These reliefs of III-V material may extend, if necessary, from the layer of dielectric material 3 or the first portion 200 of the buffer layer 20. The reliefs 203 are configured to promote the extraction of the light emitted by the LED. These reliefs 203 may, for example, be point elements, for example pads or islands of III-V material in a direction of the xy plane. A sectional view of the reliefs 203 is, for example, illustrated in FIG. 10B. These reliefs 203 are obtained, for example, by photolithography then plasma etching (for example, by reactive ion etching, commonly abbreviated RIE for Reactive Ion Etching). Wet etching may alternatively be used, for example, using a potassium hydroxide KOH solution.

[0135] These reliefs 203 may be formed at least on the first portion 200, and therefore be opposite the optically active structure. These reliefs 203 may be formed over substantially the entire exposed surface 20a. The reliefs 203 extend for example from the interface between the buffer layer 20 and the layer of dielectric material 3 or the first portion 200, depending on the portions of the buffer layer 20 considered. The reliefs 203 preferably extend in a main extension direction parallel to the z direction. Preferably, the first region 210 is not etched during texturing.

[0136] These reliefs 203 have a thickness substantially greater than or equal to 0.9.E1, preferably 0.95.E1, more preferably still over substantially the entire thickness E1. It is therefore understood that the first portion 200 may comprise a part comprising reliefs 203 and a continuous part arranged under the reliefs 203.

[0137] Alternatively, it can be provided that the buffer layer 20 is not textured.

[0138] As illustrated for example in Figure 9, the surface opposite the surface in contact with the substrate 4 may be assembled with a transmission layer 5, for example by means of an adhesion layer 7 such as an optical adhesive, for example an optical adhesive marketed by the company Norland under the name NOA. This assembly may be done after transfer to the substrate 4 and removal of the support substrate 8, and if necessary after texturizing. The transmission layer 5 may be configured to protect the components and handle them, and / or to improve the light extraction efficiency. The transmission layer 5 may be at least partially transparent. The transmission layer 5 is for example based on or made of glass.

[0139] Note that a diffusion layer or a diffusion and color conversion layer (photoluminescent for example) can be interposed between the buffer layer 20, preferably once textured, and the transmission layer 5. A transparent interposed layer can also be interposed between the diffusion layer and the transmission layer 5, this transparent interposed layer having a refractive index as close as possible to 1, preferably strictly lower than the refractive index of the transmission layer 5 and strictly lower than the refractive index of the material or materials making up the optically active structures.The color diffusion and conversion layer may include a luminescent block which may or may not include phosphors configured to, when excited by light emitted by the associated light emitting diode (formed by an optically active structure), emit light at a wavelength different from the wavelength of the light emitted by the associated light emitting diode.

[0140] Assembly methods are already known for assembling this transmission layer 5, in the form of a transparent glass substrate, with RGB sub-pixels comprising, for example, color conversion modules. According to one example, the transmission layer associated with a diffusion layer or a diffusion and color conversion layer may be added to the buffer layer 20, preferably once textured, for example by bonding. As illustrated by the transition from FIG. 8 to FIG. 9, the method may further comprise thinning the substrate 4, for example by etching the substrate 4, for example to achieve the thicknesses of the substrate 4 previously described. This thinning is preferably done after assembly with the transmission layer 5, in order to facilitate handling of the formed assembly.

[0141] As illustrated in Figure 10A for example, and preferably after a possible thinning of the substrate 4, the method may comprise a production of complementary electrical interconnections 61, configured to electrically connect, for example by the vias or TSVs formed through the layer of dielectric material 3, the substrate 4 to the electrical interconnections 60 previously produced, to form electrical connections 6 in the optoelectronic device 1 and in particular with the vias previously described. Here again, the reduction of the mechanical stresses in the stack 2 and therefore the reduction of the curvature makes it easier to produce these interconnections. In addition, the n-GaN layer being completely etched, and advantageously with the texturing of substantially the entire thickness E1 of the buffer layer 20, the optically active structures are isolated from each other.This therefore makes it possible to test the LEDs formed during their manufacture, before cutting, compared to LEDs sharing a common layer 21 of n-GaN. This LED test is further facilitated by the texturing step. Indeed, the texturing then makes it possible to eliminate any residual electrical contact by the buffer layer 20, between different optically active structures.

[0142] The complementary electrical interconnections 61 may for example comprise through vias (not shown) connecting the substrate 4 and the electrical interconnections 60, filled with an electrically conductive material, and pads.

[0143] As illustrated for example in Figures 10B and 11, the method may comprise cutting. This cutting may be configured to separate different optoelectronic devices 1 manufactured in parallel by the method, as illustrated in dotted lines in Figure 10B. This cutting may be done after the production of the complementary electrical interconnections 61. This cutting may for example be done in the z direction, and for example in the yz plane, and more particularly at the level of a second portion 201 of the buffer layer 20. This cutting is preferably done between two directly neighboring reliefs 203. The cutting may be done by the usual cutting methods, for example by laser, by mechanical sawing and / or the so-called “stealth dicing” method.Due to the etching of the n-GaN layer 21 and the buffer layer 20, and advantageously with the texturing of substantially the entire thickness Ei of the buffer layer 20, this cutting does not pass through the n-GaN layer. This therefore avoids damaging this layer during cutting and therefore avoids possible deterioration of the formed LED. This damage can conventionally occur in particular by accumulation of charges in the GaN layer during laser cutting.

[0144] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention. The present invention is not limited to the examples previously described. Many other variant embodiments are possible, for example by combining previously described features, without departing from the scope of the invention. For example, in the examples above, the optoelectronic device described is an LED. Note that the aspects previously described can be applied to other types of optoelectronic devices, for example a photodiode or a vertical-cavity surface-emitting laser diode (commonly abbreviated VCSEL). In addition, the features described in relation to one aspect of the invention can be combined with another aspect of the invention.

Claims

Claims 1. Method for manufacturing at least one optoelectronic device (1) comprising: • a supply of a stack (2) based on a III-V material and comprising: o a buffer layer (20), o a first layer (21) having a first type of charge carriers, and overlying the buffer layer (20), o at least one active region (220) configured to emit or receive light radiation, and overlying the first layer (21), o at least one second region (230) having a second type of charge carriers, and overlying the active region (220), • at least one etching of the stack (2) comprising an etching from the first layer (21) into the buffer layer (20), the buffer layer (20) being at least partially etched in a direction normal to its main extension plane, so as to delimit laterally, from the first layer (21) and the buffer layer (20), at least a first region (210) and a first non-etched portion (200) of the buffer layer (20) surmounted by the active region (220), the first region (210) and the first portion (200) of the buffer layer (20) each having a lateral flank (200a, 210a), • following the etching of the stack (2), a deposition of a layer based on a dielectric material (3) on the stack, so as to cover said lateral flanks (200a, 210a), and surmount the stack (2) so as to form a flat exposed surface (3a).

2. Manufacturing method according to the preceding claim, in which, the stack (2) having a total thickness Eo taken in the direction normal to the main extension plane of the stack (2), the etching of the first layer (21) into the buffer layer (20) is configured so that, at the end of said etching, the buffer layer (20) has a second portion (201) at the level of the etching carried out, the second portion (201) having a residual thickness Ei of between 0.

2. Eo and 0.

5. Eo.

3. Method according to any one of the preceding claims, in which the etching of the first layer (21) into the buffer layer (20) is configured so that, at the end of said etching, the buffer layer (20) has a second portion (201) at the level of the etching carried out, the second portion (201) having a residual thickness Ei of between 0.8 pm and 2 pm.

4. Method according to any one of the preceding claims, in which, the stack (2) comprising an active layer (22) comprising the at least one active region (220), and a second layer (23) comprising the at least one second region (230), the method comprises, before etching from the first layer (21) into the buffer layer (20), etching the second layer (23) and the active layer (22) down to the first layer (21), so as to form at least one active zone (2a) comprising an active region (220) and a second region (230).

5. Method according to the preceding claim, further comprising, before etching from the first layer (21) into the buffer layer (20), producing electrical interconnections (60) configured to electrically and separately connect the first layer (21) and the at least one second region (230).

6. Method according to any one of the preceding claims, in which the stack comprises several active zones (2a) each comprising a second region (230) and an active region (220), the etching of the first layer (21) into the buffer layer (20) being configured to form several first regions (210) and several first portions (200) of the buffer layer (20), each surmounted by an active zone (2a), the method further comprising a cut between the lateral flanks (200a, 210a) of said first regions (210) and of said first portions (200) so as to obtain a plurality of optoelectronic devices (1) each comprising an active zone (2a).

7. Method according to any one of the preceding claims, in which the stack (2) is arranged on a support substrate (8) having, in its main extension plane, at least one dimension between 100 mm and 300 mm.

8. Method according to any one of the preceding claims, in which the deposition of the layer based on a dielectric material (3) forms an exposed surface (3a) of the stack (2), opposite the support substrate (8), and the method further comprising the transfer of the stack (2) onto a second substrate (4) separate from the support substrate (8), via the exposed surface (3a) of the stack (2).

9. A method according to any preceding claim, further comprising texturing the buffer layer (20) so as to form a plurality of reliefs (203) on an exposed surface (20a) of the buffer layer (20).

10. Method according to the preceding claim, in which, the etching of the first layer (21) into the buffer layer (20) is configured so that, at the end of said etching, the buffer layer (20) has a second portion (201) at the level of the etching carried out, having a residual thickness Ei, the texturing is configured so that the plurality of reliefs (203) extends over at least 90% of Ei, and preferably over substantially all of Ei.

11. Method according to any one of the preceding claims, further comprising assembling the buffer layer (20) on an at least partially transparent transmission layer (5).

12. Optoelectronic device (1) comprising: • a layer based on a dielectric material (3), • a stack (2) based on a III-V material overlying the layer based on a dielectric material (3), the stack comprising: o a second region (230) having a second type of charge carriers, and overlying the layer based on a dielectric material (3), o an active region (220) configured to emit or receive light radiation, and overlying the second region (230), o a first region (210) having a first type of charge carriers, and overlying the active region (220), o a buffer layer (20) overlying the first region (210), the optoelectronic device (1) being characterized in that the first region (210) and at least a first portion (200) of the buffer layer (20) each have a lateral flank (200a, 210a), and in that the layer based on a dielectric material (3) covers said lateral flanks (200a, 210a) the layer based on a dielectric material (3) having a flat surface (3a) opposite the stack (2).

13. Optoelectronic device (1) according to the preceding claim, in which, the stack (2) having a total thickness Eo, the buffer layer (20) has a second portion (201) in contact with the layer based on a dielectric material (3), the second portion (201) being distinct from the second portion (200) of the buffer layer (20) in projection in a main extension plane of the buffer layer (20), the residual thickness E1 of the buffer layer (20) at the level of the second portion (201) being between 0.2.Eo and 0.5.Eo.

14. Optoelectronic device (1) according to any one of the two preceding claims, in which the buffer layer (20) has a first surface (20a) opposite a second surface in contact with the first region (210) and the layer based on a dielectric material (3), said first surface (20a) forming a plurality of reliefs (203).

15. Optoelectronic device (1) according to the preceding claim, in which the buffer layer (20) has a second portion (201) in contact with the layer based on a dielectric material (3), the second portion (201) having a residual thickness Ei, and the plurality of reliefs (203) extends over at least 90% of Ei, and preferably over substantially all of Ei.

16. Optoelectronic device (1) according to any one of the four preceding claims, further comprising a so-called “drive” substrate (4) configured to electrically drive the optoelectronic device (1), the layer based on a dielectric material (3) being arranged on the drive substrate (4).

17. Optoelectronic device (1) according to any one of the five preceding claims, in which the III-V material is chosen from the group consisting of GaN, AIGaN.

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