Display substrate, related test method, and display device

Abstract

Provided in the embodiments of the present disclosure are a display substrate, a related test method, and a display panel. The display substrate comprises: a plurality of common electrodes, which are arranged in a display area in an array and are electrically isolated from each other; and a test circuit. Each common electrode comprises: a first common electrode located in an odd-numbered row and an odd-numbered column, or located in an even-numbered row and an even-numbered column; and a second common electrode located in an odd-numbered row and an even-numbered column, or located in an even-numbered row and an odd-numbered column. The plurality of common electrodes are divided into a plurality of electrode groups arranged in an array, wherein each electrode group comprises a first common electrode and a second common electrode. The display substrate further comprises the test circuit, which is located in a non-display area and is configured to provide test signals to the plurality of common electrodes, so as to test the display substrate. The test circuit comprises a plurality of test sub-circuits, wherein the number of test sub-circuits is the same as the number of electrode groups, and each test sub-circuit is coupled to a respective electrode group and is configured to provide a test signal to the electrode group coupled thereto.

Description

Display substrate, related testing method and display device Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate, a method for testing a display substrate, and a display device. Background Art

[0002] With the rapid development of display-related technologies, there's a need to reduce manufacturing costs while maintaining narrow bezels and display stability. Therefore, during the display substrate manufacturing process, it's necessary to detect display defects such as short circuits, open circuits, and crosstalk. Furthermore, detecting defects as early as possible during the manufacturing process can save material waste in subsequent manufacturing steps.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and related testing methods and a display device.

[0005] According to a first aspect of the present disclosure, a display substrate is provided. The display substrate has a display area and a non-display area surrounding the display area. The display substrate includes: a plurality of common electrodes, which are arranged in an array within the display area and are electrically isolated from each other. Each common electrode includes a first common electrode and a second common electrode. The first common electrode is located in odd rows and odd columns, or even rows and even columns. The second common electrode is located in odd rows and even columns, or even rows and odd columns. The plurality of common electrodes are divided into a plurality of electrode groups arranged in an array, wherein each electrode group includes a first common electrode and a second common electrode. The array substrate also includes a test circuit, which is located in the non-display area and is configured to provide a test signal to the plurality of common electrodes to test the display substrate. The test circuit includes a plurality of sub-test circuits. The number of the plurality of sub-test circuits is the same as the number of the plurality of electrode groups. Each sub-test circuit is coupled to a different respective electrode group and is configured to provide a test signal to the coupled electrode group.

[0006] In an embodiment of the present disclosure, each sub-test circuit includes: a first test signal line configured to provide a first test signal to a first common electrode coupled to the sub-test circuit; and a second test signal line configured to provide a second test signal to a second common electrode coupled to the sub-test circuit.

[0007] In an embodiment of the present disclosure, each sub-test circuit further includes: a first test control signal line, which is coupled to the first test control circuit and is configured to provide a first test control signal to the first test control circuit; and a first test control circuit, which is coupled between the first test signal line and the second test signal line and is configured to couple the first test signal line to the second test signal line based on the first test control signal.

[0008] In an embodiment of the present disclosure, the first test control circuit includes a first control transistor, wherein a control electrode of the first control transistor is coupled to a first test control signal line, a first electrode of the first control transistor is coupled to a first test signal line, and a second electrode of the first control transistor is coupled to a second test signal line.

[0009] In an embodiment of the present disclosure, each sub-test circuit further includes: a second test control signal line, which is coupled to the second test control circuit and configured to provide a second test control signal to the second test control circuit; and a second test control circuit, which is coupled between the first common electrode and the respective first test signal lines of the sub-test circuit, or between the second common electrode and the respective second test signal lines of the sub-test circuit, and is configured to couple the first common electrode and the second common electrode to the respective first test signal lines and the second test signal lines of the sub-test circuit, respectively, based on the second test control signal.

[0010] In an embodiment of the present disclosure, the second test control circuit includes a second control transistor and a third control transistor. The control electrode of the second control transistor is coupled to the second test control signal line, the first electrode of the second control transistor is coupled to the first test signal line, and the second electrode of the second control transistor is coupled to the first common electrode. The control electrode of the third control transistor is coupled to the second test control signal line, the first electrode of the third control transistor is coupled to the second test signal line, and the second electrode of the third control transistor is coupled to the second common electrode.

[0011] In an embodiment of the present disclosure, the test circuit is configured to provide a test signal to the plurality of electrode groups so that the display substrate displays a test pattern corresponding to the test signal.

[0012] In an embodiment of the present disclosure, the plurality of common electrodes are divided into nine electrode groups arranged in a 3×3 array.

[0013] In an embodiment of the present disclosure, the nine electrode groups include a first electrode group located in the first row and first column, a second electrode group located in the second row and first column, a third electrode group located in the third row and first column, a fourth electrode group located in the first row and second column, a fifth electrode group located in the second row and second column, a sixth electrode group located in the third row and second column, a seventh electrode group located in the first row and third column, an eighth electrode group located in the second row and third column, and a ninth electrode group located in the third row and third column. The first test signal includes a first sub-test signal, a second sub-test signal, a third sub-test signal, a fourth sub-test signal, a fifth sub-test signal, a sixth sub-test signal, a seventh sub-test signal, an eighth sub-test signal, and a ninth sub-test signal. The second test signal includes a tenth sub-test signal, an eleventh sub-test signal, a twelfth sub-test signal, a thirteenth sub-test signal, a fourteenth sub-test signal, a fifteenth sub-test signal, a sixteenth sub-test signal, a seventeenth sub-test signal, and an eighteenth sub-test signal. The first control transistor includes a first sub-control transistor, a second sub-control transistor, a third sub-control transistor, a fourth sub-control transistor, a fifth sub-control transistor, a sixth sub-control transistor, a seventh sub-control transistor, an eighth sub-control transistor, and a ninth sub-control transistor. The control electrode of the first sub-control transistor is coupled to the first test control signal line, the first electrode of the first sub-control transistor is coupled to the first sub-test signal line, the second electrode of the first sub-control transistor is coupled to the tenth sub-test signal line, and the first sub-control transistor is configured to couple the first sub-test signal line to the tenth sub-test signal line based on the first test control signal. The control electrode of the second sub-control transistor is coupled to the first test control signal line, the first electrode of the second sub-control transistor is coupled to the second sub-test signal line, the second electrode of the second sub-control transistor is coupled to the eleventh sub-test signal line, and the second sub-control transistor is configured to couple the second sub-test signal line to the eleventh sub-test signal line based on the first test control signal. A control electrode of the third sub-control transistor is coupled to the first test control signal line, a first electrode of the third sub-control transistor is coupled to the third sub-test signal line, a second electrode of the third sub-control transistor is coupled to the twelfth sub-test signal line, and the third sub-control transistor is configured to couple the third sub-test signal line to the twelfth sub-test signal line based on the first test control signal. A control electrode of the fourth sub-control transistor is coupled to the first test control signal line, a first electrode of the fourth sub-control transistor is coupled to the fourth sub-test signal line, a second electrode of the fourth sub-control transistor is coupled to the thirteenth sub-test signal line, and the fourth sub-control transistor is configured to couple the fourth sub-test signal line to the thirteenth sub-test signal line based on the first test control signal.The control electrode of the fifth sub-control transistor is coupled to the first test control signal line, the first electrode of the fifth sub-control transistor is coupled to the fifth sub-test signal line, the second electrode of the fifth sub-control transistor is coupled to the fourteenth sub-test signal line, and the fifth sub-control transistor is configured to couple the fifth sub-test signal line to the fourteenth sub-test signal line based on the first test control signal. The control electrode of the sixth sub-control transistor is coupled to the first test control signal line, the first electrode of the sixth sub-control transistor is coupled to the sixth sub-test signal line, the second electrode of the sixth sub-control transistor is coupled to the fifteenth sub-test signal line, and the sixth sub-control transistor is configured to couple the sixth sub-test signal line to the fifteenth sub-test signal line based on the first test control signal. The control electrode of the seventh sub-control transistor is coupled to the first test control signal line, the first electrode of the seventh sub-control transistor is coupled to the seventh sub-test signal line, the second electrode of the seventh sub-control transistor is coupled to the sixteenth sub-test signal line, and the seventh sub-control transistor is configured to couple the seventh sub-test signal line to the sixteenth sub-test signal line based on the first test control signal. A control electrode of the eighth sub-control transistor is coupled to the first test control signal line, a first electrode of the eighth sub-control transistor is coupled to the eighth sub-test signal line, a second electrode of the eighth sub-control transistor is coupled to the seventeenth sub-test signal line, and the eighth sub-control transistor is configured to couple the eighth sub-test signal line to the seventeenth sub-test signal line based on the first test control signal. A control electrode of the ninth sub-control transistor is coupled to the first test control signal line, a first electrode of the ninth sub-control transistor is coupled to the ninth sub-test signal line, a second electrode of the ninth sub-control transistor is coupled to the eighteenth sub-test signal line, and the ninth sub-control transistor is configured to couple the ninth sub-test signal line to the eighteenth sub-test signal line based on the first test control signal.

[0014] In an embodiment of the present disclosure, the second control transistor includes a tenth sub-control transistor, an eleventh sub-control transistor, a twelfth sub-control transistor, a thirteenth sub-control transistor, a fourteenth sub-control transistor, a fifteenth sub-control transistor, a sixteenth sub-control transistor, a seventeenth sub-control transistor, and an eighteenth sub-control transistor. Control electrodes of the tenth through eighteenth sub-control transistors are all coupled to a second test control signal line. A first electrode of the tenth sub-control transistor is coupled to the first sub-test signal line, and a second electrode of the tenth sub-control transistor is coupled to a first common electrode in the first electrode group. A first electrode of the eleventh sub-control transistor is coupled to the second sub-test signal line, and a second electrode of the eleventh sub-control transistor is coupled to a first common electrode in the second electrode group. A first electrode of the twelfth sub-control transistor is coupled to the third sub-test signal line, and a second electrode of the twelfth sub-control transistor is coupled to a first common electrode in the third electrode group. A first electrode of the thirteenth sub-control transistor is coupled to the fourth sub-test signal line, and a second electrode of the thirteenth sub-control transistor is coupled to a first common electrode in the fourth electrode group. The first electrode of the fourteenth sub-control transistor is coupled to the fifth sub-test signal line, and the second electrode of the fourteenth sub-control transistor is coupled to the first common electrode in the fifth electrode group. The first electrode of the fifteenth sub-control transistor is coupled to the sixth sub-test signal line, and the second electrode of the fifteenth sub-control transistor is coupled to the first common electrode in the sixth electrode group. The first electrode of the sixteenth sub-control transistor is coupled to the seventh sub-test signal line, and the second electrode of the sixteenth sub-control transistor is coupled to the first common electrode in the seventh electrode group. The first electrode of the seventeenth sub-control transistor is coupled to the eighth sub-test signal line, and the second electrode of the seventeenth sub-control transistor is coupled to the first common electrode in the eighth electrode group. The first electrode of the eighteenth sub-control transistor is coupled to the ninth sub-test signal line, and the second electrode of the eighteenth sub-control transistor is coupled to the first common electrode in the ninth electrode group. The tenth sub-control transistor to the eighteenth sub-control transistor are configured to provide the first sub-test signal, the second sub-test signal, the third sub-test signal, the fourth sub-test signal, the fifth sub-test signal, the sixth sub-test signal, the seventh sub-test signal, the eighth sub-test signal and the ninth sub-test signal from the first sub-test signal line to the ninth sub-test signal line to the first common electrode in the first electrode group to the first common electrode in the ninth electrode group based on the second test control signal.

[0015] In an embodiment of the present disclosure, the third control transistor includes a nineteenth sub-control transistor, a twentieth sub-control transistor, a twenty-first sub-control transistor, a twenty-second sub-control transistor, a twenty-third sub-control transistor, a twenty-fourth sub-control transistor, a twenty-fifth sub-control transistor, a twenty-sixth sub-control transistor, and a twenty-seventh sub-control transistor. Control electrodes of the nineteenth through twenty-seventh sub-control transistors are all coupled to the second test control signal line. A first electrode of the nineteenth sub-control transistor is coupled to the tenth sub-test signal line, and a second electrode of the nineteenth sub-control transistor is coupled to the second common electrode in the first electrode group. A first electrode of the twentieth sub-control transistor is coupled to the eleventh sub-test signal line, and a second electrode of the twentieth sub-control transistor is coupled to the second common electrode in the second electrode group. A first electrode of the twenty-first sub-control transistor is coupled to the twelfth sub-test signal line, and a second electrode of the twenty-first sub-control transistor is coupled to the second common electrode in the third electrode group. A first electrode of the twenty-second sub-control transistor is coupled to the thirteenth sub-test signal line, and a second electrode of the twenty-second sub-control transistor is coupled to the second common electrode in the fourth electrode group. The first electrode of the twenty-third sub-control transistor is coupled to the fourteenth sub-test signal line, and the second electrode of the twenty-third sub-control transistor is coupled to the second common electrode in the fifth electrode group. The first electrode of the twenty-fourth sub-control transistor is coupled to the fifteenth sub-test signal line, and the second electrode of the twenty-fourth sub-control transistor is coupled to the second common electrode in the sixth electrode group. The first electrode of the twenty-fifth sub-control transistor is coupled to the sixteenth sub-test signal line, and the second electrode of the twenty-fifth sub-control transistor is coupled to the second common electrode in the seventh electrode group. The first electrode of the twenty-sixth sub-control transistor is coupled to the seventeenth sub-test signal line, and the second electrode of the twenty-sixth sub-control transistor is coupled to the second common electrode in the eighth electrode group. The first electrode of the twenty-seventh sub-control transistor is coupled to the eighteenth sub-test signal line, and the second electrode of the twenty-seventh sub-control transistor is coupled to the second common electrode in the ninth electrode group. The nineteenth sub-control transistor to the twenty-seventh sub-control transistor are configured to provide the tenth sub-test signal, the eleventh sub-test signal, the twelfth sub-test signal, the thirteenth sub-test signal, the fourteenth sub-test signal, the fifteenth sub-test signal, the sixteenth sub-test signal, the seventeenth sub-test signal and the eighteenth sub-test signal from the tenth sub-test signal line to the eighteenth sub-test signal line to the second common electrode in the first electrode group to the second common electrode in the ninth electrode group, respectively, based on the second test control signal.

[0016] In an embodiment of the present disclosure, the test patterns include a checkerboard pattern, a square pattern, and an I-shaped pattern.

[0017] According to a second aspect of the present disclosure, a display substrate testing method is provided. The display substrate includes a display area and a non-display area surrounding the display area. The display substrate includes a plurality of common electrodes arranged in an array within the display area and electrically isolated from each other. Each common electrode includes a first common electrode and a second common electrode. The first common electrode is located in odd rows and odd columns, or even rows and even columns. The second common electrode is located in odd rows and even columns, or even rows and odd columns. The plurality of common electrodes are divided into a plurality of electrode groups arranged in an array, each electrode group including a first common electrode and a second common electrode. The array substrate also includes a test circuit located within the non-display area and configured to provide a test signal to the plurality of common electrodes to test the display substrate. The test circuit includes a plurality of sub-test circuits. The plurality of sub-test circuits is the same number as the plurality of electrode groups. Each sub-test circuit is coupled to a different electrode group and configured to provide a test signal to the coupled electrode group. The testing method includes: providing a test signal to the coupled electrode group via each sub-test circuit so that the display substrate displays a test pattern; and testing the display substrate based on the test pattern.

[0018] In an embodiment of the present disclosure, each sub-test circuit includes: a first test signal line, which is configured to provide a first test signal to a coupled first common electrode of the sub-test circuit; a second test signal line, which is configured to provide a second test signal to a coupled second common electrode of the sub-test circuit; a first test control signal line, which is coupled to the first test control circuit and configured to provide a first test control signal to the first test control circuit; and a first test control circuit, which is coupled between the first test signal line and the second test signal line and is configured to couple the first test signal line to the second test signal line based on the first test control signal; a second test control signal line, which is coupled to the second test control circuit and is configured to provide a second test control signal to the second test control circuit; and a second test control circuit, which is coupled between the first common electrode and the respective first test signal lines of the sub-test circuit, or between the second common electrode and the respective second test signal lines of the sub-test circuit, and is configured to couple the first common electrode and the second common electrode to the respective first test signal line and the second test signal line of the sub-test circuit, respectively, based on the second test control signal.

[0019] In an embodiment of the present disclosure, the plurality of common electrodes are divided into nine electrode groups arranged in a 3×3 array.

[0020] In an embodiment of the present disclosure, displaying a checkerboard pattern in which a pixel group sharing all common electrodes in each electrode group is the smallest display portion includes: providing a first test signal and a second test signal having a first level to an electrode group located in odd columns and odd rows or even columns and even rows, so that the pixels sharing all common electrodes in the electrode group located in odd columns and odd rows or even columns and even rows maintain a first state; and providing a first test signal and a second test signal having a second level to an electrode group located in even columns and odd rows or odd columns and even rows, so that the pixels sharing all common electrodes in the electrode group located in even columns and odd rows or odd columns and even rows maintain a second state. The level levels of the first level and the second level are opposite. The first state is one of a lit state and an unlit state, and the second state is the other of a lit state and an unlit state.

[0021] In an embodiment of the present disclosure, displaying a U-shaped pattern in which a pixel group sharing all common electrodes in each electrode group is a minimum display pixel includes: providing a first test signal and a second test signal having a first level to an electrode group located in the second column and the second row, so that the pixels sharing all common electrodes in the electrode group located in the second column and the second row maintain a second state; and providing a first test signal and a second test signal having a second level to the remaining electrode groups, so that the pixels sharing all common electrodes in the remaining electrode groups maintain the first state. The first level and the second level are opposite in level. The first state is one of a lit state and an unlit state, and the second state is the other of a lit state and an unlit state.

[0022] In an embodiment of the present disclosure, an I-shaped pattern in which a pixel group sharing all common electrodes in each electrode group is displayed as a minimum display portion includes: providing a first test signal and a second test signal having a first level to the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row, so that the pixels sharing all common electrodes in the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row maintain a second state; and providing a first test signal and a second test signal having a second level to the remaining electrode groups, so that the pixels sharing all common electrodes in the remaining electrode groups maintain the first state. The first level and the second level are opposite in level. The first state is one of a lit state and an unlit state, and the second state is the other of a lit state and an unlit state.

[0023] In an embodiment of the present disclosure, a method for displaying a checkerboard pattern in which a group of pixels sharing each common electrode is a minimum display portion includes: providing a first test signal having a second level to a coupled first common electrode of a sub-test circuit so that the pixels sharing the coupled first common electrode of the sub-test circuit maintain a first state; and providing a second test signal having a first level to a coupled second common electrode of the sub-test circuit so that the pixels sharing the coupled second common electrode of the sub-test circuit maintain a second state. The first level and the second level are opposite in level. The first state is one of a lit state and an unlit state, and the second state is the other of the lit state and the unlit state.

[0024] According to a third aspect of the present disclosure, a display device is provided. The display panel includes a display substrate according to any one of the first aspects.

[0025] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present application, wherein:

[0027] FIG1 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure;

[0028] FIG2 shows a schematic block diagram of a sub-test circuit according to an embodiment of the present disclosure;

[0029] FIG3 shows a schematic block diagram of a sub-test circuit according to another embodiment of the present disclosure;

[0030] FIG4 shows a schematic block diagram of a test circuit for the first column of common electrodes in FIG1 according to an embodiment of the present disclosure;

[0031] FIG5 shows a schematic block diagram of a test circuit for the fourth column of common electrodes in FIG1 according to an embodiment of the present disclosure;

[0032] FIG6 shows a schematic block diagram of a test circuit for the seventh column of common electrodes in FIG1 according to an embodiment of the present disclosure;

[0033] FIG7 shows a top view of a sub-test circuit according to an embodiment of the present disclosure;

[0034] FIG8 shows a schematic block diagram of a display substrate displaying a checkerboard pattern according to an embodiment of the present disclosure;

[0035] FIG9 shows a timing diagram for displaying the checkerboard pattern in FIG8 according to an embodiment of the present disclosure;

[0036] FIG10 shows a schematic block diagram of a display substrate displaying a square-shaped pattern according to an embodiment of the present disclosure;

[0037] FIG11 shows a timing diagram for displaying the U-shaped pattern in FIG10 according to an embodiment of the present disclosure;

[0038] FIG12 shows a schematic block diagram of a display substrate displaying an I-shaped pattern according to an embodiment of the present disclosure;

[0039] FIG13 shows a timing diagram for displaying the I-shaped pattern in FIG12 according to an embodiment of the present disclosure;

[0040] FIG14 shows a schematic block diagram of a display substrate displaying a checkerboard pattern according to another embodiment of the present disclosure;

[0041] FIG15 shows a timing diagram for displaying the checkerboard pattern of FIG14 according to an embodiment of the present disclosure;

[0042] FIG16 shows a schematic flow chart of a method for testing a display substrate according to an embodiment of the present disclosure;

[0043] FIG17 shows a schematic flowchart of a method for displaying the checkerboard pattern in FIG8 according to an embodiment of the present disclosure;

[0044] FIG18 is a schematic flowchart showing a method for displaying the U-shaped pattern in FIG10 according to an embodiment of the present disclosure;

[0045] FIG19 is a schematic flowchart showing a method for displaying the I-shaped pattern in FIG12 according to an embodiment of the present disclosure;

[0046] FIG20 shows a schematic flowchart of a method for displaying the checkerboard pattern in FIG14 according to an embodiment of the present disclosure; and

[0047] FIG21 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0048] Corresponding reference numerals indicate corresponding parts or features throughout the several views of the drawings. DETAILED DESCRIPTION

[0049] First, it should be noted that, unless the context clearly indicates otherwise, the singular form of the words used in this document and the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "include" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless otherwise indicated herein. Where the term "example" is used in this document, especially when it is placed after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0050] In addition, it should be noted that when introducing elements of the present application and embodiments thereof, the articles "a", "an", "the" and "said" are intended to indicate the presence of one or more elements; unless otherwise specified, "plurality" means two or more; the terms "comprising", "including", "containing" and "having" are intended to be inclusive and indicate that there may be additional elements in addition to the listed elements; the terms "first", "second", "third", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance and formation order.

[0051] In the embodiment of the present disclosure, the levels of A and B being opposite means that A is at a high level and B is at a low level, or A is at a low level and B is at a high level.

[0052] As mentioned above, with the rapid development of relevant technologies in reality, it is also necessary to reduce manufacturing costs. To achieve this goal, it is necessary to detect defects as early as possible in the manufacturing process to reduce material waste.

[0053] Typically, before bonding integrated circuits (ICs), such as display driver ICs, touch driver ICs, or both, common electrodes in the display substrate are tested for defects such as short circuits or open circuits. After bonding the ICs, crosstalk related to the common electrodes, such as crosstalk caused by voltage differences between signal lines and common electrodes, is tested.

[0054] The present disclosure provides a display substrate that displays complex test patterns by grouping common electrodes, thereby testing crosstalk problems before binding ICs, thereby reducing waste of subsequent materials and further reducing the manufacturing cost of the display substrate.

[0055] The structure of a display substrate according to an embodiment of the present disclosure will be described below with reference to FIG. 1 to FIG. 7 .

[0056] Figure 1 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the display substrate may be a touch display substrate, such as a touch display substrate with touch and display driver integration (TDDI) technology. As shown in Figure 1, the display substrate 10 includes a display area AA and a non-display area BB. Figure 1 shows that the display area AA and the display substrate 10 have the same shape, specifically a rectangle. However, this is merely an illustrative example. In other embodiments of the present disclosure, the display area AA and the display substrate 10 may have different shapes, for example, with some areas having corresponding arcs and right angles. The display substrate 10 includes a plurality of common electrodes arranged in an array within the display area AA and electrically isolated from each other. Each common electrode is shared by a plurality of pixels. Each pixel is coupled to only one common electrode. Similarly, in an embodiment of the present disclosure, the plurality of common electrodes are arranged in an array forming a rectangle. However, in other embodiments of the present disclosure, the plurality of common electrodes are arranged in an array forming other shapes. Such other shapes may be square or circular. The plurality of common electrodes include a first common electrode FCE and a second common electrode SCE. The first common electrodes FCE are located in odd rows and odd columns, or even rows and even columns. The second common electrodes SCE are located in odd rows and even columns, or even rows and odd columns. In an embodiment of the present disclosure, every two first common electrodes FCE are not adjacent in the row direction and the column direction. Every two second common electrodes SCE are not adjacent in the row direction and the column direction. The multiple common electrodes are divided into a plurality of electrode groups EG arranged in an array. In an embodiment of the present disclosure, all the common electrodes are evenly divided into 9 electrode groups forming a 3×3 array: EG1, EG2, EG3, EG4, EG5, EG6, EG7, EG8, and EG9. The first electrode group EG1 is located in the first row and first column, the second electrode group EG2 is located in the second row and first column, the third electrode group EG3 is located in the third row and first column, the fourth electrode group EG4 is located in the first row and second column, the fifth electrode group EG5 is located in the second row and second column, the sixth electrode group EG6 is located in the third row and second column, the seventh electrode group EG7 is located in the first row and third column, the eighth electrode group EG8 is located in the second row and third column, and the ninth electrode group is located in the third row and third column. In other embodiments of the present disclosure, the common electrodes can be unevenly divided into electrode groups EG based on the test pattern to be displayed or the needs of actual application. That is, different electrode groups EG can include different numbers of common electrodes, or different electrode groups EG can have different areas. The number of electrode groups EG can be other positive integers. The number of electrode groups EG should be less than the number of common electrodes. Each electrode group EG includes a first common electrode FCE and a second common electrode SCE. Each common electrode is shared by multiple pixels. A pixel is coupled to one and only one common electrode. Typically, pixels are arranged in an array.In an embodiment of the present disclosure, each electrode group EG includes nine first common electrodes FCE and nine second common electrodes SCE arranged in a 3×3 array. In other embodiments of the present disclosure, each electrode group EG may include other numbers of common electrodes or multiple common electrodes arranged in other arrays, for example, 160 common electrodes arranged in a 16×10 array.

[0057] The display substrate 10 also includes a test circuit TC. The test circuit TC is located within the non-display area BB and is used to provide test signals to multiple common electrodes to test the display substrate 10. The test circuit TC includes multiple sub-test circuits STC. The number of the multiple sub-test circuits STC is the same as the number of the multiple electrode groups EG. In an embodiment of the present disclosure, the test circuit TC includes nine sub-test circuits (not shown): a first sub-test circuit STC1, a second sub-test circuit STC2, a third sub-test circuit STC3, a fourth sub-test circuit STC4, a fifth sub-test circuit STC5, a sixth sub-test circuit STC6, a seventh sub-test circuit STC7, an eighth sub-test circuit STC8, and a ninth sub-test circuit STC9. The sub-test circuits STC correspond one-to-one to the electrode groups EG. Each sub-test circuit STC is coupled to a different respective electrode group in the electrode groups EG and provides a test signal to cause the display substrate 10 to display a test pattern. Specifically, the first sub-test circuit STC1 provides a test signal to the first electrode group EG1. The second sub-test circuit STC2 provides a test signal to the second electrode group EG2. The third sub-test circuit STC3 provides a test signal to the third electrode group EG3. The fourth sub-test circuit STC4 provides a test signal to the fourth electrode group EG4. The fifth sub-test circuit STC5 provides a test signal to the fifth electrode group EG5. The sixth sub-test circuit STC6 provides a test signal to the sixth electrode group EG6. The seventh sub-test circuit STC7 provides a test signal to the seventh electrode group EG7. The eighth sub-test circuit STC8 provides a test signal to the eighth electrode group EG8. The ninth sub-test circuit STC9 provides a test signal to the ninth electrode group EG9. The test circuits will be described in detail below by electrode group with reference to Figures 2 and 3.

[0058] The test pattern may include a pattern whose smallest display portion is a group of pixels of all common electrodes in a common electrode group, such as a checkerboard pattern, a square pattern, and an I-shaped pattern. The test pattern may also include a pattern whose smallest display portion is a group of pixels sharing a single common electrode, such as a checkerboard pattern. Displaying the above test patterns will be described in detail below with reference to Figures 8 to 15.

[0059] Figure 2 shows a schematic block diagram of a sub-test circuit according to an embodiment of the present disclosure. The sub-test circuit includes a first test signal line. The first test signal line provides a first test signal to the coupled first common electrode of the sub-test circuit. As shown in Figure 2, the sub-test circuit STC includes a first test signal line FTL. The first test signal line FTL provides a first test signal to the coupled first common electrode FCE of the sub-test circuit STC. In an embodiment of the present disclosure, the first test signal lines of each sub-test circuit can be different, and thus different first test signals can be provided to the coupled first common electrodes of different sub-test circuits.

[0060] The sub-test circuit includes a second test signal line. The second test signal line provides a second test signal to a second common electrode coupled to the sub-test circuit. As shown in FIG2 , the sub-test circuit STC includes a second test signal line STL. The second test signal line STL provides a second test signal to a second common electrode SCE of the sub-test circuit STC. In an embodiment of the present disclosure, the second test signal lines of each sub-test circuit may also be different, and thus different second test signals may be provided to the second common electrodes of different sub-test circuits.

[0061] The sub-test circuit includes a first test control signal line. The first test control signal line is coupled to the first test control circuit and provides a first test control signal to the first test control circuit. As shown in FIG2 , the sub-test circuit STC includes a first test control signal line FCL and provides the first test control signal to the first test control circuit 110. In embodiments of the present disclosure, the first test control signal line of each sub-test circuit can be the same, and thus the same first test control signal can be provided to each first test control circuit.

[0062] The sub-test circuit includes a first test control circuit. The first test control circuit is coupled between a first test signal line and a second test signal line, and couples the first test signal line to the second test signal line based on a first test control signal. As shown in FIG2 , the sub-test circuit STC includes a first test control circuit 110. The first test control circuit 110 is coupled between a first test signal line FTL and a second test signal line STL, and is configured to couple the first test signal line FTL to the second test signal line STL based on a second test control signal, so that the first test signal and the second test signal provided to the electrode group EG of the sub-test circuit STC are the same.

[0063] The sub-test circuit includes a second test control signal line. The second test control signal line is connected to the second test control circuit and provides a second test control signal to the second test control circuit. As shown in FIG2 , the sub-test circuit STC includes a second test control signal line SCL and provides the second test control signal to the second test control circuit 120. In the embodiments of the present disclosure, the second test control signal line SCL of each sub-test circuit can be the same, and thus the same second control test signal can be provided to each second test control circuit.

[0064] The sub-test circuit includes a second test control circuit. The second test control circuit is coupled between the first common electrode and the first test signal line of the sub-test circuit, or between the second common electrode and the second test signal line of the sub-test circuit, and is used to couple the first common electrode and the second common electrode to the first test signal line and the second test signal line of the sub-test circuit, respectively, based on a second test control signal. As shown in FIG2 , the sub-test circuit STC1 includes a second test control circuit 120. The second test control circuit 120 is coupled between the first common electrode FCE and the first test signal line FTL, or between the second common electrode SCE and the second test signal line STL, and is used to couple the first common electrode FCE to the first test signal line FTL and the second common electrode SCE to the second test signal line STL based on the second test control signal. By providing the second test control circuit 120, interference from the test circuit can be prevented when the display substrate is normally used to display images. The first test control circuit 110 and the second test control circuit 120 are described in detail below with reference to FIG3 .

[0065] Fig. 3 shows a schematic block diagram of a sub-test circuit according to another embodiment of the present disclosure. Fig. 3 exemplarily shows a sub-test circuit STC.

[0066] The first test control circuit includes a first control transistor. The control electrode of the first control transistor is coupled to the first test control signal line, the first electrode of the first control transistor is coupled to the first test signal line, and the second electrode of the first control transistor is coupled to the second test signal line. As shown in Figure 3, the first test control circuit 110 includes a first control transistor T1. The control electrode G of the first control transistor T1 is coupled to the first test control signal line FCL, the first electrode F of the first control transistor T1 is coupled to the first test signal line FTL, and the second electrode S of the first control transistor T1 is coupled to the second test signal line STL. In other embodiments of the present disclosure, the first test control circuit 110 may include other numbers of first control transistors T1, for example, three. This embodiment will be described below with reference to Figures 4 to 6 and will not be repeated here.

[0067] The second test control circuit includes a second control transistor and a third control transistor. As shown in Figure 3, the second test control circuit 120 includes second control transistors T21, T22, T23, T24, and T25. The second test control circuit 120 includes third control transistors T31, T32, T33, and T34. In an embodiment of the present disclosure, the second test control circuit 120 includes 5 second control transistors and 4 third control transistors. In other embodiments of the present disclosure, the second test control circuit may include other numbers of second control transistors and third control transistors. The second control transistors correspond one-to-one to the first common electrodes in the electrode group corresponding to the sub-test circuit, and the number is equal. The control electrode of the second control transistor is coupled to the second test control signal line, the first electrode of the second control transistor is coupled to the first test signal line, and the second electrode of the second control transistor is coupled to the first common electrode. As shown in Figure 3, the control electrodes G of the second control transistors T21, T22, T23, T24, and T25 are coupled to the second test control signal line SCL, the first electrodes of the second control transistors T21, T22, T23, T24, and T25 are coupled to the first test signal line FTL1, and the second electrodes of the second control transistors T21, T22, T23, T24, and T25 are coupled to the first common electrode FCE.

[0068] The control electrodes of the third control transistors are coupled to the second test control signal line, the first electrodes of the third control transistors are coupled to the second test signal line, and the second electrodes of the third control transistors are coupled to the second common electrode. The third control transistors correspond one-to-one to the second common electrodes coupled to the sub-test circuits, and the number of the third control transistors is equal. As shown in FIG3 , the control electrodes G of the third control transistors T31, T32, T33, and T34 are coupled to the second test control signal line SCL, the first electrodes F of the third control transistors T31, T32, T33, and T34 are coupled to the second test signal line STL, and the second electrodes S of the third control transistors T31, T32, T33, and T34 are coupled to the second common electrode SCE.

[0069] In an embodiment of the present disclosure, the first control transistor T1, the second control transistor T2, and the third control transistor T3 are all N-type MOS transistors. In other embodiments of the present disclosure, the first control transistor T1, the second control transistor T2, and the third control transistor T3 may all be P-type MOS transistors. In addition, at least two of the first control transistor T1, the second control transistor T2, and the third control transistor T3 may be of different types.

[0070] For the nine electrode groups shown in FIG1 , the first test signal line includes nine sub-test signal lines, namely, the first sub-test signal line to the ninth sub-test signal line, which provide the first sub-test signal to the ninth sub-test signal, respectively. The second test signal line includes nine sub-test signal lines, namely, the tenth sub-test signal line to the eighteenth sub-test signal line, which provide the tenth sub-test signal to the eighteenth sub-test signal, respectively. The first control transistor includes the first sub-control transistor to the ninth sub-control transistor. The second control transistor includes the tenth sub-control transistor to the eighteenth sub-control transistor. The third control transistor includes the nineteenth sub-control transistor to the twenty-seventh sub-control transistor.

[0071] Figure 4 shows a schematic block diagram of a test circuit for the first column of common electrodes in Figure 1 according to an embodiment of the present disclosure. As shown in Figure 4, the first three common electrodes in the first column of common electrodes (two first common electrodes FCE and one second common electrode SCE) are located in the first electrode group EG1, the middle three common electrodes (two second common electrodes SCE and one first common electrode FCE) are located in the second electrode group EG2, and the last three common electrodes (two first common electrodes FCE and one second common electrode SCE) are located in the third electrode group EG3. The first control transistor T1 includes a first sub-control transistor T111, a second sub-control transistor T121, and a third sub-control transistor T131. The first test signal line FTL includes a first sub-test signal line FTL1, a second sub-test signal line FTL2, and a third sub-test signal line FTL3. The second test signal line STL includes a tenth sub-test signal line STL1, an eleventh sub-test signal line STL2, and a twelfth sub-test signal line STL3.

[0072] A control electrode G of the first sub-control transistor T111 is coupled to the first test control signal line FCL, a first electrode F of the first sub-control transistor T111 is coupled to the first sub-test signal line FTL1, and a second electrode S of the first sub-control transistor T111 is coupled to the tenth sub-test signal line STL1. The first sub-control transistor T111 is configured to couple the first sub-test signal line FTL1 to the tenth sub-test signal line STL1 based on a first test control signal from the first test control signal line, so that the first sub-test signal from the first sub-test signal line FTL1 is the same as the tenth sub-test signal from the tenth sub-test signal line STL1.

[0073] The control electrode G of the second sub-control transistor T121 is coupled to the first test control signal line FCL, the first electrode F of the second sub-control transistor T121 is coupled to the second sub-test signal line FTL2, and the second electrode S of the second sub-control transistor T121 is coupled to the eleventh sub-test signal line STL2. The second sub-control transistor T121 is configured to couple the second sub-test signal line FTL2 to the eleventh sub-test signal line STL2 based on the first test control signal from the first test control signal line FCL, so that the second sub-test signal from the second sub-test signal line FTL2 is the same as the eleventh sub-test signal from the eleventh sub-test signal line STL2.

[0074] A control electrode G of the third sub-control transistor T131 is coupled to the first test control signal line FCL, a first electrode F of the third sub-control transistor T131 is coupled to the third sub-test signal line FTL3, and a second electrode S of the third sub-control transistor T131 is coupled to the twelfth sub-test signal line STL3. The third sub-control transistor T131 is configured to couple the third sub-test signal line FTL3 to the twelfth sub-test signal line STL3 based on the first test control signal from the first test control signal line FCL, so that the third sub-test signal from the third sub-test signal line FTL3 is the same as the twelfth sub-test signal from the twelfth sub-test signal line STL3.

[0075] The second control transistor T2 includes a tenth sub-control transistor T211 and T221 , an eleventh sub-control transistor T231 , and twelfth sub-control transistors T241 and T251 .

[0076] The gate electrodes G of the tenth sub-control transistors T211 and T221 , the eleventh sub-control transistor T231 , and the twelfth sub-control transistors T241 and T251 are all coupled to the second test control signal line SCL.

[0077] The first electrodes F of the tenth sub-control transistors T211 and T221 are coupled to the first sub-test signal line FTL1, and the second electrodes of the tenth sub-control transistors T211 and T221 are coupled to the first common electrode FCE in the first electrode group EG1, for providing the first sub-test signal from the first sub-test signal line FTL1 to the first common electrode FCE in the first electrode group EG1.

[0078] The first electrode F of the eleventh sub-control transistor T231 is coupled to the second sub-test signal line FTL2, and the second electrode S of the eleventh sub-control transistor T231 is coupled to the first common electrode FCE in the second electrode group EG2, for providing the second sub-test signal from the second sub-test signal line FTL2 to the first common electrode FCE in the second electrode group EG2.

[0079] The first electrode F of the twelfth sub-control transistors T241 and T251 is coupled to the third sub-test signal line FTL3, and the second electrode S of the twelfth sub-control transistors T241 and T251 is coupled to the first common electrode FCE in the third electrode group EG3, for providing the third sub-test signal from the third sub-test signal line FTL3 to the first common electrode FCE in the second electrode group EG3.

[0080] The third control transistor T3 includes a nineteenth sub-control transistor T311 , twentieth sub-control transistors T321 and T331 , and a twenty-first sub-control transistor T341 .

[0081] The gate electrodes G of the nineteenth sub-control transistor T311 , the twentieth sub-control transistors T321 and T331 , and the twenty-first sub-control transistor T341 are all coupled to the second test control signal line SCL.

[0082] The first electrode F of the nineteenth sub-control transistor T311 is coupled to the tenth sub-test signal line STL1, and the second electrode S of the nineteenth sub-control transistor T311 is coupled to the second common electrode SCE in the first electrode group EG1, for providing the tenth sub-test signal from the tenth sub-test signal line STL1 to the second common electrode SCE in the first electrode group EG1.

[0083] The first electrode F of the twentieth sub-control transistors T321 and T331 is coupled to the eleventh sub-test signal line STL2, and the second electrode S of the twentieth sub-control transistors T321 and T331 is coupled to the second common electrode SCE in the second electrode group EG2, for providing the eleventh sub-test signal from the eleventh sub-test signal line STL2 to the second common electrode SCE in the second electrode group EG2.

[0084] The first electrode F of the twenty-first sub-control transistor T341 is coupled to the twelfth sub-test signal line STL3, and the second electrode S of the twenty-first sub-control transistor T341 is coupled to the second common electrode SCE in the third electrode group EG3, for providing the twelfth sub-test signal from the twelfth sub-test signal line STL3 to the second common electrode SCE in the third electrode group EG3.

[0085] For the second column of common electrodes, the first electrode group EG1 sequentially includes the second common electrode SCE, the first common electrode FCE, and the second common electrode SCE. The second electrode group EG2 sequentially includes the first common electrode FCE, the second common electrode SCE, and the first common electrode FCE. The third electrode group EG3 sequentially includes the second common electrode SCE, the first common electrode FCE, and the second common electrode SCE. The difference from FIG4 is that the first sub-test signal line FTL1 is coupled to one of the first common electrodes FCE in the first electrode group EG1. The tenth sub-test signal line STL1 is coupled to two second common electrodes SCE in the first electrode group EG1. The second sub-test signal line FTL2 is coupled to two first common electrodes FCE in the second electrode group EG2. The eleventh sub-test signal line STL2 is coupled to one of the second common electrodes SCE in the second electrode group EG2. The third sub-test signal line FTL3 is coupled to one of the first common electrodes FCE in the third electrode group EG3. The twelfth sub-test signal line STL3 is coupled to two second common electrodes SCE in the third electrode group EG3. The test circuit for the third column of common electrodes is the same as the test circuit shown in FIG4 and will not be described in detail here. In some embodiments, the test circuits for the common electrodes in odd columns and even columns in the same electrode group EG are different. The difference is that the arrangement order of the first common electrodes FCE and the second common electrodes SCE in adjacent columns is staggered, and the number of first common electrodes FCE and second common electrodes SCE connected to the same test signal line in the corresponding circuit varies. It should be noted that the widths of the first common electrodes FCE and the second common electrodes SCE in the column direction as shown in FIG4-6 are schematic. In actual products, the widths of the first common electrodes FCE and the second common electrodes SCE in the column direction are approximately equal to their widths in the row direction.

[0086] In an embodiment of the present disclosure, as shown in FIG4 , each electrode group EG includes 9 first common electrodes FCE and second common electrodes SCE arranged in a 3×3 array. The sum of the number of first common electrodes FCE and second common electrodes SCE connected to FTL1 and STL1 in the test circuit corresponding to one column of common electrodes is 3. In other embodiments of the present disclosure, each electrode group EG may include other numbers of common electrodes or multiple common electrodes arranged in other arrays, for example, 160 common electrodes arranged in a 16×10 array (16 columns and 10 rows), and the sum of the number of first common electrodes FCE and second common electrodes SCE connected to FTL1 and STL1 in the test circuit corresponding to one column of common electrodes is 10.

[0087] FIG5 shows a schematic block diagram of a test circuit for the fourth column common electrode in FIG1 according to an embodiment of the present disclosure. The first test signal line FTL includes a fourth sub-test signal line FTL4, a fifth sub-test signal line FTL5, and a sixth sub-test signal line FTL6. The second test signal line STL includes a thirteenth sub-test signal line STL4, a fourteenth sub-test signal line STL5, and a sixteenth sub-test signal line STL6.

[0088] The first control transistor T1 includes a fourth sub-control transistor T144 , a fifth sub-control transistor T154 , and a sixth sub-control transistor T164 .

[0089] A control electrode G of the fourth sub-control transistor T144 is coupled to the first test control signal line FCL, a first electrode F of the fourth sub-control transistor T144 is coupled to the fourth sub-test signal line FTL4, and a second electrode S of the fourth sub-control transistor T144 is coupled to the thirteenth sub-test signal line STL4. The fourth sub-control transistor T144 is configured to couple the fourth sub-test signal line FTL4 to the thirteenth sub-test signal line STL4 based on the first test control signal from the first test control signal line FCL, so that the fourth sub-test signal from the fourth sub-test signal line FTL4 is the same as the thirteenth sub-test signal from the thirteenth sub-test signal line STL4.

[0090] A control electrode G of the fifth sub-control transistor T154 is coupled to the first test control signal line FCL, a first electrode F of the fifth sub-control transistor T154 is coupled to the fifth sub-test signal line FTL5, and a second electrode S of the fifth sub-control transistor T154 is coupled to the fourteenth sub-test signal line STL5. The fifth sub-control transistor T154 is configured to couple the fifth sub-test signal line FTL5 to the fourteenth sub-test signal line STL5 based on the first test control signal from the first test control signal line FCL, so that the fifth sub-test signal from the fifth sub-test signal line FTL5 is the same as the fourteenth sub-test signal from the fourteenth sub-test signal line STL5.

[0091] A control electrode G of the sixth sub-control transistor T164 is coupled to the first test control signal line FCL, a first electrode F of the sixth sub-control transistor T164 is coupled to the sixth sub-test signal line FTL6, and a second electrode S of the sixth sub-control transistor T164 is coupled to the fifteenth sub-test signal line STL6. The sixth sub-control transistor T164 is configured to couple the sixth sub-test signal line FTL6 to the fifteenth sub-test signal line STL6 based on the first test control signal from the first test control signal line FCL, so that the sixth sub-test signal from the sixth sub-test signal line FTL6 is the same as the fifteenth sub-test signal from the fifteenth sub-test signal line STL6.

[0092] The second control transistor T2 includes a thirteenth sub-control transistor T214 , fourteenth sub-control transistors T224 and T234 , and a fifteenth sub-control transistor T244 .

[0093] The gate electrodes G of the thirteenth sub-control transistor T214 , the fourteenth sub-control transistors T224 and T234 , and the fifteenth sub-control transistor T244 are all coupled to the second test control signal line SCL.

[0094] The first electrode F of the thirteenth sub-control transistor T214 is coupled to the fourth sub-test signal line FTL4, and the second electrode S of the thirteenth sub-control transistor T214 is coupled to the first common electrode FCE in the fourth electrode group EG4, for providing the fourth sub-test signal from the fourth sub-test signal line FTL4 to the first common electrode FCE in the fourth electrode group EG4.

[0095] The first electrode F of the fourteenth sub-control transistors T224 and T234 is coupled to the fifth sub-test signal line FTL5, and the second electrode S of the fourteenth sub-control transistors T224 and T234 is coupled to the first common electrode FCE in the fifth electrode group EG5, for providing the fifth sub-test signal from the fifth sub-test signal line FTL5 to the first common electrode FCE in the fifth electrode group EG5.

[0096] The first electrode F of the fifteenth sub-control transistor T244 is coupled to the sixth sub-test signal line FTL6, and the second electrode S of the fifteenth sub-control transistor T244 is coupled to the first common electrode FCE in the sixth electrode group EG6, for providing the sixth sub-test signal from the sixth sub-test signal line FTL6 to the first common electrode FCE in the sixth electrode group EG6.

[0097] The third control transistor T3 includes twenty-second sub-control transistors T314 and T324 , a twenty-third sub-control transistor T334 , and twenty-fourth sub-control transistors T344 and T354 .

[0098] The first electrode F of the twenty-second sub-control transistors T314 and T324 is coupled to the thirteenth sub-test signal line STL4, and the second electrode S of the twenty-second sub-control transistors T314 and T324 is coupled to the second common electrode SCE in the fourth electrode group EG4, for providing the thirteenth sub-test signal from the thirteenth sub-test signal line STL4 to the second common electrode SCE in the fourth electrode group EG4.

[0099] The first electrode F of the twenty-third sub-control transistor T334 is coupled to the fourteenth sub-test signal line STL5, and the second electrode S of the twenty-third sub-control transistor STL4 is coupled to the second common electrode SCE in the fifth electrode group EG5, for providing the fourteenth sub-test signal from the fourteenth sub-test signal line STL5 to the second common electrode SCE in the fifth electrode group EG5.

[0100] The first electrode F of the twenty-fourth sub-control transistors T344 and T354 is coupled to the fifteenth sub-test signal line STL6, and the second electrode S of the twenty-fourth sub-control transistors T344 and T354 is coupled to the second common electrode SCE in the sixth electrode group EG6, for providing the fifteenth sub-test signal from the fifteenth sub-test signal line STL6 to the second common electrode SCE in the sixth electrode group EG6.

[0101] For the fifth column of common electrodes, the fourth electrode group EG4 sequentially includes a first common electrode FCE, a second common electrode SCE, and a first common electrode FCE. The fifth electrode group EG5 sequentially includes a second common electrode SCE, a first common electrode FCE, and a second common electrode SCE. The sixth electrode group EG3 includes a first common electrode FCE, a second common electrode SCE, and a first common electrode FCE. The difference from FIG5 is that the fourth sub-test signal line FTL4 is coupled to the two first common electrodes FCE in the fourth electrode group EG4. The thirteenth sub-test signal line STL4 is coupled to one second common electrode SCE in the fourth electrode group EG4. The fifth sub-test signal line FTL5 is coupled to one first common electrode FCE in the fifth electrode group EG5. The fourteenth sub-test signal line STL5 is coupled to the two second common electrodes SCE in the fifth electrode group EG5. The sixth sub-test signal line FTL6 is coupled to the two first common electrodes FCE in the sixth electrode group EG6. The fifteenth sub-test signal line STL6 is coupled to one second common electrode SCE in the sixth electrode group EG6. The test circuit for the sixth column of common electrodes is the same as the test circuit shown in FIG5 , and will not be described again here.

[0102] FIG6 shows a schematic block diagram of a test circuit for the seventh column common electrode in FIG1 according to an embodiment of the present disclosure. The first test signal line FTL includes a seventh sub-test signal line FTL7, an eighth sub-test signal line FTL8, and a ninth sub-test signal line FTL9. The second test signal line STL includes a sixteenth sub-test signal line STL7, an eighteenth sub-test signal line STL8, and a nineteenth sub-test signal line STL9.

[0103] The first control transistor T1 includes a seventh sub-control transistor T177 , an eighth sub-control transistor T187 , and a ninth sub-control transistor T197 .

[0104] A control electrode G of the seventh sub-control transistor T177 is coupled to the first test control signal line FCL, a first electrode F of the seventh sub-control transistor T177 is coupled to the seventh sub-test signal line FTL7, and a second electrode S of the seventh sub-control transistor T177 is coupled to the sixteenth sub-test signal line STL7. The seventh sub-control transistor T177 is configured to couple the seventh sub-test signal line FTL7 to the sixteenth sub-test signal line STL7 based on the first test control signal from the first test control signal line FCL, so that the seventh sub-test signal from the seventh sub-test signal line FTL7 is the same as the sixteenth sub-test signal from the sixteenth sub-test signal line STL7.

[0105] A control electrode G of the eighth sub-control transistor T187 is coupled to the first test control signal line FCL, a first electrode F of the eighth sub-control transistor T187 is coupled to the eighth sub-test signal line FTL8, and a second electrode S of the eighth sub-control transistor T187 is coupled to the seventeenth sub-test signal line STL8. The eighth sub-control transistor T187 is configured to couple the eighth sub-test signal line FTL8 to the seventeenth sub-test signal line STL8 based on the first test control signal from the first test control signal line FCL, so that the eighth sub-test signal from the eighth sub-test signal line FTL8 is the same as the seventeenth sub-test signal from the seventeenth sub-test signal line STL8.

[0106] A control electrode G of the ninth sub-control transistor T197 is coupled to the first test control signal line FCL, a first electrode F of the ninth sub-control transistor T197 is coupled to the ninth sub-test signal line FTL9, and a second electrode S of the ninth sub-control transistor T197 is coupled to the eighteenth sub-test signal line STL9. The ninth sub-control transistor T197 is configured to couple the ninth sub-test signal line FTL9 to the eighteenth sub-test signal line STL9 based on the first test control signal from the first test control signal line FCL, so that the ninth sub-test signal from the ninth sub-test signal line FTL9 is the same as the eighteenth sub-test signal from the eighteenth sub-test signal line STL9.

[0107] The second control transistor T2 includes sixteenth sub-control transistors T217 and T227 , a seventeenth sub-control transistor T237 , and eighteenth sub-control transistors T247 and T257 .

[0108] The gate electrodes G of the sixteenth sub-control transistors T217 and T227 , the seventeenth sub-control transistor T237 , and the eighteenth sub-control transistors T247 and T257 are all coupled to the second test control signal line SCL.

[0109] The first electrode F of the sixteenth sub-control transistors T217 and T227 is coupled to the seventh sub-test signal line FTL7, and the second electrode S of the sixteenth sub-control transistors T217 and T227 is coupled to the first common electrode FCE in the seventh electrode group EG7, for providing the seventh sub-test signal from the seventh sub-test signal line FTL7 to the first common electrode FCE in the seventh electrode group EG7.

[0110] The first electrode F of the seventeenth sub-control transistor T237 is coupled to the eighth sub-test signal line FTL8, and the second electrode S of the seventeenth sub-control transistor T237 is coupled to the first common electrode FCE in the eighth electrode group EG8, for providing the eighth sub-test signal from the eighth sub-test signal line FTL8 to the first common electrode FCE in the eighth electrode group EG8.

[0111] The first electrode F of the eighteenth sub-control transistors T247 and T257 is coupled to the ninth sub-test signal line FTL9, and the second electrode S of the eighteenth sub-control transistors T247 and T257 is coupled to the first common electrode FCE in the ninth electrode group EG9, for providing the ninth sub-test signal from the ninth sub-test signal line FTL9 to the first common electrode FCE in the ninth electrode group EG9.

[0112] The third control transistor T3 includes a twenty-fifth sub-control transistor T317 , twenty-sixth sub-control transistors T327 and T337 , and a twenty-seventh sub-control transistor T347 .

[0113] The first electrode F of the twenty-fifth sub-control transistor T317 is coupled to the sixteenth sub-test signal line STL7, and the second electrode S of the twenty-fifth sub-control transistor T317 is coupled to the second common electrode SCE in the seventh electrode group EG7, for providing the sixteenth sub-test signal from the sixteenth sub-test signal line STL7 to the second common electrode SCE in the seventh electrode group EG7.

[0114] The first electrode F of the twenty-sixth sub-control transistors T327 and T337 is coupled to the seventeenth sub-test signal line STL8, and the second electrode S of the twenty-sixth sub-control transistors T327 and T337 is coupled to the second common electrode SCE in the eighth electrode group EG8, for providing the seventeenth sub-test signal from the seventeenth sub-test signal line STL8 to the second common electrode SCE in the eighth electrode group EG8.

[0115] The first electrode F of the twenty-seventh sub-control transistor T347 is coupled to the eighteenth sub-test signal line STL9, and the second electrode S of the twenty-seventh sub-control transistor T347 is coupled to the second common electrode SCE in the ninth electrode group EG9, for providing the eighteenth sub-test signal from the eighteenth sub-test signal line STL9 to the second common electrode SCE in the ninth electrode group EG9.

[0116] For the seventh column of common electrodes, the seventh electrode group EG7 sequentially includes the second common electrode SCE, the first common electrode FCE, and the second common electrode SCE. The eighth electrode group EG8 sequentially includes the first common electrode FCE, the second common electrode SCE, and the first common electrode FCE. The ninth electrode group EG9 sequentially includes the second common electrode SCE, the first common electrode FCE, and the second common electrode SCE. The difference from FIG6 is that the seventh sub-test signal line FTL7 is coupled to one of the first common electrodes FCE in the seventh electrode group EG7. The sixteenth sub-test signal line STL7 is coupled to two second common electrodes SCE in the seventh electrode group EG7. The eighth sub-test signal line FTL8 is coupled to two first common electrodes FCE in the eighth electrode group EG8. The seventeenth sub-test signal line STL8 is coupled to one of the second common electrodes SCE in the eighth electrode group EG8. The ninth sub-test signal line FTL9 is coupled to one of the first common electrodes FCE in the ninth electrode group EG9. The eighteenth sub-test signal line STL9 is coupled to two second common electrodes SCE in the ninth electrode group EG9. The test circuit for the ninth column of common electrodes is the same as the test circuit shown in FIG6 , and will not be described again here.

[0117] Furthermore, in actual display substrate applications, a test circuit is located above the common electrodes and provides test signals to the common electrode columns along the column direction. Specifically, as shown in Figures 4-6, the test circuit connected to a column of common electrodes is located in the same column direction as the column of common electrodes, and the test circuit connected to a column of common electrodes is located at one end of the column of common electrodes. In some embodiments, the connection lines TX between a column of common electrodes and the test circuit extend along the column direction and are arranged sequentially along the row direction. The multiple connection lines TX coupling a column of common electrodes to the test circuit do not cross each other. This layout facilitates the fabrication of multiple connection lines TX on the same layer, saving process steps. In some embodiments, the width of a column of common electrodes along the row direction is approximately equal to the width of the test circuit connected to the column of common electrodes along the row direction. This maximizes the use of space in the row direction and further reduces the width of the test circuit in the column direction, facilitating a narrow bezel. In some embodiments, the connection lines TX can be touch signal lines or common electrode signal lines. The connection lines TX can be multiplexed, serving as touch signal lines during touch control and as common electrode signal lines during display control. The common electrode EG is multiplexed as a touch electrode during touch control.

[0118] As shown in Figure 3, a schematic block diagram of a sub-test circuit corresponding to an electrode group is provided. In some embodiments, a sub-test circuit STC1 includes test circuits distributed above multiple columns of common electrodes. For example, as shown in Figure 4, a sub-test circuit STC1 includes test circuit parts connected to FTL1 and STL1 in the test circuits corresponding to the first column of common electrodes, the second column of common electrodes, and the third column of common electrodes, respectively.

[0119] The present disclosure also provides a top view of a sub-test circuit. Figure 7 shows a top view of a sub-test circuit according to an embodiment of the present disclosure. For clarity, Figure 7 shows only a partial structure of a sub-test circuit STC. In the sub-test circuit STC, only a second control transistor T2 coupled to a first common electrode FCE and a third control transistor T3 coupled to a second common electrode SCE are shown, but this is not a limitation. For clarity, Figure 7 shows only three material layers, namely the first conductive layer L1, the second conductive layer L2, and the semiconductor layer L3. As shown in Figure 7, the sub-test circuit STC includes a second test control signal line SCL, a first test control signal line FCL, a first test signal line FTL, and a second test signal line STL1, which are arranged in sequence along a second direction (e.g., the Y direction) and are located in the first conductive layer L1. The sub-test circuit STC1 also includes a first control transistor T1, which is located between the first test signal line FTL and the second test signal line STL. The sub-test circuit STC also includes a second control transistor T2 and a third control transistor T3, which are located between the second test control signal line SCL and the first test control signal line FCL. The first control transistor T1 includes a control electrode G located in the second conductive layer L2, a first electrode F and a second electrode S located in the first conductive layer L1, and an active layer located in the semiconductor layer L3 between the control electrode G and the first electrode F and between the control electrode G and the second electrode S. The second control transistor T2 and the third control transistor T3 include a control electrode G located in the second conductive layer L2, a first electrode F and a second electrode S located in the first conductive layer L1, and an active layer located in the semiconductor layer L3 between the first electrode F and the second electrode S.

[0120] As previously described, the control electrode G of the first control transistor T1 is coupled to the first test control signal line FCL, the first electrode F of the first control transistor T1 is coupled to the first test signal line FTL, and the second electrode S of the first control transistor T1 is coupled to the second test signal line STL. The control electrode G of the second control transistor T2 is coupled to the second test control signal line SCL, the first electrode F of the second control transistor T is coupled to the first test signal line FTL, and the second electrode S of the second control transistor T2 is coupled to the first common electrode FCE. The control electrode G of the third control transistor T3 is coupled to the second test control signal line SCL, the first electrode F of the third control transistor T3 is coupled to the second test signal line STL, and the second electrode S of the third control transistor T3 is coupled to the second common electrode SCE. Details thereof will not be repeated here. As shown in FIG. 7 , the connections between the different film layers in the first conductive layer L1, the second conductive layer L2, and the semiconductor layer L3 are connected through vias VIA. In this embodiment, the signal lines used to couple the above components are all located in the second conductive layer L2.

[0121] It should be understood that this embodiment is for illustration only, and those skilled in the art can adjust the positions of various components as needed.

[0122] Figure 8 shows a schematic block diagram of a display substrate displaying a checkerboard pattern according to an embodiment of the present disclosure. In this embodiment, the checkerboard pattern comprises a pixel group that shares all common electrodes in each electrode group as the smallest display portion. The common electrodes and electrode groups of display substrate 20 and display substrate 10 are configured identically. As previously described, in other embodiments of the present disclosure, the common electrodes and electrode groups may have other configurations. As shown in Figure 8, the pixel groups corresponding to electrode groups EG1, EG3, EG5, EG7, and EG9 maintain a first state, while the pixel groups corresponding to electrode groups EG2, EG4, EG6, and EG8 maintain a second state. The first state is an unlit state, and the second state is an illuminated state. In other embodiments of the present disclosure, the first state is either an illuminated state or an unlit state, and the second state is either an illuminated state or an unlit state. In embodiments of the present disclosure, the grayscale of the illuminated state can be set according to the requirements of the embodiment. In embodiments of the present disclosure, within the same checkerboard pattern, the pre-set grayscale corresponding to the unlit state is consistent, and the pre-set grayscale corresponding to the illuminated state is consistent.

[0123] Figure 9 shows a timing diagram according to an embodiment of the present disclosure for displaying the test pattern of Figure 8. It should be understood that the signal voltages shown in the timing diagram are only schematic and do not represent actual voltage values.

[0124] As shown in Figure 9, during test phase ①, the first test control signal line FCL provides a high-level first test control signal Ctr1, turning on the first control transistor T1. The first control transistor T1 couples the first test signal line to the second test signal line, and the first test signal and the second test signal are identical. In other embodiments of the present disclosure, the first test control signal line FCL provides a low-level first test control signal Ctr1, turning off the first control transistor T1. This allows different first and second test signals to be provided.

[0125] The second test control signal line SCL provides a high-level second test control signal Ctr2, turning on the second control transistor T2 and the third control transistor T3. The second control transistor T2 provides the first test signal FTS to the first common electrode FCE. The third control transistor T3 provides the second test signal STS to the second common electrode SCE. In other embodiments of the present disclosure, the second test control signal line SCL provides a high-level second test control signal Ctr2, turning on the second control transistor T2 and the third control transistor T3.

[0126] In an embodiment of the present disclosure, for electrode groups EG1, EG3, EG5, EG7, and EG9, the first sub-test signal FTS1 is the same as the tenth sub-test signal STS1, the third sub-test signal FTS3 is the same as the twelfth sub-test signal STS3, the fifth sub-test signal FTS5 is the same as the fourteenth sub-test signal STS5, the seventh sub-test signal FTS7 is the same as the sixteenth sub-test signal STS7, and the ninth sub-test signal FTS9 is the same as the eighteenth sub-test signal STS9, and all are at a low level. The pixel groups corresponding to electrode groups EG1, EG3, EG5, EG7, and EG9 remain unlit.

[0127] In the embodiment of the present disclosure, for electrode groups EG2, EG4, EG6, and EG8, the second sub-test signal FTS2 is the same as the eleventh sub-test signal STS2, the fourth sub-test signal FTS4 is the same as the thirteenth sub-test signal STS4, the sixth sub-test signal FTS6 is the same as the fifteenth sub-test signal STS6, and the eighth sub-test signal FTS8 is the same as the seventeenth sub-test signal STS8, and all are at a high level. The pixel groups corresponding to electrode groups EG2, EG4, EG6, and EG8 remain illuminated.

[0128] In other embodiments of the present disclosure, the pixel groups corresponding to the electrode groups EG1, EG3, EG5, EG7, and EG9 may remain in a lit state, and the pixel groups corresponding to the electrode groups EG2, EG4, EG6, and EG8 may remain in an unlit state.

[0129] Figure 10 shows a schematic block diagram of a display substrate displaying a U-shaped pattern according to an embodiment of the present disclosure. In an embodiment, the U-shaped pattern has a pixel group that shares all common electrodes in each electrode group as the smallest display portion. The display substrate 30 has the same arrangement of common electrodes and electrode groups as the display substrate 10. As previously mentioned, in other embodiments of the present disclosure, the common electrodes and electrode groups may have other arrangements. As shown in Figure 10, the pixel groups corresponding to electrode groups EG1, EG2, EG3, EG4, EG6, EG7, EG8, and EG9 all remain in an unlit state, and the pixel group corresponding to electrode group EG5 remains in a lit state.

[0130] FIG. 11 shows a timing diagram for displaying the U-shaped pattern in FIG. 10 according to an embodiment of the present disclosure.

[0131] The difference between FIG. 11 and FIG. 9 is that, in test phase ①, for electrode groups EG1, EG2, EG3, EG4, EG6, EG7, EG8, and EG9, the first sub-test signal FTS1 is the same as the tenth sub-test signal STS1, the second sub-test signal FTS2 is the same as the eleventh sub-test signal STS2, the third sub-test signal FTS3 is the same as the twelfth sub-test signal STS3, the fourth sub-test signal FTS4 is the same as the thirteenth sub-test signal STS4, the sixth sub-test signal FTS6 is the same as the fifteenth sub-test signal STS6, the seventh sub-test signal FTS7 is the same as the sixteenth sub-test signal STS7, the eighth sub-test signal FTS8 is the same as the seventeenth sub-test signal STS8, and the ninth sub-test signal FTS9 is the same as the eighteenth sub-test signal STS9, and all are at a low level. The pixel groups corresponding to electrode groups EG1, EG2, EG3, EG4, EG6, EG7, EG8, and EG9 remain unlit. In the embodiment of the present disclosure, for the electrode group EG5, the fifth sub-test signal FTS5 is the same as the fourteenth sub-test signal STS5 and both are at a high level. The pixel group corresponding to the electrode group EG5 remains in a light state.

[0132] Figure 12 shows a schematic block diagram of a display substrate displaying an I-shaped pattern according to an embodiment of the present disclosure. In an embodiment, the I-shaped pattern has a pixel group that shares all common electrodes in each electrode group as the smallest display portion. The display substrate 40 has the same arrangement of common electrodes and electrode groups as the display substrate 10. As previously mentioned, in other embodiments of the present disclosure, the common electrodes and electrode groups may have other arrangements. As shown in Figure 12, the pixel groups corresponding to electrode groups EG1, EG3, EG4, EG5, EG6, EG7, and EG9 all remain unlit, while the pixel groups corresponding to electrode groups EG2 and EG8 remain lit.

[0133] FIG. 13 illustrates a timing diagram for displaying the test pattern of FIG. 12 according to an embodiment of the present disclosure.

[0134] The difference between FIG. 13 and FIG. 9 is that, in test phase ①, for electrode groups EG1, EG3, EG4, EG5, EG6, EG7, and EG9, the first sub-test signal FTS1 is the same as the tenth sub-test signal STS1, the third sub-test signal FTS3 is the same as the twelfth sub-test signal STS3, the fourth sub-test signal FTS4 is the same as the thirteenth sub-test signal STS4, the fifth sub-test signal FTS5 is the same as the fourteenth sub-test signal STS5, the sixth sub-test signal FTS6 is the same as the fifteenth sub-test signal STS6, the seventh sub-test signal FTS7 is the same as the sixteenth sub-test signal STS7, and the ninth sub-test signal FTS9 is the same as the eighteenth sub-test signal STS9, and all are at a low level. The pixel groups corresponding to electrode groups EG1, EG3, EG4, EG5, EG6, EG7, and EG9 remain unlit. In the embodiment of the present disclosure, for electrode groups EG2 and EG8, the second sub-test signal FTS2 is the same as the eleventh sub-test signal STS2, and the eighth sub-test signal FTS8 is the same as the seventeenth sub-test signal STS8, and both are at a high level. The pixel groups corresponding to electrode groups EG2 and EG8 remain illuminated.

[0135] Taking the square-shaped test pattern shown in FIG10 as an example, the crosstalk about the common electrode can be calculated using the following formula:

[0136] Among them, L I[n] Indicates the brightness of the pixel group corresponding to the electrode group n in the square shape shown in FIG10, L [n] The brightness of the pixel group corresponding to the electrode group n in the display substrate 30 that all displays the dark pattern is represented, where n is a positive integer greater than or equal to 1 and less than or equal to 9.

[0137] Generally, when Crosstalk is less than a certain threshold (eg, 2%, 1.1%, and 1.5%), it indicates that the crosstalk of the display substrate meets the requirements.

[0138] Figure 14 shows a schematic block diagram of a display substrate displaying a checkerboard pattern according to another embodiment of the present disclosure. In this embodiment, the checkerboard pattern comprises a group of pixels sharing a common electrode as its smallest display portion. In this embodiment, pixels sharing the first common electrode FCE remain unlit, while pixels sharing the second common electrode SCE remain lit. In other embodiments of the present disclosure, pixels sharing the first common electrode FCE remain lit, while pixels sharing the second common electrode SCE remain unlit.

[0139] FIG. 15 illustrates a timing diagram for displaying the checkerboard pattern of FIG. 14 , according to an embodiment of the present disclosure.

[0140] The difference between Figure 15 and Figure 9 is that in test phase ①, the first test control signal line FCL provides a low-level first test control signal Ctr1, turning off the first control transistor T1. The first test signal line FTL provides a low-level first test signal to keep pixels sharing the first common electrode FCE unlit. The second test signal line STL provides a high-level second test signal STS to keep pixels sharing the second common electrode SCE lit.

[0141] Taking the checkerboard pattern shown in Figure 14 as an example, when a checkerboard pattern with a shared common electrode as the smallest display area appears, it indicates that there is no short circuit or a short circuit problem between the common electrodes. If a partially solid color image appears in the test pattern, it indicates a disconnection problem between the common electrodes. If the test pattern appears entirely in a solid color, it indicates a short circuit problem between the common electrodes.

[0142] In addition, the present disclosure also provides a method for testing a display substrate. FIG17 shows a schematic flow chart of a method 200 for testing a display substrate according to an embodiment of the present disclosure. In this embodiment, the method 200 is used to test a display substrate 10.

[0143] At step 210, a test signal is provided to a different electrode group among the plurality of electrode groups via each sub-test circuit so that the display substrate displays a test pattern. As previously described, the sub-test circuits correspond one to one with the electrode groups. The first to ninth sub-test circuits STC1, STC2, STC3, STC4, STC5, STC6, STC7, STC8, and STC9 provide test signals to the first to ninth electrode groups EG1, EG2, EG3, EG4, EG5, EG6, EG7, EG8, and EG9, respectively.

[0144] At step 220, the display substrate is tested based on the test pattern. As mentioned above, crosstalk, short circuit and open circuit problems in the display substrate can be tested based on the test pattern.

[0145] FIG. 17 shows a schematic flowchart of a method 300 for displaying the checkerboard pattern in FIG. 8 according to an embodiment of the present disclosure.

[0146] At step 310, a first test signal and a second test signal having a first level are provided to electrode groups located in odd columns and odd rows or even columns and even rows, so that pixels sharing all common electrodes in the electrode groups located in odd columns and odd rows or even columns and even rows remain unlit. As described above, a first sub-test signal FTS1, a third sub-test signal FTS3, a fifth sub-test signal FTS5, a seventh sub-test signal FTS7, and a ninth sub-test signal FTS9, as well as a tenth sub-test signal STS1, a twelfth sub-test signal STS3, a fourteenth sub-test signal STS5, a sixteenth sub-test signal STS7, and an eighteenth sub-test signal STS9 of a low level are provided to electrode groups EG1, EG3, EG5, EG7, and EG9, so that pixels corresponding to the electrode groups remain unlit. Details thereof will not be repeated herein.

[0147] At step 320, the first test signal and the second test signal having the second level are provided to the electrode groups located in the even columns and odd rows or the odd columns and even rows, so that the pixels sharing all common electrodes of the electrode groups located in the even columns and odd rows or the odd columns and even rows remain in a lit state. As described above, the second sub-test signal FTS2, the fourth sub-test signal FTS4, the sixth sub-test signal FTS6, and the eighth sub-test signal FTS8, as well as the eleventh sub-test signal STS2, the thirteenth sub-test signal STS4, the fifteenth sub-test signal STS6, and the seventeenth sub-test signal STS8 of a high level are provided to the electrode groups EG2, EG4, EG6, and EG8, so that the pixels corresponding to the electrode groups remain in a lit state.

[0148] FIG. 18 shows a schematic flowchart of a method 400 for displaying the U-shaped pattern in FIG. 10 according to an embodiment of the present disclosure.

[0149] At step 410, a first test signal and a second test signal having a first level are provided to the electrode group located in the second column and the second row so that pixels sharing all common electrodes in the electrode group located in the second column and the second row remain in a lit state. As described above, a first sub-test signal FTS1, a second sub-test signal FTS2, a third sub-test signal FTS3, a fourth sub-test signal FTS4, a sixth sub-test signal FTS6, a seventh sub-test signal FTS7, an eighth sub-test signal FTS8, and a ninth sub-test signal FTS9 and a tenth sub-test signal STS1, an eleventh sub-test signal STS2, a twelfth sub-test signal STS3, a thirteenth sub-test signal STS4, a fifteenth sub-test signal STS6, a sixteenth sub-test signal STS7, a seventeenth sub-test signal STS8, and an eighteenth sub-test signal STS9 of a low level are provided to the electrode groups EG1, EG2, EG3, EG4, EG6, EG7, EG8, and EG9, respectively, so that the pixels corresponding to the electrode groups remain in an unlit state.

[0150] At step 420, the first test signal and the second test signal having the second level are provided to the remaining electrode groups to keep the pixels sharing all common electrodes in the remaining electrode groups unlit. As described above, the fifth sub-test signal FTS5 and the fourteenth sub-test signal STS5 having a high level are provided to EG5 to keep the pixels corresponding to the electrode group lit.

[0151] FIG. 19 shows a schematic flowchart of a method 500 for displaying the I-beam pattern in FIG. 12 according to an embodiment of the present disclosure.

[0152] At step 510, a first test signal and a second test signal having a first level are provided to the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row, so that pixels sharing all common electrodes in the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row remain in a lit state. As described above, a first sub-test signal FTS1, a third sub-test signal FTS3, a fourth sub-test signal FTS4, a fifth sub-test signal FTS5, a sixth sub-test signal FTS6, a seventh sub-test signal FTS7, and a ninth sub-test signal FTS9 and a tenth sub-test signal STS1, a twelfth sub-test signal STS3, a thirteenth sub-test signal STS4, a fourteenth sub-test signal STS5, a fifteenth sub-test signal STS6, a sixteenth sub-test signal STS7, and an eighteenth sub-test signal STS9 of a low level are provided to the electrode groups EG1, EG3, EG4, EG5, EG6, EG7, and EG9, respectively, so that the pixels corresponding to the electrode groups remain in an unlit state.

[0153] At step 520, the first test signal and the second test signal having the second level are provided to the remaining electrode groups so that the pixels sharing all common electrodes in the remaining electrode groups remain unlit. As described above, the second sub-test signal FTS2, the eighth sub-test signal FTS8, the eleventh sub-test signal STS2, and the seventeenth sub-test signal STS8 having a high level are provided to the electrode groups EG2 and EG8, respectively, so that the pixels corresponding to the electrode groups remain lit.

[0154] FIG. 20 shows a schematic flowchart of a method 600 for displaying the checkerboard pattern in FIG. 14 according to an embodiment of the present disclosure.

[0155] At step 610, a first test signal having a second level is supplied to first common electrodes in electrode groups of different sub-test circuits in the plurality of electrode groups, so that pixels sharing the first common electrodes in the electrode groups of the different sub-test circuits in the plurality of electrode groups remain unlit. As previously described, the first to ninth sub-test signals FTS1 to FTS9 of a high level are supplied to all first common electrodes FCE on the display substrate, so that all first common electrodes FCE remain unlit.

[0156] At step 620, a second test signal having a first level is supplied to the second common electrodes in the electrode groups of different sub-test circuits in the plurality of electrode groups, so that pixels sharing the second common electrodes in the electrode groups of the different sub-test circuits in the plurality of electrode groups remain illuminated. As previously described, the tenth through eighteenth sub-test signals STS1 through STS9 of a high level are supplied to all second common electrodes SCE on the display substrate, so that all second common electrodes SCE remain illuminated.

[0157] The present disclosure also provides a display device, which will be described in detail below with reference to FIG21 .

[0158] Fig. 21 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in Fig. 21, the display device 700 may include the display substrates 10 to 50 according to any embodiment of the present disclosure.

[0159] Display panel devices can be used in any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigation systems.

[0160] The display panel provided by the embodiment of the present disclosure has the same or similar beneficial effects as the display substrate provided by the aforementioned embodiment of the present disclosure. Since the display substrate has been described in detail in the aforementioned embodiment, it will not be repeated here.

[0161] The foregoing description of the embodiments is provided above for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present application. The individual elements or features of a particular embodiment are generally not limited to a particular embodiment, but, where appropriate, these elements and features are interchangeable and can be used in selected embodiments, even if not specifically shown or described. Also, it is possible to change in many ways. This change cannot be considered to be out of the present application, and all such modifications are included within the scope of the present application.

Claims

1. A display substrate having a display area and a non-display area surrounding the display area, the display substrate comprising: a plurality of common electrodes arranged in an array within the display area and electrically isolated from each other, each common electrode comprising a first common electrode and a second common electrode, wherein the first common electrode is located in odd rows and odd columns, or even rows and even columns, and the second common electrode is located in odd rows and even columns, or even rows and odd columns, and wherein the plurality of common electrodes are divided into a plurality of electrode groups arranged in an array, wherein each electrode group comprises the first common electrode and the second common electrode; and A test circuit is located in the non-display area and is configured to provide a test signal to the multiple common electrodes to test the display substrate, the test circuit includes a plurality of sub-test circuits, wherein the number of the multiple sub-test circuits is the same as the number of the multiple electrode groups, wherein each sub-test circuit is coupled to a different respective electrode group and is configured to provide the test signal to the coupled electrode group.

2. The display substrate according to claim 1, wherein Each sub-test circuit includes: a first test signal line configured to provide a first test signal to the first common electrode coupled to the sub-test circuit; and A second test signal line is configured to provide a second test signal to the second common electrode coupled to the sub-test circuit.

3. The display substrate according to claim 2, wherein: Each sub-test circuit further comprises: a first test control signal line coupled to a first test control circuit and configured to provide a first test control signal to the first test control circuit; and The first test control circuit is coupled between the first test signal line and the second test signal line and is configured to couple the first test signal line to the second test signal line based on the first test control signal.

4. The display substrate according to claim 3, wherein: The first test control circuit includes a first control transistor, wherein the control electrode of the first control transistor is coupled to the first test control signal line, the first electrode of the first control transistor is coupled to the first test signal line, and the second electrode of the first control transistor is coupled to the second test signal line.

5. The display substrate according to any one of claims 2 to 4, wherein: Each sub-test circuit further comprises: a second test control signal line coupled to a second test control circuit and configured to provide a second test control signal to the second test control circuit; and a second test control circuit, which is coupled between the first common electrode and the respective first test signal lines of the sub-test circuit, or between the second common electrode and the respective second test signal lines of the sub-test circuit, and is configured to couple the first common electrode and the second common electrode to the respective first test signal lines and the second test signal lines of the sub-test circuit, respectively, based on the second test control signal. The display substrate according to claim 5 , wherein: The second test control circuit includes a second control transistor and a third control transistor, wherein the control electrode of the second control transistor is coupled to the second test control signal line, the first electrode of the second control transistor is coupled to the first test signal line, and the second electrode of the second control transistor is coupled to the first common electrode; and The control electrode of the third control transistor is coupled to the second test control signal line, the first electrode of the third control transistor is coupled to the second test signal line, and the second electrode of the third control transistor is coupled to the second common electrode.

7. The display substrate according to claim 6, wherein: The test circuit is configured to provide the test signal to the plurality of electrode groups so that the display substrate displays a test pattern corresponding to the test signal.

8. The display substrate according to claim 6, wherein: The plurality of common electrodes are divided into nine electrode groups arranged in a 3×3 array.

9. The display substrate according to claim 8, wherein: The nine electrode groups include a first electrode group located in the first row and first column, a second electrode group located in the second row and first column, a third electrode group located in the third row and first column, a fourth electrode group located in the first row and second column, a fifth electrode group located in the second row and second column, a fifth electrode group located in the third row and second column, and a fifth electrode group located in the third row and second column. The sixth electrode group, the seventh electrode group located in the first row and third column, the eighth electrode group located in the second row and third column, and the ninth electrode group located in the third row and third column; The first test signal line includes a first sub-test signal line, a second sub-test signal line, a third sub-test signal line, a fourth sub-test signal line, a fifth sub-test signal line, a sixth sub-test signal line, a seventh sub-test signal line, an eighth sub-test signal line and a ninth sub-test signal line; The second test signal lines include a tenth sub-test signal line, an eleventh sub-test signal line, a twelfth sub-test signal line, a thirteenth sub-test signal line, a fourteenth sub-test signal line, a fifteenth sub-test signal line, a sixteenth sub-test signal line, a seventeenth sub-test signal line, and an eighteenth sub-test signal line; The first control transistor includes a first sub-control transistor, a second sub-control transistor, a third sub-control transistor, a fourth sub-control transistor, a fifth sub-control transistor, a sixth sub-control transistor, a seventh sub-control transistor, an eighth sub-control transistor and a ninth sub-control transistor, wherein: The control electrode of the first sub-control transistor is coupled to the first test control signal line, the first electrode of the first sub-control transistor is coupled to the first sub-test signal line, the second electrode of the first sub-control transistor is coupled to the tenth sub-test signal line, and the first sub-control transistor is configured to couple the first sub-test signal line to the tenth sub-test signal line based on the first test control signal; a control electrode of the second sub-control transistor being coupled to the first test control signal line, a first electrode of the second sub-control transistor being coupled to the second sub-test signal line, a second electrode of the second sub-control transistor being coupled to the eleventh sub-test signal line, and the second sub-control transistor being configured to couple the second sub-test signal line to the eleventh sub-test signal line based on the first test control signal; A control electrode of the third sub-control transistor is coupled to the first test control signal line, a first electrode of the third sub-control transistor is coupled to the third sub-test signal line, a second electrode of the third sub-control transistor is coupled to the twelfth sub-test signal line, and the third sub-control transistor is configured to couple the third sub-test signal line to the twelfth sub-test signal line based on the first test control signal; The control electrode of the fourth sub-control transistor is coupled to the first test control signal a first electrode of the fourth sub-control transistor being coupled to the fourth sub-test signal line, a second electrode of the fourth sub-control transistor being coupled to the thirteenth sub-test signal line, and the fourth sub-control transistor being configured to couple the fourth sub-test signal line to the thirteenth sub-test signal line based on the first test control signal; a control electrode of the fifth sub-control transistor coupled to the first test control signal line, a first electrode of the fifth sub-control transistor coupled to the fifth sub-test signal line, a second electrode of the fifth sub-control transistor coupled to the fourteenth sub-test signal line, and the fifth sub-control transistor configured to couple the fifth sub-test signal line to the fourteenth sub-test signal line based on the first test control signal; a control electrode of the sixth sub-control transistor coupled to the first test control signal line, a first electrode of the sixth sub-control transistor coupled to the sixth sub-test signal line, a second electrode of the sixth sub-control transistor coupled to the fifteenth sub-test signal line, and the sixth sub-control transistor configured to couple the sixth sub-test signal line to the fifteenth sub-test signal line based on the first test control signal; a control electrode of the seventh sub-control transistor coupled to the first test control signal line, a first electrode of the seventh sub-control transistor coupled to the seventh sub-test signal line, a second electrode of the seventh sub-control transistor coupled to the sixteenth sub-test signal line, and the seventh sub-control transistor configured to couple the seventh sub-test signal line to the sixteenth sub-test signal line based on the first test control signal; a control electrode of the eighth sub-control transistor being coupled to the first test control signal line, a first electrode of the eighth sub-control transistor being coupled to the eighth sub-test signal line, a second electrode of the eighth sub-control transistor being coupled to the seventeenth sub-test signal line, and the eighth sub-control transistor being configured to couple the eighth sub-test signal line to the seventeenth sub-test signal line based on the first test control signal; and The control electrode of the ninth sub-control transistor is coupled to the first test control signal line, the first electrode of the ninth sub-control transistor is coupled to the ninth sub-test signal line, the second electrode of the ninth sub-control transistor is coupled to the eighteenth sub-test signal line, and the ninth sub-control transistor is configured to connect the control electrode to the eighth sub-test signal line based on the first test control signal. The ninth sub-test signal line is coupled to the eighteenth sub-test signal line.

10. The display substrate according to claim 9, wherein: The second control transistor includes a tenth sub-control transistor, an eleventh sub-control transistor, a twelfth sub-control transistor, a thirteenth sub-control transistor, a fourteenth sub-control transistor, a fifteenth sub-control transistor, a sixteenth sub-control transistor, a seventeenth sub-control transistor, and an eighteenth sub-control transistor, wherein: The control electrodes of the tenth to eighteenth sub-control transistors are all coupled to the second test control signal line; A first electrode of the tenth sub-control transistor is coupled to the first sub-test signal line, and a second electrode of the tenth sub-control transistor is coupled to the first common electrode in the first electrode group; A first electrode of the eleventh sub-control transistor is coupled to the second sub-test signal line, and a second electrode of the eleventh sub-control transistor is coupled to the first common electrode in the second electrode group; A first electrode of the twelfth sub-control transistor is coupled to the third sub-test signal line, and a second electrode of the twelfth sub-control transistor is coupled to the first common electrode in the third electrode group; A first electrode of the thirteenth sub-control transistor is coupled to the fourth sub-test signal line, and a second electrode of the thirteenth sub-control transistor is coupled to the first common electrode in the fourth electrode group; A first electrode of the fourteenth sub-control transistor is coupled to the fifth sub-test signal line, and a second electrode of the fourteenth sub-control transistor is coupled to the first common electrode in the fifth electrode group; A first electrode of the fifteenth sub-control transistor is coupled to the sixth sub-test signal line, and a second electrode of the fifteenth sub-control transistor is coupled to the first common electrode in the sixth electrode group; A first electrode of the sixteenth sub-control transistor is coupled to the seventh sub-test signal line, and a second electrode of the sixteenth sub-control transistor is coupled to the first common electrode in the seventh electrode group; A first electrode of the seventeenth sub-control transistor is coupled to the eighth sub-test signal line, and a second electrode of the seventeenth sub-control transistor is coupled to the first common electrode in the eighth electrode group; A first electrode of the eighteenth sub-control transistor is coupled to the ninth sub-test signal line, and a second electrode of the eighteenth sub-control transistor is coupled to the first common electrode in the ninth electrode group; and The tenth sub-control transistor to the eighteenth sub-control transistor are configured to provide the first sub-test signal, the second sub-test signal, the third sub-test signal, the fourth sub-test signal, the fifth sub-test signal, the sixth sub-test signal, the seventh sub-test signal, the eighth sub-test signal and the ninth sub-test signal from the first sub-test signal line to the ninth sub-test signal line respectively to the first common electrode in the first electrode group to the first common electrode in the ninth electrode group based on the second test control signal.

11. The display substrate according to claim 10, wherein: The third control transistor includes a nineteenth sub-control transistor, a twentieth sub-control transistor, a twenty-first sub-control transistor, a twenty-second sub-control transistor, a twenty-third sub-control transistor, a twenty-fourth sub-control transistor, a twenty-fifth sub-control transistor, a twenty-sixth sub-control transistor, and a twenty-seventh sub-control transistor; The control electrodes of the nineteenth to twenty-seventh sub-control transistors are all coupled to the second test control signal line; A first electrode of the nineteenth sub-control transistor is coupled to the tenth sub-test signal line, and a second electrode of the nineteenth sub-control transistor is coupled to the second common electrode in the first electrode group; A first electrode of the 20th sub-control transistor is coupled to the 11th sub-test signal line, and a second electrode of the 20th sub-control transistor is coupled to the second common electrode in the second electrode group; A first electrode of the twenty-first sub-control transistor is coupled to the twelfth sub-test signal line, and a second electrode of the twenty-first sub-control transistor is coupled to the second common electrode in the third electrode group; The first electrode of the twenty-second sub-control transistor is coupled to the thirteenth sub-test signal line, a second electrode of the twenty-second sub-control transistor is coupled to the second common electrode in the fourth electrode group; A first electrode of the twenty-third sub-control transistor is coupled to the fourteenth sub-test signal line, and a second electrode of the twenty-third sub-control transistor is coupled to the second common electrode in the fifth electrode group; A first electrode of the twenty-fourth sub-control transistor is coupled to the fifteenth sub-test signal line, and a second electrode of the twenty-fourth sub-control transistor is coupled to the second common electrode in the sixth electrode group; A first electrode of the twenty-fifth sub-control transistor is coupled to the sixteenth sub-test signal line, and a second electrode of the twenty-fifth sub-control transistor is coupled to the second common electrode in the seventh electrode group; A first electrode of the twenty-sixth sub-control transistor is coupled to the seventeenth sub-test signal line, and a second electrode of the twenty-sixth sub-control transistor is coupled to the second common electrode in the eighth electrode group; A first electrode of the twenty-seventh sub-control transistor is coupled to the eighteenth sub-test signal line, and a second electrode of the twenty-seventh sub-control transistor is coupled to the second common electrode in the ninth electrode group; as well as The nineteenth sub-control transistor to the twenty-seventh sub-control transistor are configured to provide the tenth sub-test signal, the eleventh sub-test signal, the twelfth sub-test signal, the thirteenth sub-test signal, the fourteenth sub-test signal, the fifteenth sub-test signal, the sixteenth sub-test signal, the seventeenth sub-test signal and the eighteenth sub-test signal from the tenth sub-test signal line to the eighteenth sub-test signal line to the second common electrode in the first electrode group to the second common electrode in the ninth electrode group, respectively, based on the second test control signal.

12. The display substrate according to claim 7, wherein: The test patterns include a checkerboard pattern, a square pattern and an I-shaped pattern.

13. A method for testing a display substrate, wherein: The display substrate has a display area and a non-display area surrounding the display area, and the display substrate includes: A plurality of common electrodes are arranged in an array in the display area and are electrically isolated from each other. The common electrodes include a first common electrode and a second common electrode, wherein the first common electrode is located in odd rows and odd columns, or even rows and even columns, and the second common electrode is located in odd rows and even columns, or even rows and odd columns, and wherein the plurality of common electrodes are divided into a plurality of electrode groups arranged in an array, wherein each electrode group includes the first common electrode and the second common electrode; and a test circuit located in the non-display area and configured to provide a test signal to the plurality of common electrodes to test the display substrate, the test circuit comprising a plurality of sub-test circuits, wherein the number of the plurality of sub-test circuits is the same as the number of the plurality of electrode groups, wherein each sub-test circuit is coupled to a different respective electrode group and configured to provide the test signal to the coupled electrode group; The test method includes: providing the test signal to the coupled electrode group via each sub-test circuit, so that the display substrate displays a test pattern; and The display substrate is tested based on a test pattern.

14. The testing method according to claim 13, wherein: Each sub-test circuit includes: a first test signal line configured to provide a first test signal to the first common electrode coupled to the sub-test circuit; a second test signal line configured to provide a second test signal to the second common electrode coupled to the sub-test circuit; a first test control signal line coupled to a first test control circuit and configured to provide a first test control signal to the first test control circuit; the first test control circuit being coupled between the first test signal line and the second test signal line and configured to couple the first test signal line to the second test signal line based on the first test control signal; a second test control signal line coupled to the second test control circuit and configured to provide a second test control signal to the second test control circuit; and The second test control circuit is coupled between the first common electrode and the first test signal line of the sub-test circuit, or between the second common electrode and the sub-test circuit. The first common electrode and the second common electrode are respectively coupled to the first test signal line and the second test signal line of the sub-test circuit based on the second test control signal.

15. The testing method according to claim 14, wherein: The plurality of common electrodes are divided into nine electrode groups arranged in a 3×3 array.

16. The testing method according to claim 15, wherein: Displaying a checkerboard pattern in which the pixel group sharing all common electrodes in each electrode group is the smallest display portion includes: providing the first test signal and the second test signal having a first level to the electrode group located in odd columns and odd rows or even columns and even rows, so that pixels sharing all common electrodes in the electrode group located in odd columns and odd rows or even columns and even rows maintain a first state; and providing the first test signal and the second test signal having a second level to the electrode group located in the even columns and odd rows or the odd columns and even rows, so that the pixels sharing all common electrodes of the electrode group located in the even columns and odd rows or the odd columns and even rows maintain a second state; wherein the first level and the second level are opposite in level; and The first state is one of a lighting state and a non-lighting state, and the second state is the other of the lighting state and the non-lighting state.

17. The testing method according to claim 15, wherein: The U-shaped pattern of the pixel group that displays and shares all common electrodes in each electrode group as the minimum display pixel includes: providing the first test signal and the second test signal having a first level to the electrode group located in the second column and the second row, so that pixels sharing all common electrodes of the electrode group located in the second column and the second row maintain a second state; and providing the first test signal and the second test signal having a second level to the remaining electrode groups so that the pixels sharing all common electrodes in the remaining electrode groups maintain a first state; wherein the first level and the second level are opposite in level; and The first state is one of a lighting state and a non-lighting state, and the second state is the other of the lighting state and the non-lighting state.

18. The testing method according to claim 15, wherein: The I-shaped pattern in which the pixel group that displays and shares all common electrodes in each electrode group is the smallest display portion includes: providing the first test signal and the second test signal having a first level to the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row, so that pixels sharing all common electrodes of the electrode groups located in the first column and the second row and the electrode groups located in the third column and the second row maintain a second state; and providing the first test signal and the second test signal having a second level to the remaining electrode groups so that the pixels sharing all common electrodes in the remaining electrode groups maintain a first state; wherein the first level and the second level are opposite in level; The first state is one of a lighting state and a non-lighting state, and the second state is the other of the lighting state and the non-lighting state.

19. The testing method according to claim 15, wherein: A method for displaying a checkerboard pattern in which a group of pixels sharing each common electrode is a minimum display portion includes: providing the first test signal having a second level to the first common electrode coupled to the sub-test circuit so that pixels sharing the first common electrode coupled to the sub-test circuit maintain a first state; providing the second test signal having a first level to the second common electrode coupled to the sub-test circuit so that pixels sharing the second common electrode coupled to the sub-test circuit maintain a second state; wherein the first level and the second level are opposite in level; The first state is one of a lighting state and a non-lighting state, and the second state is the other of the lighting state and the non-lighting state.

20. A display device comprising the display substrate according to any one of claims 1 to 12.

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