Display panel and driving method therefor, and display apparatus

Abstract

A display panel and a driving method therefor, and a display apparatus, which belong to the technical field of display. The display panel comprises: a timing controller, a gate driving circuit, a source driving circuit and a subpixel array, wherein the timing controller is configured to provide a frame start signal and a plurality of clock signals for the gate driving circuit; the gate driving circuit is configured to provide a plurality of gate driving signals for the subpixel array on the basis of the frame start signal and the plurality of clock signals, such that the duration in which two adjacent rows of subpixels are in a turned-on state at the same time is greater than or equal to twice a unit scanning time; the source driving circuit is configured to provide data signals for the subpixels in the turned-on state; and the timing controller is configured in a way that the duration of the active level of the clock signals provided to clock signal lines corresponding to subpixel rows where real data is written is longer than the duration of the active level of the clock signals provided to clock signal lines corresponding to subpixel rows where interpolated data is written.

Description

Display panel, driving method thereof, and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a driving method thereof, and a display device. Background Art

[0002] In related technologies, a shift register unit in the gate drive circuit only provides gate scanning signals for one gate line. However, as display panel sizes continue to increase from 65-inch, 75-inch to 98-inch, and 110-inch, resolutions are also increasing, from FHD, UHD to 8K products, and refresh rates are increasing from 60 Hz to 120 Hz. This makes product design increasingly difficult, especially as the pixel charging rate in the product cannot be guaranteed, which in turn affects display quality. Taking a 110-inch, 8K, 120 Hz product as an example, the charging time for each row of pixels is only 1.85 μs, and the product's charging time and charging rate cannot meet design requirements.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a display panel, comprising a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array comprises a plurality of sub-pixels arranged in an N*M array, where N and M are both integers greater than 1;

[0005] The timing controller is configured to provide a frame start signal and a plurality of clock signals to the gate drive circuit; the gate drive circuit is configured to provide a plurality of gate drive signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and to scan the sub-pixel array one row or multiple rows by using the plurality of gate drive signals, so as to turn on the sub-pixels in each scanned row, so that the time length during which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to 2 times of a unit scan time, where the unit scan time is the time required to scan a row of sub-pixels; the source drive circuit is configured to provide a data signal to the sub-pixels in the turned-on state; wherein,

[0006] The gate driving circuit includes N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, and each of the shift register units is connected to at least one clock signal line for transmitting a clock signal;

[0007] The timing controller is configured to provide a clock signal having an effective level duration greater than that provided to the clock signal line corresponding to the sub-pixel row for writing real data.

[0008] In some embodiments, sub-pixel rows into which real data are written and sub-pixel rows into which interpolation data are written are alternately arranged.

[0009] In some embodiments, the N shift register units include a first-stage shift register unit connected to a first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal;

[0010] The rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0011] In some embodiments, the first-stage shift register unit to the p-th stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals further include a p-th clock signal for driving the p-th stage shift register unit to output a gate drive signal;

[0012] The duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured so that the falling edge of the frame start signal is aligned with the rising edge of the pth clock signal, where p is an integer greater than 1.

[0013] In some embodiments, the phase difference between the rising edges of each two adjacent clock signals in the multiple clock signals is the unit scan time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each of the clock signals is 40%.

[0014] In some embodiments, the period in which each row of sub-pixels is in an on state includes a charging period and a pre-charging period before the charging period, wherein the length of the charging period is equal to 2 times the unit scanning time, and the length of the pre-charging period is greater than or equal to the unit scanning time.

[0015] In some embodiments, the gate driving circuit includes m gate driving sub-circuits, and the gate driving sub-circuit includes 4n shift register units, 1≤m≤6, 1≤n≤4; m and n are both integers;

[0016] The gate driving sub-circuit includes a first shift register group and a second shift register group; one of the first shift register group and the second shift register group includes each odd-numbered shift register unit among 4n shift register units, and the other includes each even-numbered shift register unit;

[0017] Each of the adjacent 4n shift register units is connected to the 4n clock signal lines in a one-to-one correspondence, and the i-th shift register unit and the i+4n-th shift register are connected to the same clock signal line; i ranges from 1 to N-4n.

[0018] In some embodiments, the gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes 8 shift register units;

[0019] The signal input ends of the 1st to 4th shift register units respond to the frame start signal; the signal output end of the ath shift register unit is connected to the signal input end of the a+4th shift register unit; the frame start signal end STV0 of the bth shift register unit is connected to the signal output end of the b+4th shift register unit; 1≤a≤4, 1≤b≤4.

[0020] In some embodiments, the gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes 12 shift register units;

[0021] The signal input ends of the 1st to 6th shift register units respond to the frame start signal; the signal output end of the ath shift register unit is connected to the signal input end of the a+6th shift register unit; the frame start signal end STV0 of the bth shift register unit is connected to the signal output end of the b+6th shift register unit; 1≤a≤6, 1≤b≤6.

[0022] In some embodiments, the shift register unit includes:

[0023] an input circuit configured to transmit a first level signal to a pull-up node under the control of a first input signal;

[0024] A first reset circuit is configured to transmit a second level signal to the pull-up node under the control of a second input signal;

[0025] a first pull-down circuit configured to transmit the second level signal to the pull-down node under the control of a third input signal;

[0026] a second pull-down circuit configured to transmit the second level signal to the pull-up node under the control of the pull-down node voltage;

[0027] a first pull-down control circuit configured to transmit the second level signal to a pull-down control node and the pull-down node under control of the pull-up node voltage;

[0028] a second pull-down control circuit configured to transmit the power signal to the pull-down node and the pull-down control node under the control of a power signal;

[0029] a second reset circuit, configured to reset the pull-up node under the control of a reset signal;

[0030] a third pull-down circuit configured to transmit the second level signal to the cascade terminal under the control of the pull-down node voltage;

[0031] a fourth pull-down circuit configured to transmit the third level signal to the signal output terminal under the control of the pull-down node;

[0032] an output circuit configured to transmit a clock signal to a signal output terminal under control of the pull-up node voltage;

[0033] The cascade circuit is configured to transmit the clock signal to the cascade terminal under the control of the pull-up node voltage.

[0034] In some embodiments, the power signal includes a first power signal and a second power signal; the first power signal and the second power signal are same-frequency and opposite-direction signals.

[0035] In some embodiments, the input circuit includes a first transistor; the control electrode of the first transistor is connected to the first signal input terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the pull-up node.

[0036] In some embodiments, the first reset circuit includes a second transistor; the control electrode of the second transistor is connected to the second signal input terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal.

[0037] In some embodiments, the pull-down node includes a first pull-down node, and the pull-down control node includes a first pull-down control node;

[0038] The first pull-down control circuit includes: a seventh transistor and an eighth transistor;

[0039] The control electrode of the seventh transistor is connected to the pull-up node, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; the control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal;

[0040] The second pull-down control circuit includes: a ninth transistor and a tenth transistor;

[0041] The control electrode and the first electrode of the ninth transistor are both connected to the first power signal terminal, and the second electrode is connected to the first pull-down control node; the control electrode of the tenth transistor is connected to the first pull-down control node, the first electrode is connected to the first power signal terminal, and the second electrode is connected to the first pull-down node.

[0042] In some embodiments, the pull-down node further includes a second pull-down node, and the pull-down control node further includes a second pull-down control node;

[0043] The first pull-down control circuit further includes: an eleventh transistor and a twelfth transistor;

[0044] The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal; the control electrode of the twelfth transistor is connected to the pull-up node, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal;

[0045] The second pull-down control circuit further includes: a thirteenth transistor and a fourteenth transistor;

[0046] The control electrode and the first electrode of the thirteenth transistor are both connected to the second power signal terminal, and the second electrode is connected to the second pull-down control node; the control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode is connected to the second power signal terminal, and the second electrode is connected to the second pull-down node.

[0047] In some embodiments, the pull-down node includes a first pull-down node;

[0048] The first pull-down circuit includes a fourth transistor; the control electrode of the fourth transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal;

[0049] The second pull-down circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the first pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal;

[0050] The third pull-down circuit includes a sixteenth transistor; the control electrode of the sixteenth transistor is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal;

[0051] The fourth pull-down circuit includes a nineteenth transistor; the control stage of the nineteenth transistor is connected to the first pull-down node, the first electrode is connected to the signal output end, and the second electrode is connected to the third level signal end.

[0052] In some embodiments, the pull-down node further includes a second pull-down node;

[0053] The first pull-down circuit further includes a third transistor; the control electrode of the third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal;

[0054] The second pull-down circuit further includes a fifth transistor; the control electrode of the fifth transistor is connected to the second pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal;

[0055] The third pull-down circuit further includes a seventeenth transistor; the control electrode of the seventeenth transistor is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal;

[0056] The fourth pull-down circuit further includes a twentieth transistor; a control stage of the twentieth transistor is connected to the second pull-down node, a first electrode is connected to the signal output end, and a second electrode is connected to the third level signal end.

[0057] In some embodiments, the second reset circuit includes a fifteenth transistor; the control electrode of the fifteenth transistor is connected to the frame start signal terminal STV0, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the cascade terminal.

[0058] In some embodiments, the output circuit includes a twenty-first transistor and a first storage capacitor;

[0059] The control electrode of the twenty-first transistor is connected to the pull-up node, the first electrode is connected to the clock signal end, and the second electrode is connected to the signal output end; one electrode of the first storage capacitor is connected to the pull-up node, and the other electrode is connected to the signal output end.

[0060] In some embodiments, the cascade circuit includes an eighteenth transistor; the control electrode of the eighteenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal end, and the second electrode is connected to the signal output end.

[0061] In some embodiments, the shift register unit further includes a third pull-down control circuit; the third pull-down control circuit is configured to transmit the second level signal to the pull-down control node under the control of a third input signal.

[0062] In some embodiments, the pull-down control node includes a first pull-down control node;

[0063] The third pull-down control circuit includes a 22nd transistor; the control electrode of the 22nd transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal.

[0064] In some embodiments, the pull-down control node further includes a second pull-down control node;

[0065] The third pull-down control circuit package further includes a twenty-third transistor; the control electrode of the twenty-third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal.

[0066] In a second aspect, the present disclosure provides a method for driving a display panel, wherein the display panel includes a timing controller, a gate driving circuit, and a source driving circuit, and the method includes:

[0067] The timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit; the timing controller is configured so that the effective level duration of the clock signal provided by the clock signal line corresponding to the sub-pixels in the odd rows is longer than the effective level duration of the clock signal provided by the clock signal line corresponding to the sub-pixels in the even rows;

[0068] The gate drive circuit outputs a plurality of gate drive signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and uses the plurality of gate drive signals to scan the sub-pixel array row by row or multiple rows one by one, so as to turn on each scanned row of sub-pixels, so that the duration during which two adjacent rows of sub-pixels are simultaneously in the on state is greater than or equal to twice a unit scan time, where the unit scan time is the time required to scan a row of sub-pixels, wherein the sub-pixel array includes a plurality of sub-pixels arranged in an N×M array, where N and M are both integers greater than 1; the gate drive circuit includes N shift register units respectively connected to the N rows of sub-pixels in the sub-pixel array, each of the shift register units being connected to at least one clock signal line for transmitting a clock signal; the gate drive circuit includes a plurality of shift register groups alternately cascaded; and

[0069] The source driving circuit applies data signals to at least two rows of sub-pixels that are simultaneously in an on state, so that the duration of applying the data signals to at least some rows of sub-pixels is greater than the unit scanning time.

[0070] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time;

[0071] Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises:

[0072] In a charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0073] In the first precharge period of the 2kth row of sub-pixels and the first half of the charge period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels, and in the second half of the charge period of the 2kth row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2kth row of sub-pixels;

[0074] In a first pre-charge period of the 2k+1th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2k+1th row of sub-pixels;

[0075] Among them, k = 1, 2, 3, ...

[0076] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time;

[0077] Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises:

[0078] In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0079] In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels;

[0080] In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels;

[0081] In the first pre-charge period of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charge period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels;

[0082] Among them, k = 1, 2, 3, ...

[0083] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time;

[0084] Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises:

[0085] In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels;

[0086] In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels;

[0087] In the first pre-charging period of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charging period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels;

[0088] In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels;

[0089] In the first pre-charging period of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels;

[0090] In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels;

[0091] Among them, k = 1, 2, 3, ...

[0092] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time;

[0093] Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises:

[0094] In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels;

[0095] In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels;

[0096] In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels;

[0097] In the first pre-charging period of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels;

[0098] In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels;

[0099] In the first pre-charging period of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels;

[0100] Among them, k = 1, 2, 3, ...

[0101] In a third aspect, the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] FIG1 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0103] FIG2 shows a timing diagram of a driving method according to an embodiment of the present disclosure;

[0104] FIG3 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure;

[0105] FIG4 shows a schematic diagram of a frame start signal line and a clock signal line according to an embodiment of the present disclosure;

[0106] 5a and 5b show exemplary structural diagrams of a gate driving circuit provided by at least one embodiment of the present disclosure;

[0107] 6a and 6b show exemplary structural diagrams of yet another gate driving circuit provided by at least one embodiment of the present disclosure;

[0108] 7a-7b show an exemplary structural diagram of a shift register unit provided by the present disclosure;

[0109] FIG7c shows an exemplary structural diagram of yet another shift register unit provided by the present disclosure;

[0110] FIG7 d shows an exemplary structural diagram of yet another shift register unit provided by the present disclosure;

[0111] FIG8 shows a flowchart of a driving method according to an embodiment of the present disclosure;

[0112] FIG9a is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0113] FIG9b is a schematic diagram of extracting odd-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0114] FIG10 is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0115] FIG11 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure;

[0116] FIG12 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure;

[0117] FIG13 shows another timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure;

[0118] FIG14 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure;

[0119] FIG. 15 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0120] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0121] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates an "or" relationship between the preceding and following objects. Terms such as "first," "second," and "third" used in this application merely distinguish similar objects and do not indicate a specific ordering of the objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative position. If the absolute position of the described objects changes, the relative position may also change accordingly.

[0122] It should be noted that the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present invention, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present invention.

[0123] Among them, since the transistor used in the embodiment of the present invention is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; the corresponding working level end is a high level signal end, and the non-working level end is a low level signal end.

[0124] Typically, a display panel includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel regions, each of which is provided with pixel cells. The structure of the display panel is described below using the example of the direction in which each gate line extends as a row direction and the direction in which each data line extends as a column direction. When the display panel is driven to display, gate scan signals are written to the gate lines row by row, and data voltage signals are written to the data lines simultaneously, so that the pixel cells in the display panel are illuminated row by row, depending on the image to be displayed.

[0125] Among them, the gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit; in the related technology, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip; and currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate drive circuit on an array substrate (Gate On Array; GOA) is provided; wherein, the gate drive circuit includes a plurality of cascaded shift register units integrated on the array substrate, each shift register unit is connected to a gate line one-to-one, and is used to provide a gate scan signal to the gate line connected thereto.

[0126] In a first aspect, the present disclosure provides a display panel 100. As shown in FIG1 , the display panel 100 includes a timing controller 30, a gate drive circuit 10, a source drive circuit 20, and a sub-pixel array. The sub-pixel array includes a plurality of sub-pixels P arranged in an N×M array, where N and M are both integers greater than 1. The timing controller 30 is configured to provide a frame start signal and a plurality of clock signals to the gate drive circuit 10. The gate drive circuit 10 is configured to provide a plurality of gate drive signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and to scan the sub-pixel array one row or multiple rows at a time using the plurality of gate drive signals to turn on each scanned row of sub-pixels, so that the time duration during which two adjacent rows of sub-pixels are simultaneously in the on state is greater than or equal to 2 times the unit scan time, where the unit scan time is the time required to scan a row of sub-pixels. The source drive circuit 20 is configured to provide data signals to at least two rows of sub-pixels that are simultaneously in the on state.

[0127] Specifically, the timing controller 30 is connected to the gate drive circuit 10 and the source drive circuit 20, and can provide relevant control signals to the gate drive circuit 10 and the source drive circuit 20. For example, the timing controller 30 can provide the data control signal TP to the source drive circuit 20, and the source drive circuit 20 can output the data signal for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source drive circuit 20, including but not limited to a row data start signal, a data synchronization signal, a data inversion signal, etc. The timing controller 30 can also provide various control signals to the gate drive circuit 10, including but not limited to a frame start signal, a clock signal, etc. required by the gate drive circuit 10.

[0128] The gate driver circuit 10 includes N shift register units connected to N rows of sub-pixels in the sub-pixel array, each of which is connected to at least one clock signal line for transmitting a clock signal. The gate driver circuit 10 can be connected to N rows of sub-pixels through a plurality of gate signal lines extending along a first direction (the x direction in FIG1 ), for example, connecting the first row of sub-pixels P through a first gate signal line to provide a first gate drive signal G1 to the first row of sub-pixels P, and then connecting the second row of sub-pixels P through a second gate signal line to provide a second gate drive signal G2 to the second row of sub-pixels P, and so on. The first row of sub-pixels P is turned on in response to receiving the first gate drive signal G1, the second row of sub-pixels P is turned on in response to receiving the second gate drive signal G2, and so on. Continuing to refer to FIG1 , the source driver circuit 20 can be connected to M columns of sub-pixels P through a plurality of data lines extending along a second direction (the y direction in FIG1 ). For example, the source driver circuit 20 can be connected to the first column of sub-pixels P via a first data line to provide a first data signal D1 to the first column of sub-pixels P, and can be connected to the second column of sub-pixels P via a second data line to provide a second data signal D2 to the second column of sub-pixels P, and so on. For example, when the first row of sub-pixels P is turned on, the source driver circuit 20 can provide M data signals D11, D12, ..., D1M for the first row of sub-pixels to the M sub-pixels P in the first row via M data lines; when the second row of sub-pixels P is turned on, the source driver circuit 20 can provide M data signals D21, D22, ..., D2M for the second row to the M sub-pixels P in the second row via multiple data lines, and so on. Of course, the embodiments of the present disclosure are not limited to this, and this will be further explained in detail below.

[0129] In some embodiments, the gate driving circuit 10 scans the sub-pixels row by row, that is, the N gate driving signals G1, G2, ...GN generated in sequence by the gate driving circuit 10 turn on the first row of sub-pixels P, the second row of sub-pixels P... the Nth row of sub-pixels P row by row in sequence. At this time, the timing controller 30 is configured to provide the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row where the real data is written, which is greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row where the interpolated data is written.

[0130] It should be noted that in this embodiment, a row of sub-pixels is electrically connected to a shift register unit, which provides a gate drive signal. When the gate drive signal scans the row of sub-pixels (i.e., the gate drive signal turns on the row of sub-pixels), the first data signal provided by the source drive signal corresponding to the row of sub-pixels is written into the sub-pixels to complete the charging of the row of sub-pixels. Therefore, when the effective level duration of the data signal is long enough, the effective working level duration of the gate drive signal will affect the charging duration of the sub-pixels (i.e., the data signal writing duration). For each shift register unit, referring to Figure 7a, the effective level duration of the gate drive signal output by the shift register unit depends on the effective level duration of the clock signal transmitted on the clock signal line connected to the output circuit 1010. The longer the effective level duration of the clock signal, the longer the effective level duration of the gate drive signal output by the corresponding shift register unit, and therefore the longer the charging duration of the corresponding row of sub-pixels. In the embodiment of the present disclosure, the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row where real data is written is set to be greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row where interpolated data is written, that is, the charging time of the sub-pixel row where real data is written is greater than the charging time of the sub-pixel row where interpolated data is written, thereby increasing the charging rate of the sub-pixel row where real data is written, thereby improving the overall display effect. In addition, such a setting can make the duty cycle of each clock signal different, thereby enhancing the anti-interference ability of the signal. The shift register units in this article all use N-type transistors, so the effective working level mentioned in the article refers to the high level, and the effective level duration refers to the length of time the signal continues at a high level.

[0131] It should be noted that in a frame of display image, the real data is the data required to be displayed for the row of sub-pixels corresponding to the display image, and the interpolated data is data different from the data of the sub-pixels in the row corresponding to the display image. For the entire panel, real data can be written to a preset row of pixels first, and then a row of interpolated data can be written. For example, real data can be written to ten rows of pixels, and then interpolated data can be written to one row of pixels. The charging time of the pixel rows written with real data is set to be longer than the charging time of the pixel rows written with interpolated data, thereby reducing the power consumption of the display panel. Preferably, in one embodiment, the sub-pixel rows written with real data and the sub-pixel rows written with interpolated data are arranged alternately. This arrangement can make the display more uniform and improve the display effect. For example, for a 4K2K (resolution 3840×2160) display panel, the number of horizontal pixels is 3840 and the number of vertical pixels is 2160. If the multiple sub-pixels contained in each pixel are arranged horizontally, the display panel includes 2160 rows of sub-pixels. The sub-pixel rows into which real data are written may include the 1st row of sub-pixels, the 3rd row of sub-pixels, the 5th row of sub-pixels... the 2159th row of sub-pixels, and the sub-pixel rows into which interpolated data are written may include the 2nd row of sub-pixels, the 4th row of sub-pixels... the 2160th row of sub-pixels. If the charging time for each row of sub-pixels is equal, when the refresh frequency is 60Hz, the scanning time of 1 frame is 1 / 60 second, that is, the time spent scanning 2160 rows of sub-pixels is 1 / 60 second, then the time spent scanning each row of sub-pixels (that is, the unit scanning time) H = 1 / 60 ÷ 2160 ≈ 1.85us. In this application, the charging time of the sub-pixel row into which real data is written is set to be greater than the time of the sub-pixel row into which interpolated data is written. For example, the scanning time of the sub-pixel row into which real data is written is set to 2us, and the scanning time of the sub-pixel row into which interpolated data is written is set to 1.7us. In this way, the average scanning time for scanning a row of sub-pixels is 1.85us, and the refresh frequency can still be maintained at 60Hz. At the same time, the charging rate of the local sub-pixels of the display panel (that is, the charging rate of the sub-pixel row into which real data is written) can be improved, thereby improving the display effect of the entire display panel.

[0132] FIG2 shows a timing diagram of a driving method according to an embodiment of the present disclosure.

[0133] During time period T1 (first time period), the first row of sub-pixels and the second row of sub-pixels are sequentially turned on. For example, during a first sub-period T11 of the first time period T1, the first gate drive signal G1 is at a high level, thereby turning on the first row of sub-pixels; and during a second sub-period T12 of the first time period T1, the second gate drive signal G2 is at a high level, thereby turning on the second row of sub-pixels.

[0134] In period T2 (second period), the third row of sub-pixels and the fourth row of sub-pixels are sequentially turned on, and data signals are applied to the first row of sub-pixels and the second row of sub-pixels. For example, upon the arrival of the first high-level pulse of the data control signal TP, the source driver circuit 20 applies one of the first row of data signals DATA1 and the second row of data signals DATA2 (in this embodiment, the first row of data signals DATA1) to the first row of sub-pixels and the second row of sub-pixels.

[0135] In period T3 (third period), the first row of sub-pixels is turned off, and data signals are applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels. For example, upon the arrival of the second high-level pulse of the data control signal TP, one of the third row of data signal DATA3 and the fourth row of data signal DATA4 is applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels that are in the turned-on state.

[0136] Similarly, for the third and fourth rows of sub-pixels, the first period is period T2 in FIG. 2 , the second period is periods T3 and T4 in FIG. 2 , and the third period is period T5 in FIG. During period T2, the third and fourth rows of sub-pixels are sequentially turned on. For example, during the first sub-period T21 of period T2, the third gate drive signal G3 is at a high level, thereby turning on the third row of sub-pixels. During the second sub-period T22 of period T2, the fourth gate drive signal G4 is at a high level, thereby turning on the fourth row of sub-pixels. During periods T3 and T4, the fifth and sixth rows of sub-pixels are sequentially turned on, and one of the third row data signal DATA3 and the fourth row data signal DATA4 is applied to the third and fourth rows of sub-pixels. During period T5, the third row of sub-pixels is turned off, and one of the fifth row data signal DATA5 and the sixth row data signal DATA6 is applied to the fourth, fifth, and sixth rows of sub-pixels.

[0137] The length of the second time period can be set to be greater than or equal to 2H, so that the length of time that the data signal is applied to each row of sub-pixels is greater than or equal to 2H. For example, in the example of Figure 2, the time period in which the data signal is applied to the sub-pixels in the first row is time period T2, and the time period in which the data signal is applied to the sub-pixels in the second row is time periods T2 and T3. The lengths of time periods T1 and T2 can be set to 2H, and the length of time period T3 can be set to H. In this case, the actual charging time of the sub-pixels in the first row is 2H (the length of time period T2), and the actual charging time of the sub-pixels in the second row is 3H (the sum of the lengths of time periods T2 and T3). Similarly, the actual charging time of the sub-pixels in the third row is 2H, and the actual charging time of the sub-pixels in the fourth row is 3H.

[0138] In this embodiment, by turning on two rows of sub-pixels in sequence and applying data signals to the two rows of sub-pixels that are simultaneously turned on, the actual charging time of some sub-pixels (for example, odd-numbered rows of sub-pixels) can reach 2H or longer, while the actual charging time of another part of the sub-pixels (for example, even-numbered rows of sub-pixels) can reach 3H or longer.

[0139] For example, the gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, wherein the N shift register units include a first-stage shift register unit (e.g., GOA1) connected to the first row of sub-pixels in the sub-pixel array. The multiple clock signals include a first clock signal (e.g., CLK1) for driving the first-stage shift register unit to output a gate drive signal. For example, in the disclosed embodiment, the shift register unit connected to the first row of sub-pixels is referred to as the first-stage shift register unit.

[0140] FIG3 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0141] As shown in Figure 3, the rising edge of the frame start signal STV is earlier than the rising edge of the first clock signal CLK1, and the falling edge of the frame start signal STV is no later than the falling edge of the first clock signal CLK1. The phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time. Based on this setting, display defects can be improved and a better display effect can be achieved.

[0142] FIG4 shows a schematic diagram of a frame start signal line and a clock signal line according to an embodiment of the present disclosure.

[0143] As shown in Figures 3 and 4, if the falling edge of the frame start signal line STV is aligned with the falling edge of the clock signal line CLK1, then the frame start signal line STV will not cause pull-down interference to the clock signal CLK1 when it is pulled down. The width of the frame start signal line STV is greater than the width of the clock signal line CLK, so the resistance of the frame start signal line STV is greater than the resistance of the clock signal line CLK. When the falling edge of the frame start signal line STV is earlier than the falling edge of the clock signal line CLK1, and the phase difference between the falling edge of the frame start signal line STV and the falling edge of the clock signal line CLK1 is, for example, 1 hour or greater, the falling edge of the frame start signal STV when it is pulled down is relatively slow, thereby having a smaller impact on the clock signal line CLK1 and not being balanced with the interference to the clock signals CLK2 and subsequent clock signals. In the embodiment of the present disclosure, the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is set to 0.2H~0.6H. In this way, the frame start signal STV can have a greater pull-down effect on the clock signal CLK1, thereby balancing the interference of the clock signal CLK1 and the clock signals thereafter, improving the phenomenon of poor horizontal stripes, and achieving a better display effect.

[0144] For example, the first-stage shift register unit to the P-th-stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals also include the P-th clock signal for driving the P-th-stage shift register unit to output a gate drive signal; the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and the phase difference and duty cycle are configured so that the falling edge of the frame start signal is aligned with the rising edge of the P-th clock signal, and P is an integer greater than 1.

[0145] For example, the value of P is related to the number of clock signals connected to the gate drive circuit. When the gate drive circuit is connected to an 8CLK signal, P is 4; when the gate drive circuit is connected to a 12CLK signal, P is 6.

[0146] For example, if the frame revelation signal STV is connected to the first through fourth shift register units, the P-th shift register unit is the fourth shift register unit. Setting the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 to 0.2H to 0.6H, setting the duty cycle of the clock signal to 40% to 45%, and coordinating the phase difference and duty cycle so that the falling edge of the frame start signal is aligned with the rising edge of the fourth clock signal CLK4 can further improve display defects and achieve a better display effect.

[0147] For example, in some embodiments, the phase difference between the rising edges of each two adjacent clock signals in the plurality of clock signals is a unit scan time H, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%. For example, as shown in FIG6 , the high-level duration t1 of the frame start signal STV is 8 hours, the high-level duration t3 of each clock signal CLK is 3.2 hours, and the cycle time t4 of the clock signal CLK is 8 hours, so the duty cycle of the clock signal is 3.2 / 8 = 40%. The phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the clock signal CLK1 is 5 hours, the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2 hours, and the start and end times of the clock signals CLK differ by t5 by 1 hour. The rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. That is to say, when the phase difference between the clock signals is 1H, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2H and the duty cycle of the clock signal is 40%, the rising edge of the clock signal CLK4 can be aligned with the falling edge of the frame start signal STV.

[0148] For example, in some other embodiments, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.3H, the duty cycle of the clock signal is set to 3.3 / 8=41.25%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.4H, the duty cycle of the clock signal is set to 3.4 / 8=42.5%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.6H, the duty cycle of the clock signal is set to 3.6 / 8=45%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV.

[0149] For example, when the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV, when the frame start signal STV ends, the clock signal CLK4 immediately starts to rise, generating a second-order PU, fully controlling the GOA output, and avoiding leakage of the PU point in the shift register unit, so that each sub-pixel can achieve a better charging effect.

[0150] For example, setting the clock signal's duty cycle to 40% to 45% can also improve poor display in some situations. The clock signal's duty cycle is typically 50%, but when the duty cycle is 50%, poor display may occur due to in-plane coupling and other factors. The disclosed embodiments set the duty cycle to 40% to 45%, which can address poor display in this situation.

[0151] For example, each of the multiple initial data frames can be divided into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any initial data frame includes odd-numbered row data of the initial data frame, and the other includes even-numbered row data of the initial data frame.

[0152] In some embodiments, the gate drive circuit can be divided into m gate drive sub-circuits, each gate drive sub-circuit includes 4n shift register units, 1≤m≤6, 1≤n≤4 and m, n are both integers. Among them, the gate drive sub-circuit can be divided into a first shift register group and a second shift register group, and the two shift register groups are respectively connected to different initial gate scan signals. Specifically, the first shift register may include 2n odd-numbered shift register units, such as the 1st shift register unit, the 3rd shift register unit, the 5th shift register unit... the 4n-1th shift register unit, and accordingly, the second shift register group includes 2n even-numbered shift register units, such as the 2nd shift register unit, the 4th shift register unit, the 6th shift register unit... the 4nth shift register unit. Of course, the first shift register group may also include even-numbered shift register units, and the second shift register group may include odd-numbered shift register units, which is not limited here.

[0153] Furthermore, the m gate drive sub-circuits are connected to m groups of clock signal lines, each group of clock signal lines including 4n clock signal lines. That is, each of the 4n adjacent shift register units is connected to the 4n clock signal lines in a one-to-one correspondence, and the i-th shift register unit is connected to the same clock signal line as the i+4n-th shift register. For example, if m=2 and n=2, the gate drive circuit includes two gate drive sub-circuits, each of which includes 8 shift register units. That is, the gate drive circuit includes 16 shift register units and is connected to 8 clock signal lines, wherein the 1st to 8th shift registers are connected to clk1-clk8 in a one-to-one correspondence, and the 9th to 16th shift register units are also connected to clk1-clk8 in a one-to-one correspondence.

[0154] Exemplarily, FIG5a-5b are cascade diagrams of gate driving circuits when m=1 and n=2.

[0155] As shown in Figure 5a, the gate drive circuit includes eight cascaded shift register units GOA1, GOA2, ..., GOA8, and is connected to eight different CLK lines. The input terminals Input of the first to fourth shift register units GOA1 to GOA4 can be connected to the frame start signal terminal STV1. After the fourth shift register unit GOA4, the input terminal Iaput of the a-th shift register unit GOAa is connected to the output terminal of the a-4th shift register unit GOA(a-4)th shift register unit, where 5≤a≤A. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of G3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal RST of the b-th shift register unit GOAb is connected to the output terminal OUT of the b+4th shift register unit GOA(b+4), where 1≤b≤4.

[0156] For a 4K2K (resolution 3840×2160) display panel, the number of horizontal pixels is 3840 and the number of vertical pixels is 2160. If the multiple sub-pixels contained in each pixel are arranged horizontally, the display panel includes 2160 rows of sub-pixels. When the display panel includes 2160 rows of sub-pixels and each shift register unit corresponds to a row of sub-pixels, the number of shift register units included in the gate drive circuit can be 2160. Figure 5b shows the last shift register unit GOA2160 and the dummy shift register unit (Dummy GOA). As shown in Figure 5b, the last four rows of GOAs can be reset by four rows of Dummy GOAs. For example, Dummy GOA1 (Dum1) resets GOA2157, Dummy GOA 2 (Dum2) resets GOA2158, and so on. Each Dummy GOA can be reset by STV1. STV0 is the total reset signal, which is connected to GOA9 and subsequent units. The waveforms of STV0 and STV1 are exactly the same, so they can be connected together externally.

[0157] The gate drive circuit shown in Figures 5a and 5b uses eight clock signals CLK1 to CLK8, wherein the clock signal terminal CLK of the first shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar manner, the ninth to sixteenth shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0158] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output terminal OUT under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first shift register unit GOA1 generates a first gate drive signal G1, the second shift register unit GOA2 generates a second gate drive signal G2, and so on. By connecting the units in series, the gate drive signal generated by one shift register unit can be shifted relative to the gate drive signal generated by another shift register unit.

[0159] For example, FIG6 a - FIG6 b are cascade diagrams of gate driving circuits when m=1 and n=3 (12clk).

[0160] As shown in Figure 6a, the gate drive circuit includes 12 cascaded shift register units GOA1, GOA2, ..., GOA12, and is connected to 12 different CLK lines. The input terminals "Input" of the first to sixth shift register units GOA1 to GOA6 can be connected to the frame start signal terminal STV1. After the sixth shift register unit GOA6, the input terminal "Input" of the a-th shift register unit GOAa is connected to the output terminal of the a-6th shift register unit GOA(a-6), where 7 ≤ a ≤ 12. For example, the output of GOA1 is connected to the input of GOA7, the output of GOA2 is connected to the input of GOA8, the output of G3 is connected to the input of GOA9, the output of G4 is connected to the input of GOA10, the output of G5 is connected to the input of GOA11, and so on. The reset terminal RST of the b-th shift register unit GOAb is connected to the output terminal OUT of the b+6th shift register unit GOA(b+6), where 1 ≤ b ≤ 6.

[0161] The gate drive circuit shown in Figures 6a and 6b uses 12 clock signals CLK1 to CLK12, wherein the clock signal terminal CLK of the first shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the 12th shift register unit GOA12 is connected to receive the 12th clock signal CLK12. In a similar manner, the 13th to 24th shift register units GOA13 to GOA24 are connected to receive the first to twelfth clock signals CLK1 to CLK12, respectively.

[0162] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output terminal OUT under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first shift register unit GOA1 generates a first gate drive signal G1, the second shift register unit GOA2 generates a second gate drive signal G2, and so on. By connecting the units in series, the gate drive signal generated by one shift register unit can be shifted relative to the gate drive signal generated by another shift register unit.

[0163] The present disclosure also provides a specific structure of the above-mentioned shift register unit, with reference to Figures 7a-7d. The shift register unit may include: an input circuit connected to a first signal input terminal, a first level signal terminal, and a pull-up node, for transmitting a first level signal to the pull-up node in response to a first input signal; a first reset circuit connected to a second signal input terminal, a second level signal terminal, and the pull-up node, for transmitting a second level signal to the pull-up node in response to a second input signal; a first pull-down circuit connected to a third signal input terminal, a second level signal terminal, and the pull-down node, for transmitting a second level signal to the pull-down node in response to a third input signal; a second pull-down circuit connected to the pull-down node, the second level signal terminal, and the pull-up node, for transmitting a second level signal to the pull-up node in response to a voltage on the pull-down node; and a first pull-down control circuit connected to the pull-up node, the pull-down node, the pull-down control node, and the second level signal terminal, for transmitting a second level signal to the pull-down node and the pull-down control node under control of the voltage on the pull-up node. The second pull-down control circuit is connected to the power signal terminal, the pull-down node, and the pull-down control node, and is configured to transmit the power signal to the pull-down node and the pull-down control node in response to the power signal. The second reset circuit is connected to the frame start signal terminal STV0 and the pull-up node, and is configured to reset the pull-up node in response to the reset signal. The third pull-down circuit is configured to transmit the second level signal to the cascade signal terminal in response to the pull-down node voltage. The fourth pull-down circuit is configured to reset the signal output terminal in response to the pull-down node voltage. The output power supply is configured to transmit a clock signal to the signal output terminal in response to the pull-up node voltage. The cascade circuit is configured to transmit the clock signal to the cascade signal terminal output in response to the pull-up node voltage.

[0164] In some examples, the input circuit includes a first transistor. The first transistor has a control electrode connected to the first signal input terminal, a first electrode connected to the first level signal terminal, and a second electrode connected to the pull-up node. The first transistor is configured to write the first level signal to the pull-up node under the control of the first input signal.

[0165] In some examples, the first reset circuit includes a second transistor, wherein the second transistor has a control electrode connected to the second signal input terminal, a first electrode connected to the pull-up node, and a second electrode connected to the second level signal terminal. The second transistor is configured to write the second level signal to the pull-up node under the control of the second input signal.

[0166] In some examples, the second reset circuit includes a fifteenth transistor; the fifteenth transistor has a control electrode connected to the frame start signal terminal STV0, a ​​first electrode connected to the clock signal terminal, and a second electrode connected to the cascade terminal. The fifteenth transistor is configured to transmit the clock signal to the cascade terminal under control of the reset signal.

[0167] In some examples, the output circuit includes a twenty-first transistor and a first storage capacitor; the twenty-first transistor has a control electrode connected to the pull-up node, a first electrode connected to the clock signal terminal, and a second electrode connected to the signal output terminal; one electrode of the first storage capacitor is connected to the pull-up node, and the other electrode is connected to the signal output terminal. The twenty-first transistor is configured to transmit the clock signal to the signal output terminal under control of the pull-up node voltage.

[0168] In some examples, the cascade circuit includes an eighteenth transistor; the eighteenth transistor has a control electrode connected to the pull-up node, a first electrode connected to the clock signal terminal, and a second electrode connected to the signal output terminal. In other examples, the eighteenth transistor has a control electrode connected to the pull-up node, a first electrode connected to the clock signal, and a second electrode connected to the cascade signal terminal.

[0169] In some examples, the power signal terminal includes a first power signal terminal and a second power signal terminal, the pull-down node includes a first pull-down node and a second pull-down node, and the pull-down control node includes a first pull-down control node and a second pull-down control node.

[0170] Correspondingly, in some examples, the first pull-down control circuit includes a seventh transistor and an eighth transistor, wherein the control electrode of the seventh transistor is connected to the pull-up node, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second-level signal terminal. The control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second-level signal terminal. The second pull-down control circuit includes a ninth transistor and a tenth transistor, wherein the control electrode and the first electrode of the ninth transistor are both connected to the first power supply signal terminal, and the second electrode is connected to the first pull-down control node; the control electrode of the tenth transistor is connected to the first pull-down control node, the first electrode is connected to the first power supply signal terminal, and the second electrode is connected to the first pull-down node. The first pull-down circuit includes a fourth transistor, wherein the control electrode of the fourth transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second-level signal terminal. The second pull-down circuit includes a sixth transistor, wherein the control electrode of the sixth transistor is connected to the first pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second-level signal terminal. The third pull-down circuit includes a sixteenth transistor, wherein the control electrode of the sixteenth transistor is connected to the first pull-down node, and the second electrode is connected to the second-level signal terminal. The fourth pull-down circuit includes a nineteenth transistor, the control stage of the nineteenth transistor is connected to the first pull-down node, the first electrode is connected to the signal output end, and the second electrode is connected to the third level signal end.

[0171] In some other embodiments, the first pull-down control circuit further includes an eleventh transistor and a twelfth transistor, wherein the control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal; the control electrode of the twelfth transistor is connected to the pull-up node, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The second pull-down control circuit further includes a thirteenth transistor and a fourteenth transistor, wherein the control electrode and the first electrode of the thirteenth transistor are both connected to the second power supply signal terminal, and the second electrode is connected to the second pull-down control node; the control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode is connected to the second power supply signal terminal, and the second electrode is connected to the second pull-down node. The first pull-down circuit further includes a third transistor, wherein the control electrode of the third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The second pull-down circuit further includes a fifth transistor, wherein the control electrode of the fifth transistor is connected to the second pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal. The third pull-down circuit further includes a seventeenth transistor, wherein the control electrode of the seventeenth transistor is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The fourth pull-down circuit further includes a twentieth transistor; the control stage of the twentieth transistor is connected to the second pull-down node, the first electrode is connected to the signal output end, and the second electrode is connected to the third level signal end.

[0172] It should be noted that the third and fourth transistors in the first pull-down circuit have the same structure and function; they simply operate in a time-sharing manner. Similarly, the fifth and sixth transistors in the second pull-down circuit have the same structure and function. The sixteenth and seventeenth transistors in the third pull-down circuit have the same structure and function. The nineteenth and twentieth transistors in the fourth pull-down circuit have the same structure and function. The seventh and eleventh transistors in the first pull-down control circuit have the same structure and function, and the eighth and twelfth transistors have the same structure and function. The ninth and thirteenth transistors in the second pull-down control circuit have the same structure and function, and the tenth and fourteenth transistors have the same structure and function. The input circuit, first reset circuit, second reset circuit, output circuit, and cascade circuit have the same structure and function as described above, and therefore will not be repeated here.

[0173] It should be noted that the signals output by the cascade signal terminal and the signal output terminal are identical, except that the shift register unit has two output terminals: one for connecting to the gate line and the other for cascading. The separate cascade subcircuit is provided to reduce the load on the signal output terminal, thereby preventing it from affecting the gate drive signal outputted by the signal output terminal.

[0174] The specific structure of the shift register unit disclosed in the present invention is described below in conjunction with specific embodiments.

[0175] 7a-7b , which illustrate a first example of a shift register unit provided by the present disclosure, the shift register unit includes an input circuit 1001, a first reset circuit 1002, a first pull-down circuit 1003, a second pull-down circuit 1004, a first pull-down control circuit 1005, a second pull-down control circuit 1006, a second reset circuit 1007, a third pull-down circuit 1008, a fourth pull-down circuit 1009, an output circuit 1010, and a cascade circuit 1011. The shift register unit specifically includes first to twenty-first transistors M21. Specifically, the input circuit 1001 includes a first transistor M1; the first reset circuit 1001 includes a second transistor M2; the first pull-down circuit 1003 includes a fourth transistor M4 and a third transistor M3; the second pull-down circuit 1004 includes a fifth transistor M5 and a sixth transistor M6; the first pull-down control circuit 1005 includes a seventh transistor M7, an eighth transistor M8, an eleventh transistor M11 and a twelfth transistor M12; the second pull-down control circuit 1007 includes a ninth transistor M9, a tenth transistor M10, a thirteenth transistor M13 and a fourteenth transistor M14; the second reset circuit 1006 includes a fifteenth transistor M15; the third pull-down circuit 1008 includes a sixteenth transistor M16 and a seventeenth transistor M17; the cascade circuit 1011 includes an eighteenth transistor M18; the fourth pull-down circuit 1009 includes a nineteenth transistor M19 and a twentieth transistor M20; and the output circuit 1010 includes a twenty-first transistor M21 and a first storage capacitor C1.

[0176] Among them, the control electrode of the first transistor M1 is connected to the first signal input terminal Input, the first electrode is connected to the first level signal terminal VDS, and the second electrode is connected to the pull-up node PU; the control electrode of the second transistor M2 is connected to the second signal input terminal Reset, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the third transistor M3 is connected to the third signal input terminal PD_F, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the fourth transistor M4 is connected to the third signal input terminal PD_F, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the fifth transistor M5 is connected to the second pull-down node Node PD_B, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL end; the control electrode of the sixth transistor M6 is connected to the first pull-down node PD_A, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL end; the control electrode of the seventh transistor M7 is connected to the pull-up node PU, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal LVGL end; the control electrode of the eighth transistor M8 is connected to the pull-up node PU, the first electrode is connected to the first pull-down control node PD_CNA, and the second electrode is connected to the second level signal LVGL end; the control electrode and the first electrode of the ninth transistor M9 are both connected to the first power supply signal end VDD1, and the second electrode is connected to the first pull-down control node PD_C NA; the control electrode of the tenth transistor M10 is connected to the first pull-down control node PD_CNA, the first electrode is connected to the first power signal terminal VDD1, and the second electrode is connected to the first pull-down node PD_A; the control electrode of the eleventh transistor M11 is connected to the pull-up node PU, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the twelfth transistor M12 is connected to the pull-up node PU, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal; the control electrode and the first electrode of the thirteenth transistor M13 are both connected to the second power signal terminal VDD2, and the second electrode is connected to the second pull-down control node PD_CNB; the control electrode of the fourteenth transistor M14 is connected to the second pull-down The control node PD_CNB has a first electrode connected to the second power signal terminal VDD2, and a second electrode connected to the second pull-down node PD_B; the control electrode of the fifteenth transistor M15 is connected to the frame start signal terminal STV0STV0, a ​​first electrode connected to the first clock signal terminal VDD1, and a second electrode connected to the cascade signal terminal OC; the control electrode of the sixteenth transistor M16 is connected to the first pull-down node PD_A, and a second electrode connected to the second level signal LVGL terminal; the control electrode of the seventeenth transistor M17 is connected to the second pull-down node PD_B, and a second electrode connected to the second level signal LVGL terminal; the control electrode of the eighteenth transistor M18 is connected to the pull-up node PU, a first electrode connected to the first clock signal terminal VDD1, and a second electrode connected to the signal output terminal GoutN;The control electrode of the 19th transistor M19 is connected to the first pull-down node PD_A, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal terminal VGL. A 20th transistor M20 is connected to the control electrode of the 20th transistor M20 is connected to the second pull-down node PD_B, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal terminal VGL. A 21st transistor M21 has a control electrode connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal VDD1, and the second electrode is connected to the signal output terminal GoutN. One electrode of the first storage capacitor C1 is connected to the pull-up node PU, and the other electrode is connected to the signal output terminal GoutN.

[0177] It should be noted that, in this embodiment, the first input signal inputted by the first signal input terminal is the cascade signal terminal of the shift register unit of the four upper stages of the current shift register unit (if the current shift register unit is the Nth stage, the cascade signal terminal of the N-4th stage shift register unit is connected), the second input signal connected to the second signal input terminal is the cascade signal terminal of the shift register unit of the four lower stages of the current shift register unit (the cascade signal terminal of the N+4th stage), and the third input signal inputted by the third signal input terminal is the pull-up node voltage of the previous stage (the N-1th stage pull-up node voltage). In this way, when the pull-up node of the previous shift register unit is pulled high, the pull-down node and the pull-down control node of the current shift register unit can be pre-pulled low, thereby improving the competitive relationship between the pull-up node and the pull-down node to enhance the instantaneous low-temperature startup capability and service life.

[0178] The working principle of the shift register unit of this embodiment is described below.

[0179] In the discharge stage, before the frame, that is, before display, a high-level signal is first input to the frame start signal terminal, and the pull-up node PU is discharged through the low-level signal input by the low-level signal terminal to prevent residual charge on the pull-up node PU from causing display abnormalities.

[0180] In the input phase, a high-level signal is input to the first signal input terminal Input, the first transistor M1 is turned on, the pull-up node PU is pulled high by the high-level signal, and the first storage capacitor C1 is charged.

[0181] In the output phase, since the pull-up node PU is pulled high in the input phase, the eighteenth transistor M18 and the twenty-first transistor M21 are both turned on, and the high-level signal inputted from the clock signal terminal is outputted through the signal output terminal GoutN and the cascade signal terminal OCN.

[0182] During the reset phase, a high-level signal is input to the frame start signal terminal STV0, the fifteenth transistor M15 is turned on, and the second-level signal LVGL, i.e., a low-level signal, pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the pull-up node PU is pulled low, the eighteenth transistor M18 and the twenty-first transistor M21 are turned off, and the signal output terminal GoutN and the cascade signal output terminal GoutN no longer output high-level signals. At the same time, the first pull-down control node PD_CNA and the pull-down node are both high-level signals, the fifth transistor M5, the sixteenth transistor M16, and the nineteenth transistor M19 are turned on, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal GoutN, and the cascade signal output terminal OCN, until the pull-up node PU is pulled high at the start of the next frame scan.

[0183] Referring to Figure 7c, Figure 7c illustrates a second example of a shift register unit provided by the present disclosure. This example differs from the first example in Figure 7b in that the shift register unit further includes a third pull-down control subcircuit 1012, and the third input signal inputted to the third input signal terminal is different. Third pull-down control circuit 1012 includes a twenty-second transistor M22 and a twenty-third transistor M23. Similarly, the twenty-second transistor M22 and the twenty-third transistor M23 have the same structure and function, differing only in their operating timing.

[0184] Specifically, the second exemplary shift register unit includes: first to twenty-third transistors M23. The control electrode of the first transistor M1 is connected to the first signal input terminal Input, the first electrode is connected to the first level signal terminal VDS, and the second electrode is connected to the pull-up node PU; the control electrode of the second transistor M2 is connected to the second signal input terminal Reset, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the third transistor M3 is connected to the third signal input terminal PD_F, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the fourth transistor M4 is connected to the third signal input terminal PD_F, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal LVGL terminal; The control electrode of the fifth transistor M5 is connected to the second pull-down node PD_B, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL end; the control electrode of the sixth transistor M6 is connected to the first pull-down node PD_A, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal LVGL end; the control electrode of the seventh transistor M7 is connected to the pull-up node PU, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal LVGL end; the control electrode of the eighth transistor M8 is connected to the pull-up node PU, the first electrode is connected to the first pull-down control node PD_CNA, and the second electrode is connected to the second level signal LVGL end; the control electrode of the ninth transistor M9 is connected to the first pull-down node PD_CNA, and the second electrode is connected to the second level signal LVGL end. The first electrode is connected to the first power signal terminal VDD1, and the second electrode is connected to the first pull-down control node PD_CNA; the control electrode of the tenth transistor M10 is connected to the first pull-down control node PD_CNA, the first electrode is connected to the first power signal terminal VDD1, and the second electrode is connected to the first pull-down node PD_A; the control electrode of the eleventh transistor M11 is connected to the pull-up node PU, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the twelfth transistor M12 is connected to the pull-up node PU, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal; the control electrode and the first electrode of the thirteenth transistor M13 are both connected The control electrode of the fourteenth transistor M14 is connected to the second pull-down control node PD_CNB, the first electrode is connected to the second power signal terminal VDD2, and the second electrode is connected to the second pull-down node PD_B; the control electrode of the fifteenth transistor M15 is connected to the frame start signal terminal STV0, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the cascade terminal; the control electrode of the sixteenth transistor M16 is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal LVGL terminal; the control electrode of the seventeenth transistor M17 is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal;The control electrode of the eighteenth transistor M18 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CLKA, and the second electrode is connected to the signal output terminal GoutN; the control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD_A, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal VGL terminal; the twentieth transistor M20; the control electrode of the twentieth transistor M20 is connected to the second pull-down node PD_B, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal VGL terminal; the control electrode of the twenty-first transistor M21 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CLKA, and the second electrode is connected to the signal output terminal GoutN; one electrode of the first storage capacitor C1 is connected to the pull-up node PU, and the other electrode is connected to the signal output terminal GoutN. The twenty-second transistor M22 has a control electrode connected to the third signal input terminal PD_F, a first electrode connected to the first pull-down control node PD_CNA, and a second electrode connected to the second level signal LVGL terminal. The twenty-third transistor M23 has a control electrode connected to the third signal input terminal PD_F, a first electrode connected to the second pull-down control node PD_CNB, and a second electrode connected to the second level signal LVGL terminal. The twenty-second transistor M22 is configured to transmit the second level signal LVGL to the first pull-down control node PD_CNA under the control of the third input signal.

[0185] It should be noted that, in this embodiment, the first input signal input by the first signal input terminal is the cascade signal terminal of the shift register unit of the upper four levels of the shift register unit of this level (if the shift register unit of this level is the Nth level, the cascade signal terminal of the shift register unit of the N-4th level is connected), the second input signal connected to the second signal input terminal is the cascade signal terminal of the shift register unit of the lower four levels of the shift register unit of this level (the cascade signal terminal of the N+4th level), and the third input signal input by the third signal input terminal is the cascade signal terminal of the shift register unit of the upper five levels (the cascade signal terminal of the N-5th level), that is, when the shift register unit in the N-5th row outputs a high level, the pull-down node and the pull-down control node of the Nth level are pulled down. In this way, the complexity of the circuit can be reduced while ensuring that the circuit function is not affected, and the border of the display panel can be reduced to 200 microns, thereby increasing the screen-to-body ratio.

[0186] The working principle of the second example is basically the same as that of the first example. The difference is that when the shift register unit in the N-5th row outputs a high level, it can not only lower the voltage of the pull-down node, but also lower the voltage of the pull-down control node, further improving the competition relationship between the pull-up node PU and the pull-down node.

[0187] Referring to Figure 7d, Figure 7d is a third example of a shift register unit provided by the present disclosure. This example differs from the second example in Figure 7c in that the first electrode of the eighteenth transistor M18 in the cascade circuit and the first electrode of the twenty-first transistor M21 in the output circuit are connected to different clock signals. The former is connected to the second clock signal terminal CLKB, while the latter is connected to the first clock signal terminal CLKA. That is, the signal output terminal GoutN of the shift register unit outputs the first clock signal CLKA, and the cascade signal terminal OCN outputs the second clock signal CLKB. This design can increase the diversity of the circuit. In addition, the first input signal inputted by the first signal input terminal Input, the second input signal inputted by the second signal input terminal Reset, and the third input signal inputted by the third signal input terminal PD_F are all different from those in the second example. Among them, the first signal input terminal Input is connected to the signal output terminal GoutN of the upper four-stage shift register unit (the signal output terminal GoutN of the N-4th stage), the second signal input terminal Reset is connected to the signal output terminal GoutN of the lower four-stage shift register unit (the signal output terminal GoutN of the N+4th stage), and the third signal input terminal PD_F is connected to the cascade signal terminal OCN of the upper four-stage shift register unit (the cascade signal terminal OCN of the N-4th stage).

[0188] The other circuit structures and working principles of the third example are the same as those of the second example and will not be described again here.

[0189] In a second aspect, the present disclosure provides a method for driving a display panel, and a flow chart of the driving method is shown in Figure 8. As shown in Figure 8, the driving method includes steps S801 to S803.

[0190] Step S801: The timing controller applies a frame start signal and multiple clock signals to the gate driving circuit; the clock signals can make the charging time of the sub-pixels in the odd rows longer than the charging time of the sub-pixels in the even rows.

[0191] Step S802: The gate drive circuit outputs multiple gate drive signals to the sub-pixel array based on the frame start signal and multiple clock signals, and uses the multiple gate drive signals to scan the sub-pixel array one row or multiple rows at a time to turn on each scanned row of sub-pixels, so that the time duration that two adjacent rows of sub-pixels are simultaneously in the on state is greater than or equal to 2 times the unit scan time. For example, the unit scan time is the time required to scan a row of sub-pixels. The sub-pixel array includes multiple sub-pixels arranged in an N×M array, where N and M are both integers greater than 1. The gate drive circuit includes N shift register units respectively connected to the N rows of sub-pixels in the sub-pixel array, and each shift register unit is connected to at least one clock signal line that transmits a clock signal; the gate drive circuit includes multiple groups of shift register groups that are alternately cascaded.

[0192] Step S803: the source driving circuit applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, so that the duration for which the data signals are applied to at least some rows of sub-pixels is greater than the unit scanning time.

[0193] For example, the multiple clock signals may include 8 clock signals. The N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive 8 clock signals respectively. For example, the gate drive circuit, frame start signal, clock signal, gate drive signal, data signal, etc. can be referred to Figures 1, 2A and 2B for the above-mentioned related description, and will not be repeated here.

[0194] For example, in the first time period, the nth row of sub-pixels and the n+1th row of sub-pixels are turned on in sequence, where n is an integer and 1≤n≤N-3; in the second time period, the n+2th row of sub-pixels and the n+3th row of sub-pixels are turned on in sequence, and one of the nth row of data signals and the n+1th row of data signals is applied to the nth row of sub-pixels and the n+1th row of sub-pixels, and the length of the second time period is greater than or equal to 2 times the unit scanning time; in the third time period, the nth row of sub-pixels is turned off, and one of the n+2th row of data signals and the n+3th row of data signals is applied to the n+1th row of sub-pixels, the n+2th row of sub-pixels and the n+3th row of sub-pixels.

[0195] Figure 9a is a schematic diagram of extracting even-numbered rows of data from an initial data frame provided by at least one embodiment of the present disclosure. Figure 9b is a schematic diagram of extracting odd-numbered rows of data from an initial data frame provided by at least one embodiment of the present disclosure. As shown in Figures 9a and 9b, the odd-numbered rows of data from an initial data frame can be extracted to form a first target data frame, and the even-numbered rows of data from the initial data frame can be extracted to form a second target data frame. Alternatively, the odd-numbered rows of data from an initial data frame can be extracted to form a second target data frame, and the even-numbered rows of data from the initial data frame can be extracted to form a first target data frame. By decomposing a data frame into odd frames and even frames, and using the time originally used to display one frame of data to display two frames of data, the refresh rate of the display panel can be increased, thereby improving the display effect. For ease of description, in some of the following embodiments, odd frames and even frames are used to represent the first target data frame and the second target data frame.

[0196] For example, the multiple initial data frames include a first initial data frame and a second adjacent initial data frame. In the first frame, a first target data frame corresponding to the first initial data frame is applied to the subpixel array; in the second frame, a second target data frame corresponding to the first initial data frame is applied to the subpixel array; in the third frame, the first target data frame corresponding to the second initial data frame is applied to the subpixel array; and in the fourth frame, the second target data frame corresponding to the second initial data frame is applied to the subpixel array. In this manner, the first target data frame and the second target data frame are displayed alternately.

[0197] Figure 10 is a schematic diagram of extracting even-numbered row data of an initial data frame provided by at least one embodiment of the present disclosure. As shown in Figure 10, in Mode 1 and Mode 2, the first target data frame and the second target data frame are displayed alternately. The first initial data frame is an odd frame b1 and an even frame c1, the second initial data frame is an odd frame b2 and an even frame c2, the third initial data frame is an odd frame b3 and an even frame c3, and so on. In Mode 1, the odd frame b can be displayed first, and then the even frame c can be displayed, for example, in the order of b1~c1~b2~c2~b3~c3... In Mode 2, the even frame c can be displayed first, and then the odd frame b can be displayed, for example, in the order of c1~b1~c2~b2~c3~b3...

[0198] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the fourth frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0199] For example, as shown in FIG10 , in Mode 3 and Mode 4, the odd and even frames corresponding to each initial data frame are displayed continuously, and two adjacent odd frames are displayed continuously, and two adjacent even frames are displayed continuously. In Mode 3, they are displayed in the order of b1 to c1 to c2 to b2 to b3 to c3… In Mode 4, they are displayed in the order of c1 to b1 to b2 to c2 to c3 to b3… The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0200] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the fourth frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0201] For example, as shown in FIG10 , in modes 5 and 6, the odd frames of two adjacent initial data frames are displayed continuously, and the even frames of two adjacent initial data frames are displayed continuously, and the odd and even frames corresponding to each initial data frame are separated. In mode 5, the sequence of b1 to b2 to c1 to c2 to b3 to b4… is displayed. In mode 6, the sequence of c1 to c2 to b1 to b2 to c3 to c4… is displayed. The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0202] For example, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the length of the charging period is equal to 2 times the unit scanning time, and the length of the pre-charging period is greater than or equal to the unit scanning time.

[0203] For example, the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time, the duration of the pre-charging period is 1.2 times the unit scan time, and the start and end times of the periods of sub-pixels in the on state in two adjacent rows differ by a unit scan time.

[0204] FIG10 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure. In FIG10 , the period during which each row of sub-pixels is in an on state (the corresponding gate drive signals, such as G1-G6, are at a high level) includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in FIG10 , the duration during which each row of sub-pixels is in an on state is 3.2H, wherein the first 1.2H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0205] For example, in some embodiments, as shown in FIG10 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be: in the charging period of the 2k-1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k-1 row sub-pixel; in the first pre-charging period of the 2k row sub-pixel and the first half of the charging period of the 2k row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k row sub-pixel, and in the second half of the charging period of the 2k row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k row sub-pixel; and in the first pre-charging period (or the entire pre-charging period) of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; where k=1, 2, 3,…

[0206] For example, as shown in Figure 10, when displaying odd frames, in the charging period of the 1st row of sub-pixels, the 1st row of data signals are applied to the 1st row of sub-pixels; in the first pre-charging period and the first half of the charging period of the 2nd row of sub-pixels, the 1st row of data signals are applied to the 2nd row of sub-pixels, and in the second half of the charging period of the 2nd row of sub-pixels, the 3rd row of data signals are applied to the 2nd row of sub-pixels; in the first pre-charging period (or the entire pre-charging period) of the 3rd row of sub-pixels, the 1st row of data signals are applied to the 3rd row of sub-pixels, and in the charging period of the 3rd row of sub-pixels, the 3rd row of data signals are applied to the 3rd row of sub-pixels; and so on.

[0207] For example, in a specific embodiment, as shown in FIG10 , the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time H (i.e., 3.2H), of which the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging period of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging period of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving mode can be:

[0208] In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels;

[0209] In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels;

[0210] In the first pre-charging period (or the entire pre-charging period) of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charging period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels;

[0211] In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels;

[0212] In the first pre-charging period (or the entire pre-charging period) of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels;

[0213] In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels;

[0214] Among them, k = 1, 2, 3, ...

[0215] Figure 11 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure. In Figure 11, the period in which each row of sub-pixels is in the on state 1 includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 11, the duration of each row of sub-pixels in the on state is 3.2H, wherein the first 1.2H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H.

[0216] For example, in some embodiments, as shown in FIG11 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0217] In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0218] In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels;

[0219] In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels;

[0220] In the first pre-charging period (or the entire pre-charging period) of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charging period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels;

[0221] Among them, k = 1, 2, 3, ...

[0222] For example, in some examples, as shown in Figure 11, when displaying an even frame, in the second half of the charging period of the first row of sub-pixels, the second row of data signals are applied to the first row of sub-pixels; in the charging period of the second row of sub-pixels, the second row of data signals are applied to the second row of sub-pixels; in the first pre-charging period and the first half of the charging period of the third row of sub-pixels, the second row of data signals are applied to the third row of sub-pixels, and in the second half of the charging period of the third row of sub-pixels, the fourth row of data signals are applied to the third row of sub-pixels; in the first pre-charging period (or the entire pre-charging period) of the fourth row of sub-pixels, the second row of data signals are applied to the fourth row of sub-pixels, and in the charging period of the fourth row of sub-pixels, the fourth row of data signals are applied to the fourth row of sub-pixels; and so on.

[0223] For example, in a specific embodiment, as shown in FIG11 , the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time H (i.e., 3.2H), of which the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging period of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging period of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving mode can be:

[0224] In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels;

[0225] In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels;

[0226] In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels;

[0227] In the first pre-charging period (or the entire pre-charging period) of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels;

[0228] In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels;

[0229] In the first pre-charging period (or the entire pre-charging period) of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels;

[0230] Among them, k = 1, 2, 3, ...

[0231] In the above embodiment, pre-charging can achieve charging boost because the data signal hardly needs to consider the rising delay and the difference between the data signals of two adjacent rows is small, so the image quality of the display device is good.

[0232] For example, in the above embodiment, the duration for which the data signal is applied to each row of sub-pixels is greater than the unit scan time; or, the duration for which the data signal is applied to the first row of sub-pixels is equal to the unit scan time, and the duration for which the data signal is applied to each row of sub-pixels except the first row of sub-pixels is greater than the unit scan time.

[0233] It should be understood that in the embodiments of the present disclosure, the charging period and the pre-charging period are intended to distinguish between two different (sub) periods in the period when each row of sub-pixels is in the on state. Part or all of the pre-charging period of a row or several rows of sub-pixels may not undergo pre-charging operations, and the first half of the charging period of the first row of sub-pixels may not undergo charging operations.

[0234] The embodiments of the present disclosure turn on each row of sub-pixels in sequence and apply data signals to each row of sub-pixels that are in the turned-on state at the same time, so that the actual charging time of some sub-pixels (the total time of the pre-charging period and the charging period) can reach 2H or more.

[0235] In some embodiments, a portion of sub-pixels and another portion of sub-pixels may be driven in different ways in different frames, so that the actual charging time of each sub-pixel in at least one frame is greater than the unit scanning time.

[0236] In the above embodiments, the gate driving circuit is described as being connected to 8 CLK signals. In other embodiments, the gate driving circuit may be connected to 12 CLK signals. This case will be described below.

[0237] FIG12 shows another timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0238] As shown in Figure 12, the high-level duration t1 of the frame start signal STV is 9 hours, the high-level duration t3 of the clock signal CLK is 5 hours, the cycle time t4 of the clock signal CLK is 12 hours, the phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is 4 hours, the phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0 hours, and the phase difference T5 of each clock signal CLK is 1 hour. The duty cycle of the clock signal CLK is 41.6%, which is mainly selected to consider in-plane signal coupling or display defects. The phase difference between the falling edge of STV and the falling edge of CLK1 is 0 hours. Because STV is connected to the first 6 CLKs and generates a first-order PU level, the falling edge of STV is aligned with the rising edge of CLK6. That is, after STV ends, CLK immediately starts to rise, generating a second-order PU, fully controlling the GOA output and avoiding leakage at the PU point.

[0239] Figure 13 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 13, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 14, the duration of each row of sub-pixels in the on state is 5H, wherein the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0240] For example, in some embodiments, as shown in FIG14 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0241] In a charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0242] In the first precharge period of the 2kth row of sub-pixels and the first half of the charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels, and in the second half of the charging period of the 2kth row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2kth row of sub-pixels;

[0243] In the first precharge period of the 2k+1th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2k+1th row of sub-pixels; wherein k=1, 2, 3, . . .

[0244] For example, in a specific embodiment, as shown in FIG14 , the driving mode may be:

[0245] In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels;

[0246] In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels;

[0247] In the first pre-charge period of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charge period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels;

[0248] In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels;

[0249] In the first pre-charging period of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels;

[0250] In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels;

[0251] Among them, k = 1, 2, 3, ...

[0252] Figure 15 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 15, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 15, the duration of each row of sub-pixels in the on state is 5H, wherein the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0253] For example, in some embodiments, as shown in FIG15 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0254] In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0255] In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels;

[0256] In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels;

[0257] In the first pre-charging period (or the entire pre-charging period) of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charging period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels;

[0258] Among them, k = 1, 2, 3, ...

[0259] For example, in a specific embodiment, as shown in FIG15 , the driving mode may be:

[0260] In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels;

[0261] In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels;

[0262] In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels;

[0263] In the first pre-charging period (or the entire pre-charging period) of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels;

[0264] In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels;

[0265] In the first pre-charging period (or the entire pre-charging period) of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels;

[0266] Among them, k = 1, 2, 3, ...

[0267] In the above embodiment, pre-charging can achieve charging boost because the data signal hardly needs to consider the rising delay and the difference between the data signals of two adjacent rows is small, so the image quality of the display device is good.

[0268] At least one embodiment of the present disclosure further provides a display device comprising the display panel of the aforementioned embodiment. The display device may be any device, such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigation system, or any combination of electronic devices and hardware, without limitation in the embodiments of the present disclosure.

[0269] It should be noted that for the sake of clarity and brevity, the embodiments of the present disclosure do not provide all components of the display device. To achieve the necessary functions of the electronic device, those skilled in the art may provide and configure other components not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0270] For the relevant description and technical effects of the display device, reference may be made to the relevant description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be repeated here.

[0271] There are a few points to note:

[0272] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0273] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0274] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display panel comprising a timing controller, a gate driver circuit, a source driver circuit, and a sub-pixel array; the sub-pixel array comprising a plurality of sub-pixels arranged in an N*M array, where N and M are both integers greater than 1; The timing controller is configured to provide a frame start signal and a plurality of clock signals to the gate drive circuit; the gate drive circuit is configured to provide a plurality of gate drive signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and to scan the sub-pixel array one row or multiple rows by using the plurality of gate drive signals, so as to turn on the sub-pixels in each scanned row, so that the time length during which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to 2 times of a unit scan time, where the unit scan time is the time required to scan a row of sub-pixels; the source drive circuit is configured to provide a data signal to the sub-pixels in the turned-on state; wherein, The gate driving circuit includes N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, and each of the shift register units is connected to at least one clock signal line for transmitting a clock signal; The timing controller is configured to provide a clock signal having an effective level duration greater than that provided to the clock signal line corresponding to the sub-pixel row for writing real data.

2. The display panel according to claim 1, wherein The sub-pixel rows into which the real data is written and the sub-pixel rows into which the interpolation data is written are alternately arranged.

3. The display panel according to claim 1, wherein: The N shift register units include a first-stage shift register unit connected to a first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal; The rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

4. The display panel according to claim 3, wherein: The first-stage shift register unit to the p-th stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals also include a p-th clock signal for driving the p-th stage shift register unit to output a gate drive signal; The duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured so that the falling edge of the frame start signal is aligned with the rising edge of the pth clock signal, where p is an integer greater than 1.

5. The display panel according to claim 4, wherein: The phase difference between the rising edges of every two adjacent clock signals in the multiple clock signals is the unit scan time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%.

6. The display panel according to any one of claims 1 to 5, wherein: The period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scanning time, and the duration of the pre-charging period is greater than or equal to the unit scanning time.

7. The display panel according to claim 1, wherein: The gate driving circuit includes m gate driving sub-circuits, each of which includes 4n shift register units, where 1≤m≤6, 1≤n≤4; m and n are both integers; The gate driving sub-circuit includes a first shift register group and a second shift register group; one of the first shift register group and the second shift register group includes each odd-numbered shift register unit among 4n shift register units, and the other includes each even-numbered shift register unit; Each of the adjacent 4n shift register units is connected to the 4n clock signal lines in a one-to-one correspondence, and the i-th shift register unit and the i+4n-th shift register are connected to the same clock signal line; i ranges from 1 to N-4n.

8. The display panel according to claim 7, wherein: The gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes 8 shift register units; The signal input ends of the 1st to 4th shift register units respond to the frame start signal; the signal output end of the ath shift register unit is connected to the signal input end of the a+4th shift register unit; the frame start signal end of the bth shift register unit is connected to the signal output end of the b+4th shift register unit; 1≤a≤4, 1≤b≤4.

9. The display panel according to claim 3, wherein: The gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes 12 shift register units; The signal input ends of the 1st to 6th shift register units respond to the frame start signal; the signal output end of the ath shift register unit is connected to the signal input end of the a+6th shift register unit; the frame start signal end STV0 of the bth shift register unit is connected to the signal output end of the b+6th shift register unit; 1≤a≤6, 1≤b≤6.

10. The display panel according to claim 1, wherein The shift register unit includes: an input circuit configured to transmit a first level signal to a pull-up node under the control of a first input signal; A first reset circuit is configured to transmit a second level signal to the pull-up node under the control of a second input signal; a first pull-down circuit configured to transmit the second level signal to the pull-down node under the control of a third input signal; a second pull-down circuit configured to transmit the second level signal to the pull-up node under the control of the pull-down node voltage; a first pull-down control circuit configured to transmit the second level signal to a pull-down control node and the pull-down node under control of the pull-up node voltage; a second pull-down control circuit configured to transmit the power signal to the pull-down node and the pull-down control node under the control of a power signal; a second reset circuit, configured to reset the pull-up node under the control of a reset signal; a third pull-down circuit configured to transmit the second level signal to the cascade terminal under the control of the pull-down node voltage; a fourth pull-down circuit configured to transmit the third level signal to the signal output terminal under the control of the pull-down node; an output circuit configured to transmit a clock signal to a signal output terminal under control of the pull-up node voltage; The cascade circuit is configured to transmit the clock signal to the cascade terminal under the control of the pull-up node voltage.

11. The display panel according to claim 10, wherein: The power signal includes a first power signal and a second power signal; the first power signal and the second power signal are same-frequency and opposite-direction signals.

12. The display panel according to claim 11, wherein: The input circuit includes a first transistor; the control electrode of the first transistor is connected to the first signal input terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the pull-up node.

13. The display panel according to claim 11, wherein: The first reset circuit includes a second transistor; the control electrode of the second transistor is connected to the second signal input terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal.

14. The display panel according to claim 11, wherein: The pull-down node includes a first pull-down node, and the pull-down control node includes a first pull-down control node; The first pull-down control circuit includes: a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is connected to the pull-up node, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; the control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal; The second pull-down control circuit includes: a ninth transistor and a tenth transistor; The control electrode and the first electrode of the ninth transistor are both connected to the first power signal terminal, and the second electrode is connected to the first pull-down control node; the control electrode of the tenth transistor is connected to the first pull-down control node, the first electrode is connected to the first power signal terminal, and the second electrode is connected to the first pull-down node.

15. The display panel according to claim 14, wherein: The pull-down node further includes a second pull-down node, and the pull-down control node further includes a second pull-down control node; The first pull-down control circuit further includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal; the control electrode of the twelfth transistor is connected to the pull-up node, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal; The second pull-down control circuit further includes: a thirteenth transistor and a fourteenth transistor; The control electrode and the first electrode of the thirteenth transistor are both connected to the second power signal terminal, and the second electrode is connected to the second pull-down control node; the control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode is connected to the second power signal terminal, and the second electrode is connected to the second pull-down node.

16. The display panel according to claim 11, wherein The pull-down node includes a first pull-down node; The first pull-down circuit includes a fourth transistor; the control electrode of the fourth transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; The second pull-down circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the first pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal; The third pull-down circuit includes a sixteenth transistor; the control electrode of the sixteenth transistor is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; The fourth pull-down circuit includes a nineteenth transistor; the control stage of the nineteenth transistor is connected to the first pull-down node, the first electrode is connected to the signal output end, and the second electrode is connected to the third level signal end.

17. The display panel according to claim 16, wherein: The pull-down node further includes a second pull-down node; The first pull-down circuit further includes a third transistor; the control electrode of the third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal; The second pull-down circuit further includes a fifth transistor; the control electrode of the fifth transistor is connected to the second pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal; The third pull-down circuit further includes a seventeenth transistor; The control electrode of the seventeenth transistor is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal; The fourth pull-down circuit further includes a twentieth transistor; a control stage of the twentieth transistor is connected to the second pull-down node, a first electrode is connected to the signal output end, and a second electrode is connected to the third level signal end.

18. The display panel according to claim 11, wherein: The second reset circuit includes a fifteenth transistor; the control electrode of the fifteenth transistor is connected to the frame start signal terminal STV0, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the cascade terminal.

19. The display panel according to claim 11, wherein: The output circuit includes a twenty-first transistor and a first storage capacitor; The control electrode of the twenty-first transistor is connected to the pull-up node, the first electrode is connected to the clock signal end, and the second electrode is connected to the signal output end; one electrode of the first storage capacitor is connected to the pull-up node, and the other electrode is connected to the signal output end.

20. The display panel according to claim 11, wherein The cascade circuit includes an eighteenth transistor; the control electrode of the eighteenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal end, and the second electrode is connected to the signal output end.

21. The display panel according to claim 10, wherein: The shift register unit further includes a third pull-down control circuit; the third pull-down control circuit is configured to transmit the second level signal to the pull-down control node under the control of a third input signal.

22. The display panel according to claim 21, wherein: The pull-down control node includes a first pull-down control node; The third pull-down control circuit includes a 22nd transistor; the control electrode of the 22nd transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal.

23. The display panel according to claim 22, wherein: The pull-down control node further includes a second pull-down control node; The third pull-down control circuit package further includes a twenty-third transistor; the control electrode of the twenty-third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal.

24. A method for driving a display panel, wherein: The display panel includes a timing controller, a gate driving circuit, and a source driving circuit, and the method includes: The timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit; the timing controller is configured so that the effective level duration of the clock signal provided by the clock signal line corresponding to the sub-pixels in the odd rows is longer than the effective level duration of the clock signal provided by the clock signal line corresponding to the sub-pixels in the even rows; The gate drive circuit outputs a plurality of gate drive signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and uses the plurality of gate drive signals to scan the sub-pixel array row by row or multiple rows one by one, so as to turn on the sub-pixels in each scanned row, so that the time length during which two adjacent rows of sub-pixels are simultaneously in the on state is greater than or equal to 2 times the unit scan time, where the unit scan time is the time required to scan a row of sub-pixels, wherein the sub-pixel array includes a plurality of sub-pixels arranged in an N×M array, where N and M are both integers greater than 1; the gate drive circuit includes comprising N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, each of the shift register units being connected to at least one clock signal line for transmitting a clock signal; the gate driving circuit comprising a plurality of shift register groups alternately cascaded; and The source driving circuit applies data signals to at least two rows of sub-pixels that are simultaneously in an on state, so that the duration of applying the data signals to at least some rows of sub-pixels is greater than the unit scanning time.

25. The driving method according to claim 22, wherein: The pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period being the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises: In a charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels; In the first precharge period of the 2kth row of sub-pixels and the first half of the charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels, and in the second half of the charging period of the 2kth row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2kth row of sub-pixels; In a first pre-charge period of the 2k+1th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2k+1th row of sub-pixels; Among them, k = 1, 2, 3, ...

26. The driving method according to claim 24, wherein: The pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period being the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises: In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels; In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels; In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels; In the first pre-charge period of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charge period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels; Among them, k = 1, 2, 3, ...

27. The driving method according to claim 24, wherein: The pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period being the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises: In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels; In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels; In the first pre-charging period of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charging period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels; In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels; In the first pre-charging period of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels; In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels; Among them, k = 1, 2, 3, ...

28. The driving method according to claim 24, wherein: The pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period being the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels of two adjacent rows are in the on state differ by a unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state comprises: In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels; In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels; In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels; In the first pre-charging period of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels; In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels; In the first pre-charging period of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels; Among them, k = 1, 2, 3, ...

29. A display device comprising the display panel according to any one of claims 1 to 23.

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