Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a plurality of first active patterns; a plurality of first metal wires; and a plurality of conductive portions. Each conductive portion comprises: a first conductive portion and a second conductive portion that are distributed in a first direction; adjacent first metal wires on two sides of each conductive portion comprise a first sub-metal wire and a second sub-metal wire, wherein the first sub-metal wire is electrically connected to a second portion, and a first portion is electrically connected to a first electrode by means of the corresponding conductive portion; and at least the distance between the orthographic projection of the second conductive portion on a substrate and the orthographic projection of the first sub-metal wire on the substrate is greater than the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second sub-metal wire on the substrate.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Virtual reality technology seamlessly integrates real-world and virtual-world information. Compared to conventional display products, the most notable feature of VR display products is their ultra-high resolution. Liquid crystal display (LCD) technology is currently the best choice for achieving ultra-high PPI. This is because LCD display architectures use only a single switching transistor (TFT) in the pixel area, making it highly suitable for achieving high PPI.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] substrate;

[0006] The first active layer is located on one side of the substrate and includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction;

[0007] The first metal layer includes: a plurality of first metal lines; the second portion overlaps with a portion of the first metal line in an orthographic projection of the substrate;

[0008] The second metal layer includes: a plurality of second metal lines extending along a second direction;

[0009] The first conductive layer comprises: a plurality of conductive portions located in the display area; at least one of the plurality of conductive portions having an orthographic projection of the substrate located between orthographic projections of adjacent first metal lines on the substrate; the conductive portions comprising: a first conductive portion and a second conductive portion distributed along the first direction; the orthographic projection of the first conductive portion on the substrate having an overlapping region with the orthographic projection of the first portion on the substrate, and the second conductive portion having an overlapping region with the orthographic projection of the second portion on the substrate; and the first conductive portion and the second conductive portion extending in different directions;

[0010] The second conductive layer includes: a plurality of first electrodes located in the display area;

[0011] Among them, the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein, the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; at least the distance between the orthographic projection of the second conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate is greater than the distance between the orthographic projection of the second conductive part on the substrate and the orthographic projection of the second sub-metal wire on the substrate.

[0012] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0013] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0014] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0015] The first conductive portion extends along an extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

[0016] In one possible implementation, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; an extension line of the first outer edge intersects an extension line of the second outer edge;

[0017] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0018] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0019] The first outer edge extends along the first direction; the extending direction of the second outer edge is the same as the extending direction of the first sub-metal portion.

[0020] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0021] The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal trace;

[0022] The distance between the orthographic projection of the second sub-edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0023] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0024] The second sub-edge extends along an extending direction of the first sub-metal portion.

[0025] In a possible implementation manner, the first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion.

[0026] In a possible implementation manner, a first bending portion is provided between the first sub-metal portion and the second sub-metal portion; and the first outer edge has a second bending portion;

[0027] The orthographic projection of the second bent portion on the substrate is located in an area between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is a connecting line of the first bent portions of two adjacent first metal wires.

[0028] In a possible embodiment, the array substrate further includes: a third metal layer located on a side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate;

[0029] The orthographic projection of the first bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire facing the first conductive portion.

[0030] In a possible implementation manner, the first outer edge has a second bent portion;

[0031] The orthographic projection of the second bent portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate. The first metal edge is the outer edge of the second metal wire facing the first conductive portion.

[0032] In a possible embodiment, the first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and the extension direction of the first conductive portion is the same as the extension direction of the first sub-metal portion.

[0033] In a possible embodiment, the first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; the extension direction of the first electrode portion is the same as the extension direction of the first sub-metal portion, and the extension direction of the second electrode portion is the same as the extension direction of the second sub-metal portion.

[0034] In a possible implementation manner, the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second conductive portion on the substrate have an overlapping area, and are electrically connected at the overlapping position.

[0035] In a possible implementation manner, the first conductive portion has a third outer edge facing the first sub-metal line, and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge.

[0036] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0037] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0038] In a possible implementation, the second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located on a side of the second metal wire away from the first conductive portion.

[0039] In a possible implementation, the second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

[0040] In a possible implementation manner, the second metal wire has a sixth outer edge extending along the second direction;

[0041] The orthographic projection of a portion of the sixth outer edge on the substrate coincides with the orthographic projection of the fifth outer edge on the substrate.

[0042] In one possible embodiment, the second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion;

[0043] The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along the second direction and are arranged overlappingly along the first direction;

[0044] The first active pattern row and the second active pattern row both include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects the fourth direction.

[0045] In a possible implementation manner, in the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

[0046] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0047] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1A is a schematic diagram showing a crosstalk problem in a display panel;

[0049] FIG1B is a second schematic diagram of a display panel having crosstalk defects;

[0050] FIG1C is a third schematic diagram of a display panel having crosstalk defects;

[0051] FIG1D is a fourth schematic diagram of a display panel having crosstalk defects;

[0052] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0053] FIG2B is a schematic diagram of a single film layer of the third metal layer in FIG2A ;

[0054] FIG2C is a schematic diagram of a single film layer of the first active layer in FIG2A ;

[0055] FIG2D is a schematic diagram of a single film layer of the second metal layer in FIG2A ;

[0056] FIG2E is a schematic diagram of a single film layer of the first metal layer in FIG2A ;

[0057] FIG2F is a schematic diagram of a single film layer of the first conductive layer in FIG2A ;

[0058] FIG2G is a schematic diagram of a single film layer of the second conductive layer in FIG2A ;

[0059] FIG3 is a schematic cross-sectional view of the dashed line A1A2 in FIG2A ;

[0060] FIG4A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0061] FIG4B is a schematic diagram of a first metal wire M11 and associated structures provided in an embodiment of the present disclosure;

[0062] FIG4C is a schematic diagram of adjacent pixel electrodes and associated structures provided by an embodiment of the present disclosure;

[0063] FIG. 4D is a diagram of the first coupling capacitor C corresponding to FIG. 4A . dp1 Schematic diagram of the composition;

[0064] FIG. 4E is a diagram of the second coupling capacitor C corresponding to FIG. 4A . dp2 Schematic diagram of the composition;

[0065] FIG5 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0066] FIG6A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0067] FIG6B is a schematic diagram of a single film layer of the first conductive layer in FIG6A ;

[0068] FIG6C is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0069] FIG7 is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0070] FIG8 is a sixth schematic diagram of an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] Those skilled in the art will readily appreciate that the methods and contents may be transformed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited solely to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be combined arbitrarily unless there is a conflict.

[0072] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0073] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0074] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0075] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0076] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0077] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0078] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0079] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0080] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0081] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0082] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0083] In the related art virtual reality (VR) head-mounted display product, the coupling capacitance Cdp1 between the data line and the electrically connected pixel is 1.322Ff; the coupling capacitance Cdp2 between the data line and the adjacent pixel is 1.173Ff; the difference in coupling capacitance between Cdp1 and Cdp2 (i.e. ) is 11.27%, which is a large difference. In the column inversion structure, the pixel electrode is affected by the large difference in coupling capacitance between the two adjacent data lines (loaded with data signals of opposite polarity), and the voltage of the pixel electrode is easily deviated from the level, which makes crosstalk prone to occur in the vertical direction.

[0084] Specifically, as shown in FIG1A , there is a first coupling capacitor C between the data line and its own pixel electrode (the own pixel electrode can be understood as the pixel electrode electrically connected to the data line) inside the pixel. dp1 , and a second coupling capacitor C with an adjacent pixel electrode (a pixel electrode not electrically connected to the data line) dp2 , when C dp1 >C dp2 When the difference is large, conventional crosstalk problems may occur. For example, when displaying a picture with white in the middle and black at the edges as shown in FIG1B , the picture may appear bright at the top and dark at the bottom, with the middle as the boundary, as shown in FIG1C . Specifically, in conjunction with FIG1B , FIG1C and FIG1D , pixel A1 and pixel A2 are two pixels at different positions on the same data line, pixel B1 and pixel B2 are two pixels at different positions on the same data line, pixel B1 and pixel A1 are two pixels in the same row on adjacent data lines, and pixel B2 and pixel A2 are two pixels in the same row on adjacent data lines; when the pixel self-coupling effect (the first coupling capacitor C dp1 ) and mutual coupling effect (second coupling capacitance C dp2 ) are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, causing the voltage difference between pixel A1 and the common electrode voltage (Vcom) to increase, and the display is bright; the charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, causing the voltage difference between pixel A2 and the common electrode voltage (Vcom) to decrease, and the display is dark, that is, the undesirable phenomenon of bright top and dark bottom of the Crosstalk screen occurs.

[0085] In view of this, referring to Figures 2A-2G and Figure 3, wherein Figure 2B is a schematic diagram of a single film layer of the third metal layer in Figure 2A, Figure 2C is a schematic diagram of a single film layer of the first active layer in Figure 2A, Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A, Figure 2E is a schematic diagram of a single film layer of the first metal layer in Figure 2A, Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A, Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A, Figure 3 is a schematic diagram of a cross-section at the dotted line A1A2 in Figure 2A, and Figure 4A is a schematic diagram of only a portion of the film layers in Figure 2A. An embodiment of the present disclosure provides an array substrate, which includes:

[0086] substrate 11;

[0087] The first active layer C1 is located on one side of the substrate 11 and includes a plurality of first active patterns C11. The first active pattern C11 includes a first portion CA and a second portion CB distributed along a first direction X. The second portion CB extends in a different direction from the first portion CA.

[0088] The first metal layer M1 includes: a plurality of first metal lines M11; an orthographic projection of a first portion CA on the substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate 11; a portion of the orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of the orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors; the second portion CB may serve as a first electrode of the first transistor at a position where it overlaps with the first metal line M11; the second portion CB may be conductive at a position where it overlaps with the first metal line M11, thereby achieving electrical connection between the first transistor and the data line;

[0089] The second metal layer M2 includes: a plurality of second metal lines M21 extending along the second direction Y;

[0090] The first conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive portions D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; the conductive portion D11 includes: a first conductive portion DA and a second conductive portion DB distributed along the first direction X; the orthographic projection of the first conductive portion DA on the substrate 11 overlaps with the orthographic projection of the first portion CA on the substrate 11, and the second conductive portion DB overlaps with the orthographic projection of the second portion CB on the substrate 11; the first conductive portion DA and the second conductive portion DB extend in different directions; specifically, the first conductive layer D1 may be a transparent conductive layer, and the conductive portion D11 may serve as the second electrode of the first transistor, connecting the first active pattern C11 to the first electrode D21; specifically, the orthographic projection of the conductive portion D11 on the substrate 11 may be a meander, and the maximum length of the conductive portion D11 in the first direction X may be greater than the length in the second direction Y;

[0091] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as that of the first conductive layer D1; specifically, the first electrodes D21 may be pixel electrodes; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be in a meandering shape; the length of the first electrodes D21 in the first direction X may be greater than the length in the second direction Y;

[0092] Among them, the first metal wire M11 adjacent to both sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first sub-metal wire MA, and the other first metal wire M11 is used as the second sub-metal wire MB; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; at least the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0093] In the embodiment of the present disclosure, at least the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second conductive portion DB and the second sub-metal line MB on the substrate 11. This can increase the spacing between the second conductive portion DB and the first sub-metal line MA, thereby reducing the capacitance between the second conductive portion DB and the first sub-metal line MA, and increasing the capacitance between the second sub-metal line MB, thereby reducing the difference between the two, thereby improving poor vertical crosstalk.

[0094] The first metal line M11 and its associated structure can form a first coupling capacitor Cdp1 with its own pixel electrode and its associated structure; the first metal line M11 and its associated structure can form a second coupling capacitor Cdp2 with the adjacent pixel electrode and its associated structure; wherein the own pixel electrode and its associated structure can be the area shown in the dotted box in FIG4A, and specifically can include: the first electrode D21 (as shown in the dotted box S1 in FIG4A), and the conductive portion D11 connected to the first electrode D21 through the second via K2 (as shown in the dotted box S2 in FIG4A), and the conductive portion D11 through the first via K The first active pattern C11 connected to the first active pattern C11 is located at a portion of the second metal line M21 on a side away from the second metal line M21 in the first direction X (as shown by the dotted box S3 in FIG4A , that is, the portion of the first active pattern C11 located below the second metal line M21. Since the time during which each row of pixels is turned on is very short within a display frame, it can be considered that the gate of the first transistor in the pixel is turned off for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator). The first metal line M11 and the associated structure can be shown as shown by the dotted box in FIG4B . The region may specifically include: the first metal line M11 (as shown in the dotted box S4 in FIG4B ), and a portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3 and located on the side of the second metal line M21 close to the second metal line M21 in the first direction X (as shown in the dotted box S5 in FIG4B , that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrode and associated structure may be as shown in the dotted box in FIG4C , and specifically include: the adjacent first electrode D21 (as shown in the dotted box S6 in FIG4C ), And the adjacent conductive portion D11 to which the adjacent first electrode D21 is connected through the second via K2 (as shown in the dotted box S7 in Figure 4C ), and the adjacent first active pattern C11 to which the adjacent conductive portion D11 is connected through the first via K1 is located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S8 in Figure 4C , that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21); the composition of the first coupling capacitor Cdp1 can be as shown in Figure 4D , and the composition of the second coupling capacitor Cdp2 can be as shown in Figure 4E .

[0095] After research by the inventors of this application, it was found that the main reason for the difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is the asymmetry of the design of the first active pattern C11. In addition, since the film layer between the first active layer C1 and the first conductive layer D1 is relatively thin, and the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 overlap up and down (as shown in the area of ​​the thick solid frame S in FIG4D ), the facing capacitance is relatively large, while there is no such overlap in the second coupling capacitor Cdp2, thereby forming a difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2. (In addition, although the overlapping area between the first active pattern C11 and the first electrode D21 in the first coupling capacitor Cdp1 is larger than the overlapping area between the first active pattern C11 and the conductive portion D11, due to the presence of a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored); and since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 dominates the second coupling capacitor Cdp2.

[0096] In the embodiment of the present disclosure, by making the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the second sub-metal line MB on the substrate 11, the lateral capacitance between the first metal line M11 and the second conductive part DB can be increased, thereby increasing the second coupling capacitance Cdp2. Since the overlapping capacitance between the first active pattern C11 and the conductive part D11 (the area shown by the thick solid box S in Figure 4D) accounts for the majority of the first coupling capacitance Cdp1, the reduced distance between the conductive part D11 and the second sub-metal line MB will not have a significant impact on the first coupling capacitance Cdp1, thereby reducing the difference between the second coupling capacitance Cdp2 and the first coupling capacitance Cdp1, thereby improving poor vertical crosstalk.

[0097] It should be noted that the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the minimum spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; when the outer edge of the orthographic projection of the second conductive portion DB on the substrate 11 is partially uneven due to the manufacturing process, the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the average spacing between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; similarly, in the second conductive portion DB When the outer edge of the orthographic projection of the substrate 11 is a straight line, the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be the minimum distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11; when the outer edge of the orthographic projection of the second conductive part DB on the substrate 11 is partially uneven due to the manufacturing process, the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be the average distance between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0098] It should be noted that the first sub-metal line MA is electrically connected to the second portion CB. This can be understood as the first sub-metal line MA being electrically connected to the second portion CB via the first transistor.

[0099] In one possible embodiment, referring to FIG2A , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; a distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11.

[0100] In one possible embodiment, referring to FIG2A , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first conductive portion DA extends along the extension direction of the second sub-metal portion M1b, and the second conductive portion DB extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first conductive portion DA is the same as the extension direction of the second sub-metal portion M1b, and the extension direction of the second conductive portion DB is the same as the extension direction of the first sub-metal portion M1a.

[0101] In one possible embodiment, as shown in FIG2A , the first outer edge w1 is parallel to the second outer edge w2. In the disclosed embodiment, the conductive portion D11 can be shifted rightward as a whole, thereby ensuring that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0102] In a possible embodiment, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: 0.05μm≤(ab) / 2≤0.15μm; specifically, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: 0.06μm≤(ab) / 2≤0.14μm; specifically, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: 0.07μm≤(ab) / 2≤0.13μm; specifically, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive portion DB, the first sub-metal wire MA, and the second sub-metal wire MB can satisfy the relationship: The line MA and the second sub-metal line MB can satisfy the relationship: 0.09μm≤(ab) / 2≤0.11μm; specifically, the second conductive portion DB, the first sub-metal line MA, and the second sub-metal line MB can satisfy the relationship: (ab) / 2=0.1μm; in the embodiment of the present disclosure, after the second conductive portion DB is shifted right by 0.1μm, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.253Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.264Ff; the difference in coupling capacitance between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.87%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0103] In a possible embodiment, referring to FIG5 , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; an extension line of the first outer edge w1 intersects with an extension line of the second outer edge w2; a distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11. In the embodiment of the present disclosure, the upper end of the conductive portion D11 can be straightened, so that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second conductive portion DB and the second sub-metal line MB on the substrate 11; specifically, after the upper end of the conductive portion D11 is straightened, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.187Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.176Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.93%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0104] In one possible embodiment, referring to FIG5 , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b alternately arranged along a first direction; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first outer edge w1 extends along the first direction X; the second outer edge w2 extends along the extension direction of the first sub-metal portion M1a. Specifically, the extension direction of the second outer edge w2 is the same as the extension direction of the first sub-metal portion M1a.

[0105] In one possible embodiment, in combination with Figures 6A and 6B, the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; the first outer edge w1 includes: a first sub-edge portion w11, and a second sub-edge portion w12; the second sub-edge portion w12 is located on a side of the first sub-edge portion w11 away from the first conductive portion DA, and the second sub-edge portion w12 is located on a side of the extension line of the first sub-edge portion w11 facing the first sub-metal trace MA; a distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate. In the embodiment of the present disclosure, the upper end of the conductive portion D11 can be retracted, thereby achieving a distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11, which is greater than the distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate.

[0106] In a possible embodiment, as shown in FIG6A and FIG6B, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.3μm≤ab≤0.9μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.4μm≤ab≤0.8μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.5μm≤ab≤0.7μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.5μm≤ab≤0.7μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB can satisfy the relationship: ab = 0.6μm; in the embodiment of the present disclosure, after the upper end of the conductive portion D11 is retracted by 0.6um, the first coupling capacitance Cdp1 between the first metal wire M11 and the connected pixel is 1.185Ff; the second coupling capacitance Cdp2 between the first metal wire M11 and the adjacent pixel is 1.175Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.84%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal wire M11, thereby avoiding the occurrence of vertical crosstalk.

[0107] In one possible embodiment, in combination with Figures 6A and 6B, the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the second sub-edge w12 extends along the extension direction of the first sub-metal portion M1a, specifically, the extension direction of the second sub-edge w12 is the same as the extension direction of the first sub-metal portion M1a.

[0108] In a possible embodiment, in combination with Figures 6A and 6B, the first sub-edge w11 extends along the extension direction of the second sub-metal portion M1b; the second outer edge w21 extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first sub-edge w11 is the same as the extension direction of the outer edge of the first conductive portion DA toward the first sub-metal wire MA, that is, the extension line of the outer edge of the first conductive portion DA toward the first sub-metal wire MA can be used as the first sub-edge w11; the extension direction of the second sub-edge w12 is parallel to the extension direction of the second outer edge w2.

[0109] In a possible embodiment, as shown in Figure 6C, there is a first bending portion O between the first sub-metal portion M1a and the second sub-metal portion M1a; the first outer edge w1 has a second bending portion Q; the second bending portion Q is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the first connecting line OO on the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA, and the first connecting line OO is the connecting line of the first bending portions O of two adjacent first metal wires M11.

[0110] In a possible embodiment, in combination with Figure 6C, the array substrate also includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal wires M31 extending along the second direction Y; the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second metal wire M21 on the substrate; the orthographic projection of the second bend portion Q on the substrate 11 is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second metal edge f2 on the substrate 11, and the second metal edge f2 is the outer edge of the third metal wire M31 on the side facing the first conductive portion DA.

[0111] In one possible embodiment, as shown in conjunction with Figures 6A and 6B , the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA. In the disclosed embodiment, the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, thereby achieving a larger spacing between the second conductive portion DB and the first sub-metal wire MA while ensuring the conductive effect of the second via K2 (which connects the conductive portion D11 to the first electrode D21), thereby avoiding the situation where the improper positioning of the second bend Q may affect the conductive effect of the second via K2 connecting the conductive portion D11 to the first electrode D21.

[0112] In a possible implementation, as shown in FIG. 6A and FIG. 6B , the second outer edge w2 includes a third bending portion P, and the orthographic projection of the third bending portion P on the substrate 11 may overlap with the orthographic projection of the first connecting line OO on the substrate 11 .

[0113] In one possible embodiment, as shown in Figures 2A, 5, or 6A, the first conductive portion DA is located between two adjacent first sub-metal portions M1a in the second direction Y; the second conductive portion DB is located between two adjacent second sub-metal portions M1b in the second direction Y. The first conductive portion DA extends in the same direction as the first sub-metal portion M1a. That is, within conductive portion D11, the bending trends of the first conductive portion DA and the second conductive portion DB align with the bending trend of the first metal wire M11, and conductive portion D11 bends accordingly at the location where the first metal wire M11 bends.

[0114] In one possible embodiment, referring to FIG. 2A , the first electrode D21 includes: a first electrode portion DC and a second electrode portion DD distributed along a first direction X; an extension direction of the first electrode portion DC is the same as an extension direction of the first sub-metal portion M1a, and an extension direction of the second electrode portion DD is the same as an extension direction of the second sub-metal portion M1b.

[0115] It should be noted that, in Figure 2A, only part of the second electrode portion DD is shown. The second electrode portion DD may have more parts, but the extension direction of the remaining parts of the second electrode portion DD that are not shown may be consistent with the extension direction of the second electrode portion DD shown in the figure. It is only an extension in the extension direction. Specifically, it can be combined with what is shown in Figure 8. The embodiments of the present disclosure are not limited to this.

[0116] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the first electrode portion DC on the substrate 11 and the orthographic projection of the second conductive portion DB on the substrate 11 have an overlapping area and are electrically connected at the overlapping position.

[0117] In a possible embodiment, as shown in FIG. 2A , the first conductive portion DA has a third outer edge w3 facing the first sub-metal wire MA and a fourth outer edge w4 facing the second sub-metal wire MB; the third edge w3 is parallel to the fourth outer edge w4.

[0118] In one possible embodiment, as shown in FIG2A , the distance c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than the distance d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11. In other words, the conductive portion D11 can be shifted rightward as a whole to achieve a distance a between the second conductive portion DB and the first sub-metal trace MA that is greater than the distance b between the second conductive portion DB and the second sub-metal trace MB.

[0119] In one possible embodiment, as shown in Figure 6A, the distance c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is equal to the distance d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11.

[0120] In a possible implementation, as shown in FIG. 2A , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y. The fifth outer edge w5 is located on a side of the second metal line M21 away from the first conductive portion DA.

[0121] In one possible embodiment, as shown in FIG7 , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y. The orthographic projection of the second metal line M21 on the substrate covers the orthographic projection of the fifth outer edge w5 on the substrate. In the disclosed embodiment, by retracting the upper end of the second conductive portion DB relative to the second metal line M21, the facing capacitance generated by the vertical overlap of the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 (such as the area indicated by the thick solid box S in FIG4D ) can be reduced or eliminated, thereby reducing the first coupling capacitor Cdp1, reducing the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2, and reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0122] In the disclosed embodiment, after the upper end of the second conductive portion DB is retracted into the second metal line M21, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.259Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.136Ff; and the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 9.77%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0123] In a possible embodiment, as shown in FIG. 7 , the second metal wire M21 has a sixth outer edge w6 extending along the second direction Y; the orthographic projection of a portion of the sixth outer edge w6 on the substrate 11 coincides with the orthographic projection of the fifth outer edge w5 on the substrate 11 .

[0124] In one possible embodiment, as shown in FIG8 , the second portion CB includes: a first sub-portion CB1 and a second sub-portion CB2; the first sub-portion CB1 extends along the second direction Y, and the orthographic projection of the first sub-portion CB1 on the substrate 11 overlaps with the orthographic projection of the first metal line M11 on the substrate 11; the second sub-portion CB2 connects the first sub-portion CB1 and the first portion CA; the plurality of first active patterns C11 include: a first active pattern row C100 and a second active pattern row C200; the first active pattern row C100 and the second active pattern row C200 extend along the second direction Y and are arranged to overlap along the first direction X;

[0125] Both the first active pattern row C100 and the second active pattern row C200 include multiple first active patterns C11. In the first active pattern row C100, the second sub-portion CB2 extends along the third direction Z1. In the second active pattern row C200, the second sub-portion CB2 extends along the fourth direction Z2, with the third direction Z1 intersecting the fourth direction Z2. Specifically, for the two adjacent first sub-metal lines MA and the second sub-metal line MB on either side of the conductive portion D11, the second sub-portion CB2 of the first active pattern row C100 can be located in the first direction X and offset to one side of the first sub-metal line MA, while the second sub-portion CB2 of the second active pattern row C200 can be located in the first direction X and offset to one side of the second sub-metal line MB.

[0126] In the embodiment implemented in FIG8 , by making the first active pattern C11 of adjacent rows a mirror image structure, darker pixel rows and brighter pixel rows can be alternately distributed. If the pixels in the odd-numbered rows are brighter, the pixels in the even-numbered rows are darker. The brightness difference between the upper and lower rows of pixels is neutralized, reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk. Specifically, in the odd-numbered pixel rows, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixels is 1.192Ff, and in the odd-numbered pixel rows, the first metal line M11 is 0.010Ff. The second coupling capacitance Cdp2 between M11 and the adjacent pixel is 1.301Ff; in the even pixel rows, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.312Ff, and in the even pixel rows, the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.177Ff; in the odd rows, the pixel second coupling capacitance Cdp2 is greater than the first coupling capacitance Cdp1, and in the even pixel rows, the first coupling capacitance Cdp1 is greater than the second coupling capacitance Cdp2, and the brightness difference between the upper and lower rows of pixels is neutralized.

[0127] In a possible implementation manner, the third direction Z1 and the fourth direction Z2 are located on different sides of the first direction X.

[0128] In one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 10° to 80°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 20° to 70°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 30° to 60°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 40° to 50°.

[0129] In one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 10° to 80°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 20° to 70°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 30° to 60°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 40° to 50°.

[0130] In a possible implementation, as shown in FIG8 , in the first active pattern row C100 , the first sub-portion CB1 and the first portion CA are located on different sides of the second sub-portion CB2 ; in the second active pattern row C200 , the first sub-portion CB1 and the first portion CA are located on the same side of the second sub-portion CB2 .

[0131] In a possible embodiment, as shown in Figures 2A and 3, the first conductive layer D1 is located on the side of the first active layer C1 facing away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 passing through the first insulating layer F1, and the conductive portion D11 is electrically connected to the first portion CA through the first via K1.

[0132] In one possible embodiment, as shown in Figures 2A and 3, the first electrode D21 is located on a side of the first conductive layer D1 facing away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 passing through the second insulating layer F2; the first electrode D21 is electrically connected to the K2 conductive portion D11 through the second via hole.

[0133] In one possible implementation, the first insulating layer F1 includes one or a combination of the following:

[0134] a first gate insulating layer 15;

[0135] a first interlayer dielectric layer 16;

[0136] A second interlayer dielectric layer 17 .

[0137] 3 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0138] In a possible implementation, as shown in FIG. 3 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0139] In a possible embodiment, in combination with FIG2A and FIG3 , the array substrate further includes: a third via K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal wire M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3 .

[0140] In one possible embodiment, as shown in FIG2A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. Specifically, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In one possible embodiment, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11. In this way, the first electrode D21 and the conductive portion D11 are electrically connected in the overlapping region through the second via K2.

[0141] The orthographic projection of the first metal wire M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In one possible embodiment, the orthographic projection of the first via K1 on the substrate 11 is located at an overlapping region between the orthographic projections of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11. In this way, the first portion CA and the conductive portion D11 are electrically connected at the overlapping region through the first via K1.

[0142] In one possible embodiment, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping region of the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11. In this way, the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0143] In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X.

[0144] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17. In combination with rightward shifting of the conductive portion D11 and / or upward shifting of the second metal trace M21, precise capacitance difference control can be achieved to reduce the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 difference.

[0145] In a possible embodiment, as shown in FIG3 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0146] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0147] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0148] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0149] In a possible implementation, the third metal line M31 may be used to shield at least a portion of the first active pattern C11 of the first transistor to prevent external ambient light from illuminating the first active pattern C11 and affecting the characteristics of the first transistor.

[0150] In one possible implementation, as shown in FIG2A , the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal line M31 of the array substrate covers the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0151] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0152] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0154] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; The first active layer is located on one side of the substrate and includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction; The first metal layer includes: a plurality of first metal lines; the second portion overlaps with a portion of the first metal line in an orthographic projection of the substrate; The second metal layer includes: a plurality of second metal lines extending along a second direction; The first conductive layer comprises: a plurality of conductive portions located in the display area; at least one of the plurality of conductive portions having an orthographic projection of the substrate located between orthographic projections of adjacent first metal lines on the substrate; the conductive portions comprising: a first conductive portion and a second conductive portion distributed along the first direction; the orthographic projection of the first conductive portion on the substrate having an overlapping region with the orthographic projection of the first portion on the substrate, and the second conductive portion having an overlapping region with the orthographic projection of the second portion on the substrate; and the first conductive portion and the second conductive portion extending in different directions; The second conductive layer includes: a plurality of first electrodes located in the display area; Among them, the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein, the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; at least the second conductive part is projected on the substrate, and the distance between the first sub-metal wire and the second sub-metal wire is greater than the distance between the second sub-metal wire and the second sub-metal wire.

2. The array substrate according to claim 1, wherein: The second conductive portion has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

3. The array substrate according to claim 2, wherein: The first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions; The first conductive portion extends along an extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

4. The array substrate according to claim 1, wherein: The second conductive portion has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; an extension line of the first outer edge intersects an extension line of the second outer edge; The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

5. The array substrate according to claim 4, wherein: The first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions; The first outer edge extends along the first direction; the extending direction of the second outer edge is the same as the extending direction of the first sub-metal portion.

6. The array substrate according to claim 1, wherein: The second conductive portion has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal trace; The distance between the orthographic projection of the second sub-edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

7. The array substrate according to claim 6, wherein: The first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions; The second sub-edge extends along an extending direction of the first sub-metal portion.

8. The array substrate according to claim 7, wherein: The first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion.

9. The array substrate according to claim 6, wherein: A first bending portion is provided between the first sub-metal portion and the second sub-metal portion; and a second bending portion is provided at the first outer edge. The orthographic projection of the second bent portion on the substrate is located in an area between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is a connecting line of the first bent portions of two adjacent first metal wires.

10. The array substrate according to claim 9, wherein: The array substrate further comprises: a third metal layer located on a side of the first active layer facing the substrate; the third metal layer comprises: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate; The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire facing the first conductive portion.

11. The array substrate according to claim 6, wherein: The first outer edge has a second bent portion; The orthographic projection of the second bent portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate. The first metal edge is the outer edge of the second metal wire facing the first conductive portion.

12. The array substrate according to any one of claims 3, 5, 8 to 11, wherein: The first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and the extension direction of the first conductive portion is the same as the extension direction of the first sub-metal portion.

13. The array substrate according to any one of claims 3, 5, 8 to 12, wherein: The first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; the extending direction of the first electrode portion is the same as the extending direction of the first sub-metal portion, and the extending direction of the second electrode portion is the same as the extending direction of the second sub-metal portion.

14. The array substrate according to claim 13, wherein: The orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second conductive portion on the substrate have an overlapping area, and are electrically connected at the overlapping position.

15. The array substrate according to any one of claims 1 to 14, wherein: The first conductive portion has a third outer edge facing the first sub-metal line and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge.

16. The array substrate according to claim 15, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

17. The array substrate according to claim 16, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

18. The array substrate according to any one of claims 1 to 17, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located on a side of the second metal line away from the first conductive portion.

19. The array substrate according to any one of claims 1 to 17, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

20. The array substrate according to claim 19, wherein: The second metal line has a sixth outer edge extending along the second direction; The orthographic projection of a portion of the sixth outer edge on the substrate coincides with the orthographic projection of the fifth outer edge on the substrate.

21. The array substrate according to any one of claims 1 to 20, wherein: The second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and the orthographic projection of the first sub-portion on the substrate overlaps with the orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion; The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along the second direction and are arranged overlappingly along the first direction; The first active pattern row and the second active pattern row both include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects the fourth direction.

22. The array substrate according to claim 21, wherein: In the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

23. A display panel, wherein: Comprising the array substrate according to any one of claims 1-22.

24. A display device, wherein: Comprising the display panel as claimed in claim 23.

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