Memory detection method and apparatus

Abstract

Disclosed are a memory detection method and apparatus, relating to the technical field of storage. Upon obtaining a physical address containing a target area in a memory possibly having a fault, a computing device performs a read operation and / or a write operation on the target area, and performs secondary confirmation of the working status of the target area in the memory in the read operation and / or write operation execution process. Upon obtaining the physical address comprised in fault information, the computing device performs the read operation and / or the write operation on the target area corresponding to the physical address in the memory, and obtains memory patrol scrubbing information in the read operation and / or write operation execution process, so as to re-determine a fault in the target area. Multi-dimensional factors (the read operation and / or the write operation) are taken into account in the re-determination process, and therefore, the patrol scrubbing information obtained in the re-determination process conforms to the actual situation of the target area, so that using the patrol scrubbing information can improve the accuracy of detecting the working status of the target area.

Description

Memory detection method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 20, 2024, with application number 202410317567.5 and application name “Memory detection, repair method and system”, and claims priority to the Chinese patent application filed with the State Intellectual Property Office on May 13, 2024, with application number 202410595440.X and application name “A memory detection method and device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a memory detection method and device. Background Art

[0003] During the operation of a computing device, a memory failure in the device triggers fault analysis and processing of the faulty memory. If a memory failure occurs during operation, it is detected by the device's memory controller and the corresponding correctable error (CE) or uncorrectable error (UCE) is detected. Fault analysis based on the CE or UCE determines the memory failure mode, which is then used to isolate the memory accordingly.

[0004] However, occasional memory failures are also detected by the memory controller and generate corresponding CE or UCE. Fault analysis using the aforementioned CE or UCE will result in an incorrect operating state (e.g., failure mode). Isolating the memory based on this incorrect failure mode will result in a waste of memory storage resources. Summary of the Invention

[0005] The present application provides a memory detection method and device to solve the problem of inaccurate determination of the working status of the memory in cases where occasional memory failures occur.

[0006] This application adopts the following technical solution.

[0007] In a first aspect, the present application provides a memory detection method. The memory detection method can be applied to a computer system or to a computing device that supports the computer system to implement the memory detection method. For example, the computing device may be a server or a terminal, and the computing device includes a memory. In one possible example, the memory detection method includes: the computing device obtains fault information including the physical address of the memory, and then performs a read operation and / or a write operation on the target area based on the fault information. And, the computing device obtains the inspection information of the memory during the execution of the read operation and / or the write operation, and then detects the working status of the target area based on the inspection information. The target area is the storage space corresponding to the physical address in the memory.

[0008] In the first aspect of the present application, after obtaining the physical address included in the fault information, the computing device performs a read operation and / or a write operation on the target area corresponding to the physical address to achieve a re-determination of the fault in the target area. The accuracy of the inspection information obtained by the re-determination is relatively high, and the inspection information can be used to improve the accuracy of the working status of the detected area. In addition, because the re-determination process combines multi-dimensional factors (read operations and / or write operations), the inspection information obtained in the above-mentioned re-determination process fits the actual situation of the target area, and the computing device can further improve the accuracy of the working status of the detected target area by using the inspection information.

[0009] In one possible scenario, the computing device may further include a processor, a memory controller, and a management controller. The memory detection method shown in the first aspect above and any possible implementation of the first aspect below may be executed by any one of the processor, the memory controller, and the management controller.

[0010] In a possible example, a basic input output system (BIOS) runs in the processor.

[0011] In a possible example, the management controller may be a baseboard management controller (BMC) or an embedded controller (EC).

[0012] In one possible scenario, the working status is used to indicate whether the target area is normal or abnormal. When the working status indicates that the target area is abnormal, the working status also indicates a failure mode of the memory.

[0013] For example, the failure mode may include: a cell failure mode, a cacheline address (CA) failure mode, a row failure mode, a bank failure mode, a device / chip failure mode, and a rank failure mode.

[0014] In a possible implementation, three possible scenarios are provided below for fault information.

[0015] In the first possible scenario, the fault information includes the CE of the cell in the memory and the physical address of the cell.

[0016] In the second possible scenario, the fault information includes the UCE of the cell in the memory and the physical address of the cell.

[0017] In the third possible scenario, the fault information includes the CE and UCE of the cell in the memory and the physical address of the cell.

[0018] In a possible implementation, with respect to inspection information, three possible scenarios are provided below.

[0019] In a first possible scenario, the inspection information includes the inspection CE of the cell in the memory and the physical address of the cell.

[0020] In the second possible scenario, the inspection information includes the inspection UCE of the cell in the memory and the physical address of the cell.

[0021] In a third possible scenario, the inspection information includes the inspection CE, inspection UCE, and physical address of the cell in the memory.

[0022] In a possible implementation, the target area includes cells in the same row in the memory.

[0023] In the present application, the computing device performs read and / or write operations on a local area in the memory (cells in the same row), avoiding read and / or write operations on the entire memory, reducing the search scope while improving the efficiency of the search.

[0024] In a possible example, the target area includes cells in the same bank and the same row in the memory.

[0025] For example, the target area is a row of cells in the same bank indicated by the row address in the physical address.

[0026] In another possible example, the target area includes cells in the same row and the same rank in the memory. A rank in the memory includes multiple chips, and each chip in the multiple chips includes multiple layers of banks.

[0027] The cells in the same row in the same rank may be cells in the same row in the n-th layer bank among multiple banks under the same rank.

[0028] For example, a memory rank consists of two chips (chip 1 and chip 2), each of which contains five layers of banks. The first row of the first layer bank in chip 1 and the first row of the first layer bank in chip 2 are called cells in the same row of the same rank.

[0029] Alternatively, the third row in the second-level bank in chip 1 and the third row in the second-level bank in chip 2 are called cells in the same row in the same rank.

[0030] In one possible implementation, the computing device performs a read operation and / or a write operation on the target area according to the fault information, including: the computing device performs a read operation and / or a write operation on the target area according to the physical address in the fault information within a time limit.

[0031] In the present application, by limiting the time for the computing device to perform read operations and / or write operations, the impact of long read operations and / or write operations on the normal operation of the business on the computing device, such as causing high processing delays for the business, is avoided, thereby reducing the impact on the normal operation of the business.

[0032] In one possible scenario, a computing device receives a user-configured time limit.

[0033] In one possible implementation, the working status indicates a failure mode of the target area. After the computing device detects the working status of the target area based on the inspection information, the above-mentioned memory detection method also includes: the computing device determines an isolation strategy that has a mapping relationship with the failure mode based on the failure mode of the target area, and uses the isolation strategy to isolate the target area.

[0034] In this application, the computing device isolates the target area of ​​the fault to prevent it from affecting other areas of the memory, thereby improving the stability and reliability of the memory. Furthermore, by isolating the target area of ​​the fault, the computing device avoids writing data to the target area of ​​the fault, which could cause data corruption, thereby ensuring data integrity.

[0035] In one possible implementation, the computing device detects the operating status of the target area based on the inspection information, including: the computing device processes the inspection information using an analysis strategy to obtain the operating status of the target area. The analysis strategy indicates a rule for using the inspection information to determine the operating status of the area.

[0036] In one possible example, a computing device receives a user-configured analysis policy.

[0037] In a second aspect, the present application provides a memory detection device. The memory detection device is applied to a computer system or a computing device that supports the computer system to implement a memory detection method. The memory detection device includes various modules for executing the memory detection method in the first aspect or any optional implementation of the first aspect. For example, the memory detection device includes a first acquisition module, an execution module, a second acquisition module, and a detection module. Among them:

[0038] The first acquisition module is used to acquire fault information, where the fault information includes a physical address of the memory.

[0039] The execution module is used to perform a read operation and / or a write operation on a target area according to the fault information; the target area is a storage space in the memory corresponding to the physical address.

[0040] The second acquisition module is used to acquire inspection information of the memory during the execution of the read operation and / or write operation.

[0041] The detection module is used to detect the working status of the target area based on the inspection information.

[0042] In a possible implementation, the target area includes cells in the same row in the memory.

[0043] In a possible implementation, the fault information includes one or more of the following: a physical address of a cell in a memory, a correctable error of the cell, and an uncorrectable error of the cell.

[0044] In a possible implementation, the inspection information includes one or more of the following: a physical address of a cell in a memory, a correctable error of the cell during inspection, and an uncorrectable error of the cell during inspection.

[0045] In a possible implementation, the execution module is specifically configured to perform a read operation and / or a write operation on the target area according to the physical address in the fault information within a time limit.

[0046] In a possible implementation, the device further includes an isolation module configured to determine, based on a failure mode of the target area, an isolation strategy having a mapping relationship with the failure mode, and isolate the target area using the isolation strategy.

[0047] In a possible implementation, the working status indicates a failure mode of the target area, where the failure modes include: cell failure mode, CA failure mode, row failure mode, bank failure mode, device failure mode, and rank failure mode.

[0048] For more detailed implementation details of the memory detection device, please refer to the description of any implementation method in the first aspect above, as well as the content of the following specific implementation methods, which will not be repeated here.

[0049] In a third aspect, the present application provides a chip comprising: a processor and a power supply circuit. The power supply circuit is used to supply power to the processor, and the processor is used to execute the method in the first aspect or any possible implementation of the first aspect.

[0050] In a fourth aspect, the present application provides a computing device. The computing device includes a memory and a chip, wherein the memory is used to store computer instructions; when the chip executes the computer instructions, it implements the method of the first aspect or any possible implementation of the first aspect.

[0051] In a fifth aspect, the present application provides a computer-readable storage medium storing a computer program or instruction. When the computer program or instruction is executed by a processing device, the method in the above-mentioned first aspect or any possible implementation of the first aspect is implemented.

[0052] In a sixth aspect, the present application provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processing device, it implements the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0053] The beneficial effects of the second to sixth aspects above can be referred to the first aspect or any possible implementation of the first aspect, and will not be described in detail here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a schematic diagram of the structure of a memory provided by the present application;

[0055] FIG2 is a schematic diagram of a computer system provided by the present application;

[0056] FIG3 is a flow chart of a memory detection method provided by the present application;

[0057] FIG4 is a flow chart of a memory isolation method provided by the present application;

[0058] FIG5 is a second flow chart of a memory detection method provided by the present application;

[0059] FIG6 is a structural diagram of a memory detection device provided by the present application;

[0060] FIG7 is a second structural diagram of a memory detection device provided in this application. DETAILED DESCRIPTION

[0061] To address the issue of inaccurate determination of the working status of memory, this embodiment provides a memory detection method. After a computing device obtains the physical address of a target memory region containing a potentially faulty memory region, it performs a read and / or write operation on the target region. During the read and / or write operation, the working status of the target memory region is reconfirmed, thereby improving the accuracy of memory detection.

[0062] Specifically, after obtaining the physical address included in the fault information, the computing device performs a read and / or write operation on the target area in memory corresponding to the physical address, and obtains inspection information of the memory during the read and / or write operation to re-determine the fault in the target area. Because this re-determination process incorporates multiple factors (read and / or write operations), the inspection information obtained in this re-determination process is consistent with the actual situation of the target area. Utilizing this inspection information can improve the accuracy of detecting the working status of the target area.

[0063] In a possible example, the computing device may further include a processor, a memory controller, and a management controller. The memory detection method described in this application may be executed by any one of the processor, the memory controller, and the management controller.

[0064] To facilitate understanding, the technical terms involved in this application are first introduced.

[0065] A BMC is a small operating system independent of the processor. It is a chip integrated into the motherboard or plugged into the motherboard via a bus. Externally, it presents itself as a standard RJ45 (registered jack 45) network port and has a uniquely addressed firmware system. Computing devices typically use a BMC to monitor hardware performance, record anomalies, and generate alarms. The BMC runs BMC firmware.

[0066] BIOS is a set of programs that are fixed to a read-only memory (ROM) on the computer's motherboard. It stores the computer's most important basic input and output programs, self-test programs after power-on, and detection programs. It can read and write specific information about system settings from the processor.

[0067] The following is an example of a memory structure, as shown in Figure 1, which is a schematic diagram of the structure of a memory provided by this application. The smallest storage structure in the memory shown in Figure 1 is called a cell. A large number of cells can form a bank. The size of the memory array is mxn, where m represents the number of rows in the memory array and n represents the number of columns in the memory array. A row represents cells connected to the same row address line (wordline), and the row size represents the number of cells included in a row.

[0068] A bank includes multiple wordlines and multiple column address lines (bitlines). A cell in a bank is connected to a wordline and a bitline. Multiple banks can form a chip in the memory, and multiple chips can form a rank in the memory.

[0069] A memory failure refers to a problem or failure in the random access memory (RAM) of a computer device, which prevents it from reading or writing data normally, thereby affecting the stability and performance of the computer device. Memory failures can generally be divided into two types: soft failures and hard failures:

[0070] Soft failures: Soft failures are temporary memory problems, typically caused by temporary electromagnetic interference, transmission errors, or temporary memory chip failures. Soft failures can cause temporary crashes or errors on a computing device, but may recover after waiting or restarting the computing device.

[0071] Hard failures: Hard failures are persistent issues with the memory hardware itself, such as chip damage, connection problems, and circuit shorts. Hard failures typically require isolating the faulty area or replacing the memory directly. Hard failures can be classified into the following failure modes: cell failure mode, row failure mode, CA failure mode, column failure mode, bank failure mode, device failure mode, and rank failure mode.

[0072] The cell failure mode indicates that in the same bank of memory, cells with the same wordline and bitline fail, and the cumulative number of cell failures is greater than or equal to a threshold of 1.

[0073] CA failure mode indicates that the number of CA errors in the same row in the same bank is greater than or equal to the threshold 2.

[0074] Row failure mode indicates that the number of error cells or CAs in the same row of the same bank is greater than or equal to the threshold of 3.

[0075] Column failure mode indicates that the number of error cells in the same column of the same bank is greater than or equal to the threshold of 4.

[0076] Bank failure mode indicates that the number of rows in the same bank experiencing row failure mode is greater than or equal to a threshold of 5; or the number of columns in the same bank experiencing column failure mode is greater than or equal to a threshold of 6.

[0077] Device failure mode, indicating that the number of banks in the same chip that experience bank failure mode is greater than or equal to the threshold of 7.

[0078] Rank failure mode, indicating that the number of chips with device failure mode in the same rank is greater than or equal to the threshold of 8.

[0079] It is worth noting that the above threshold values ​​1 to 8 may be integers greater than or equal to 1. The threshold values ​​1 to 8 are set according to user needs and are not limited in this application.

[0080] Next, the memory detection method provided in this application is introduced in detail with reference to the accompanying drawings.

[0081] First, referring to Figure 2 , which is a schematic diagram of a computer system provided by this application, as shown in Figure 2 , the computer system includes a processor 110 , a memory 120 , and a management controller 130 , which can be connected via a bus 140 .

[0082] As a possible implementation, the computer system described above may also be referred to as a memory detection system. The computer system may be a computing device, such as a server, terminal, memory array, edge device, embedded device, or other electronic device used to perform computing or storage tasks. The server may be a centralized server, a distributed server, a storage server, or a high-performance computing server.

[0083] The processor 110 is used to run application programs (or applications). For example, an application 111 is run on the processor 110. This application does not limit the application 111 and may include video software, storage management software, chat software, or game software. While running the application 111, the processor 110 reads or writes to the memory 120. The processor 110 may also run a BIOS to collect fault information, inspection information, and the like from the memory 120.

[0084] The processor 110 may include one or more processing units, for example: the above-mentioned processing units may be a processor (central processing unit, CPU), an application processor (application processor, AP), a modem processor, a graphics processing unit (GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA), discrete gates, transistor logic devices, discrete hardware components, a baseband processor, a neural-network processing unit (NPU), and / or an artificial intelligence (AI) chip, etc., or any one or a combination thereof.

[0085] Memory 120 stores data required by application 111 during operation, such as program code, variables, and data structures. Memory 120 can be a dynamic random access memory (DRAM) type memory, such as double data rate synchronous dynamic random access memory (DDR SDRAM) or high bandwidth memory (HBM).

[0086] The management controller 130 can be a BMC or EC. The BMC or EC monitors the hardware operation of the computer system and handles hardware anomalies. For example, the BMC monitors the operation or working status of the memory 120 in the computer system and isolates the memory 120 if the working status indicates a fault.

[0087] Bus 140 is used to transmit information between processor 110, memory 120, and management controller 130. In addition to a data bus, bus 140 may also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus 140 in the figure.

[0088] The bus 140 may be a Peripheral Component Interconnect Express (PCIe) high-speed bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (UBus or UB), a Compute Express Link (CXL), a Cache Coherent Interconnect for Accelerators (CCIX) or other bus, a Quick Path Interconnect (QPI) bus, an Intelligent Platform Management Interface (IPMI), a Serial Peripheral Interface (SPI), or other standards or protocols for implementing data interaction. For example, the processor 110 may access data in the memory 120 via the PCIe bus. The processor 110 may be connected to the management controller 130 via the DDR. Here, different management controllers 130 may use different data buses to communicate with the processor 110. Therefore, the DDR bus may also be replaced with other types of data buses. The embodiment of the present application does not limit the bus type.

[0089] It should be noted that Figure 2 is only an example provided in an embodiment of the present application. The computer system may also include other processors (such as coprocessors) or management controllers, or power supplies, hard disks, optical drives, chassis, cooling systems, and other input and output controllers and interfaces that support the operation of the processors, which are not shown in Figure 2. The embodiments of the present application do not limit the form and quantity of the other processors, management controllers, or the above-mentioned hardware that supports the operation of the processors.

[0090] In a possible embodiment, the computer system shown in FIG. 2 may further include a memory controller.

[0091] The memory controller is responsible for managing and controlling the memory, coordinating the reading and writing of data in the memory, and processing memory access requests from the processor 110 and other devices. The main functions of the memory controller include: memory management, speed matching, error detection and correction, etc. Among them, memory management refers to the allocation, release and management of storage resources in the memory to ensure that data is stored correctly in the memory. Speed ​​matching refers to coordinating the memory access speed with the data transmission speed to ensure the speed matching of the processor 110 and other components in the computer system and optimize system performance. Error detection and correction refers to the ability to identify a CE or UCE generated by the memory 120 during operation, and to correct the CE or UCE generated in the memory, such as isolating the faulty area in the memory where the CE is generated.

[0092] In one possible scenario, the memory controller is located inside the processor 110 .

[0093] In a possible scenario, the memory controller is located outside the processor 110 , such as in a north bridge chip in a computer system, and the memory controller is connected to the processor 110 via a bus 140 .

[0094] To address the problem of inaccurate determination of the working status of memory in situations such as occasional memory failures, this embodiment provides a possible memory detection method based on the system shown in Figure 2 to address the aforementioned problem. Figure 3 is a flow chart of a memory detection method provided by this application. The memory detection method can be executed by a computing device 310, which can be the computer system shown in Figure 2. As shown in Figure 3, the memory detection method can include the following steps S310 to S340.

[0095] S310 , the computing device 310 obtains fault information.

[0096] The fault information includes the physical address of the memory.

[0097] In a possible implementation, the computing device 310 obtains the fault information, including: the computing device 310 obtains the fault information of the memory 120 by polling or interruption.

[0098] Exemplarily, the processor 110 in the computing device 310 obtains the fault information of the memory 120 through polling or interruption.

[0099] For example, the processor 110 obtains fault information of the memory 120 through the bus 140 .

[0100] Exemplarily, the computing device 310 utilizes the management controller 130 to receive the fault information reported by the processor 110 through the IPMI. The fault information is obtained by the processor 110 from the memory 120 in a polling manner.

[0101] Exemplarily, the computing device 310 utilizes the management controller 130 to receive fault information reported by the processor 110 through IPMI. The fault information is that the processor 110 receives an interrupt request during normal operation, and then suspends the normal operating task according to the interrupt request to obtain it from the memory 120 or the memory controller.

[0102] The interrupt request may be issued by the memory 120 .

[0103] It is worth noting that the above-mentioned IPMI is only an example of a bus for managing communication between the controller 130 and the processor 110 and should not be understood as limiting the present application. In other embodiments of the present application, PCIe, SPI, etc. may also be used.

[0104] For fault information, three possible examples are provided below.

[0105] In a first possible example, the fault information includes the CE of the cell in the memory and the physical address of the cell.

[0106] In a second possible example, the fault information includes the UCE of the cell in the memory and the physical address of the cell.

[0107] In a third possible example, the fault information includes the CE and UCE of the cell in the memory and the physical address of the cell.

[0108] In a possible scenario, the physical address is the physical address of a storage unit in the memory where a failure (soft failure or hard failure) occurs.

[0109] For example, a 32-bit physical address is used to represent the rank address, 2 bits represent the chip address, 3 bits represent the bank address, 12 bits represent the row address, and 12 bits represent the column address. For example, a 32-bit physical address can be divided into [rank address | chip address | bank address | row address | column address].

[0110] Exemplarily, a 32-bit physical address is 0x12345678 (in hexadecimal notation), where 0x1 represents a rank address, 0x2 represents a chip address, 0x3 represents a bank address, 0x345 represents a row address, and 0x678 represents a column address.

[0111] It should be noted that the number of bits of the above physical address is only an example and should not be understood as limiting the present application. In other embodiments of the present application, the physical address may also be 20 bits or 64 bits.

[0112] In one possible embodiment, when the computer system shown in FIG2 includes a memory controller, computing device 310 utilizes management controller 130 to receive fault information reported by processor 110 via IPMI. This includes: computing device 310 utilizes management controller 130 to obtain fault information collected by processor 110, where processor 110 obtains the fault information from the memory controller via polling or interrupts. The memory controller records the fault information of memory 120.

[0113] Exemplarily, the processor 100 polls the memory controller to periodically obtain fault information from the memory controller.

[0114] Exemplarily, after receiving the interrupt request initiated by the memory controller, the processor 100 suspends the normal running business and obtains fault information from the memory controller.

[0115] The memory controller sends an interrupt request to the processor 100 only after collecting one or more pieces of fault information from the memory 120 .

[0116] In a possible scenario, the processor 110 obtains the fault information of the memory 120 by polling or interrupting, including: the processor 110 obtains the fault information of the memory 120 from the memory controller by polling or interrupting.

[0117] In a possible implementation, the computing device 310 obtains the fault information of the memory 120 , including: a memory controller obtains the fault information of the memory 120 .

[0118] S320 : The computing device 310 performs a read operation and / or a write operation on the target area according to the fault information.

[0119] The target area is the storage space in the memory 110 corresponding to the physical address.

[0120] The above-mentioned read operation and / or write operation may also be referred to as an access operation.

[0121] The data used in the above access operation may be data preset by the user, data stored in the storage space indicated by the physical address, or data stored in the storage space indicated by the address adjacent to the physical address, which is not limited in this application.

[0122] The read operation can be a random read or a sequential read. A random read is an operation that randomly reads data from any location in the target area. A sequential read is an operation that reads data from the target area in a predetermined order. For example, the predetermined order can be from low address bits to high address bits, or from high address bits to low address bits.

[0123] The write operation can be either random or sequential. Random write refers to the operation of writing data randomly at any location in the target area. Sequential write refers to the operation of writing data sequentially in the target area according to a predetermined order. For example, the predetermined order can be from low address bits to high address bits, or from high address bits to low address bits.

[0124] For access operations, three possible examples are provided below.

[0125] In a first possible example, the computing device 310 only performs a read operation on the target area.

[0126] In a second possible example, the computing device 310 performs a write operation only on the target area.

[0127] In a third possible example, the computing device 310 performs a read operation and a write operation on the target area. This application does not limit whether the computing device 310 performs the read operation first and then the write operation, or performs the write operation first and then the read operation.

[0128] In a possible scenario, the target area is cells in the same row in the memory.

[0129] Exemplarily, the cells in the same row may be cells connected to the same row address line, that is, cells in the same row in the same bank. For example, the target area is a row of cells indicated by a row address in the physical address, and the row address in the physical address of the cells in the row is the same.

[0130] Exemplarily, the target area includes cells in the same row in the same rank in the memory, that is, the cells in the same row in the same rank may be cells in the same row in the n-th layer bank in multiple banks under the same rank.

[0131] For example, a memory rank consists of two chips (chip 1 and chip 2), each of which contains five layers of banks. The first row of the first layer bank in chip 1 and the first row of the first layer bank in chip 2 are called cells in the same row of the same rank.

[0132] Alternatively, the third row in the second-level bank in chip 1 and the third row in the second-level bank in chip 2 are called cells in the same row in the same rank.

[0133] In one possible example, a cell can only store one bit of data, that is, 0 or 1. The read operation refers to reading the 0 or 1 stored in all cells in the same row indicated by the physical address, and the write operation refers to setting all cells in the same row indicated by the physical address to 0 or 1 respectively.

[0134] In one possible implementation, the computing device 310 performs a read operation and / or a write operation on the target area based on the fault information, including: the computing device 310 performs a read operation and / or a write operation on the target area based on the physical address in the fault information within a specified time limit.

[0135] The time limit indicates the maximum time taken by the computing device 310 to access the target area, and for example, the time limit is 5-99 milliseconds (ms), which is not limited in this application. The time limit may also be less than 5ms or greater than 99ms.

[0136] For example, when the time limit is 10 ms, the time taken by the computing device 310 to access the target area does not exceed 10 ms.

[0137] In one possible implementation, the computing device 310 performs a read operation and / or a write operation on the target area according to the fault information, including: the computing device 310 performs a read operation and / or a write operation on the target area according to the physical address in the fault information within a set number of accesses.

[0138] For example, if the number of accesses is set to 10, the computing device 310 will perform 10 read operations and / or write operations on each cell in the target area.

[0139] In one possible implementation, the computing device 310 performs a read operation and / or a write operation on the target area based on the fault information, including: the computing device 310 performs a read operation and / or a write operation on the target area based on the physical address in the fault information within a set number of accesses (such as N, where N is an integer greater than or equal to 1) and a specified time limit.

[0140] For the content of this implementation method, please refer to the description of the above two possible implementation methods, which will not be repeated here.

[0141] In one possible scenario, when the computing device 310 reaches a time limit for performing an access operation, it will stop accessing the target area, or when the processor 110 reaches a threshold number (such as N mentioned above), it will stop accessing the target area.

[0142] S330: The computing device 310 obtains patrol information of the memory during the execution of a read operation and / or a write operation.

[0143] Regarding the computing device 310 obtaining content of patrol information of a process memory during a read operation and / or a write operation, two possible scenarios are provided below.

[0144] In one possible scenario, the computing device 310 uses the processor 110 to collect inspection information of the memory 120 while performing a read operation and / or a write operation on a target area.

[0145] In another possible scenario, the computing device 310 uses the management controller 130 to collect memory inspection information when performing a read operation and / or a write operation on a target area.

[0146] In another possible scenario, when the computing device 310 shown in FIG2 includes a memory controller, the memory controller in the computing device 310 performs a read operation and / or a write operation on the target area and, during the execution process, collects inspection information of the memory 120. After collecting the inspection information, the memory controller sends an interrupt request to the processor 110, and the processor 110 reads the inspection information recorded by the memory controller in response to the interrupt request.

[0147] For inspection information, three possible examples are provided below.

[0148] In a first possible example, the inspection information includes the CE of the cell and the physical address of the cell.

[0149] In a second possible example, the inspection information includes the UCE of the cell and the physical address of the cell.

[0150] In a third possible example, the inspection information includes the CE and UCE of the cell and the physical address of the cell.

[0151] In a possible scenario, the physical address is the physical address of a cell where a memory failure occurs during the inspection process of the computing device 310 .

[0152] In a possible scenario, since the CE or UCE is generated during a patrol scrubbing process, the CE or UCE may also be referred to as a patrol scrubbing (PS) CE or PS UCE.

[0153] S340 : The computing device 310 detects the working status of the target area according to the inspection information.

[0154] In a possible scenario, the above working status is used to indicate that a row of cells indicated by a row address in the physical address is operating normally.

[0155] In another possible scenario, the above working status is used to indicate that one or more cell failures exist in a row of cells indicated by the row address in the physical address, as well as corresponding failure modes.

[0156] In a possible implementation, the computing device 310 detects the working status of the target area according to the inspection information, including: the computing device 310 detects the working status of the target area according to the inspection information and the analysis strategy.

[0157] The analysis strategy indicates the rules for using inspection information to determine the working status of the target area.

[0158] For analysis strategies, please refer to the content shown in Table 1 below.

[0159] Table 1

[0160] The threshold values ​​a to e can be set according to user needs, and the threshold values ​​a to b can be integers greater than or equal to 1, which are not limited in this application. For example, the threshold value a can be 2, the threshold value e can be 3, and so on.

[0161] It is worth noting that the contents shown in Table 1 above are only examples and should not be understood as limitations on the present application. The contents of Table 1 above can be set by the user as needed. For example, the computing device 310 can receive the analysis strategy configured by the user through the redfish interface. The redfish interface is an interface provided to the outside by the management controller 130 (such as BMC) in the computing device 310. The analysis strategy received by the computing device 310 will be saved in the BMC. In other embodiments of the present application, more or fewer failure modes and corresponding judgment rules may also be included. For example, Table 1 above may also include a CA failure mode, and the corresponding judgment rule is that the number of erroneous CAs in the same row in the same bank is greater than or equal to the threshold value f. Table 1 above may also include a column failure mode, and the corresponding judgment rule is that the number of erroneous cells in the same column in the same bank is greater than or equal to the threshold value g.

[0162] In this application, the computing device 310 receives the analysis strategy configured by the user through the redfish interface, which enables the user to use different analysis strategies to determine the fault mode according to different usage scenarios (such as when applied in HPC or storage servers, etc.), thereby realizing the flexible configuration of the analysis strategy and the corresponding processing of the analysis strategy for different scenarios, thereby improving the accuracy of the obtained fault mode.

[0163] In one possible scenario, the computing device 310 detects the working status of the area based on the inspection information and analysis strategy, including: the computing device 310 determines the number of inspection CEs and inspection UCEs triggered at the same physical address based on the inspection information. The sum of the number of inspection CEs and inspection UCEs triggered at the same physical address is the number of cell errors in the same row and column. If the number of errors is greater than or equal to the threshold a, a cell failure mode exists in the memory. If the number of errors CA in the row indicated by the above physical address is greater than or equal to the threshold f, a CA failure mode exists in the memory. If the number of cells that have a cell failure mode in the row indicated by the above physical address is greater than or equal to the threshold b, a row failure mode exists in the memory. If the number of rows that have a row failure mode in the bank indicated by the above physical address is greater than or equal to the threshold c, a bank failure mode exists in the memory. If the number of banks that have a bank failure mode in the chip indicated by the above physical address is greater than or equal to the threshold d, a device failure mode exists in the memory. If the number of chips with device failure mode under the rank indicated by the above physical address is greater than or equal to the threshold e, then a rank failure mode exists in the memory.

[0164] In one possible example, if a cell has both a cell failure mode and a row failure mode for the row to which the cell belongs, only the row failure mode is displayed in the memory. If a row has both a row failure mode and a bank failure mode for the bank to which the row belongs, only the bank failure mode is displayed in the memory. If a bank has both a bank failure mode and a device failure mode for the chip to which the bank belongs, only the device failure mode is displayed in the memory. If a chip has both a device failure mode and a rank failure mode for the rank to which the chip belongs, only the rank failure mode is displayed in the memory.

[0165] In one possible embodiment, the computing device 310 detects the operating status of the target area based on the inspection information and the analysis strategy, including: the computing device 310 determines, based on the inspection information, that the sum of the number of inspection CEs and the number of inspection UCEs triggered at the same physical address is equal to the number of errors in the same cell (i.e., the cell in the same row and column as described above). If the number of errors is less than a threshold a and greater than 0, the computing device 310 determines that a soft failure exists in the memory. For example, if the number of errors is 1 and the threshold a is 2, then if the number of errors is less than the threshold a, the computing device 310 determines that a soft failure exists in the cell indicated by the physical address.

[0166] If the number of errors is greater than or equal to the threshold a, the computing device 310 determines that a hard failure occurs in the memory.

[0167] Furthermore, the computing device 310 may further determine the failure mode of the memory according to the contents shown in Table 1. For details, please refer to the description below Table 1 and will not be elaborated here.

[0168] Exemplarily, when the fault information includes only one CE and the corresponding physical address 1, the computing device 310 performs an access operation on a row of cells (target area) indicated by the row address in physical address 1, thereby obtaining inspection information of the target area during the access operation. The inspection information includes the inspection CE and physical address 2, and physical address 2 has the same row address as physical address 1. If the inspection information includes only one set of inspection CEs and the corresponding physical address 2, the computing device 310 determines that the cell indicated by physical address 2 has a soft failure. If the inspection information includes three sets of inspection CEs and the corresponding physical address 2, the computing device 310 determines that the cell indicated by physical address 2 has a hard failure, and according to Table 1 above, the specific fault mode can be determined to be a cell fault mode.

[0169] If the inspection information includes two groups of inspection CEs and corresponding physical address 2, and two groups of inspection CEs and corresponding physical address 3, and the row addresses of physical address 2 and physical address 3 are the same, then the computing device 310 can determine that the specific failure mode is a row failure mode according to Table 1 above.

[0170] If the fault information includes a CE and its corresponding physical address 1, and a UCE and its corresponding physical address 4, and physical addresses 1 and 4 have different row addresses but the same bank address, computing device 310 performs an access operation on a row of cells (target area) indicated by the row addresses of physical addresses 1 and 4, thereby obtaining inspection information about the target area during the access operation. If the inspection information only includes two sets of UCEs and their corresponding physical address 5, and physical address 5 has the same row address as physical address 1, meaning that the cells indicated by physical addresses 1 and 5 are in the same row in the same bank, computing device 310 determines, based on Table 1 above, that the cell at physical address 5 has a cell fault mode.

[0171] If the inspection information includes two groups of inspection CEs and the corresponding physical address 1, two groups of UCEs and the corresponding physical address 5, two groups of inspection CEs and the corresponding physical address 4, and two groups of CEs and the corresponding physical address 6, and the physical address 6 is the same as the row address of the physical address 4, then the computing device 310 determines according to Table 1 above that the row to which the physical address 1 belongs has a row fault mode, and the row to which the physical address 6 belongs has a row fault mode, and further determines that the bank indicated by the physical address 1 and the physical address 2 has a bank fault mode.

[0172] In a possible embodiment, the above-mentioned inspection information may include an identifier for indicating that CE and UCE are not collected, and the computing device 310 detects the working status of the area based on the inspection information, including: the computing device 310 determines that the working status of the area is normal, that is, there is no fault, based on the identifier in the inspection information.

[0173] After computing device 310 detects that the target area is faulty and determines the fault mode of the target area, computing device 310 can perform corresponding repairs based on the memory fault mode. The following provides a possible embodiment of computing device 310 performing corresponding repairs based on the memory fault mode.

[0174] As shown in Figure 4, Figure 4 is a flow chart of a memory isolation method provided by this application. In this embodiment, the working status determined by the method shown in Figure 3 indicates the failure mode of the region, and the method shown in Figure 4 may include the following steps S410 to S420.

[0175] S410 : The computing device 310 determines, based on the failure mode of the target area, an isolation strategy that has a mapping relationship with the failure mode.

[0176] For the above mapping relationship, please refer to the content shown in Table 2 below.

[0177] Table 2

[0178] The first isolation strategy can update the status of the cell indicated by the physical address in the memory mapping table of the memory controller, such as marking it as unavailable. This isolates the cell (i.e., prevents it from participating in access operations) and establishes an address mapping between the cell and the redundant cell, thereby maximizing the available memory capacity. The cell and the redundant cell are located in the same bank.

[0179] The second isolation strategy is to isolate the faulty row and establish an address mapping between the faulty row and the redundant row, so that the redundant row can replace the faulty row, thereby maximizing the available memory capacity. The faulty row and the redundant row are in the same bank.

[0180] The third isolation strategy is to isolate the faulty bank and establish an address mapping between the faulty bank and a redundant bank so as to replace the faulty bank with the redundant bank. The faulty bank and the redundant bank are located in the same chip.

[0181] Alternatively, the faulty bank is isolated, and on the operating system (OS) running on the processor 110, the mapping relationship between the address space of the existing process and the physical address of the faulty bank is adjusted to a mapping relationship between the address space of the process and the physical address of an idle bank, so as to avoid affecting the normal operation of the process on the processor 110.

[0182] The fourth isolation strategy can be to isolate the faulty chip and establish an address mapping between the faulty chip and a redundant chip so that the faulty chip can be replaced with the redundant chip. The faulty chip and the redundant chip can be in the same rank or different ranks.

[0183] Alternatively, the faulty chip is isolated, and on the OS side running on the processor 110, the mapping relationship between the address space of the existing process and the physical address of the faulty chip is adjusted to the mapping relationship between the address space of the process and the physical address of the idle chip, so as to avoid affecting the normal operation of the process on the processor 110.

[0184] The above-mentioned isolation strategy five can be to isolate the faulty rank and establish an address mapping between the aforementioned faulty rank and the redundant rank to replace the faulty rank with the redundant rank.

[0185] Alternatively, the faulty rank is isolated, and on the OS side running on processor 110, the mapping relationship between the address space of the existing process and the physical address of the faulty rank is adjusted to the mapping relationship between the address space of the process and the physical address of the idle rank, so as to avoid affecting the normal operation of the process on processor 110.

[0186] The aforementioned isolation strategy can be set according to user needs, and this application does not limit this.

[0187] It is worth noting that the content of Table 2 above is only an example and should not be understood as a limitation of the present application. In other embodiments of the present application, Table 2 above may also include "field" information, which is used to identify the isolation strategy. For example, isolation strategy one can be identified by field "000", isolation strategy two can be identified by field "001", isolation strategy three can be identified by field "010", isolation strategy four can be identified by field "011", and isolation strategy five can be identified by field "100". In addition, Table 2 above may also include a failure mode of CA failure mode, and the corresponding isolation strategy is isolation strategy six, which is to isolate the faulty CA and replace the faulty CA with a redundant CA, thereby maximizing the available storage capacity of the memory. Among them, a mapping relationship will be established between the redundant CA and the faulty CA.

[0188] S420 : The computing device 310 isolates the target area using an isolation strategy.

[0189] For example, after the computing device 310 detects that the cell corresponding to physical address 2 in the target area has a cell failure mode, the computing device 310 will use the above isolation strategy to isolate the cell corresponding to physical address 2.

[0190] For the specific means of isolation mentioned above, reference may be made to conventional technical means of isolating a faulty area in a memory in the prior art, which will not be described in detail here.

[0191] In the present application, the computing device 310 uses an isolation strategy to isolate the screen area, so that redundant storage resources can be used to replace faulty storage resources, thereby fully utilizing storage resources. Furthermore, the storage of data using faulty storage resources is avoided, which may cause data failure and improve data stability.

[0192] With respect to the contents of Figures 3 and 4 above, a complete embodiment is provided below. As shown in Figure 5 , Figure 5 is a second flow chart diagram of a memory detection method provided by this application. The method shown in Figure 5 can be applied to a memory detection system, which can be the computer system shown in Figure 2 . The contents shown in Figure 5 include the following steps ① to ⑩.

[0193] Step ①: The memory controller 510 collects fault information of the memory 120 during operation.

[0194] In one possible example, the memory controller 510 in the memory detection system detects the operating status of the memory (normal or abnormal) in real time during the operation of the memory detection system, and determines the CE or UCE corresponding to the abnormality when the memory 120 operates abnormally.

[0195] When the memory controller determines the CE or UCE corresponding to the memory 120 , it sends an interrupt request to the processor 110 .

[0196] Step ②: The processor 110 obtains fault information.

[0197] In a possible example, the processor 110 suspends normal running services according to the interrupt request and obtains fault information of the memory 120 during operation from the memory controller 510 .

[0198] Step ③: The processor 110 sends the fault information to the management controller 130 .

[0199] The above fault information includes the physical address of the memory.

[0200] In a possible example, the processor 110 sends the fault information to the management controller 130 through IPMI.

[0201] It is worth noting that the above-mentioned IPMI is only an example of a bus for managing communication between the controller 130 and the processor 110 and should not be understood as limiting the present application. In other embodiments of the present application, PCIe, SPI, etc. may also be used.

[0202] Step ④: The management controller 130 sends an inspection request to the processor 110 according to the fault information.

[0203] In a possible example, the management controller 130 sends a patrol request to the processor 110 according to the fault information, including: the management controller 130 extracts a physical address from the fault information, encapsulates the physical address into the patrol request, and then sends the patrol request to the processor.

[0204] In a possible embodiment, the inspection request further includes: the number of access operations to the target area.

[0205] In another possible embodiment, the inspection request further includes: a time limit for indicating an access operation to the target area.

[0206] In another possible embodiment, the inspection request further includes: the number of access operations to the target area, and a time limit for indicating the access operation to the target area.

[0207] For the contents of the above three possible embodiments, reference may be made to the description of S320 in FIG. 3 , which will not be elaborated here.

[0208] In a possible embodiment, the management controller 130 deduplicates the physical addresses in the fault information, that is, when there are multiple identical physical addresses, only one is retained.

[0209] Step ⑤: In response to the patrol request, the processor 110 instructs the memory controller 510 to perform an access operation on the target area indicated by the physical address.

[0210] The access operation includes a read operation and / or a write operation.

[0211] Illustratively, the processor 110 responds to the patrol request and configures the patrol address of the memory controller 510 to be the row address in the physical address according to the physical address in the patrol request, and then the memory controller 510 accesses the cells in the same row of the memory array indicated by the row address.

[0212] For example, the processor 110 may configure the patrol address of the memory controller 510 through BIOS.

[0213] In one possible scenario, the processor 110 may further configure the memory controller 510 to perform access operations of the number of times and / or a time limit for performing access operations.

[0214] In one possible example, the processor 110 may be configured by updating the firmware of the memory controller 510 .

[0215] Step 6: The memory controller 510 collects inspection information generated during the process of the memory controller 510 performing access operations on the target area.

[0216] In a possible implementation, when reading / writing data, the memory controller 510 uses an error-correcting code (ECC) to detect whether an abnormality occurs during the reading / writing process. If an abnormality occurs, it will be recorded as a patrol CE or patrol UCE.

[0217] In a possible scenario, the memory controller 510 will also record the physical address where the patrol CE or patrol UCE occurs.

[0218] Furthermore, the memory controller 510 uses the CE and the physical address where the CE appears, and / or the UCE and the physical address where the UCE appears as patrol information.

[0219] For the contents of the CE, UCE and physical address collected by the memory controller 510, reference may be made to conventional technical means for collecting CE or UCE in the prior art, which will not be described in detail here.

[0220] In a possible scenario, if the memory controller 510 does not detect a CE or UCE during an access operation, it generates an indicator indicating that neither a CE nor a UCE is collected as inspection information.

[0221] In a possible example, the inspection information may further include: operating environment information, such as memory temperature, voltage, and other information.

[0222] Step 7: The processor 110 obtains the inspection information collected by the memory controller 510.

[0223] For the content of step ⑥, please refer to the description of obtaining fault information in the above step ①, which will not be repeated here.

[0224] Step ⑧: The processor 110 sends the inspection information as an access response to the management controller 130.

[0225] In a possible example, the processor 110 reports the inspection information to the management controller 130 through IPMI.

[0226] Step 9: The management controller 130 detects the working status of the area according to the inspection information carried in the access response.

[0227] For the content of step ⑧, please refer to the description of S340 in Figure 3 above, and will not be repeated here.

[0228] Optionally, the method shown in FIG5 further includes the following steps (10).

[0229] Step (10): When the working status indicates a failure mode, the management controller 130 instructs the processor 110 to isolate and repair the memory.

[0230] In one possible example, the management controller 130 determines an isolation strategy that is mapped to the failure mode of the region, and then sends an isolation instruction including a field indicating the isolation strategy to the processor 110. The processor 110 configures parameters in the memory controller 510 according to the isolation instruction, so that the memory controller 510 isolates the target region.

[0231] For example, the above isolation instruction may also include: a physical address of the isolated area, such as the physical address of the above fault cell, fault row, fault bank, fault chip, and fault rank.

[0232] The processor 110 instructs the memory controller 510 to isolate the faulty cell, faulty row, faulty bank, faulty chip, and faulty rank according to the fields in the instruction and the physical address of the isolated area.

[0233] In a possible example, after isolation is completed, the memory controller 510 returns isolation information to the processor 110 , and the processor 110 further reports the isolation information to the management controller 130 through IPMI.

[0234] The isolation information is used to indicate whether isolation is successful or failed.

[0235] Regarding the description of the management controller 130 determining the isolation strategy having a mapping relationship with the failure mode according to the failure mode of the region, reference may be made to the contents shown in Table 2 in FIG. 4 , which will not be described in detail here.

[0236] In a possible embodiment, since the content shown in Figure 5 adjusts the configuration of the memory controller 510, in order to avoid the memory management controller 510 affecting the normal inspection of the memory 120, the management controller 130 sends a restore default configuration instruction to the processor 110, and the processor 110 restores the configuration of the memory controller 510 to the default configuration according to the restore default configuration instruction.

[0237] For example, the default configuration is to perform a global inspection on the memory, and the global inspection takes 200ms.

[0238] In a possible embodiment, the management controller 130 sends a patrol request to the processor 110 according to the fault information, and the process of the processor 110 configuring the memory controller 510 is recorded in a related log.

[0239] The memory detection method provided by the present application has been described in detail above with reference to Figures 1 to 5 . The memory detection device provided by the present application will now be described with reference to Figure 6 , which is a schematic diagram of the structure of a memory detection device provided by the present application. Memory detection device 600 can be used to implement the functions of computing device 310 in the above method embodiment, thereby also achieving the beneficial effects of the above method embodiment.

[0240] As shown in FIG6 , the memory detection apparatus 600 includes a first acquisition module 610, an execution module 620, a second acquisition module 630, and a detection module 640. The memory detection apparatus 600 is used to implement the functions of the computing device 310 in the method embodiments corresponding to FIG1 to FIG5 . In one possible example, the specific process of the memory detection apparatus 600 for implementing the above-mentioned memory detection method includes the following process:

[0241] The first acquisition module 610 is configured to acquire fault information, where the fault information includes a physical address of a memory.

[0242] The execution module 620 is configured to execute a read operation and / or a write operation on a target area according to the fault information; the target area is a storage space in the memory corresponding to the physical address.

[0243] The second acquisition module 630 is configured to acquire inspection information of the memory during a read operation and / or a write operation.

[0244] The detection module 640 is used to detect the working status of the target area according to the inspection information.

[0245] To further implement the functions of the method embodiments shown in Figures 1 to 5 , the present application also provides a memory detection device, as shown in Figure 7 , which is a second structural diagram of a memory detection device provided by the present application. The memory detection device 600 further includes an isolation module 650 .

[0246] The isolation module is used to determine an isolation strategy that has a mapping relationship with the failure mode according to the failure mode of the target area, and isolate the target area using the isolation strategy.

[0247] It should be noted that, in other embodiments, the first acquisition module 610 can be used to execute any step in the memory detection method, the execution module 620 can be used to execute any step in the memory detection method, the second acquisition module 630 can be used to execute any step in the memory detection method, and the detection module 640 can be used to execute any step in the memory detection method. The steps that the first acquisition module 610, the execution module 620, the second acquisition module 630, and the detection module 640 are responsible for implementing can be specified as needed. The full functionality of the memory detection device is achieved by having the first acquisition module 610, the execution module 620, the second acquisition module 630, and the detection module 640 respectively implement different steps in the memory detection method.

[0248] It is worth noting that the computing device 310 of the aforementioned embodiment may correspond to the memory detection device 600, and may correspond to the corresponding subject corresponding to Figures 2 to 5 of the method according to the embodiment of the present application, and the operations and / or functions of each module in the memory detection device 600 are respectively for implementing the corresponding processes of each method of the corresponding embodiments in Figures 2 to 5. For the sake of brevity, they will not be repeated here.

[0249] When the memory detection device implements any of the memory detection methods shown in the aforementioned figures via software, the memory detection device and its various modules may also be software modules. The memory detection method is implemented by calling the software module via a chip (e.g., the aforementioned processor 110, memory controller 510, and management controller 130). The chip may be a CPU, an ASIC, or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), an FPGA, a generic array logic (GAL), or any combination thereof.

[0250] For a more detailed description of the memory detection device, please refer to the relevant description of the embodiment shown in the aforementioned figures, and will not be repeated here. It is understood that the memory detection device shown in the aforementioned figures is only an example provided in this embodiment. Depending on the type of memory, the memory detection device may include more or fewer units, and this application is not limited to this.

[0251] When the memory detection device is implemented via hardware, the hardware may be implemented via a chip. The chip includes a power supply circuit and a processor. The power supply circuit is used to power the processor, and the processor is used to implement the method of any possible implementation method in the above embodiments. The beneficial effects can be found in the description of any aspect of the above embodiments and will not be repeated here.

[0252] It is understood that the processor in the embodiments of the present application may be a CPU, NPU or GPU, or may be other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0253] In addition, the memory detection device shown in Figures 6 and 7 can also be implemented through a communication device. The communication device here can refer to the computer system in the aforementioned embodiment, or, when the communication device is a chip or chip system applied to a computing device, the memory detection device can also be implemented through the above-mentioned chip or chip system.

[0254] The method steps in the embodiments of the present application can also be implemented by a chip executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in RAM, flash memory, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a communication device. Of course, the processor and the storage medium can also exist in the communication device as discrete components.

[0255] The present application also provides a computing device, which includes a memory and the above-mentioned chip, and is used to implement the functions of the computing device 310 in the above-mentioned method. In one possible design, the above-mentioned memory is used to store program instructions and / or data.

[0256] In a possible example, the computing device provided in this embodiment may be the computer system provided in Figure 2. The processor 110 and the management controller 130 shown in Figure 2 are the aforementioned chips.

[0257] In a possible example, the computer system shown in FIG2 further includes a memory controller, which may also be the aforementioned chip.

[0258] The present application also provides a computer program product including instructions. This computer program product can be software or a program product including instructions that can be run on a computing device or stored on any available medium. When this computer program product is run on at least one computing device, it causes the at least one computing device to perform the aforementioned memory detection method.

[0259] The present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute the memory detection method.

[0260] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the process or function described in the embodiments of the present application is performed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD).

[0261] In the various embodiments of the present application, unless otherwise specified or logically conflicting, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships. The various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. The size of the sequence number of each of the above processes does not mean the order of execution. The order of execution of each process should be determined by its function and inherent logic.

[0262] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A memory detection method, characterized in that: The method is applied to a computing device, the computing device including a memory, and the method includes: Acquiring fault information, wherein the fault information includes a physical address of the memory; Performing a read operation and / or a write operation on a target area according to the fault information; the target area is a storage space in the memory corresponding to the physical address; Obtaining inspection information of the memory during a read operation and / or a write operation; The working status of the target area is detected according to the inspection information.

2. The method according to claim 1, characterized in that The target area includes storage cells in the same row in the memory.

3. The method according to claim 1 or 2, characterized in that The fault information includes one or more of the following: a physical address of a cell in the memory, a correctable error of the cell, and an uncorrectable error of the cell.

4. The method according to claim 1 or 2, characterized in that The inspection information includes one or more of the following: a physical address of a cell in the memory, a correctable error of the cell during inspection, and an uncorrectable error of the cell during inspection.

5. The method according to any one of claims 1 to 4, characterized in that The performing a read operation and / or a write operation on the target area according to the fault information includes: Within the time limit, a read operation and / or a write operation is performed on the target area according to the physical address in the fault information.

6. The method according to any one of claims 1 to 5, characterized in that The working status indicates a fault mode of the target area. After detecting the working status of the target area according to the inspection information, the method further includes: Determining, according to the failure mode of the target area, an isolation strategy having a mapping relationship with the failure mode; The target area is isolated using the isolation strategy.

7. The method according to any one of claims 1 to 6, characterized in that The working status indicates the failure mode of the target area, and the failure mode includes: cell failure mode, address failure mode, row failure mode, memory array bank failure mode, storage chip device failure mode, storage column rank failure mode.

8. A memory detection device, characterized in that: The apparatus is applied to a computing device, the computing device includes a memory, and the apparatus includes: A first acquisition module is configured to acquire fault information, where the fault information includes a physical address of the memory; an execution module, configured to perform a read operation and / or a write operation on a target area according to the fault information; the target area being a storage space in the memory corresponding to the physical address; A second acquisition module is used to acquire inspection information of the memory during a read operation and / or a write operation; A detection module is used to detect the working status of the target area according to the inspection information.

9. The device according to claim 8, characterized in that The target area includes cells in the same row in the memory.

10. The device according to claim 8 or 9, characterized in that The fault information includes one or more of the following: a physical address of a cell in the memory, a correctable error of the cell, and an uncorrectable error of the cell.

11. The device according to claim 8 or 9, characterized in that The inspection information includes one or more of the following: a physical address of a cell in the memory, a correctable error of the cell during inspection, and an uncorrectable error of the cell during inspection.

12. The device according to any one of claims 8 to 11, characterized in that The execution module is specifically configured to execute a read operation and / or a write operation on the target area according to the physical address in the fault information within a time limit.

13. The device according to any one of claims 8 to 12, characterized in that The device further comprises: an isolation module; The isolation module is configured to determine, based on the failure mode of the target area, an isolation strategy having a mapping relationship with the failure mode, and isolate the target area using the isolation strategy.

14. The device according to any one of claims 8 to 13, characterized in that The working status indicates the failure mode of the target area, and the failure mode includes: cell failure mode, address failure mode, row failure mode, memory array bank failure mode, storage chip device failure mode, storage column rank failure mode.

15. A chip, characterized in that: include: Processor and power supply circuit; The power supply circuit is used to supply power to the processor; The processor is configured to execute the method according to any one of claims 1 to 7.

16. A computing device, characterized in that comprising a memory and the chip as claimed in claim 15; The memory is used to store computer instructions, and when the chip executes the computer instructions, it implements the method according to any one of claims 1 to 7.

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