Array substrate, display panel, and display device

Abstract

An array substrate (001), a display panel comprising the array substrate (001), and a display device. The array substrate (001) comprises: a base substrate (101), wherein the base substrate (101) comprises a display area (AA) and at least one fan-out area (FA) located on one side of the display area (AA); a plurality of data lines (103), which extend in a first direction (Y) in the display area (AA) and are arranged in a second direction (X); a plurality of fan-out lines (104), which are located in the at least one fan-out area (FA) and are electrically connected to the plurality of data lines (103), wherein the fan-out line (104) on the outermost side of the fan-out area (FA) is a first fan-out line (1041), and the remaining fan-out lines (104) are second fan-out lines (1042); and a plurality of dummy lines (105), which are located on the side of the first fan-out line (1041) away from the second fan-out lines (1042), wherein the dummy line (105) closest to the first fan-out line (1041) is a first dummy line (1051), and at least part of the first dummy line (1051) loads an electrical signal.

Description

Array substrate, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 18, 2024, with application number 202410333671.3 and invention name "Array substrate, display panel and display device", the entire content of which is incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0004] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] The array substrate, display panel, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0006] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0007] A base substrate, the base substrate comprising a display area and at least one fan-out area located on one side of the display area;

[0008] a plurality of data lines extending along a first direction and arranged along a second direction in the display area;

[0009] a plurality of fan-out lines located in the at least one fan-out area, the plurality of fan-out lines being electrically connected to the plurality of data lines, the outermost fan-out line in the fan-out area being a first fan-out line, and the remaining fan-out lines being a second fan-out line;

[0010] A plurality of dummy lines are located on a side of the first fan-out line away from the second fan-out line. The dummy line with the smallest distance from the first fan-out line is a first dummy line. At least some of the first dummy lines carry electrical signals.

[0011] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, there are multiple fan-out areas, and the first dummy lines between adjacent fan-out areas are electrically connected.

[0012] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a jumper extending along the second direction between adjacent fan-out areas;

[0013] The first dummy line and the jumper line are arranged in different layers, and the first dummy lines between adjacent fan-out areas are electrically connected through the jumper line.

[0014] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a common electrode connection line extending along the first direction between adjacent fan-out areas, and a common electrode branch line located on at least one side of the common electrode connection line in the second direction;

[0015] The orthographic projection of the jumper line on the base substrate overlaps with the orthographic projection of the common electrode connection line on the base substrate, and the orthographic projection of the common electrode branch line on the base substrate.

[0016] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the jumper wire is insulated from the common electrode connection line and the common electrode branch line; or, the jumper wire is electrically connected to the common electrode connection line and / or the common electrode branch line.

[0017] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, there are multiple fan-out areas, and the array substrate also includes a common electrode connecting line extending along the first direction between adjacent fan-out areas, and a common electrode branch line located on at least one side of the common electrode connecting line in the second direction; the first virtual line is integrally arranged with the common electrode branch line.

[0018] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a first electrostatic release structure and a second electrostatic release structure located between adjacent fan-out areas; wherein,

[0019] The electrostatic input end of the first electrostatic release structure is electrically connected to the data line, the electrostatic output end of the first electrostatic release structure is electrically connected to the electrostatic input end of the second electrostatic release structure, and the electrostatic output end of the second electrostatic release structure is electrically connected to the common electrode branch line.

[0020] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first electrostatic release structure extends along the second direction, and the second electrostatic release structure extends along the first direction.

[0021] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first electrostatic release structure and the second electrostatic release structure have the same structure.

[0022] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a short circuit line located on the side of the first electrostatic release structure close to the display area, and the short circuit line connects the electrostatic output end of the first electrostatic release structure and the electrostatic input end of the second electrostatic release structure.

[0023] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a first common electrode bus located on the side of the short-circuit line close to the display area, and a common electrode located in the display area, wherein the first common electrode bus is integrally arranged with the common electrode connecting line, and the first common electrode bus is electrically connected to the common electrode.

[0024] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second common electrode bus located on the side of the dummy line away from the display area, and the second common electrode bus is integrally arranged with the common electrode connecting line and the common electrode branch line.

[0025] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a binding area located on a side of the fan-out area away from the display area, the binding area including a reference signal terminal; the first dummy line is electrically connected to the reference signal terminal.

[0026] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the reference signal terminal is a common voltage signal terminal or a ground signal terminal.

[0027] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first dummy line is electrically connected to the 2nth fan-out line away from the first dummy line.

[0028] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first dummy line is electrically connected to the second fan-out line away from the first dummy line.

[0029] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the line width of the dummy line is substantially the same as the line width of the fan-out line.

[0030] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, a plurality of pixel electrodes are arranged in an array in the display area, the plurality of pixel electrodes are electrically connected to the data lines, and the size of the pixel electrodes in the first direction is smaller than the size of the pixel electrodes in the second direction.

[0031] On the other hand, an embodiment of the present disclosure provides an array substrate, comprising:

[0032] A base substrate, the base substrate comprising a display area, at least one fan-out area located on one side of the display area, and a binding area located on at least one side of the fan-out area;

[0033] a plurality of data lines extending along a first direction and arranged along a second direction in the display area;

[0034] a plurality of fan-out lines located in the at least one fan-out area, the plurality of fan-out lines being electrically connected to the plurality of data lines, the outermost fan-out line in the fan-out area being a first fan-out line, the remaining fan-out lines being a second fan-out line, and a lateral capacitance being provided between two adjacent fan-out lines;

[0035] a plurality of dummy lines, located on a side of the first fan-out line away from the second fan-out line, the dummy lines being floating;

[0036] A circuit board includes a test point, the test point is connected in series with a ground capacitor, the test point is electrically connected to the first fan-out line, and the ground capacitor is substantially equal to the lateral capacitor.

[0037] On the other hand, an embodiment of the present disclosure provides a display panel, comprising the array substrate provided in the embodiment of the present disclosure, and an opposite substrate disposed opposite to the array substrate.

[0038] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the fan-out line includes a lead portion extending along the first direction;

[0039] The array substrate also includes a protective structure located on a side of the lead portion away from the base substrate, the orthographic projection of the protective structure on the base substrate overlaps with the orthographic projection of the lead portion on the base substrate, and the orthographic projection of the protective structure on the base substrate is arranged to extend relative to the orthographic projection of the opposing substrate on the base substrate.

[0040] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram of wiring near two fan-out areas in the related art;

[0042] FIG2 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0043] FIG3 is an enlarged structural diagram of the display area AA in FIG2 ;

[0044] FIG4 is a schematic diagram of an enlarged structure of the Z1 area in FIG2 ;

[0045] FIG5 is a schematic structural diagram of the layer where the common electrode is located in FIG4 ;

[0046] FIG6 is a schematic structural diagram of the layer where the gate lines are located in FIG4 ;

[0047] FIG7 is a schematic structural diagram of the active layer in FIG4 ;

[0048] FIG8 is a schematic structural diagram of the layer where the data line is located in FIG4;

[0049] FIG9 is a schematic structural diagram of the layer where the vias are located in FIG4 ;

[0050] FIG10 is a schematic structural diagram of the layer where the pixel electrode is located in FIG4 ;

[0051] FIG11 is an enlarged structural diagram of the Z2 region in FIG2 ;

[0052] FIG12 is an enlarged structural diagram of the Z3 region in FIG2 ;

[0053] FIG13 is another enlarged structural diagram of the Z1 region in FIG2 ;

[0054] FIG14 is a schematic structural diagram of the layer where the gate lines are located in FIG13;

[0055] FIG15 is an enlarged structural diagram of the Z4 region in FIG4 ;

[0056] FIG16 is an equivalent circuit diagram of a first electrostatic release structure and a second electrostatic release structure;

[0057] FIG17 is a schematic diagram of an enlarged structure of the Z5 area in FIG15 ;

[0058] FIG18 is a schematic diagram of wiring of two fan-out areas and their vicinity provided by an embodiment of the present disclosure;

[0059] FIG19 is another schematic diagram of wiring of two fan-out areas and their vicinity provided by an embodiment of the present disclosure;

[0060] FIG20 is another schematic diagram of wiring of two fan-out areas and their vicinity provided by an embodiment of the present disclosure;

[0061] FIG21 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0062] FIG22 is a schematic diagram of an enlarged structure of a display panel provided by an embodiment of the present disclosure corresponding to the Z2 area in FIG1 ;

[0063] FIG23 is a schematic diagram of the enlarged structure of the display panel provided by an embodiment of the present disclosure corresponding to the Z3 area in FIG1 . DETAILED DESCRIPTION

[0064] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0065] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0066] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0067] Competition in the TFT-LCD market is becoming increasingly fierce. As the development of high frequency, high refresh rate, and high resolution (PPI) gradually slows down, fat modules and screen empowerment are another way to enhance product competitiveness.

[0068] FIG1 is a wiring diagram near two fan-out areas in the related art. As can be seen from FIG1 , the data line (DAL) is electrically connected to the circuit board (e.g., chip-on-film COF) through the fan-out lines (FA1, FA2). However, when the fan-out lines (FA1, FA2) are very long, the load capacitance of the outermost fan-out line corresponding to a single COF relative to the other inner fan-out lines will be different. Take the outermost fan-out line as the first fan-out line (FA1) and the remaining fan-out lines as the second fan-out line (FA2) as an example. Because the first fan-out line (FA1) has a data signal only on one side and the other side is a floating dummy line (DYL), and the second fan-out line (FA2) has data signals on both sides, there is a difference in the lateral capacitance between the first fan-out line (FA1) and the second fan-out line (FA2). On products that are sensitive to charging rates, there is a color difference between the display area controlled by the first fan-out line (FA1) and the display area controlled by the second fan-out line (FA2), which manifests as poor bright line.

[0069] In order to at least improve the above-mentioned technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate. FIG2 is a schematic structural diagram of the array substrate provided in the embodiment of the present disclosure, FIG3 is an enlarged structural diagram of the display area AA in FIG2, FIG4 is an enlarged structural diagram of the Z1 area in FIG2, FIG5 to FIG10 are schematic structural diagrams of each film layer in FIG4, FIG11 is an enlarged structural diagram of the Z2 area in FIG2, and FIG12 is an enlarged structural diagram of the Z3 area in FIG2. As shown in FIG2 to FIG12, the array substrate provided in the embodiment of the present disclosure includes:

[0070] The base substrate 101 includes a display area AA and at least one fan-out area FA located on one side of the display area AA.

[0071] In some embodiments, as shown in FIG. 3 , the display area AA of the present disclosure is provided with a plurality of gate lines 102 arranged along a first direction Y and extending along a second direction X, a plurality of data lines 103 extending along the first direction Y and arranged along a second direction X, and a plurality of sub-pixels SP located within the area defined by the gate lines 102 and the data lines 103. The sub-pixels SP in a row have the same color, at least two adjacent sub-pixels SP in a column constitute a pixel P, and the sub-pixels SP within the same pixel P have different colors. One gate line 102 is coupled to a row of sub-pixels SP, and one data line 103 is coupled to two columns of sub-pixels SP. Sub-pixels SP in adjacent rows coupled to the same data line 103 are located in adjacent columns. In other words, the present disclosure can provide a tri-gate product in which the multiple sub-pixels SP of two pixels P are controlled by two data lines 103 and three gate lines 102. This reduces the number of data lines 103 and, accordingly, the number of source driver ICs, significantly lowering material costs.

[0072] It should be noted that in the present disclosure, "row" refers to the arrangement along the extension direction of the gate line 102 (i.e., the second direction X), and "column" refers to the arrangement along the extension direction of the data line 103 (i.e., the first direction Y). In some embodiments, the sub-pixel SP may include a red sub-pixel area R, a green sub-pixel area G, and a blue sub-pixel area B, and the red sub-pixel area R, green sub-pixel area G, and blue sub-pixel area B adjacent to each other in the same column constitute a pixel P. In the present disclosure, a pixel P is illustrated as including three sub-pixels SP. Optionally, a pixel P may also include four or other numbers of sub-pixels SP, for example, also including white sub-pixels, which is not limited here. In addition, the color of the sub-pixel SP can be understood as follows: after the opposing substrate and the array substrate are aligned, the color resist provided on the opposing substrate corresponds to the color of the sub-pixel SP, or the color resist structure provided on the array substrate corresponds to the color of the sub-pixel SP (i.e., COA technology).

[0073] In some embodiments, the base substrate 101 may be a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like. The material of the gate line 102 may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), or nickel (Ni). The gate line 102 may have a single-layer structure or a laminated structure, such as a single-layer structure composed of a molybdenum metal layer. The material of the data line 103 may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), or nickel (Ni). The data line 103 may have a single-layer structure or a laminated structure, such as a laminated structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0074] Continuing to refer to Figures 2, 4, 6, 11 and 12, it can be seen that the array substrate provided by the embodiment of the present disclosure also includes a plurality of fan-out lines 104 located in at least one fan-out area PA, and the plurality of fan-out lines 104 are electrically connected to the plurality of data lines 103. The outermost fan-out line 104 in the fan-out area PA is the first fan-out line 1041, and the remaining fan-out lines 104 are the second fan-out lines 1042.

[0075] In some embodiments, the fan-out line 104 is provided in the same layer and with the same material as the gate line 102. It should be noted that, in the present disclosure, "the same layer" refers to a layer structure formed by a single patterning process using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0076] In some embodiments, as shown in Figures 2, 4, 6, 11, and 12, the array substrate of the present disclosure further includes a plurality of dummy lines 105 disposed on a side of the first fan-out line 1041 away from the second fan-out line 1042. The dummy lines 105 are not electrically connected to the data lines 103. The dummy lines 105 that are the smallest distance from the first fan-out line 1041 are first dummy lines 1051. At least some of the first dummy lines 1051 are loaded with electrical signals, for example, all of the first dummy lines 105 are loaded with electrical signals. In some embodiments, the dummy lines 105 are provided in the same layer and material as the gate lines 102. The other dummy lines 105 other than the first dummy lines 105 may or may not be loaded with electrical signals, which is not limited in the present disclosure.

[0077] In the array substrate provided in the embodiments of the present disclosure, both sides of the second fan-out line 1042 carry data signals. By loading an electrical signal onto the first dummy line 1051 closest to the first fan-out line 1041, one side of the first fan-out line 1041 carries the data signal, while the other side carries the electrical signal on the first dummy line 1051. This allows the lateral capacitance of the outermost first fan-out line 1041 to be infinitely close to the lateral capacitance of the inner second fan-out line 1042, effectively improving the problem of poor bright line performance caused by the difference in lateral capacitance between the first and second fan-out lines 1041, 1042.

[0078] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4 , there are multiple fan-out areas FA. To facilitate loading electrical signals for the first dummy lines 1051 , electrical connections between adjacent fan-out areas FA may be provided.

[0079] In some embodiments, as shown in Figures 2, 4, 6, and 10, the array substrate provided in embodiments of the present disclosure further includes a jumper line 106 extending between adjacent fan-out areas FA along the second direction X and disposed at a different layer from the first dummy line 1051. For example, the jumper line 106 is formed from the same layer and material as the top conductive layer (e.g., indium tin oxide (ITO) layer) of the array substrate. Optionally, the first dummy lines 1051 between adjacent fan-out areas FA can be electrically connected via the jumper line 106. In some embodiments, as shown in Figures 4, 6, 9, and 10, the first dummy line 1051 and the jumper line 106 are electrically connected via at least one first via V1 extending through the insulating layer therebetween.

[0080] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 4, 6, and 10, may further include a common electrode connection line 107 extending between adjacent fan-out areas FA along a first direction Y, and a common electrode branch line 108 located on at least one side of the common electrode connection line 107 in a second direction X. Optionally, the common electrode connection line 107 and the common electrode branch line 108 are provided in the same layer and material as the gate line 102. Continuing with Figures 2, 4, 6, and 10, it can be seen that to ensure that the first dummy lines 1051 outside adjacent fan-out areas FA are electrically connected to each other via the jumper line 106, the present disclosure arranges that the orthographic projection of the jumper line 106 on the base substrate 101 overlaps with the orthographic projection of the common electrode connection line 107 on the base substrate 101 and the orthographic projection of the common electrode branch line 108 on the base substrate 101. In other words, the jumper line 106 crosses the common electrode connection line 107 and the common electrode branch line 108 in the second direction X.

[0081] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the jumper 106 can be insulated from the common electrode connection line 107 and the common electrode branch line 108. In this case, the first dummy line 1051 can be directly loaded with an electrical signal through a circuit board (for example, a chip-on-film COF); or, the jumper 106 can also be electrically connected to the common electrode connection line 107 and / or the common electrode branch line 108. In this case, the first dummy line 1051 can be directly loaded with an electrical signal through a circuit board (for example, a chip-on-film COF), or the common electrode connection line 107 and / or the common electrode branch line 108 can be directly loaded with an electrical signal through a circuit board (for example, a chip-on-film COF), and the electrical signal is then transmitted to the first dummy line 1051 via the jumper 106.

[0082] In some embodiments, Figure 13 is another enlarged schematic diagram of the structure of the Z1 region in Figure 2, and Figure 14 is a schematic diagram of the structure of the layer where the gate lines are located in Figure 13. As can be seen from Figures 13 and 14, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first dummy line 1051 can also be integrated with the common electrode branch line 108, so that after the common electrode branch line 108 is loaded with an electrical signal through a circuit board (e.g., a chip on film COF), the electrical signal can be transmitted from the common electrode branch line 108 to the first dummy line 1051.

[0083] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 4, and 13 to 16, further includes a first electrostatic discharge structure 109 and a second electrostatic discharge structure 110 located between adjacent fan-out areas FA; wherein the electrostatic input terminal esd_in of the first electrostatic discharge structure 109 is electrically connected to the data line 103, the electrostatic output terminal esd_out of the first electrostatic discharge structure 109 is electrically connected to the electrostatic input terminal esd_in of the second electrostatic discharge structure 110, and the electrostatic output terminal esd_out of the second electrostatic discharge structure 110 is electrically connected to the common electrode branch line 108. In this way, static electricity on the data line 103 can be released to the common electrode branch line 108 through the first electrostatic discharge structure 109 and the second electrostatic discharge structure 110 in sequence, thereby preventing interference with the data line 103 caused by excessive static electricity.

[0084] In some embodiments, as shown in Figures 2, 4, 13 and 14, in the present disclosure, the first electrostatic release structure 109 may extend along the second direction X, and the second electrostatic release structure 110 may extend along the first direction Y. For example, the first electrostatic release structure 109 extends along the second direction X on the side of the dummy line 105 close to the display area AA, and the second electrostatic release structure 110 extends along the first direction Y on the side of the common electrode connection line 107 close to the fan-out area FA, so that the first electrostatic release structure 109 and the second electrostatic release structure 110 reasonably utilize the space between adjacent fan-out areas FA, which is conducive to narrow frame design.

[0085] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, in order to simplify the design, the structures of the first electrostatic release structure 109 and the second electrostatic release structure 110 can be the same. Figure 15 is an enlarged structural schematic diagram of the Z4 area in Figure 4, and Figure 16 is an equivalent circuit diagram of the first electrostatic release structure 109 and the second electrostatic release structure 110. As shown in Figures 2, 4, 6 to 10, and 13 to 16, the first electrostatic release structure 109 and the second electrostatic release structure 110 both include a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein the gate g1 of the first transistor M1, the first electrode s1 of the first transistor M1, and the second electrode d2 of the second transistor M2 are connected, and the gate g1 of the first transistor M1 serves as the electrostatic input terminal esd_in, the first electrode s1 of the first transistor M1 and the second electrode d2 of the second transistor M2 are reused, and the gate g1 of the first transistor M1 can be connected through the first switching electrode 11 1 is electrically connected to the first electrode s1 of the first transistor M1 (equivalent to the second electrode d2 of the second transistor M2), optionally, the gate g1 of the first transistor M1 is electrically connected to the first transfer electrode 111 through a second via V2 penetrating the insulating layer therebetween, and the first electrode s1 of the first transistor M1 (equivalent to the second electrode d2 of the second transistor M2) is electrically connected to the first transfer electrode 111 through a third via V3 penetrating the insulating layer therebetween; the second electrode d1 of the first transistor M1, the gate g2 of the second transistor M2, the first electrode s2 of the second transistor M2, the gate g3 of the third transistor M3, and the third transistor M The first electrode s3 of the second transistor M3 is connected to the first electrode s3 of the fourth transistor M3 and the second electrode d4 of the fourth transistor M4, wherein the gate g2 of the second transistor M2 is multiplexed with the gate g3 of the third transistor M3, the second electrode d1 of the first transistor M1 is multiplexed with the first electrode s2 of the second transistor M2, the first electrode s3 of the third transistor M3 is multiplexed with the second electrode d4 of the fourth transistor M4, and the gate g2 of the second transistor M2 (equivalent to the gate g3 of the third transistor M3) is connected to the second electrode d1 of the first transistor M1 (equivalent to the first electrode s2 of the second transistor M2) and the first electrode s3 of the third transistor M3 (equivalent to the gate g3 of the third transistor M3) through the second switching electrode 112. The second electrode d4 of the fourth transistor M4 is electrically connected; optionally, the gate g2 of the second transistor M2 (equivalent to the gate g3 of the third transistor M3) is electrically connected to the second transfer electrode 112 via a fourth via V4 penetrating the insulating layer therebetween, the second electrode d1 of the first transistor M1 (equivalent to the first electrode s2 of the second transistor M2) is electrically connected to the second transfer electrode 112 via a fifth via V5 penetrating the insulating layer therebetween, and the first electrode s3 of the third transistor M3 (equivalent to the second electrode d4 of the fourth transistor M4) is electrically connected to the second transfer electrode 112 via a sixth via V6 penetrating the insulating layer therebetween;The second electrode d3 of the third transistor M3, the gate g4 of the fourth transistor M4, and the first electrode s4 of the fourth transistor M4 are connected, and the gate g4 of the fourth transistor M4 serves as the electrostatic output terminal esd_out. The second electrode d3 of the third transistor M3 and the first electrode s4 of the fourth transistor M4 are multiplexed. The gate g4 of the fourth transistor M4 and the first electrode s4 of the fourth transistor M4 (equivalent to the second electrode d3 of the third transistor M3) are electrically connected via a third transfer electrode 113. Optionally, the gate g4 of the fourth transistor M4 and the third transfer electrode 113 are electrically connected via a seventh via V7 penetrating the insulating layer therebetween. The first electrode s4 of the fourth transistor M4 (equivalent to the second electrode d3 of the third transistor M3) and the third transfer electrode 113 are electrically connected via an eighth via V8 penetrating the insulating layer therebetween.

[0086] In some embodiments, as shown in FIG17 , to improve etching uniformity, the transistors M1 to M4 of the present disclosure may further include an island structure sd formed in the same layer and material as the first electrodes s1 to s4 and the second electrodes d1 to d4. FIG17 illustrates the fourth transistor M4 including the island structure sd as an example. Of course, in some embodiments, the transistors M1 to M4 may not include the island structure sd, and this disclosure is not limited thereto.

[0087] In some embodiments, the first transfer electrodes 111, the second transfer electrodes 112, and the third transfer electrodes 113 are formed from the same layer and material as the top conductive layer of the array substrate (e.g., indium tin oxide (ITO)). The gate electrodes g1-g4 are formed from the same layer and material as the gate lines 102. The first electrodes s1-s4 and the second electrodes d1-d4 are formed from the same layer and material as the data lines 103. The layer where the data lines 103 are located is between the layer where the gate lines 102 are located and the layer where the transfer electrodes 112-113 are located. The layer where the gate lines 102 are located is also between the layer where the data lines 103 are located and the base substrate 101. The insulating layer between the layer where the gate lines 102 are located and the layer where the data lines 103 are located can be a gate insulating layer (GI), and the insulating layer between the layer where the data lines 103 are located and the layer where the transfer electrodes 112-113 are located can include a passivation layer (PVX). In some embodiments, the insulating layer between the layer where the data lines 103 are located and the layer where the transfer electrodes 112-113 are located can also include an organic layer (ORG), a color resist layer (RGB), etc.

[0088] In some embodiments, the transistors M1 to M4 of the present disclosure may be p-type transistors or n-type transistors. The transistors M1 to M4 may be bottom-gate transistors, top-gate transistors, or dual-gate transistors, etc., without limitation herein. In the present disclosure, the first electrodes s1 to s4 of the transistors M1 to M4 may be sources, and the second electrodes d1 to d4 may be drains, or the first electrodes s1 to s4 of the transistors M1 to M4 may be drains, and the second electrodes d1 to d4 may be sources, without limitation herein. The active layers a1 to a4 of the transistors M1 to M4 may be made of amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (e.g., indium gallium zinc oxide IGZO), etc.

[0089] In some embodiments, the gate insulating layer (GI) and passivation layer (PVX) can be made of at least one of inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). The planarization layer (ORG) can be made of, but not limited to, at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and novolac epoxy acrylic resin. The color resist layer (RGB) can include red, green, and blue resists.

[0090] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 6, and 13 to 16, may further include a short-circuit line (short ring) 111 located on the side of the first electrostatic discharge structure 109 near the display area AA. The short-circuit line 114 connects the electrostatic output terminal esd_out of the first electrostatic discharge structure 109 with the electrostatic input terminal esd_in of the second electrostatic discharge structure 110. Optionally, the short-circuit line 114 is provided in the same layer and material as the gate line 102.

[0091] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 to 6, 13, and 14, may further include a first common electrode bus 115 located on the side of the short-circuit line 114 near the display area AA, and a common electrode 116 located in the display area AA. The first common electrode bus 115 is integrally provided with the common electrode connection line 107 and the common electrode branch line 108, and the first common electrode bus 115 is electrically connected to the common electrode 116. In some embodiments, the layer where the common electrode 116 is located is located between the layer where the gate line 102 is located and the base substrate 101, and the material of the common electrode 116 includes at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO).

[0092] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 6, 13 and 14, it can also include a second common electrode bus 117 located on the side of the virtual line 105 away from the display area AA. In order to simplify the pattern, the second common electrode bus 117 is integrally arranged with the common electrode connecting line 107 and the common electrode branch line 108 in the present disclosure.

[0093] In some embodiments, the sealant outside the display area AA can be illuminated on the side of the base substrate 101 to achieve curing of the sealant. Accordingly, to allow the irradiated light to pass through, as shown in Figures 4, 6, 11, 12, 13, and 14, the present disclosure can provide multiple hollow structures OW in all or part of the signal lines with larger line widths, for example, the second common electrode bus line 117, the gate drive circuit signal line 118, etc., can be provided with multiple hollow structures OW in all or part.

[0094] In some embodiments, FIG18 is a schematic diagram of wiring arrangements of two fan-out areas FA and their vicinities provided in an embodiment of the present disclosure. As shown in FIG18 , the array substrate of the present disclosure may further include a bonding area BA located on a side of the fan-out area FA away from the display area AA. The bonding area BA includes a reference signal terminal 119. The first dummy line 1051 is electrically connected to the reference signal terminal 119 so as to load an electrical signal to the first dummy line 1051 through the reference signal terminal 119. Optionally, the reference signal terminal 119 is a common voltage signal terminal capable of loading a common voltage signal (com), or a ground signal terminal capable of loading a ground signal (gnd).

[0095] In some embodiments, FIG19 is another schematic diagram of wiring arrangements of two fan-out areas FA and their vicinities provided in an embodiment of the present disclosure. As shown in FIG19 , in the array substrate provided in an embodiment of the present disclosure, a first dummy line 1051 can be electrically connected to the 2nth fan-out line 104 located away from it. FIG19 specifically illustrates the electrical connection of the first dummy line 1051 to the second fan-out line 104 located away from it. Since data signals are loaded in a "+, -, +, -, +, -, ..." manner, the data signals on both sides of the second fan-out line 1042 have the same polarity. By electrically connecting the first dummy line 1051 to the 2nth fan-out line 104 located away from it, the present disclosure ensures that the data signals on both sides of the first fan-out line 1041 have the same polarity. This ensures that the operating environment of the first fan-out line 1041 is consistent with that of the second fan-out line 1042, resulting in uniform lateral capacitance, thereby alleviating the bright line problem caused by the difference in lateral capacitance between the two.

[0096] Furthermore, when the first dummy line 1051 of the present disclosure is electrically connected to the second fan-out line 104 located away from it, the crossover between the two can be made shorter, which helps reduce the voltage drop (IR drop). Optionally, to ensure that the crossover between the first dummy line 1051 and the 2nth fan-out line 104 located away from it is as short as possible, the present disclosure can set the crossover position where the first dummy line 1051 connects to the 2nth fan-out line 104 adjacent to the bonding terminal DAP (the bonding terminal DAP is electrically connected to the fan-out line 104). Of course, in some embodiments, the present disclosure can also set the crossover position where the first dummy line 1051 connects to the 2nth fan-out line 104 at other locations, which is not limited by the present disclosure.

[0097] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 6, and 11 to 14, the line width of the dummy line 105 can be approximately the same as the line width of the fan-out line 104. Specifically, the line width of the dummy line 105 located outside the inclined portion 401 contained in the fan-out line 104 is approximately the same as the line width of the inclined portion 401, and the line width of the dummy line 105 located outside the lead portion 402 contained in the fan-out line 104 is approximately the same as the line width of the lead portion 402, so as to ensure better etching uniformity. Continuing to refer to Figures 4, 6, 11 to 14, it can be seen that a plurality of dummy lines 105 are provided on the outside of the inclined portion 401 contained in the fan-out line 104. In order to achieve better etching uniformity and prevent adjacent wiring from short-circuiting, the spacing between adjacent dummy lines 105 in the present disclosure can be roughly the same as the spacing between adjacent inclined portions 401. In other words, the wiring density of the dummy lines 105 outside the inclined portion 401 can be roughly the same as the wiring density of the inclined portion 401.

[0098] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent, or there may be some deviations (for example, a deviation of ±5%). Therefore, as long as the "approximately the same" relationship between related features meets the error allowance, it falls within the scope of protection of the present disclosure.

[0099] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 and 10, the sub-pixel SP includes a pixel electrode 121. Optionally, the pixel electrode 121 is a slit electrode. The pixel electrode 121 can be located in the top conductive layer of the array substrate. The pixel electrode 121 is electrically connected to the data line 103. The size of the pixel electrode 121 in the first direction Y is smaller than the size of the pixel electrode 121 in the second direction X, so as to facilitate the use of a three-gate structure for pixel layout.

[0100] In some embodiments, FIG20 is another wiring diagram of two fan-out areas FA and their vicinity provided in an embodiment of the present disclosure. As shown in FIG20, in the array substrate provided in an embodiment of the present disclosure, the dummy lines 105 are all floating (ie, no electrical signal is loaded), and the array substrate further includes a circuit board 122 (e.g., a printed circuit board PCB). The circuit board 122 includes a test point 1221, and the test point 1221 is electrically connected to the first fan-out line 1041. The test point 1221 is connected in series with a ground capacitor C1. This ground capacitor C1 and the lateral capacitance C2 of the in-plane fan-out line 105 are in parallel. Therefore, the total load capacitance of the first fan-out line 1041 is the sum of C1 and C2, while the total load capacitance of the second fan-out line 1042 is 2*C2. Therefore, as long as the ground capacitance C1 and the lateral capacitance C2 between two adjacent fan-out lines 104 are roughly equal (for example, equal, or within the error range caused by manufacturing, measurement, etc.), the capacitance difference between the first fan-out line 1041 and the second fan-out line 1041 can be neutralized, thereby improving the bright line problem.

[0101] In some embodiments, as shown in Figures 4 to 10, the array substrate provided by the embodiment of the present disclosure may further include a transfer line 123, a fourth transfer electrode 124, and a transistor TFT connecting the pixel electrode 121 with the data line 103 and the gate line 102; wherein the transfer line 123 is connected between the common electrode 116 and the first common electrode bus 115, and optionally, the first common electrode bus 115 and the transfer line 123 are electrically connected through a ninth via hole V9 penetrating the insulating layer between the two, and the common electrode 116 and the transfer line 123 are electrically connected through a tenth via hole V10 penetrating the insulating layer between the two; the fourth transfer electrode 124 connects the gate g1 of the first transistor M1 and the data line 103. The fourth transfer electrode 124 is electrically connected to the data line 103. Optionally, the fourth transfer electrode 124 is electrically connected to the gate g1 of the first transistor M1 through at least one eleventh via hole V11 penetrating the insulating layer therebetween. The fourth transfer electrode 124 is electrically connected to the data line 103 through at least one twelfth via hole V12 penetrating the insulating layer therebetween. The gate g of the transistor TFT is partially reused with the gate line 102. The first electrode s of the transistor TFT is integrally provided with the data line 103. The second electrode d of the transistor TFT is electrically connected to the pixel electrode 121 through a thirteenth via hole V13. The active layer a of the transistor TFT can be made of amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (e.g., indium gallium zinc oxide IGZO), etc. Other essential components of the array substrate are well understood by those skilled in the art and are not described in detail here. They should not be construed as limiting the present disclosure.

[0102] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel. FIG21 is a schematic structural diagram of the display panel provided by an embodiment of the present disclosure. As shown in FIG21 , the display panel of the present disclosure includes the array substrate 001 provided by the embodiment of the present disclosure, and an opposing substrate 002 disposed opposite the array substrate 001. Because the principles for solving the problems of the display panel are similar to those for solving the problems of the aforementioned array substrate, the implementation of the display panel can refer to the embodiments of the aforementioned array substrate, and the repeated parts will not be repeated here.

[0103] In some embodiments, FIG22 is a schematic diagram of the enlarged structure of the display panel provided in an embodiment of the present disclosure, corresponding to the Z2 region in FIG1 , and FIG23 is a schematic diagram of the enlarged structure of the display panel provided in an embodiment of the present disclosure, corresponding to the Z3 region in FIG1 . As can be seen from FIG22 and FIG23 , the fan-out line 104 includes a lead portion 402 extending along the first direction Y; the array substrate 001 also includes a protective structure 125 located on the side of the lead portion 402 away from the base substrate 101. The orthographic projection of the protective structure 123 on the base substrate 101 overlaps with the orthographic projection of the lead portion 402 on the base substrate 101, and the orthographic projection of the protective structure 125 on the base substrate 101 is arranged to be extended relative to the orthographic projection of the opposing substrate 002 on the base substrate 101. In this way, the protective structure 125 can be used to protect the fan-out line 104 during the cutting process of the opposing substrate 002, preventing the fan-out line 104 from being cut. Optionally, the protection structure 125 may include a first sub-protection structure located at the layer where the data line 103 is located, and / or a second sub-protection structure located at the layer where the pixel electrode 121 is located.

[0104] It should be understood that when the first dummy line 1051 is loaded with a signal through the reference signal terminal 119, the first dummy line 1051 will also be wired outside the lead portion 402. At this time, in order to protect the first dummy line 1051, a protective structure 125 can also be set on the first dummy line 1051 outside the lead portion 402.

[0105] In some embodiments, as shown in FIG21 , the display panel provided by the embodiment of the present disclosure may further include a liquid crystal layer 003 disposed between an array substrate 001 and an opposing substrate 002. A first polarizer 004 may be disposed on a side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on a side of the opposing substrate 002 away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0106] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel. The backlight module can be a direct-type backlight module or an edge-entry backlight module. Optionally, the edge-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0107] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-scale micro light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when the micro light-emitting device is used as a backlight source, it can achieve a more precise dynamic backlight effect. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0108] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0109] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0110] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: A base substrate, the base substrate comprising a display area and at least one fan-out area located on one side of the display area; a plurality of data lines extending along a first direction and arranged along a second direction in the display area; a plurality of fan-out lines located in the at least one fan-out area, the plurality of fan-out lines being electrically connected to the plurality of data lines, the outermost fan-out line in the fan-out area being a first fan-out line, and the remaining fan-out lines being a second fan-out line; A plurality of dummy lines are located on a side of the first fan-out line away from the second fan-out line. The dummy line with the smallest distance from the first fan-out line is a first dummy line. At least some of the first dummy lines carry electrical signals.

2. The array substrate according to claim 1, wherein: There are multiple fan-out areas, and the first dummy lines between adjacent fan-out areas are electrically connected.

3. The array substrate according to claim 2, wherein: Also included are jumper wires extending along the second direction between adjacent fan-out areas; The first dummy line and the jumper line are arranged in different layers, and the first dummy lines between adjacent fan-out areas are electrically connected through the jumper line.

4. The array substrate according to claim 3, wherein: It also includes a common electrode connection line extending along the first direction between adjacent fan-out areas, and a common electrode branch line located on at least one side of the common electrode connection line in the second direction; The orthographic projection of the jumper line on the base substrate overlaps with the orthographic projection of the common electrode connection line on the base substrate, and the orthographic projection of the common electrode branch line on the base substrate.

5. The array substrate according to claim 4, wherein: The jumper wire is insulated from the common electrode connection wire and the common electrode branch wire; or the jumper wire is electrically connected to the common electrode connection wire and / or the common electrode branch wire.

6. The array substrate according to claim 1, wherein: There are multiple fan-out areas, and the array substrate also includes a common electrode connecting line extending along the first direction between adjacent fan-out areas, and a common electrode branch line located on at least one side of the common electrode connecting line in the second direction; the first dummy line is integrally arranged with the common electrode branch line.

7. The array substrate according to any one of claims 4 to 6, wherein: It also includes a first electrostatic release structure and a second electrostatic release structure located between adjacent fan-out areas; wherein, The electrostatic input end of the first electrostatic release structure is electrically connected to the data line, the electrostatic output end of the first electrostatic release structure is electrically connected to the electrostatic input end of the second electrostatic release structure, and the electrostatic output end of the second electrostatic release structure is electrically connected to the common electrode branch line.

8. The array substrate according to claim 7, wherein: The first electrostatic release structure extends along the second direction, and the second electrostatic release structure extends along the first direction.

9. The array substrate according to claim 7 or 8, wherein: The first electrostatic discharge structure and the second electrostatic discharge structure have the same structure.

10. The array substrate according to any one of claims 7 to 9, wherein: It also includes a short-circuit line located on a side of the first electrostatic release structure close to the display area, and the short-circuit line connects the electrostatic output end of the first electrostatic release structure and the electrostatic input end of the second electrostatic release structure.

11. The array substrate according to claim 10, wherein: It also includes a first common electrode bus located on the side of the short-circuit line close to the display area, and a common electrode located in the display area. The first common electrode bus is integrally arranged with the common electrode connecting line and is electrically connected to the common electrode.

12. The array substrate according to any one of claims 4 to 10, wherein: It also includes a second common electrode bus located on a side of the dummy line away from the display area, wherein the second common electrode bus is integrally provided with the common electrode connecting line and the common electrode branch line.

13. The array substrate according to any one of claims 1 to 12, wherein: It also includes a binding area located on a side of the fan-out area away from the display area, the binding area includes a reference signal terminal; the first dummy line is electrically connected to the reference signal terminal.

14. The array substrate according to claim 13, wherein: The reference signal terminal is a common voltage signal terminal or a ground signal terminal.

15. The array substrate according to any one of claims 1 to 12, wherein: The first dummy line is electrically connected to a 2nth fan-out line away from the first dummy line.

16. The array substrate according to claim 15, wherein: The first dummy line is electrically connected to a second fan-out line that is far away from the first dummy line.

17. The array substrate according to any one of claims 1 to 16, wherein: The line width of the dummy line is substantially the same as the line width of the fan-out line.

18. The array substrate according to any one of claims 1 to 17, wherein: A plurality of pixel electrodes are arranged in an array in the display area, the plurality of pixel electrodes are electrically connected to the data line, and a size of the pixel electrodes in the first direction is smaller than a size of the pixel electrodes in the second direction.

19. An array substrate, wherein: include: A base substrate, the base substrate comprising a display area, at least one fan-out area located on one side of the display area, and a binding area located on at least one side of the fan-out area; a plurality of data lines extending along a first direction and arranged along a second direction in the display area; a plurality of fan-out lines located in the at least one fan-out area, the plurality of fan-out lines being electrically connected to the plurality of data lines, the outermost fan-out line in the fan-out area being a first fan-out line, the remaining fan-out lines being a second fan-out line, and a lateral capacitance being provided between two adjacent fan-out lines; a plurality of dummy lines, located on a side of the first fan-out line away from the second fan-out line, the dummy lines being floating; A circuit board includes a test point, the test point is connected in series with a ground capacitor, the test point is electrically connected to the first fan-out line, and the ground capacitor is substantially equal to the lateral capacitor.

20. A display panel, wherein: The invention comprises the array substrate according to any one of claims 1 to 19, and an opposite substrate arranged opposite to the array substrate.

21. The display panel according to claim 20, wherein: The fan-out line includes a lead portion extending along the first direction; The array substrate also includes a protective structure located on a side of the lead portion away from the base substrate, the orthographic projection of the protective structure on the base substrate overlaps with the orthographic projection of the lead portion on the base substrate, and the orthographic projection of the protective structure on the base substrate is arranged to extend relative to the orthographic projection of the opposing substrate on the base substrate.

22. A display device, wherein: Comprising the display panel as claimed in claim 20 or 21.

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