Solar cell and manufacturing method therefor, and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics, and discloses a solar cell and a manufacturing method therefor, and a photovoltaic module, for use in optimizing cell efficiency of a solar cell having an amorphous silicon film layer. The solar cell comprises: a semiconductor substrate having a first surface and a second surface that are opposite to each other; a first semiconductor layer arranged on the first surface, wherein the first semiconductor layer is provided with first parts located in middle areas in the first surface and second parts located in edge areas in the first surface, and the crystallization rate of the first parts is greater than that of the second parts, wherein the edge areas surround the middle areas, and the edge areas are adjacent to edges of the first surface, and the first semiconductor layer comprises at least one of amorphous silicon and nanocrystalline silicon.

Description

Solar cell and manufacturing method thereof, and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the Patent Office of China on March 19, 2024, with application number 202410317992.4 and application name “Heterojunction solar cell and its preparation method”, the Chinese patent application filed with the Patent Office of China on July 26, 2024, with application number 202411017051.5 and application name “A solar cell and its manufacturing method, photovoltaic module”, and the Chinese patent application filed with the Patent Office of China on September 3, 2024, with application number 202411231282.6 and application name “A solar cell and its manufacturing method, photovoltaic module”, all of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0004] In solar cell structures, laser treatment of the amorphous silicon layer on the velvet surface causes the amorphous silicon layer to heat up after absorbing light, allowing hydrogen in the amorphous silicon layer to escape, increasing effective doping. Furthermore, the laser treatment can reduce the contact resistance of the solar cell, thereby reducing energy loss during current collection and improving cell efficiency. However, if the laser treatment area is not appropriate, it can lead to increased recombination in some areas of the solar cell, affecting cell efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a solar cell and a method for manufacturing the same, as well as a photovoltaic module, so as to reduce contact resistance, reduce recombination, and improve cell efficiency.

[0006] In a first aspect, the present application provides a solar cell, comprising:

[0007] a semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] A first semiconductor layer is arranged on the first surface, and the first semiconductor layer has a first portion located in the middle area of ​​the first surface and a second portion located in the edge area of ​​the first surface, the crystallization rate of the first portion is greater than the crystallization rate of the second portion; wherein the edge area surrounds the middle area, and the edge area is adjacent to the edge of the first surface, and the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

[0009] When the above technical solution is adopted, the first semiconductor layer forms a crystallized structure only in the first portion located in the middle region of the semiconductor substrate, so that the first portion has a crystallized portion and a non-crystallized portion, while the second portion of the first semiconductor layer located in the edge region of the semiconductor substrate is not crystallized, retaining the original amorphous structure, so that the overall crystallization rate of the first portion of the first semiconductor layer is greater than the overall crystallization rate of the second portion. The crystallized structure in the first portion is formed by laser irradiation. Due to the non-uniformity of the laser beam across the entire width and the non-uniform thickness of the first semiconductor layer, when the laser is applied to the edge of the semiconductor substrate, the laser damages the passivation of the first semiconductor layer at the edge, thereby increasing the recombination at the edge. Therefore, the present application does not form a crystallized structure at the edge by laser, retains the amorphous structure at the edge of the first semiconductor layer, and reserves the second portion of the edge, thereby ensuring the passivation effect of the second portion at the edge and reducing the recombination at the edge. The middle region of the first semiconductor layer is the first portion with a relatively high crystallization rate, which reduces the contact resistance. Therefore, by setting a reasonable area with a crystallized structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0010] In a second aspect, the present application further provides a photovoltaic assembly, comprising a solar cell, wherein the solar cell is any one of the solar cells described above.

[0011] Since the photovoltaic module adopts the solar cell of the first aspect and any one of the above items, the photovoltaic module has the same beneficial effects as the first aspect, which will not be described in detail here.

[0012] In a third aspect, the present application further provides a method for manufacturing a solar cell, comprising:

[0013] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other;

[0014] forming a first semiconductor layer on the first surface, wherein the first semiconductor layer has a middle portion located in a middle region of the first semiconductor layer and an edge portion located in a peripheral region of the middle portion;

[0015] The middle portion is irradiated with laser so that the crystallization rate of the middle portion is greater than that of the edge portion; wherein the edge portion surrounds the middle portion, and the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

[0016] When the above technical solution is adopted, the middle part of the middle region of the first semiconductor layer is crystallized by laser, so that the crystallization rate is improved, while the edge part of the first semiconductor layer located in the peripheral area of ​​the middle part is not irradiated with laser, and the amorphous structure is retained. Due to the unevenness of the full width of the laser and the uneven thickness of the first semiconductor layer, when the laser acts on the edge part of the first semiconductor layer, the laser will damage the passivation of the edge part, thereby increasing the recombination of the edge part. Therefore, the present application does not form a crystallized structure at the edge part by laser, and retains the amorphous structure of the edge part of the first semiconductor layer, thereby ensuring the passivation effect at the edge part and reducing the recombination of the edge. In addition, the middle part is formed by laser crystallization in the middle region of the first semiconductor layer, which reduces the contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved. When the first semiconductor layer includes an amorphous silicon layer and / or a nanocrystalline silicon layer, the crystallization rate can be improved by laser irradiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] FIG1 is a schematic structural diagram of a solar cell provided in an embodiment of the present application, wherein the first side does not include an electrode;

[0019] FIG2 is a schematic structural diagram of a first surface of a solar cell including an electrode provided in an embodiment of the present application;

[0020] FIG3 is a partial enlarged schematic diagram of FIG2 ;

[0021] FIG4 is a schematic diagram of a partial arrangement of a transparent conductive layer on a first surface of a solar cell provided in an embodiment of the present application;

[0022] FIG5 is a schematic cross-sectional view of section AA in FIG4 ;

[0023] FIG6 is a schematic cross-sectional view of the BB section in FIG4 ;

[0024] FIG7 is a partial enlarged schematic diagram of FIG2;

[0025] 8 to 19 are schematic flow charts of the steps of a method for manufacturing a solar cell provided in an embodiment of the present application;

[0026] FIG20 is a schematic diagram showing a comparison of EL test images of a solar cell provided by an embodiment of the present application and a conventional solar cell with an amorphous region;

[0027] FIG21 is a schematic diagram showing a comparison of the contact resistance of the P region of a solar cell provided by an embodiment of the present application and a conventional solar cell without a crystallization region;

[0028] FIG22 is a schematic diagram of crystallization of the top of a pyramid provided in an embodiment of the present application;

[0029] FIG23 schematically shows a structure diagram of a crystallized amorphous silicon film layer according to an embodiment of the present application;

[0030] FIG24A schematically shows a test bitmap of crystallizing regions 1 to 7 on the front side using a Raman spectrometer according to an embodiment of the present application;

[0031] FIG24B schematically shows a Raman spectrum corresponding to test areas 1 to 7 according to an embodiment of the present application.

[0032] Reference numerals: 100 is a first semiconductor layer, 1 is a first strip portion, 11 is a first portion, 12 is a second portion, 13 is an intrinsic amorphous silicon layer, 14 is a p-type amorphous silicon layer, 15 is an overlapping portion, 2 is a second semiconductor layer, 21 is a tunneling oxide layer, 22 is an n-type doped polysilicon layer, 3 is an edge isolation region, 4 is a first gate electrode, 5 is a second gate electrode, 6 is a semiconductor substrate, 7 is a transparent conductive layer, 71 is a first transparent conductive layer, 72 is a second transparent conductive layer, 73 is a third transparent conductive layer, 8 is a passivation layer, 9 is an anti-reflection layer, and 10 is a PN isolation region;

[0033] 30 is an amorphous silicon film layer, 31 is an N-type doped amorphous silicon film layer, 40 is a microcrystalline silicon film layer, 110 is a first region, 120 is a second region, and 70 is a doped layer. DETAILED DESCRIPTION

[0034] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0035] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0037] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0039] As shown in Figures 1-7, an embodiment of the present application provides a solar cell comprising a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has a first and second opposing surfaces. The first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 comprises a first portion 11 located in the middle region of the first surface and a second portion 12 located in the edge region of the first surface. The crystallization rate of the first portion 11 is greater than that of the second portion 12. The edge region surrounds the middle region and is immediately adjacent to the edge of the first surface. The projected area of ​​the middle region on the first surface accounts for more than 90% of the area of ​​the first surface, and the edge region has a generally rectangular ring-shaped structure. The first semiconductor layer 100 comprises at least one of amorphous silicon and nanocrystalline silicon. That is, the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon. The crystallization rate of each of the amorphous silicon and nanocrystalline silicon layers can be improved after laser crystallization. For example, if the first semiconductor layer 100 is an amorphous silicon layer, after laser crystallization, the amorphous silicon layer will partially crystallize to form nanocrystalline grains. When the first semiconductor layer 100 is nanocrystalline silicon, or a combination of amorphous silicon and nanocrystalline silicon, the crystallinity or crystallization rate of the first semiconductor layer 100 may increase after laser crystallization.

[0040] In actual applications, the present embodiment does not specifically limit the material and conductivity type of the semiconductor substrate 6. For example, the semiconductor substrate 6 may be a silicon substrate. Alternatively, the semiconductor substrate 6 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0041] Secondly, the first surface of the semiconductor substrate 6 corresponds to the backlight side of the solar cell, and the second surface of the semiconductor substrate 6 corresponds to the light-facing side of the solar cell, ie, the front side.

[0042] When adopting the above technical solution, the first semiconductor layer 100 forms a crystallized structure only in the first part 11 located in the middle area of ​​the semiconductor substrate 6, so that the first part 11 has a crystallized part and another non-crystallized part. In other words, the first part 11 is not entirely a crystallized structure, but most of it is an amorphous structure, and only a part forms a crystallized structure, such as nanocrystal, while the second part 12 of the first semiconductor layer 100 located in the edge area of ​​the semiconductor substrate 6 is not crystallized and retains the original amorphous structure (it should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon, the crystallization rate or crystallinity of the nanocrystalline silicon in the second part 12 remains unchanged), so that the overall crystallization rate of the first part 11 of the first semiconductor layer 100 is greater than the overall crystallization rate of the second part 12. The crystallized structure in the first portion 11 is formed by laser irradiation. Due to the non-uniformity of the laser across the entire width and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge of the semiconductor substrate 6, the laser will damage the passivation of the first semiconductor layer 100 at the edge, thereby increasing the recombination at the edge. Therefore, the present application does not form a crystallized structure at the edge of the first semiconductor layer 100 by laser, but retains the amorphous structure at the edge of the first semiconductor layer 100, reserving the second portion 12 at the edge, thereby ensuring the passivation effect of the second portion 12 at the edge and reducing the recombination at the edge, and forming the first portion 11 with a crystallized structure in the middle region of the first semiconductor layer 100. The crystallized structure in the first portion 11 reduces the contact resistance. At the same time, the amorphous structure in the first portion 11 has a good passivation effect. Therefore, by setting reasonable crystallized and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized, thereby improving the cell efficiency.

[0043] It can be understood that when at least a portion of the first surface of the semiconductor substrate 6 is a velvet surface, a plurality of pyramid-like layers are formed on the velvet surface. As shown in FIG22 , the first semiconductor layer 100 is conformally arranged on the velvet surface, and the degree of crystallization of the portion of the first semiconductor layer 100 covering at least a portion of the top of the pyramid-like layer is greater than the degree of crystallization of the other portion of the first semiconductor layer 100 covering the base of the pyramid-like layer. In the process of observing the degree of crystallization of the first semiconductor layer 100, if the observed area is too small, for example, only the base area of ​​the pyramid-like layer is observed, the degree of crystallization of the first semiconductor layer 100 cannot be accurately obtained. Therefore, the observed area should contain at least one pyramid-like layer. Preferably, the observed area should be greater than or equal to 5*5μm. 2 This is to prevent the inability to accurately obtain the crystallization degree of the first semiconductor layer 100 by only observing the pyramid-like base region.

[0044] In some possible implementations, the contact resistance of the first portion 11 is lower than the contact resistance of the second portion 12. Since the first portion 11 has a crystalline structure or a higher crystallinity, and the second portion 12 has an amorphous structure or a lower crystallinity, the effective doping of the first portion 11 is increased, which can reduce the contact resistance of the first portion 11 compared to the second portion 12, thereby reducing the energy loss during the current collection process of the first portion 11 and improving the battery efficiency. For example, as shown in FIG21, when the first semiconductor layer 100 is disposed in the P region, by comparing the P region contact resistance of a cell without a crystallization region and a cell with a crystallization region, it can be seen that the overall contact resistance of a solar cell having the first semiconductor layer 100 with the first portion 11 is lower than the overall contact resistance of a solar cell having the first semiconductor layer 100 without the first portion 11.

[0045] This embodiment provides a solar cell, wherein a first semiconductor layer 100 entirely covers the first surface, wherein the first portion 11 is rectangular and the second portion 12 is annular. Specifically, the first semiconductor layer 100 is a continuous, single-surface structure covering the entire first surface and is generally rectangular in shape. The first portion 11 located in the middle region is correspondingly rectangular, and the second portion 12 located in the edge region is correspondingly rectangular and annular. The first semiconductor layer 100 can form one side of a bifacial solar cell, serving as either a P region or an N region. Because the first semiconductor layer 100 comprises amorphous silicon and / or nanocrystalline silicon, it can form a heterojunction structure.

[0046] On this basis, a third semiconductor layer having a conductivity type opposite to that of the first semiconductor layer 100 is provided on the second surface. The third semiconductor layer includes a polycrystalline silicon layer or an amorphous silicon layer. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer may also form a heterojunction structure. The structure of the third semiconductor layer may be similar to that of the first semiconductor layer 100, and may also include a first portion and a second portion, with the crystallization rate of the first portion being greater than the crystallization rate of the second portion.

[0047] In one example, the conductivity type of the first semiconductor layer is P-type and the conductivity type of the third semiconductor layer is N-type. The first semiconductor layer includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate to the first surface. The third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, with the third intrinsic amorphous silicon layer disposed proximate to the second surface, thereby forming a bifacial heterojunction cell. Of course, the conductivity type of the first semiconductor layer can also be N-type, and the conductivity type of the third semiconductor layer can be P-type, which will not be further described.

[0048] In another example, a polysilicon layer is disposed on the second surface, and the third semiconductor layer can form a tunneling passivation contact structure. Specifically, the first semiconductor layer has a P-type conductivity type, and the third semiconductor layer has an N-type conductivity type. The first semiconductor layer comprises a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate the first surface. The third semiconductor layer comprises an N-type doped polysilicon layer disposed on the second surface, with a tunneling oxide layer disposed between the N-type doped polysilicon layer and the second surface. The tunneling oxide layer and the N-type doped polysilicon layer form the tunneling passivation contact structure. The third semiconductor layer can be disposed locally on the second surface, for example, in the form of multiple strips, forming a poly-finger structure. Doped fields can be selectively formed on the substrate between the poly-finger strips. Alternatively, the third semiconductor layer can be formed entirely on the second surface, with thicker portions in the metallized contact areas and thinner portions in the non-metallized areas. The first semiconductor layer can have a heterojunction structure, forming a bifacial hybrid solar cell. Of course, the conductivity type of the first semiconductor layer may be N-type, and the conductivity type of the third semiconductor layer may be P-type, which will not be described in detail.

[0049] As long as they have an amorphous silicon layer and / or a nanocrystalline silicon layer, bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to the cell structure in this application where the edges are amorphous and the middle area is crystalline to improve cell efficiency.

[0050] As shown in FIG1 , this embodiment provides another solar cell, which further includes a second semiconductor layer 2 disposed on a first surface. The first semiconductor layer 100 includes a plurality of first strip-shaped portions 1 extending along a first direction, and the second semiconductor layer 2 includes a plurality of second strip-shaped portions extending along the first direction. The first strip-shaped portions 1 and the second strip-shaped portions are alternately arranged along the second direction. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the first and second directions intersect. In the case where the first semiconductor layer 100 is disposed on the first surface, to achieve the arrangement of P and N regions on the first surface, the first semiconductor layer 100 is one of a P region and an N region, and the second semiconductor layer 2 is the other of the P and N regions. With respect to the strip-shaped first strip-shaped portions 1, the first portion 11 is located in the middle region of the first strip-shaped portions 1 in the direction of extension, and the second portion 12 is located at the edge regions at both ends of the direction of extension, thereby achieving the arrangement of an amorphous structure at the edges of the first semiconductor layer 100.

[0051] As shown in Figures 6 and 7, in some embodiments, for the strip-shaped first strip portion 1, the first portion 11 includes a strip-shaped middle portion extending along the first direction and strip-shaped edge portions disposed on both sides of the middle portion along the second direction. The middle portion and the edge portions may have the same length along the first direction, wherein the crystallization rate of the middle portion is greater than that of the edge portions, and the crystallization rate of the edge portions may be the same as that of the second portion 12. That is, along the second direction, the first portion 11 is further divided into the middle portion and the edge portions, and the entire second portion 12 has an amorphous structure. In the second direction, not all areas of the first portion 11 undergo crystallization, but only the middle portion undergoes crystallization. Both sides of the middle portion and the second portion 12 have an amorphous structure and do not undergo laser crystallization. Because the first portion 11 has a crystallized structure and the second portion 12 has an amorphous structure, the overall crystallization rate of the middle portion is greater than that of the edge portion and the second portion 12. Such arrangement ensures that the middle portion with a relatively high crystallinity rate does not include the overlapping portion 15 where the first strip portion 1 is overlapped on the second strip portion, so that the first strip portion 1 and the second strip portion of different conductive types have better insulation in the overlapping portion 15, thereby reducing leakage.

[0052] Furthermore, in this embodiment, the width of the edge portion on one side of the middle portion of the first strip portion 1 along the second direction is less than or equal to 100 μm. This configuration minimizes the width of the edge portion to increase the area of ​​the middle portion, thereby reducing contact resistance and improving current collection capability.

[0053] As shown in FIG1 , in some possible implementations, along the second direction, the crystallization rate of at least one first strip portion 1 near the edge of the first surface is the same as the crystallization rate of the second portion 12. With this arrangement, for the strip-shaped first strip portions 1, multiple first strip portions 1 are arranged along the second direction. In the arrangement direction, the entire area of ​​at least one first strip portion 1 near the edge of the first surface has the same crystallization rate as the second portion 12. That is, at least one first strip portion 1 near the edge is not laser crystallized, while the remaining first strip portions 1 form amorphized second portions 12 only at the two end edges in the extension direction, thereby achieving the configuration of an edge amorphous structure of the first semiconductor layer 100.

[0054] For example, in the second direction, the crystallization rate of the entire area of ​​the two strip-shaped portions 1 respectively located on the two edges of the first surface is the same as the crystallization rate of the second portion 12, or two, three or more first strip-shaped portions 1 having the same crystallization rate as the second portion 12 are reserved near the edge of each first surface.

[0055] In some embodiments, the width of the second portion 12, along the direction from the first portion 11 to the second portion 12 and perpendicular to the side length of the semiconductor substrate 6, is 0.3 mm to 12 mm. This means that a 0.3 mm to 12 mm edge region around the first semiconductor layer 100 of the semiconductor substrate 6 is reserved and not subjected to laser crystallization. If the width of the second portion 12 is too wide, the area of ​​the first portion 11 of the solar cell with the crystallized structure is small, resulting in less reduction in series resistance and greater current collection losses. If the width of the second portion 12 is too small, the edges of the first semiconductor layer 100 may be thinner due to limitations in the coating process. Furthermore, the laser irradiation angle at the edge of the solar cell may be too large, resulting in a deviation in the energy distribution within the laser spot. This can easily lead to excessive laser energy density in some areas, potentially damaging the passivation of the first semiconductor layer 100 at the edge. Therefore, to reduce the overall contact resistance of the solar cell and minimize damage to the passivation, the width of the second portion 12 is selected to be 0.3 mm to 12 mm.

[0056] Furthermore, the width of the second portion 12 is 0.3 mm to 3 mm. This further increases the area of ​​the first portion 11 of the first semiconductor layer 100, reduces contact resistance, and improves battery efficiency. Specifically, the width of the second portion 12 can be 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, etc.

[0057] For example, for the first semiconductor layer 100 including the plurality of first strip-shaped portions 1, along the extension direction (first direction) of the first strip-shaped portions 1, the extension lengths of the second portions 12 at both end edges of the first strip-shaped portions 1 are 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (second direction) of the plurality of first strip-shaped portions 1, the crystallization rates of the two first strip-shaped portions 1 near the two side edges of the first surface are the same as the crystallization rate of the second portions 12.

[0058] In some embodiments, when the first side of a solar cell comprises a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 may comprise amorphous silicon and / or nanocrystalline silicon. The second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, except for a different conductivity type. Specifically, the second semiconductor layer 2 also comprises a first portion located in the middle region of the first side and a second portion located in the edge region of the first side. The first portion of the second semiconductor layer 2 may or may not be entirely laser crystallized. For details, refer to the above description of the first portion 11 of the first semiconductor layer 100 and are not further elaborated here.

[0059] For example, taking the case where the first semiconductor layer corresponds to the P region and the second semiconductor layer corresponds to the N region, the first semiconductor layer may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked together, and the second semiconductor layer may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked together, with both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer being disposed proximate to the semiconductor substrate. Of course, the conductivity types of the first semiconductor layer and the second semiconductor layer may be interchangeable, which will not be further described.

[0060] With this arrangement, the first and second semiconductor layers of different conductivity types disposed on the first surface can both form a heterojunction structure, resulting in a heterojunction back-contact cell with both a P-region heterojunction structure and an N-region heterojunction structure on the back side. This cell has the advantages of a heterojunction structure with good passivation, high conversion efficiency, long service life, and low energy consumption. As long as it has an amorphous silicon layer and / or a nanocrystalline silicon layer, the heterojunction back-contact cell can also be applied to the cell structure described in this application, which has an amorphous structure at the edge and a crystalline structure in the middle region, to improve cell efficiency.

[0061] As shown in Figures 1 to 7, in some embodiments, when the first surface of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed, and the second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.

[0062] For example, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface, wherein the tunneling oxide layer 21 is disposed close to the semiconductor substrate 6. For example, when the second semiconductor layer 2 corresponds to the N region and the first semiconductor layer 100 corresponds to the P region, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22. The first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface, wherein the intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P region and the first semiconductor layer 100 corresponds to the N region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0063] In this way, by arranging a second semiconductor layer 2 and a first semiconductor layer 100 of different conductivity types on the first surface, a hybrid back contact cell having both a tunneling passivation contact structure and a heterojunction structure on the back is formed, wherein the first semiconductor layer 100 is a heterojunction structure. The cell has the advantages of high conversion efficiency, good stability, and low Auger recombination of the tunneling passivation contact structure and good passivation effect, high conversion efficiency, long service life, and low energy consumption for preparation of the heterojunction structure. As long as it has an amorphous silicon layer and / or a nanocrystalline silicon layer, the hybrid back contact cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle area is a crystalline structure in the present application to improve the cell efficiency. Of course, when the second semiconductor layer 2 is other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, a back contact cell with different structures in the P region and N region can be formed.

[0064] As shown in Figures 1 and 4 to 7, in some possible implementations, the first strip portion 1 has an overlapping portion 15 that overlaps the second strip portion, and the first portion 11 does not include the overlapping portion 15; and / or, the solar cell further includes a first transparent conductive layer 71 that covers a portion of the first portion 11, and the projection of the middle portion of the first portion 11 on the first transparent conductive layer 71 is at least located within the boundary of the first transparent conductive layer 71. In this manner, by providing the first transparent conductive layer 71, the carrier transport capability of the first semiconductor layer 100 is improved, and a good ohmic contact can be formed with the electrode, thereby improving the conductive performance. The middle portion having a crystallized structure does not exceed the boundary of the first transparent conductive layer 71, thereby reducing the contact resistance within the effective conductive area of ​​the first transparent conductive layer 71, improving the conductive performance, and improving the battery efficiency.

[0065] As shown in Figures 5 to 7, further, in some embodiments, the solar cell also includes a second transparent conductive layer 72 and a third transparent conductive layer 73, the second transparent conductive layer 72 covers part of the overlapping portion 15 and part of the second strip portion; the third transparent conductive layer 73 covers part of the second portion 12, mainly covering the position of the second portion 12 close to the edge of the semiconductor substrate 6; wherein, a PN isolation region 10 is provided between the adjacent first transparent conductive layer 71 and the second transparent conductive layer 72; and an edge isolation region 3 is provided between the first transparent conductive layer 71 and the third transparent conductive layer 73 and between the second transparent conductive layer 72 and the third transparent conductive layer 73.

[0066] When using the above technical solution, electrical insulation between the P and N regions is achieved through the PN isolation region 10, and electrical insulation between the PN region located in the middle region and the dead zone located in the edge region is achieved through the edge isolation region. It should be noted that the dead zone may include a stack of a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is stacked on the second semiconductor layer. The first semiconductor layer located in the dead zone belongs to the edge region of the second portion, and the third transparent conductive layer 73 is disposed on the first semiconductor layer located in the dead zone. The projection of the middle portion of the first strip-shaped portion is located within the boundary of the first transparent conductive layer. Therefore, the middle portion does not enter the boundary of the edge isolation region and / or the boundary of the PN isolation region. The irradiation range of the laser does not enter the edge isolation region and the PN isolation region. Since the isolation region does not have a crystalline structure or has a low crystallization rate, the electrical insulation effect of the isolation region is guaranteed.

[0067] For example, as shown in Figures 6 and 7, the first semiconductor layer 100 has an overlapping portion 15 that overlaps the second semiconductor layer 2 in the second direction. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polycrystalline silicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form the overlapping portion 15. In this case, the PN isolation region 10 spans a portion of the overlapping portion 15 and a portion of the non-overlapping portion of the first semiconductor layer 100. As shown in Figure 5, the edge isolation region 3 spans a portion of the stack of the first semiconductor layer 100 and the second semiconductor layer 2 and a portion of the second portion 12, specifically, spans the sidewalls and a portion of the bottom wall of the recessed portion of the semiconductor substrate.

[0068] Based on the PN isolation region 10 and the edge isolation region 3, along the second direction, as shown in FIG6 , the distance between the boundary of the middle portion (i.e., the crystallized region) of the first semiconductor layer 100 and the boundary of the PN isolation region 10 is greater than or equal to zero; and / or, as shown in FIG5 , along the first direction and / or the second direction, the distance between the boundary of the middle portion (i.e., the crystallized region) of the first portion 11 of the first semiconductor layer 100 and the boundary of the edge isolation region 3 is greater than or equal to zero. In other words, the middle portion does not enter the boundary of the edge isolation region 3 and / or the boundary of the PN isolation region 10, and the laser irradiation range does not enter the edge isolation region 3 and the PN isolation region 10. Because the first semiconductor layer 100 within the edge isolation region 3 and the PN isolation region 10 still has an amorphous structure or a low crystallization rate, the electrical insulation effect of the edge isolation region 3 and the PN isolation region 10 is ensured.

[0069] As shown in Figures 5 to 7 , the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 can further be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layer can be a single-layer film or a laminated film.

[0070] As shown in Figure 20, in this embodiment, the EL (electroluminescent) test of a solar cell is a method for detecting internal defects in solar cells. In the image obtained by the EL test, the brightness of the first portion 11, which has a relatively high crystallinity, is greater than that of the second portion 12, which has a relatively low crystallinity. Under the same conditions, the brightness of the first portion 11 in the EL test image is greater than that of the second portion 12, indicating that the contact resistance of the first portion 11 is lower than that of the second portion 12. When the solar cell is powered on for testing, the electroluminescent brightness of the first portion 11, which has a lower contact resistance, is higher, while the electroluminescent brightness of the second portion 12 is lower. The image of solar cell B in Figure 20 shows that solar cell B has a first portion 11 in the middle region and a second portion 12 in the edge region. The brightness of the first portion 11 in the middle region is higher than that of the second portion 12 in the edge region. A comparison with the image of solar cell C shows that solar cell C does not have the first portion 11 in the middle region. Therefore, the brightness of solar cell C is uniform across its entire surface and is lower overall than that of solar cell B, indicating that solar cell C has a higher overall contact resistance.

[0071] As shown in Figures 2 and 3, in some possible implementations, the solar cell further includes a first gateline electrode 4 extending along a first direction. The first gateline electrode 4 is conductively disposed on the first portion 11 of the first semiconductor layer 100 and extends from the first portion 11 to the second portion 12, specifically from the middle portion of the first portion 11 to the second portion 12. The first gateline electrode 4 does not extend into the edge isolation region 3. The extension direction of the first gateline electrode 4 is consistent with the extension direction of the first strip portion 1, and the first gateline electrode 4 is capable of collecting carriers from both the first portion 11 and a portion of the second portion 12 on the same first semiconductor layer 100. Therefore, the carrier collection capability of the first gateline electrode 4 for the first semiconductor layer 100 can be improved.

[0072] For a solar cell having a second semiconductor layer 2, the solar cell further includes a second gate electrode 5 conductively disposed on the second semiconductor layer 2. The second gate electrode 5 extends along a first direction, which is consistent with the extension direction of the second semiconductor layer 2. In the case of a first transparent conductive layer 71 and a second transparent conductive layer 72, the first gate electrode 4 is disposed on the first transparent conductive layer 71, and the second gate electrode 5 is disposed on the second transparent conductive layer 72.

[0073] In some embodiments, the side of the semiconductor substrate on which the amorphous semiconductor layer is provided has a velvet structure, the amorphous semiconductor layer is conformal to the velvet structure, the velvet structure has a light trapping effect, increases the collection of light, and the velvet structure can achieve better contact with the electrode. When the first part of the first semiconductor layer is laser crystallized, the laser is irradiated on the velvet structure of the first part, and the crystallization temperature can be reached, so that a local area of ​​the first part forms a crystallized microcrystalline structure or nanocrystalline structure. In this way, the crystallized area has both an amorphous structure and a crystallized structure. The crystallized structure reduces the contact resistance, but reduces the passivation effect, and the recombination may increase, which is not conducive to the photoelectric efficiency. Therefore, by forming a crystallized structure in a local area of ​​a part of the velvet structure, the two factors of contact resistance and passivation effect can be balanced, so that the battery efficiency is optimized.

[0074] This embodiment describes the structure of a solar cell only from the perspective of the first semiconductor layer. Also using Figures 1-7 as examples, the solar cell includes a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has a first and second opposing surfaces. The first semiconductor layer 100 is disposed on the first surface. The first semiconductor layer 100 includes a middle portion located in its central region and an edge portion located in a region surrounding the middle portion. The middle portion includes amorphous silicon and nanocrystalline silicon, and the edge portion is amorphous silicon. The edge portion surrounds the middle portion. It should be noted that the edge portion here does not refer to the edge of the semiconductor substrate 6. There is a certain distance between the edge portion of the first semiconductor layer 100 and the edge of the semiconductor substrate 6.

[0075] Because a crystallized structure is formed only in the middle portion of the middle region of the first semiconductor layer, the middle portion contains nanocrystalline silicon and amorphous silicon, while the edge portion of the first semiconductor layer located in the peripheral region of the middle portion is not crystallized, retaining the original amorphous silicon. This results in a higher overall crystallization rate in the middle portion of the first semiconductor layer than in the edge portion. The nanocrystalline silicon in the middle portion is formed by laser irradiation of amorphous silicon. Due to the unevenness of the laser beam across the entire width and the uneven thickness of the first semiconductor layer, when the laser beam acts on the edge portion of the first semiconductor layer, the laser beam damages the passivation of the edge portion of the first semiconductor layer, thereby increasing recombination at the edge. Therefore, the present application does not form nanocrystalline silicon in the edge portion by laser beam, retaining the amorphous silicon at the edge portion of the first semiconductor layer. This ensures the passivation effect of the edge portion near the edge of the semiconductor substrate, reduces recombination at the edge portion, and the crystallization rate in the middle portion of the first semiconductor layer is relatively high, thereby reducing contact resistance. Therefore, by providing a reasonable region with a crystallized structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and improved.

[0076] In some embodiments, the first semiconductor layer is entirely covered on the first surface, and the edge portion is annular in shape between the middle portion and the edge of the first surface. In this configuration, the entire first surface of the solar cell is covered with the first semiconductor layer, forming one side of a bifacial solar cell, which can serve as a P region or an N region, and the first semiconductor layer on this side can form a heterojunction structure. As long as the bifacial solar cell has the first semiconductor layer described in this application, it can also be applied to the cell structure described in this application in which the edge is amorphous silicon and the middle portion has amorphous silicon and nanocrystalline silicon to improve cell efficiency.

[0077] In some possible implementations, the solar cell further includes a third semiconductor layer disposed on the second surface, the third semiconductor layer comprising at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. This configuration forms a bifacial solar cell. The semiconductor layers on the first and second surfaces can be the same or different. As long as the bifacial cell has the first semiconductor layer described in this application, it is suitable for the cell structure described in this application in which the edge portion is amorphous silicon and the middle portion is composed of amorphous silicon and nanocrystalline silicon, thereby improving cell efficiency.

[0078] Taking the structures shown in Figures 1, 2 and 7 as an example, in some embodiments, when a first semiconductor layer 100 is provided on the first surface, the solar cell also includes a second semiconductor layer 2 provided on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are both in the shape of long strips extending along the first direction and are adjacent to each other along the second direction. The first semiconductor layer 100 includes an overlapping portion 15 stacked on the second semiconductor layer 2; the first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, the first direction and the second direction intersect, and the middle portion does not include the overlapping portion 15.

[0079] When adopting the above technical solution, the first semiconductor layer 100 and the second semiconductor layer 2 in a long strip shape are adjacent to each other along the second direction. The first semiconductor layer 100 includes an overlapping portion 15 stacked on the second semiconductor layer 2, and the middle portion having amorphous silicon and nanocrystalline silicon does not include the overlapping portion 15, that is, the overlapping portion 15 is amorphous silicon. Therefore, the first semiconductor layer 100 and the second semiconductor layer 2 of different conductive types have better insulation in the overlapping portion 15, thereby reducing leakage.

[0080] As shown in Figures 4 and 6, in some possible implementations, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, with the projection of the middle portion on the semiconductor substrate 6 completely located within the projection of the first transparent conductive layer 71 on the semiconductor substrate 6. With this arrangement, the first transparent conductive layer 71 improves the carrier transport capability of the first semiconductor layer 100, enabling good ohmic contact with the electrode and improved conductivity. Furthermore, the middle portion of the amorphous silicon and nanocrystalline silicon does not extend beyond the boundaries of the first transparent conductive layer 71, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer 71, improving conductivity, and enhancing cell efficiency.

[0081] As shown in Figures 5 and 6, in some embodiments, the semiconductor substrate 6 includes a recessed portion on the first surface, the recessed portion including sidewalls and a bottom wall. The recessed portion is recessed relative to the remainder of the first surface toward the second surface, with the central portion located within the recessed portion. In this configuration, the recessed portion is formed by etching into the surface of the semiconductor substrate 6 and typically has a textured surface. Positioning the central portion comprising amorphous silicon and nanocrystalline silicon within the recessed portion increases the contact area of ​​the central portion, facilitating current collection.

[0082] As shown in Figures 5 and 6, in some possible implementations, a first spacing L1 is defined between the boundary of the middle portion and the boundary of the first semiconductor layer 100 along a first direction; and a second spacing L2 is defined between the boundary of the middle portion and the boundary of the first semiconductor layer 100 along a second direction; wherein the first spacing L1 is greater than the second spacing L2. Because the portion of the first semiconductor layer 100 near the edge of the semiconductor substrate 6 has large defects, poor passivation, large leakage current, and severe recombination, the first spacing L1 between the middle portion and the boundary of the first semiconductor layer 100 is set larger to avoid edge defects, while the second spacing L2 is not close to the edge of the semiconductor substrate 6. Therefore, as long as the middle portion comprising amorphous silicon and nanocrystalline silicon does not include an overlapping portion, the second spacing L2 can be reduced as much as possible to increase the area of ​​the middle portion, thereby reducing contact resistance and improving current collection capability.

[0083] In some possible implementations, the first spacing L1 is 0.2 mm to 12 mm, and / or the second spacing L2 is less than or equal to 100 μm. If the width of the first spacing L1 is too wide, the middle portion of the solar cell as a whole is smaller, the reduction in series resistance is small, and the loss during current collection is large; if the width of the first spacing L1 is too small, the defects closer to the edge are larger, the passivation effect is poor, the recombination is larger, and the leakage current is large. Therefore, considering the reduction of the overall contact resistance of the solar cell and avoiding edge defects, the first spacing L1 is selected to be 0.2 mm to 12 mm. If the second spacing L2 is too large, the middle portion is smaller and the current collection loss is large. Therefore, the second spacing L2 is less than or equal to 100 μm.

[0084] As shown in Figures 2 and 3, in some possible implementations, the solar cell further includes a first gateline electrode 4 disposed on the first semiconductor layer 100 and extending along a first direction. The first gateline electrode 4 extends from above the middle portion to above the edge portion. The extension direction of the first gateline electrode 4 is consistent with the extension direction of the first semiconductor layer 100, and the first gateline electrode 4 can collect carriers from both the middle portion and the edge portion. Therefore, the carrier collection capability of the first gateline electrode 4 for the first semiconductor layer 100 can be improved.

[0085] Furthermore, in this embodiment, along the second direction, the ratio of the width of the first gate electrode 4 to the width of the middle portion is 10% to 120%, and specifically can be 10%, 30%, 50%, 80%, 100%, 120%, etc. The ratio of the width of the first gate electrode 4 to the width of the middle portion is selected based on the material and carrier transport capability of the first semiconductor layer 100. If the carrier transport capability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be increased to increase the contact area between the first gate electrode 4 and the middle portion and reduce the contact resistance. Conversely, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be reduced to save electrode material while still meeting current collection requirements.

[0086] For example, the width of the first gateline electrode 4 can be 30 μm to 600 μm. Specifically, when the first gateline electrode 4 is fabricated using a screen printing process, the width of the first gateline electrode 4 is 30 μm to 80 μm. When the first gateline electrode 4 is fabricated using a deposition method such as electroplating, the width of the first gateline electrode 4 is 100 μm to 600 μm. The width of the middle portion is 200 μm to 700 μm. The appropriate width of the first gateline electrode 4 is selected based on the width of the middle portion and the electrode fabrication process.

[0087] Furthermore, when the solar cell includes a first transparent conductive layer 71, the first gateline electrode 4 extends along a first direction and is disposed on the first transparent conductive layer 71. Along the second direction, the width of the first gateline electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion. For example, the width of the first transparent conductive layer 71 is 120 μm to 800 μm, the width of the middle portion is 200 μm to 700 μm, and the ratio of the width of the first transparent conductive layer 71 to the middle portion is 1.2 to 1.5. The width of the first transparent conductive layer 71 is selected appropriately based on the width of the middle portion. The width of the first gateline electrode 4 is also selected appropriately based on the widths of the middle portion, the first transparent conductive layer 71, and the electrode fabrication process. With this arrangement, the first gateline electrode 4 can be positioned directly opposite the middle portion, with the width of the first transparent conductive layer 71 greater than the width of the middle portion, thereby improving current collection capability.

[0088] Based on the solar cell described in any of the above embodiments, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell described in any of the above embodiments.

[0089] Since the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the above solar cell, which will not be described in detail here.

[0090] The present application also provides a method for manufacturing a solar cell. The method can be used to manufacture the solar cell described in Figures 1 to 7 and any of the above embodiments. The method comprises the following steps:

[0091] In step S100 , a semiconductor substrate 6 is provided. The semiconductor substrate 6 has a first surface and a second surface opposite to each other.

[0092] In step S200 , a first semiconductor layer 100 is formed on the first surface of the semiconductor substrate 6 . The first semiconductor layer 100 has a middle portion located in its middle region and an edge portion located in a peripheral region of the middle portion.

[0093] In step S300 , the middle portion is irradiated with laser light so that the crystallization rate of the middle portion is greater than that of the edge portion; wherein the edge portion surrounds the middle portion, and the first semiconductor layer 100 includes at least one of amorphous silicon and nanocrystalline silicon.

[0094] When adopting the above technical solution, the middle part of the middle area of ​​the first semiconductor layer 100 is crystallized by laser, so that the crystallization rate is improved, while the edge part of the first semiconductor layer 100 located in the peripheral area of ​​the middle part is not irradiated with laser, and the amorphous structure is retained. Due to the unevenness of the entire laser width and the uneven thickness of the first semiconductor layer 100, when the laser acts on the edge part of the first semiconductor layer 100, the laser will damage the passivation of the edge part, thereby increasing the recombination of the edge part. Therefore, the present application does not form a crystallized structure at the edge part by laser, and retains the amorphous structure of the edge part of the first semiconductor layer 100, thereby ensuring the passivation effect at the edge part and reducing the recombination of the edge part. In addition, the middle part of the first semiconductor layer 100 is laser crystallized to form a crystallized structure, thereby reducing the contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0095] Furthermore, the first surface has a first side and a second side arranged opposite to each other along a first direction. Then, irradiating the middle portion with laser light in step S300 specifically includes the following steps:

[0096] In step S301 , laser irradiation is started at a position at a first distance from a first side, passes through a middle portion along a first direction, and stops at a position at a second distance from a second side.

[0097] When using the above technical solution, the laser irradiates the first semiconductor layer along the direction from the first side to the second side. The starting point of the middle portion of the irradiation is a first distance from the first side, and the ending point of the irradiation is a second distance from the second side. Only the middle portion of the first semiconductor layer is irradiated, and the laser irradiation is stopped at the edges on both sides of the middle portion. The irradiation can be repeated multiple times along the first direction so that the entire range of the middle portion perpendicular to the first direction is irradiated by the laser. In the width direction of the first semiconductor layer, a gap is left between the irradiation area of ​​the first semiconductor layer and the width boundary of the first semiconductor layer. This ensures that the formed middle portion does not enter the PN isolation region used to isolate the P region from the N region, thereby ensuring the electrical insulation effect of the PN isolation region.

[0098] Furthermore, the first distance and / or the second distance is 0.2mm to 12mm. That is, the unirradiated edge portion of the first semiconductor layer is reserved. If the edge portion is too wide, the area of ​​the central portion of the entire solar cell is smaller, the reduction in series resistance is small, and the loss during current collection is large. If the width of the edge portion of the first semiconductor layer is too small, on the one hand, the edge portion of the first semiconductor layer is thinner due to the limitations of the coating process. On the other hand, the angle of laser irradiation at the edge of the solar cell is too large, and the energy distribution within the laser spot is deviated. It is easy for the laser energy density to be too high in some parts, causing damage to the passivation of the first semiconductor layer at the edge. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the first distance and / or the second distance are selected to be 0.2mm to 12mm.

[0099] In some possible implementations, the first semiconductor layer includes an amorphous silicon layer. Laser irradiation of a central portion of the first semiconductor layer causes the amorphous silicon layer to partially crystallize into nanocrystals. Using an amorphous silicon layer for the first semiconductor layer provides better passivation in the portion not irradiated by the laser, and provides enhanced insulation in the isolation region.

[0100] In some embodiments, the wavelength of the laser is 325 nm to 532 nm. Specifically, the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and / or the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 Specifically, the energy density of the laser can be 200mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 5000mJ / cm 2 、6000mJ / cm2 Etc. The pulse width of the laser can be on the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is conducive to the crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of ​​the velvet structure. If the laser energy density is too small, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure.

[0101] As shown in FIG8 to FIG19, this embodiment provides a specific process for manufacturing a solar cell. Taking the preparation of a hybrid back-contact cell having a tunneling passivation contact structure and a heterojunction structure on the back side as an example, the preparation process of the back-contact cell is as follows:

[0102] Step 1: As shown in FIG8 , the silicon wafer is polished and cleaned. Specifically, the silicon wafer is placed in a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer. The polishing morphology of both sides is regulated by controlling the temperature, time, and concentration of the chemical solution. The obtained silicon wafer is used as a semiconductor substrate 6, which can be an n-type, p-type, or intrinsic silicon substrate.

[0103] Step 2: As shown in FIG9 , a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the backlight surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 are formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition. In addition, the tunneling oxide layer 21 can be formed by a high-temperature reaction of oxygen with the semiconductor substrate 6, or by a wet chemical method, such as a reaction of silicon with ozone, or an oxidation reaction of silicon with nitric acid. The thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, and optionally, the thickness is 1.4 nm. The thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, and optionally, the thickness is 120 nm.

[0104] Step 3: As shown in FIG10 , the intrinsic polysilicon layer 23 is doped by high temperature diffusion to form an n-type doped polysilicon layer 22, and a phosphorus oxide layer, namely a phosphorus silicon glass layer 24, is generated. The doping concentration of the n-type doped polysilicon layer 22 is 1×10 19 cm -3 ~5×10 20 cm -3 .

[0105] Step 4: As shown in FIG11 , the phosphosilicate glass layer 24 formed after phosphorus diffusion is removed by using an HF solution.

[0106] Step 5: As shown in Figure 12, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. The silicon nitride mask layer 25 acts as a hydrogen source, providing hydrogen atoms at the interface between the crystalline silicon and the tunnel oxide layer 21 to passivate dangling bonds and also passivates some defects within the crystalline silicon. It also serves as a mask to protect the N-region film layer during subsequent P-region patterning.

[0107] Step 6: As shown in FIG13 , the P region is patterned using a laser process, and all P region film layers are laser ablated up to the semiconductor substrate 6. The laser can be a 532 nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used.

[0108] Step 7: As shown in Figure 14, the exposed semiconductor substrate 6 in the P region is textured using a wet etching process to obtain a textured structure, such as a pyramid structure. The silicon nitride mask layer 25 is then removed. This wet etching process serves two purposes: firstly, to remove the damaged layer of the semiconductor substrate 6 in the P region after laser treatment, thus cleaning the interface; and secondly, to remove the silicon nitride mask layer 25 deposited in the N region.

[0109] Step 8: As shown in Figure 15 , an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the entire backlight surface of the semiconductor substrate 6 to form a P-region emitter. The intrinsic amorphous silicon layer 13 has a thickness of 2nm to 20nm, and optionally, a thickness of 8nm; the p-type amorphous silicon layer 14 has a thickness of 5nm to 50nm, and optionally, a thickness of 15nm. Simultaneously, a passivation layer 8 and an anti-reflection layer 9 are sequentially deposited on the front velvet surface of the semiconductor substrate 6. The anti-reflection layer 9 can be any combination of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0110] Step 9: As shown in Figure 16, a laser process is used to pattern the N region, and the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polysilicon layer 22 are removed to expose the n-type doped polysilicon layer 22. An oxide layer will be generated on the n-type doped polysilicon layer 22, which will be removed by a wet etching process. The laser can use a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser can be used. The wet etching process can use a chain device, with the semi-finished product facing up and protected by a water film. The back is exposed to the HF solution to remove the oxide layer and the silicon nitride plated on the back.

[0111] Step 10: As shown in Figure 16, a laser process is used to irradiate the central region of the p-type amorphous silicon layer 14 in the P region, forming a first portion 11 with a crystallized structure in the central region of the p-type amorphous silicon layer 14. The p-type amorphous silicon layer 14 near the edge of the semiconductor substrate 6 is not irradiated, retaining its original amorphous structure and forming a second portion 12. The laser can be a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves along the extension direction of the p-type amorphous silicon layer 14. Ideally, the width of the laser treatment range is consistent with the width of the P region (p-type amorphous silicon layer 14), maximizing the laser treatment area. Even if the laser action range extends beyond the P region and reaches the isolation region, it will not affect the cell performance. However, considering production capacity, the laser treatment area should be minimized, and it is recommended that the laser action area should not extend beyond the P region. The laser treatment range avoids the edge of the semiconductor substrate 6 within 0.3mm to 3mm. The two outermost p-type amorphous silicon layers 14, approximately 1 mm wide, of the multiple p-type amorphous silicon layers 14 are not laser treated. The remaining p-type amorphous silicon layers 14, approximately 1 mm in width, are not laser treated. It should be noted that the laser processes in steps 9 and 10 can be performed in the same step, in either order. To save laser processing time, the crystallization process is performed after the P region is patterned using laser light.

[0112] Step 11: As shown in FIG17 , a transparent conductive layer 7 is deposited on the backlight side of the semiconductor substrate 6. The transparent conductive layer 7 can be one or more of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide, in a laminate or single layer. Optionally, a tin-doped indium oxide film layer is used.

[0113] Step 12: As shown in Figure 18, the transparent conductive layer 7 on the N and P regions is disconnected to form a PN isolation region. This allows the transparent conductive layer 7 to form a first transparent conductive layer 71 located on the P region and a second transparent conductive layer 72 located on the N region, achieving insulation between the P and N regions. The transparent conductive layer 7 is disconnected near the edge of the semiconductor substrate 6 in the N and P regions, forming a third transparent conductive layer located on the edge. The PN isolation region between the P and N regions spans the overlapping area between the N and P regions and part of the p region to achieve better insulation.

[0114] Step 13: As shown in FIG19 , a first gate line electrode 4 and a second gate line electrode 5 are deposited on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively. The first gate line electrode 4 has two ends extending onto the second portions 12 on both sides as shown in FIG1 . The first gate line electrode 4 and the second gate line electrode 5 can be made of silver, copper, aluminum, or a combination thereof.

[0115] In other embodiments, the present application also provides a heterojunction solar cell and a method for preparing the same.

[0116] The heterojunction solar cell includes: a silicon wafer (i.e., a semiconductor substrate 6) having opposite front and back sides; an intrinsic amorphous silicon film layer (i.e., an intrinsic amorphous silicon layer 13) located on the front side (i.e., the light-facing side, the second side) and the back side (i.e., the backlight side, the first side) of the silicon wafer; and a doping layer 70 located on the intrinsic amorphous silicon film layer, the doping layer 70 having a first region 110 and a second region 120, the second region 120 surrounding the edge of the silicon wafer, the second region 120 surrounding the first region 110, the material of the first region 110 being microcrystalline silicon, and the material of the second region 120 being amorphous silicon; wherein the doping type of the doping layer 70 located on the front side of the silicon wafer is N-type doping, and the doping type of the doping layer 70 on the back side of the silicon wafer is P-type doping.

[0117] The doped layer 70 on the front side of the silicon wafer can be the aforementioned third semiconductor layer disposed on the second side. The doped layer 70 on the back side of the silicon wafer can be the aforementioned first semiconductor layer 100 disposed on the first side, or the second semiconductor layer 2 disposed on the first side. For example, if the doped layer 70 on the back side of the silicon wafer is the aforementioned first semiconductor layer 100 disposed on the first side, the first region 110 corresponds to the first portion 11, and the second region 120 corresponds to the second portion 12.

[0118] By crystallizing the amorphous silicon film layer in the middle area on the front and back sides of the silicon wafer, that is, the first area 110, into a microcrystalline silicon film layer, the area outside the middle area, that is, the second area 120, remains as an amorphous silicon film layer. On the one hand, the high deposition rate of amorphous silicon and the excellent electrical properties of microcrystalline silicon can be utilized at the same time. On the other hand, the process difficulty is low, which can greatly reduce costs and increase production capacity, making silicon heterojunction solar cells more competitive in the market.

[0119] The method for preparing a heterojunction solar cell includes operations S110 to S130:

[0120] In operation S110, a silicon wafer having an amorphous silicon film layer 30 deposited on both sides is provided, wherein the two sides of the silicon wafer include a front side and a back side opposite to each other, and the amorphous silicon film layer 30 includes a first region 110 and a second region 120 on both sides. The boundary between the first region 110 and the second region 120 surrounds the edge of the silicon wafer, the second region 120 is close to the edge of the silicon wafer, and the first region 110 is farther away from the edge of the silicon wafer than the second region 120.

[0121] In operation S120 , the front amorphous silicon film layer is doped into an N-type, and the back amorphous silicon film layer is doped into a P-type.

[0122] In operation S130 , the amorphous silicon in the second region 120 on both sides of the silicon wafer is crystallized into microcrystalline silicon.

[0123] In this embodiment, the material of the intrinsic amorphous silicon film layer is a-Si:H(i) as an example. The material of the N-type doped amorphous silicon film layer 31 is a-Si:H(n + ) is used as an example. The material of the P-type doped amorphous silicon film layer (ie, the p-type amorphous silicon layer 14) is a-Si:H(p + ) is used as an example. The material of the microcrystalline silicon film layer 40 obtained by crystallizing the N-type doped amorphous silicon film layer 31 is μ-Si:H(n + ) is used as an example. The material of the microcrystalline silicon film layer 40 obtained by crystallizing the P-type doped amorphous silicon film layer is μ-Si:H(p + ) is used as an example for illustration. It is understandable that those skilled in the art can make other equivalent substitutions for the above materials without departing from the purpose of the disclosure of this application.

[0124] Figure 23 schematically illustrates a cross-sectional structure of the amorphous silicon film layer 30 after crystallization according to an embodiment of the present application. As shown in Figure 23, after the amorphous silicon in the second region 120 on both sides of the silicon wafer is crystallized into microcrystalline silicon, a doped layer 70 is formed. The doped layer 70 on both sides of the silicon wafer includes a first region 110 and a second region 120. The second region 120 is the surrounding area of ​​the doped layer 70, i.e., the edge region. The first region 110 is the area excluding the second region 120, i.e., the central region. According to an embodiment of the present application, the amorphous silicon film layer 30 in the second region 120 on both the front and back sides of the silicon wafer is retained. By crystallizing the amorphous silicon film layer 30 in the central region into a microcrystalline silicon film layer 40 and retaining the amorphous silicon film layer 30 in the edge region, the amorphous silicon film layer 30 in the edge region has better uniformity and lower conductivity than the microcrystalline silicon film layer 40. Therefore, the amorphous silicon film layer 30 in the edge region of the embodiment of the present application can effectively improve the leakage of the cell edge, while the microcrystalline silicon film layer 40 in the central region can improve the VOC, FF, Rsh and other parameters of the prepared heterojunction solar cell and reduce the series resistance. The performance parameters (Rs, Rsh, VOC, FF) of the silicon heterojunction solar cell provided in the embodiment of the present application are tested as follows: series resistance Rs is between 3.00E-04Ω and 7.00E-04Ω; parallel resistance Rsh is between 1.00E+05Ω and 3.00E+05Ω; open circuit voltage Voc is between 0.748V and 0.750V; efficiency Eff is between 25.50% and 25.75%.

[0125] FIG24A schematically shows a test bitmap of crystallization of regions 1 to 7 on the front side using a Raman spectrometer according to an embodiment of the present application. FIG24B schematically shows a Raman spectrum corresponding to test regions 1 to 7 according to an embodiment of the present application. As shown in FIG24A and FIG24B , a Raman spectrometer is used to test the first region 110 (laser irradiation region, regions 4 to 7) and the second region 120 (non-laser irradiation region, regions 1 to 3). The characteristic peaks of the μ-Si:H(n+) region 4 to 7 test positions are all asymmetric Lorentzian line peaks, with a characteristic peak of 510 cm -1 The characteristic peak of the a-Si:H(n+) region 1 to 3 test sites is 480 cm -1 , indicating that after laser irradiation, the first area 110 (laser irradiation area) on the front of the cell has been crystallized, and the second area 120 (non-laser irradiation area) is still the amorphous silicon film 31 (the characteristic peak of single crystal silicon is 520cm -1 , the characteristic peak of amorphous silicon is 480cm -1 , Microcrystalline silicon characteristic peak 500~518cm -1 ).

[0126] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0127] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A solar cell, wherein: include: a semiconductor substrate having a first side and a second side opposite to each other; A first semiconductor layer is arranged on the first surface, the first semiconductor layer has a first portion located in the middle area of ​​the first surface and a second portion located in the edge area of ​​the first surface, the crystallization rate of the first portion is greater than the crystallization rate of the second portion; wherein the edge area surrounds the middle area and is adjacent to the edge of the first surface, the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

2. The solar cell according to claim 1, wherein The first semiconductor layer entirely covers the first surface, the first portion is rectangular, and the second portion is ring-shaped.

3. The solar cell according to claim 2, wherein The solar cell further includes a third semiconductor layer disposed on the second surface. The third semiconductor layer includes a polycrystalline silicon layer or an amorphous silicon layer. The third semiconductor layer and the first semiconductor layer have different conductivity types.

4. The solar cell according to claim 1, wherein The third semiconductor layer is a polysilicon layer, and is arranged in a strip shape on the second surface, or the entire third semiconductor layer is arranged on the second surface, and the third semiconductor layer includes a thicker portion arranged in a strip shape and a thinner portion except the thicker portion.

5. The solar cell according to claim 1, wherein The solar cell also includes a second semiconductor layer arranged on the first surface, the first semiconductor layer includes a plurality of first strip portions extending along the first direction, the second semiconductor layer includes a plurality of second strip portions extending along the first direction, the first strip portions and the second strip portions are alternately arranged along the second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the first direction and the second direction intersect.

6. The solar cell according to claim 5, wherein In the first strip portion, the first portion includes a strip-shaped middle portion extending along a first direction and strip-shaped edge portions arranged on both sides of the middle portion along a second direction, and a crystallization rate of the middle portion is greater than that of the edge portion.

7. The solar cell according to claim 6, wherein In the first strip-shaped portion, a width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm.

8. The solar cell according to claim 5, wherein The second semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer.

9. The solar cell according to claim 5, wherein Along the second direction, a crystallization rate of at least one first strip portion close to an edge of the first surface is the same as a crystallization rate of the second portion.

10. The solar cell according to claim 1, wherein A contact resistance of the first portion is smaller than a contact resistance of the second portion.

11. The solar cell according to claim 6, wherein The first strip portion has an overlapping portion overlapping the second strip portion, and the first portion does not include the overlapping portion; and / or, The solar cell further includes a first transparent conductive layer covering a portion of the first portion, and a projection of the middle portion on the first transparent conductive layer is at least located within a boundary of the first transparent conductive layer.

12. The solar cell according to claim 11, wherein It also includes a second transparent conductive layer and a third transparent conductive layer, wherein the second transparent conductive layer covers a portion of the overlapping portion and a portion of the second strip portion; The third transparent conductive layer covers a portion of the second portion; A PN isolation region is provided between the adjacent first transparent conductive layer and the second transparent conductive layer; An edge isolation region is provided between the first transparent conductive layer and the third transparent conductive layer and / or between the second transparent conductive layer and the third transparent conductive layer.

13. The solar cell according to claim 1, wherein In an image obtained by an EL test of the solar cell, the brightness of the first portion is greater than the brightness of the second portion.

14. The solar cell according to claim 1, wherein The device further includes a first gate line electrode extending along the first direction. The first gate line electrode is conductively disposed on the first portion of the first semiconductor layer and extends from the first portion to the second portion.

15. The solar cell according to claim 1, wherein Along a direction from the first portion to the second portion and perpendicular to the side length of the semiconductor substrate, a width of the second portion is 0.3 mm to 12 mm.

16. A photovoltaic module comprising a solar cell, wherein: The solar cell is the solar cell according to any one of claims 1 to 15.

17. A method for manufacturing a solar cell, wherein: include: Providing a semiconductor substrate having a first surface and a second surface opposite to each other; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer has a middle portion located in a middle region of the first semiconductor layer and an edge portion located in a peripheral region of the middle portion; The middle portion is irradiated with laser light so that a crystallization rate of the middle portion is greater than a crystallization rate of the edge portion; wherein the edge portion surrounds the middle portion, and the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

18. The method for manufacturing a solar cell according to claim 17, wherein: The first surface has a first side and a second side arranged opposite to each other along a first direction; The irradiating the middle portion with a laser comprises: The laser is used to start irradiation at a position a first distance from the first side, pass through the middle portion along a first direction, and stop irradiation at a position a second distance from the second side.

19. The method for manufacturing a solar cell according to claim 18, wherein: The first distance and / or the second distance is / are 0.2 mm to 12 mm.

20. The method for manufacturing a solar cell according to claim 17, wherein: The first semiconductor layer includes an amorphous silicon layer. After the middle portion is irradiated with the laser, a portion of the amorphous silicon layer is crystallized to form nanocrystalline grains.

21. The method for manufacturing a solar cell according to claim 17, wherein: The wavelength of the laser is 325nm to 532nm; And / or, the energy density of the laser is 200mJ / cm 2 ~6000mJ / cm 2 .

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