Chip packaging structure and manufacturing method therefor, and chip and electronic device

Abstract

Provided in the present application are a chip packaging structure and a manufacturing method therefor, and a chip and an electronic device. The chip packaging structure comprises two packaging units arranged in a stacked manner, wherein one end of a through-silicon via of a first die in a first packaging unit is connected to a circuit layer in the first die, and the other end thereof protrudes from a passive face of the first die; a first conductive structure of the first packaging unit penetrates through a first encapsulant structure; and a second rewiring layer of the first packaging unit covers a second surface of the first encapsulant structure and the passive face of the first die, the through-silicon via extends into a second rewiring layer, and the second rewiring layer is electrically connected to both the through-silicon via and the first conductive structure. The chip packaging structure provided in the present application has the advantage of size miniaturization, and also has structural stability and circuit stability.

Description

Chip packaging structure and manufacturing method thereof, chip and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 21, 2024, with application number 202410331604.8, and priority to the Chinese patent application entitled “Chip packaging structure and manufacturing method thereof, chip and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to chip packaging technology in the field of microelectronics technology, and in particular to a chip packaging structure and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0003] With the continuous evolution of FO+ (Fan-out and Package plus) packaging structures, chip packaging structures are becoming increasingly complex, and multi-dimensional packaging of active devices is becoming increasingly aggressive. Traditional 2.5D packaging processes have drawbacks such as high cost, complex processes, and the inability to miniaturize the package structure. 3D packaging structures facilitate miniaturization of the overall package structure through chip stacking.

[0004] Based on the interconnection design of the internal lines of the 3D packaging structure, how to meet the stability and life of the internal circuit while reducing the cost of the packaging process is the research and development direction of the industry. Summary of the Invention

[0005] The embodiments of the present application provide a chip packaging structure and a manufacturing method thereof, a chip and an electronic device, which achieve miniaturization of the packaging structure to meet the stability and life of the internal circuit.

[0006] In a first aspect, an embodiment of the present application provides a chip packaging structure, comprising a first packaging unit and a second packaging unit arranged in a stacked manner, wherein the first packaging unit comprises a first redistribution layer, a first die packaging layer and a second redistribution layer arranged in a stacked manner, the first die packaging layer comprises a first die, a first conductive structure, a second conductive structure and a first sealing structure, the first die comprises an active surface, a passive surface opposite to the active surface and a side surface connected between the active surface and the passive surface, the first sealing structure wraps part of the first die, the first sealing structure comprises a first surface and a second surface arranged opposite to each other, the first conductive structure is distributed on the periphery of the side surface of the first die and passes through the first surface and the second surface, and the second conductive structure is at least partially located on the first die. A die is located between the active surface of the die and the first surface and is electrically connected to the circuit layer within the first die. The first die includes a through-silicon via (TSV), one end of the TSV is electrically connected to the circuit layer within the first die, and the other end extends from the passive surface of the first die. The first redistribution layer is located between the second packaging unit and the first die packaging layer. The first redistribution layer is used to electrically connect the second die in the second packaging unit and the first conductive structure. The first redistribution layer is also used to electrically connect the second die and the second conductive structure. The second redistribution layer is located on the side of the first die packaging layer facing away from the first redistribution layer. Part of the TSV extends into the second redistribution layer. The second redistribution layer is electrically connected to the TSV and the first conductive structure, respectively.

[0007] In one embodiment, the first redistribution layer covers the first surface, and the second redistribution layer covers the second surface and the passive surface of the first die.

[0008] The embodiments of the present application achieve a layered arrangement of the first die and the second die by stacking the first and second packaging units, and achieve line transmission between different layer structures through the first and second redistribution layers. Therefore, the embodiments of the present application provide a 3D packaging structure that achieves a design with a miniaturized overall size of the chip packaging structure. The embodiments of the present application achieve an electrical connection between the first die and the second redistribution layer by partially extending the through-silicon via into the second redistribution layer. The cross-layer extension of the through-silicon via architecture helps to improve the stability of the connection between the first die packaging layer and the second redistribution layer, which not only improves the structural strength but also helps to improve the speed and stability of signal transmission.

[0009] In one possible implementation, the first die encapsulation layer further includes a protective structure, partially embedded within the first sealing structure and covering one end of the first conductive structure; a portion of the second surface is flush with the passive surface of the first die. In this embodiment, the protective structure protects one end of the first conductive structure. The protective structure is used to protect the first conductive structure during the manufacturing process, preventing copper contamination from grinding or cutting the first conductive structure during processes such as grinding and cutting.

[0010] In one possible implementation, the material of the protective structure is an organic material. In one embodiment, the material of the protective structure is any one of epoxy resin material (EMC), photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PBO), photosensitive benzocyclobutene (PSBCB), and benzocyclobutene (BCB), or a combination of at least two of them. In one embodiment, the dielectric constant range of the protective structure is: less than or equal to 3.4. The material of the protection structure constrained by this solution is an organic material, which can make the material of the protection structure consistent with the material of the second redistribution layer, which is beneficial to simplifying the manufacturing difficulty during the manufacturing process. The dielectric constant of the material constraining the protection structure is less than or equal to 3.4, which can achieve a higher signal transmission speed.

[0011] In a possible implementation, all of the second surfaces are flush with the passive surface of the first die. This solution is beneficial for saving steps in the manufacturing process and reducing manufacturing difficulty.

[0012] In one possible implementation, the second redistribution layer includes a second substrate and a second conductive circuit embedded in the second substrate, the second substrate covers the second surface and the passive surface of the first die, one end of a portion of the second conductive circuit is located inside the second substrate, and the other end extends out of the surface of the second substrate facing away from the first die packaging layer, and the through silicon via extends from the surface of the second substrate adjacent to the first die packaging layer into the interior of the second substrate and connects the second conductive circuit. This solution provides a specific architecture for the second redistribution layer, in which one end of the second conductive circuit is located inside the second substrate, and the through silicon via extends into the second substrate and connects to the second conductive circuit, thereby achieving both physical structural connection and electrical signal connection. Moreover, the connection location is wrapped by the second substrate, that is, located inside the second substrate, which is beneficial to improving structural strength and electrical signal stability.

[0013] In one possible implementation, the second redistribution layer includes a second substrate and a second conductive circuit embedded in the second substrate, the second substrate covering the protective structure, a portion of the second surface, and the passive surface of the first die; one end of a portion of the second conductive circuit is located inside the second substrate, and the other end extends out of the surface of the second substrate facing away from the first die packaging layer, the through silicon via extends from the surface of the second substrate adjacent to the first die packaging layer into the interior of the second substrate and connects to the corresponding second conductive circuit; both ends of a portion of the second conductive circuit extend out of the second substrate, and a portion of the second conductive circuit extends from the surface of the second substrate adjacent to the first die packaging layer and passes through the protective structure and is connected to the first conductive structure. In the embodiment of the present application, the second conductive circuit located at the periphery of the first die passes through the second substrate from the top surface of the second substrate, and a portion of this portion of the second conductive circuit is located inside the protective structure, and the through silicon via passes through the bottom surface of the first die from the interior of the first die, and a portion of the through silicon via is located inside the second substrate, thereby improving the strength and stability of the packaging structure. Since the stiffness and strength of the second conductive circuit and the silicon via are greater than the stiffness and strength of the second substrate, the second conductive circuit and the silicon via both pass through the top surface of the second substrate, which can improve the bonding strength between the second substrate and the first bare chip packaging layer. The bonding surface position between the first bare chip packaging layer and the second redistribution layer has a conductive structure perpendicular to the thickness direction, which not only ensures that the position of this bonding surface is not easily deformed, which is beneficial to the structural stability of the packaging structure, but also can improve the stability of signal transmission between the first bare chip packaging layer and the second redistribution layer.

[0014] In one possible implementation, the dielectric constant of the second substrate is less than or equal to 3.4. The smaller the dielectric constant of the second substrate, the higher the signal transmission speed of the second redistribution layer L3. In this embodiment of the present application, the dielectric constant of the second substrate is constrained to be less than or equal to 3.4, thereby achieving a higher signal transmission speed.

[0015] In one possible implementation, the material of the second substrate is any one or a combination of at least two of epoxy resin material (EMC), photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PBO), photosensitive benzocyclobutene (PSBCB), and benzocyclobutene (BCB).

[0016] In one possible implementation, there are multiple first bare chips, and the multiple first bare chips are arranged in parallel. Adjacent first bare chips are isolated by the first sealing structure, and the multiple first bare chips are electrically connected through the first redistribution layer and / or the second redistribution layer.

[0017] In one possible implementation, the number of the second bare chips is at least two, the second packaging unit further includes a second sealing structure and a circuit layer, the circuit layer includes a bottom filler and a third conductive structure, the bottom filler wraps the third conductive structure and connects the second bare chip, and the second sealing structure at least wraps the second bare chip.

[0018] In a second aspect, an embodiment of the present application provides a chip, comprising a substrate and a chip packaging structure provided by any possible implementation of the first aspect, wherein the chip packaging structure is arranged on the substrate.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, comprising a circuit board and a chip provided by any possible implementation of the second aspect, wherein the chip is arranged on the circuit board.

[0020] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, comprising:

[0021] A prefabricated packaging structure is provided, wherein the prefabricated packaging structure includes a first unit and a second unit stacked together.

[0022] The first unit includes a first redistribution layer and a first die packaging layer arranged in a stacked manner, the first die packaging layer includes a first die, a first conductive structure, a second conductive structure, and a first sealing structure, the first die includes an active surface, a passive surface opposite to the active surface, and a side surface connected between the active surface and the passive surface, the first sealing structure partially wraps the first die, the passive surface is covered with a protective layer, the first conductive structure is distributed around the side surface and penetrates the first sealing structure, the first sealing structure includes a first surface and a second surface arranged opposite to each other, all of the second surfaces are flush with the passive surface, the second conductive structure is at least partially located between the active surface and the first surface of the first die and is electrically connected to a circuit layer in the first die, a through silicon via is provided in the first die, one end of the through silicon via is electrically connected to the circuit layer in the first die, and the other end is adjacent to the protective layer;

[0023] The second unit is located on a side of the second conductive structure away from the first die, the second unit includes a second die and a third conductive structure, a portion of the third conductive structure is electrically connected to the second die and the second conductive structure, and a portion of the third conductive structure is electrically connected to the second die and the first conductive structure;

[0024] removing the protective layer covering the passive surface of the first die and a portion of the material of the first die so that the other end of the through-silicon via extends out of the passive surface and is exposed; removing a portion of the material on the second surface side of the first sealing structure so that one end of the first conductive structure extends out of the second surface and is exposed;

[0025] A second redistribution layer is formed on the second surface of the first sealing structure and the passive surface of the first die. Part of the through silicon via extends into the second redistribution layer. The second redistribution layer electrically connects the through silicon via and the first conductive structure.

[0026] The chip packaging structure manufacturing method provided in the embodiment of the present application can produce a chip packaging structure with miniaturized overall size and stable structural strength, and can also improve the speed and stability of signal transmission.

[0027] In a possible implementation, a method for fabricating a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die includes:

[0028] Coating a first protective layer on the second surface and the passive surface, wherein the first protective layer covers the exposed portion of the first conductive structure and the through silicon via;

[0029] Performing chemical mechanical polishing on the surface of the first protective layer so that the end surfaces of the first conductive structure and the through silicon via are exposed;

[0030] Fabricating a second conductive circuit, wherein one end of the second conductive circuit is respectively connected to the first conductive structure and an end surface of the through silicon via;

[0031] A second protective layer is applied, wherein the second protective layer wraps the second conductive circuit, and the other end of the second conductive circuit extends out of the second protective layer.

[0032] In a possible implementation, materials of the first protective layer and the second protective layer are both organic materials.

[0033] In a possible implementation, before the step of forming a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die, the manufacturing method further includes:

[0034] An organic solution is sprayed on the second surface and the passive surface, and the organic solution is used to achieve consistency between the second surface and the passive surface.

[0035] In a fifth aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, comprising:

[0036] A prefabricated packaging structure is provided, wherein the prefabricated packaging structure includes a first unit and a second unit stacked together.

[0037] The first unit includes a first redistribution layer and a first die packaging layer arranged in a stacked manner, the first die packaging layer including a first die, a first conductive structure, a second conductive structure, a first sealing structure and a protective structure, the first die including an active surface, a passive surface opposite to the active surface, and a side surface connected between the active surface and the passive surface, the first sealing structure partially wraps the first die, the passive surface covers the protective layer, the first conductive structure is distributed around the periphery of the side surface and penetrates the first sealing structure, the protective structure is partially embedded in the first sealing structure and covers one end of the first conductive structure; a portion of the second surface is flush with the passive surface, the second conductive structure is at least partially located between the active surface and the first surface of the first die and is electrically connected to a circuit layer in the first die, a through silicon via is provided in the first die, one end of the through silicon via is electrically connected to the circuit layer in the first die, and the other end is adjacent to the protective layer;

[0038] The second unit is located on a side of the second conductive structure away from the first die, the second unit includes a second die and a third conductive structure, a portion of the third conductive structure is electrically connected to the second die and the second conductive structure, and a portion of the third conductive structure is electrically connected to the second die and the first conductive structure;

[0039] removing the protective layer and a portion of the material of the first die covering the passive surface, so that the other end of the through-silicon via extends from the passive surface and is exposed; and simultaneously removing a portion of the material of the first sealing structure and a portion of the material of the protective structure, so that the first conductive structure is partially covered by the protective structure;

[0040] A second redistribution layer is formed on the second surface and the passive surface, a portion of the through silicon via extends into the second redistribution layer, and the second redistribution layer is electrically connected to the through silicon via and the first conductive structure.

[0041] The chip packaging structure manufacturing method provided in the embodiment of the present application can produce a chip packaging structure with miniaturized overall size and stable structural strength, and can also improve the speed and stability of signal transmission.

[0042] In a possible implementation, a method for fabricating a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die includes:

[0043] Coating a first protective layer on the second surface, the surface of the protective structure and the passive surface, wherein the first protective layer covers the exposed portion of the through silicon via;

[0044] Performing chemical mechanical polishing on the surface of the first protective layer so that the end surface of the through silicon via is exposed;

[0045] Removing part of the first protective layer and part of the material of the protective structure corresponding to the first conductive structure to form a groove, so that at least part of the end surface of the first conductive structure is exposed at the bottom of the groove;

[0046] Fabricating a second conductive circuit, wherein one end of a portion of the second conductive circuit is located in the groove and connected to the first conductive structure, and one end of the second conductive circuit is connected to an end surface of the through-silicon via;

[0047] A second protective layer is applied, wherein the second protective layer wraps the second conductive circuit, and the other end of the second conductive circuit extends out of the second protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic diagram of an electronic device provided in one embodiment of the present application;

[0049] FIG2 is a schematic diagram of a chip packaging structure provided in one embodiment of the present application;

[0050] FIG3 is a schematic diagram of a first packaging unit in the embodiment shown in FIG2 ;

[0051] FIG4 is an exploded schematic diagram of the first packaging unit shown in FIG3 ;

[0052] FIG5 is a schematic diagram of a chip packaging structure provided in one embodiment of the present application;

[0053] FIG6 is a schematic diagram of a first packaging unit in the embodiment shown in FIG5 ;

[0054] FIG7 is a schematic diagram of a chip packaging structure provided in one embodiment of the present application;

[0055] FIG8 is a schematic diagram of a method for manufacturing a chip packaging structure provided in one embodiment of the present application;

[0056] FIG9 is a schematic diagram of a method for manufacturing a prefabricated packaging structure provided in one embodiment of the present application;

[0057] FIG10 is a schematic diagram of a method for fabricating a second redistribution layer on the bottom surface of the first sealing material structure and the bottom surface of the first die according to an embodiment of the present application;

[0058] FIG11 is a schematic diagram of a method for manufacturing a chip packaging structure provided in another embodiment of the present application;

[0059] FIG12 is a schematic diagram of a method for manufacturing a prefabricated packaging structure provided in another embodiment of the present application;

[0060] FIG13 is a schematic diagram of a method for fabricating a second redistribution layer on the bottom surface of the first sealing structure and the bottom surface of the first bare die according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] Explanation of terms

[0062] Rework Distribution Layer (RDL): refers to an additional metal wiring layer located on the chip during the semiconductor packaging process, which is used to change the original design of the IC circuit contact position (I / O pad). RDL is implemented through wafer-level metal wiring process and bump process, allowing the IC to adapt to different packaging forms. The main advantages of RDL include reducing parasitic capacitance, reducing clock wiring delay and reducing signal crosstalk. In packaging technology, RDL provides more flexibility and optimization space, allowing the chip to better adapt to different applications and environmental requirements.

[0063] The following describes possible implementations of the present application in conjunction with the accompanying drawings in possible implementations of the present application.

[0064] Figure 1 is a schematic diagram of an electronic device provided in one embodiment of the present application. Referring to Figure 1, in one embodiment, the electronic device 1000 includes a chip 100 and a circuit board 200, and the chip 100 is arranged on the circuit board 200. An electronic device 300 can also be provided on the circuit board 200, and the electronic device 300 can be electrically connected or communicatively connected to the chip 100. For example, the electronic device 300 can be a camera module, a radio frequency module, an audio module, and the like. The electronic device 1000 provided in this application can be, but is not limited to: a terminal device (such as a mobile terminal, a wearable terminal, etc.), a communication device (such as a server, a network product, etc.), a household appliance, a vehicle-mounted device, an energy storage device, and the like.

[0065] In one embodiment, the chip 100 is fixed to the circuit board 200 via solder balls, or the chip 100 can be assembled on the surface of the circuit board 200 via SMT (surface mount technology) technology. The chip 100 can be electrically connected to other circuits or electronic components on the circuit board 200. For example, the chip 100 can be electrically connected to other circuits or electronic components on the circuit board 200 by gold wire bonding, or the chip 100 can be electrically connected to other circuits or electronic components on the circuit board 200 via structures such as pads.

[0066] In one embodiment, the chip 100 includes a chip packaging structure 10, a substrate 20 and other devices 30. The chip packaging structure 10 is arranged on the substrate 20. For example, the chip packaging structure 10 can be connected to the surface of the substrate 20 by a connector (such as a solder ball, a pad or a gold wire). Other devices 30 can also be set on the surface of the substrate 20. For example, the other devices 30 can be but not limited to passive devices (capacitors, inductors, etc.), other chip packaging structures, etc. The substrate 20 is connected between the chip packaging structure 10 and the circuit board 200 to realize the transmission of current and other signals between the chip packaging structure 10 and the circuit board 200. In one embodiment, all devices on the substrate 20 (including the chip packaging structure 10, other devices 30, etc.) can be plastic-encapsulated as a whole by packaging materials.

[0067] FIG2 is a schematic diagram of a chip packaging structure provided in one embodiment of the present application. Referring to FIG2 , in one embodiment, chip packaging structure 10 includes a first packaging unit 11 and a second packaging unit 12, with second packaging unit 12 stacked on top of first packaging unit 11. The bottom surface of first packaging unit 11 is used to connect to the chip substrate (such as substrate 20 in FIG1 ).

[0068] Figure 3 is a schematic diagram of the first packaging unit in the embodiment shown in Figure 2. Figure 4 is an exploded schematic diagram of the first packaging unit shown in Figure 3. In order to clearly mark the structural features of each part, Figure 4 schematically expresses the three layers of the first packaging unit along the stacking direction in an exploded diagram.

[0069] Referring to Figures 2, 3 and 4, the first packaging unit 11 includes a first redistribution layer L1, a first bare chip packaging layer L2 and a second redistribution layer L3 arranged in a stacked manner. The first redistribution layer L1 is connected between the first bare chip packaging layer L2 and the second packaging unit 12. The second redistribution layer L3 is connected between the first bare chip packaging layer L2 and the substrate (such as the substrate 20 in Figure 1), and the second redistribution layer L3 is used to fix the chip packaging structure 10 to the substrate. The first bare chip packaging layer L2 includes a first bare chip 111, a first conductive structure 112, a second conductive structure 114 and a first sealing structure 113. In one embodiment, the number of first bare chips 111 in the first bare chip packaging layer L2 is one. The first bare chip 111 is located in the central area of ​​the first bare chip packaging layer L2.

[0070] The first bare chip 111 includes an active surface S1, a passive surface S2, and a side surface S3 connected to the active surface S1 and the passive surface S2. The first sealing structure 113 partially wraps the first bare chip 111. In one embodiment, the first sealing structure 113 wraps the active surface S1 and the side surface S3 of the first bare chip 111. The passive surface S2 is not covered by the first sealing structure 113. The passive surface S2 is connected to the second redistribution layer L3. The first bare chip 111 includes a substrate layer 1111 and a circuit layer 1112, and the circuit layer 1112 is stacked on the top surface of the substrate layer 1111. In one embodiment, the bottom surface of the substrate layer 1111 constitutes the passive surface S2 of the first bare chip 111. The surface of the circuit layer 1112 facing away from the substrate layer 1111 constitutes the active surface S1 of the first bare chip 111. In one embodiment, the side surface of the substrate layer 1111 and the side surface of the circuit layer 1112 are coplanar and together constitute the side surface S3 of the first die 111. In one embodiment, the substrate layer 1111 is made of silicon. Conductive circuits are disposed in the circuit layer 1112.

[0071] Referring to Figures 2, 3, and 4, the first die 111 includes a through-silicon via (TSV) 1113, which is used to electrically connect the circuit layer 1112 of the first die 111 and the second redistribution layer L3. One end of the TSV 1113 electrically connects to the circuit layer 1112 within the first die 111, while the other end extends from the passive surface S2 of the first die 111. The TSV 1113 penetrates the substrate layer 1111 of the first die 111, with a portion of the TSV 1113 protruding from the passive surface S2 of the first die 111. In one embodiment, the TSV 1113 vertically penetrates the substrate layer 1111 along the thickness direction of the first die package layer L2 (i.e., the stacking direction of the first redistribution layer L1, the first die package layer L2, and the second redistribution layer L3). Multiple TSVs 1113 are provided within the first die 111, spaced apart and arranged on the bottom side of the circuit layer 1112. In one embodiment, one of the TSVs includes at least one conductive pillar, and the conductive pillars are insulated and isolated from each other. In any TSV 1113 , the number of conductive pillars is two, three, four, five, or six.

[0072] 2 , 3 , and 4 , the first conductive structure 112 is distributed around the side surface S3 of the first die 111 and penetrates the first sealing structure 113. The first sealing structure 113 includes a first surface and a second surface S5 that are oppositely disposed. In one embodiment, the first conductive structure 112 vertically penetrates the first sealing structure 113 along the thickness direction of the first die packaging layer L2 (i.e., the stacking direction of the first redistribution layer L1, the first die packaging layer L2, and the second redistribution layer L3). The first conductive structure 112 penetrates the first surface and the second surface S5. In one embodiment, there are multiple first conductive structures 112, and the multiple first conductive structures 112 surround the side surface S3 of the first die 111 and are spaced apart. For example, the outer edge of the first die 111 is a quadrilateral, and the first die 111 includes four side surfaces S3. The same number or different numbers of first conductive structures 112 can be disposed around the periphery of each side surface S3.

[0073] Referring to Figures 2, 3, and 4, the second conductive structure 114 is used to electrically connect the first die 111 to the circuitry within the first redistribution layer L1. The second conductive structure 114 is located on the active surface S1 of the first die 111. One end of the second conductive structure 114 is electrically connected to the circuit layer 1112 within the first die 111. The other end of the second conductive structure 114 is located on the first surface of the first sealing structure 113, meaning that the end surface of the other end of the second conductive structure 114 is not covered by the first sealing structure 113. In one embodiment, the end surface of the other end of the second conductive structure 114 is flush or coplanar with the first surface of the first sealing structure 113. In other embodiments, the other end of the second conductive structure 114 may extend outside the first sealing structure 113 or protrude relative to the first surface of the first sealing structure 113. In one embodiment, there are multiple second conductive structures 114, each of which is spaced apart and distributed between the active surface S1 of the first die 111 and the first redistribution layer L1. In one embodiment, the extension direction of the second conductive structure 114 is the thickness direction of the first die packaging layer L2 .

[0074] In one embodiment, the first conductive structure 112 and the second conductive structure 114 may both be made of copper.

[0075] Referring to Figure 4 , in one embodiment, the first die encapsulation layer L2 further includes a protective structure 119. The protective structure 119 is partially embedded in the first encapsulation structure 113 and covers one end of the first conductive structure 112. A portion of the second surface S5 of the first encapsulation structure 113 is flush with the passive surface S2 of the first die 111. In one embodiment, the bottom surface S6 of the protective structure 119 is coplanar with a portion of the second surface S5 of the first encapsulation structure 113, meaning that the bottom surface S6 of the protective structure 119 is not covered by the first encapsulation structure 113. The protective structure 119 protects the first conductive structure 112 during the manufacturing process, preventing copper contamination caused by grinding and cutting during processes such as grinding and cutting. Along the thickness of the first die encapsulation layer L2, the vertical projection of the first conductive structure 112 on the protective structure 119 is located within the protective structure 119, and the bottom surface of the protective structure 119 is larger than the bottom surface of the first conductive structure 112. The protective structure 119 and the first conductive structure 112 form a T-shaped cross-section. In one embodiment, the material of the protective structure 119 is an organic material, such as, but not limited to, epoxy resin (EMC), photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PBO), photosensitive benzocyclobutene (PSBCB), and benzocyclobutene (BCB). In one embodiment, the dielectric constant of the protective structure is less than or equal to 3.4.

[0076] Referring to Figures 3 and 4, the first redistribution layer L1 is located between the second packaging unit 12 and the first bare die packaging layer L2. The first redistribution layer L1 is used to electrically connect the second bare die 121 in the second packaging unit 12 and the first conductive structure 112. The first redistribution layer L1 is also used to electrically connect the second bare die 121 and the second conductive structure 114. The first redistribution layer L1 covers the first surface of the first sealing structure 113. The first redistribution layer L1 is used to achieve electrical connection between the first bare die packaging layer L2 and the second packaging unit 12. The first redistribution layer L1 includes a first substrate 115 and a plurality of first conductive lines 116. In one embodiment, the plurality of first conductive lines 116 are spaced apart from each other and penetrate the first substrate 115 along the thickness direction of the first redistribution layer L1. Some of the first conductive lines 116 are electrically connected to the second conductive structure 114 to achieve electrical connection between the circuit layer 1112 in the first bare die 111 and the circuit in the second packaging unit 12. A portion of the first conductive traces 116 is electrically connected to the first conductive structure 112 , so as to achieve electrical connection between the circuit in the second package unit 12 and the second redistribution layer L3 .

[0077] Referring to Figures 3 and 4, the second redistribution layer L3 is located on the side of the first die packaging layer L2 away from the first redistribution layer L1. The second redistribution layer L3 is electrically connected to the through silicon via 1113 and the first conductive structure 112 respectively. The second redistribution layer L3 covers the second surface S5 of the first sealing structure 113, the bottom surface S6 of the protective structure 119 and the passive surface S2 of the first die. The second redistribution layer L3 is used to achieve electrical connection between the first die packaging layer L2 and the substrate. The second redistribution layer L3 includes a second substrate 117 and a plurality of second conductive lines 118. In one embodiment, the plurality of second conductive lines 118 are spaced apart from each other and pass through the second substrate 117 along the thickness direction of the second redistribution layer L3. Part of the second conductive line 118 passes through the second substrate 117 and the protective structure 119, and one end of this part of the second conductive line 118 passes through the protective structure 119 and is electrically connected to the first conductive structure 112. The top of a portion of the second conductive circuit 118 is located inside the second substrate 117 (it can be understood that the top of this portion of the second conductive circuit 118 does not extend out of the second substrate 117 and is wrapped by the second substrate 117), and its other end passes through the second substrate 117, and part of the silicon through-hole 1113 extends into the second substrate 117 of the second redistribution layer L3 and is electrically connected to this portion of the second conductive circuit 118.

[0078] The embodiment of the present application realizes a layered arrangement of the first die and the second die by stacking the first packaging unit 11 and the second packaging unit 12, and realizes line transmission between different layer structures by the first redistribution layer and the second redistribution layer. Therefore, the embodiment of the present application provides a 3D packaging structure, which realizes a design with a miniaturized overall size of the chip packaging structure. The embodiment of the present application realizes an electrical connection between the first die and the second redistribution layer by partially extending the silicon via into the second redistribution layer. The structure of the silicon via extending across the layers is conducive to improving the stability of the connection between the first die packaging layer and the second redistribution layer, which not only improves the structural strength, but also helps to improve the speed and stability of signal transmission.

[0079] In one embodiment, the material of the second substrate 117 is an organic material, for example, the organic material includes but is not limited to: epoxy resin material (EMC), photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PBO), photosensitive benzocyclobutene (PSBCB), benzocyclobutene (BCB).

[0080] In one embodiment, the second substrate 117 is made of the same material as the first substrate 115. In one embodiment, the second conductive trace 118 is made of the same material as the first conductive trace 116.

[0081] In one embodiment, the dielectric constant of the second substrate 117 is within a range of 3.4 or less. The smaller the dielectric constant of the second substrate, the higher the signal transmission speed of the second redistribution layer L3. In this embodiment, the dielectric constant of the second substrate 117 is constrained to be 3.4 or less, thereby achieving a higher signal transmission speed. In one embodiment, the dielectric constant of the second substrate 117 can be 2.2 or 2.0 to achieve even higher transmission speeds.

[0082] Referring to Figures 3 and 4, the top surface of the second substrate 117 is combined with the passive surface S2 of the first die 111, the second surface S5 of the first sealing structure 113, and the bottom surface S6 of the protective structure 119. In one embodiment, the top surface of the second substrate 117 is flat, which facilitates the coating process during the manufacturing process. One end of a portion of the second conductive line 118 is located inside the second substrate 117, and the other end extends out of the bottom surface of the second substrate 117. The through-silicon via 1113 extends from the top surface of the second substrate 117 into the interior of the second substrate 117 and connects the corresponding second conductive line 118. Both ends of a portion of the second conductive line 118 extend out of the second substrate 117. A portion of the second conductive line 118 extends from the top surface of the second substrate 117 and passes through the protective structure 119 and is connected to the first conductive structure 112. Specifically, a second conductive trace 118 located on the periphery of the first die 111 passes through the top surface of the second substrate 117 and out of the second substrate 117. Part of this second conductive trace 118 is located within the protection structure 119. A through-silicon via 1113 passes through the interior of the first die 111 and out of the passive surface S2 of the first die 111. Part of this through-silicon via 1113 is located within the second substrate 117. Since the stiffness and strength of the second conductive circuit 118 and the silicon through-via 1113 are greater than the stiffness and strength of the second substrate 117, the second conductive circuit 118 and the silicon through-via 1113 both pass through the top surface of the second substrate 117, and can utilize the second conductive circuit 118 and the silicon through-via 1113 to enhance the bonding strength between the second substrate 117 and the first bare chip packaging layer L2. The bonding surface position between the first bare chip packaging layer L2 and the second redistribution layer L3 has a conductive structure perpendicular to the thickness direction, which not only ensures that the position of this bonding surface is not easily deformed, which is beneficial to structural stability, but also enhances the stability of signal transmission between the first bare chip packaging layer L2 and the second redistribution layer L3.

[0083] 2 , the second packaging unit 12 includes a second die 121, a circuit layer, and a second sealing structure 123. The circuit layer includes a bottom filler 124 and a third conductive structure 122. The bottom filler 124 wraps around the third conductive structure 122 and is connected to the bottom surface of the second die 121. The second sealing structure 123 wraps around the side and top surfaces of the second die 121. In one embodiment, a portion of the second sealing structure 123 may also cover a portion of the surface of the bottom filler 124. For example, a portion of the second sealing structure 123 covers the edge area and side surfaces of the top surface of the bottom filler 124. The second die 121 is disposed in the middle area of ​​the top surface of the bottom filler 124, and the side and top surfaces of the second die 121 are both covered by the second sealing structure 123. In one embodiment, the third conductive structure 122 is embedded in the bottom filler 124 , the top surface of the third conductive structure 122 is not covered by the bottom filler 124 , and part of the bottom filler 124 is between the bottom surface of the third conductive structure 122 and the first redistribution layer L1 .

[0084] A portion of the third conductive structure 122 is used to electrically connect the second die 121 and the second conductive structure 114. Specifically, one end of this portion of the third conductive structure 122 is electrically connected to the second die 121, and the other end is electrically connected to a portion of the first conductive trace 116 in the first redistribution layer L1. The second die 121, third conductive structure 122, first conductive trace 116, second conductive structure 114, circuit layer 1112 of the first die 111, through-silicon vias 1113 of the first die 111, and second conductive trace 118 are sequentially connected to form a conductive circuit. In one embodiment, the portion of the first conductive trace 116 connected to the second conductive structure 114 extends into the underfill 124 and connects to the corresponding third conductive structure 122.

[0085] A portion of the third conductive structure 122 electrically connects the second die 121 and the first conductive structure 112. Specifically, one end of this portion of the third conductive structure 122 is electrically connected to the second die 121, and the other end is electrically connected to a portion of the first conductive trace 116 in the first redistribution layer L1. The second die 121, the third conductive structure 122, the first conductive trace 116, the first conductive structure 112, and the second conductive trace 118 are sequentially connected to form a conductive circuit. In one embodiment, the portion of the first conductive trace 116 connected to the first conductive structure 112 extends into the underfill 124 and connects to the corresponding third conductive structure 122.

[0086] In one embodiment, the number of the second dies 121 is at least two. For example, the chip package structure 10 provided in the embodiment shown in FIG2 includes two second dies 121, which are isolated from each other by a second sealing structure 123. In one embodiment, the two second dies 121 can be electrically connected via the first redistribution layer L1 to enable exchange of electrical signals or communication signals between the two.

[0087] In one embodiment, the third conductive structure 122 and the first conductive line 116 may be connected via solder balls.

[0088] In one embodiment, solder balls may be disposed on the bottom surface of the second conductive trace 118 , and the chip package structure 10 may be connected to the substrate via the solder balls.

[0089] Figure 5 is a schematic diagram of a chip packaging structure provided in one embodiment of the present application. Figure 6 is a schematic diagram of a first packaging unit in the embodiment shown in Figure 5 .

[0090] In conjunction with Figure 2 , referring to Figures 5 and 6 , in one embodiment, the first die encapsulation layer L2 does not include a protective structure, and the entire bottom surface of the first sealing structure 113 is flush with the passive surface S2 of the first die 111. This solution helps save steps in the manufacturing process and reduces manufacturing difficulty. In one embodiment, the first conductive structure 112 in the first die encapsulation layer L2 penetrates the first sealing structure 113, with a portion of the first conductive structure 112 extending from the second surface S5 of the first sealing structure 113, and a portion of the first conductive structure 112 is located within the second substrate 117 of the second redistribution layer L3. In this embodiment, part of the first conductive structure 112 is located in the second substrate 117, and part of the silicon-through via 1113 is located in the second substrate 117, so that the top surface of the second substrate 117 (the position where the second substrate 117 is combined with the first bare chip packaging layer L2) has the first conductive structure 112 and the silicon-through via 1113 passing through. The first conductive structure 112 and the silicon-through via 1113 can provide structural strength and stability of the combination position between the first bare chip packaging layer L2 and the second redistribution layer L3, and can also improve the stability of signal transmission between the first bare chip packaging layer L2 and the second redistribution layer L3.

[0091] FIG7 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application. In conjunction with FIG5 , refer to FIG7 . In one embodiment, the number of the first bare chips 111 is multiple, and the multiple first bare chips 111 are arranged in parallel, and the adjacent first bare chips 111 are isolated by the first sealing structure 113, and the multiple first bare chips 111 are electrically connected through the first redistribution layer L1 and / or the second redistribution layer L3. In the embodiment shown in FIG7 , the number of the first bare chips 111 is three. In one embodiment, the three first bare chips 111 are an IVR (Integrated Voltage Regulator), an IPD (Integrated Passive Device), and a bridge chip (Bridge Die).

[0092] Figures 8, 9, and 10 are schematic diagrams of a method for manufacturing a chip packaging structure according to one embodiment of the present application. Figures 11, 12, and 13 are schematic diagrams of a method for manufacturing a chip packaging structure according to another embodiment of the present application.

[0093] FIG8 is a schematic diagram of a method for manufacturing a chip packaging structure provided in one embodiment of the present application. Referring to FIG8 , in one embodiment, the method for manufacturing a chip packaging structure includes the following steps.

[0094] Step S101 : providing a prefabricated packaging structure 10P.

[0095] The prefabricated package structure 10P described in step S101 includes a stacked first unit 11P and a second unit 12P. The first unit 11P includes a first redistribution layer L1 and a first die encapsulation layer L2. The first die encapsulation layer L2 includes a first die 111, a first conductive structure 112, a second conductive structure 114, and a first sealing structure 113. In FIG8 , the prefabricated package structure 10P is placed in an inverted orientation. To meet the requirements of the manufacturing process, the first die 111 is placed top-down. The tops (or top surfaces) and bottoms (or bottom surfaces) of the other structures are also placed top-down in the same manner.

[0096] Referring to Figure 8, the first bare chip 111 includes an active surface S1, a passive surface S2, and a side surface S3 connected to the active surface S1 and the passive surface S2. The first sealing structure 113 wraps the active surface S1 and the side surface S3 of the first bare chip 111, and the passive surface S2 is covered with a protective layer 1101. In one embodiment, the material of the protective layer 1101 is DAF (Die Attach Film), and the protective layer 1101 is used to adhere the first bare chip 111 to the glass wafer. The first conductive structure 112 is distributed on the periphery of the side surface S3 and penetrates the first sealing structure 113. In this embodiment, the end face of the bottom end of the first conductive structure 112 is flush with the entire bottom surface of the first sealing structure 113. The second conductive structure 114 is located on the active surface S1 of the first bare chip 111, one end of the second conductive structure 114 is electrically connected to the circuit layer 1112 in the first bare chip 111, and the other end is located on the first surface of the first sealing structure 113. A silicon-through via 1113 is provided in the first bare chip 111, one end of the silicon-through via 1113 is electrically connected to the circuit layer 1112 in the first bare chip 111, and the other end is adjacent to the protective layer 1101; the second unit 12P includes a second bare chip 121 and a third conductive structure 122, part of the third conductive structure 122 is electrically connected to the second bare chip 121 and the second conductive structure 114, and part of the third conductive structure 122 is electrically connected to the second bare chip 121 and the first conductive structure 112.

[0097] In step S102, material is removed to expose the through-silicon via 1113 and the first conductive structure 112. Specifically, part of the material on the bottom surface side of the first die 111 of the first unit 11P and part of the material on the bottom surface side of the first sealing structure 113 are removed, so that the other end of the through-silicon via 1113 extends from the bottom surface of the first die 111 and is exposed, and one end of the first conductive structure 112 extends from the bottom surface of the first sealing structure 113 and is exposed. As shown in FIG8 , in one embodiment, step S102 includes two material removal processes. During the first material removal process, the protective layer 1101 on the bottom surface of the first die 111 is removed, and part of the material on the top of the first conductive structure 112 is also removed. At this time, the through-silicon via 1113 is still inside the first die 111 and has not yet been exposed. The second material removal process uses a pre-grinding and lapping process combined with RIE etching and cleaning processes to partially expose both the first conductive structure 112 and the through-silicon via 1113.

[0098] Step S103: Fabricating a second redistribution layer L3. Specifically, a second redistribution layer is fabricated on the bottom surface of the first sealing structure 113 and the bottom surface of the first die. A second conductive trace 118 is disposed within the second redistribution layer. Portions of the through-silicon vias 1113 extend into the second redistribution layer L3 and are electrically connected to portions of the second conductive trace 118. Portions of the second conductive trace 118 are electrically connected to the first conductive structure 112.

[0099] FIG9 is a schematic diagram of a method for manufacturing a prefabricated package structure 10P according to an embodiment of the present application. Referring to FIG9 , in one embodiment, the method for manufacturing the prefabricated package structure 10P includes the following steps.

[0100] In step S1011, a release layer RL (Release Layer) is applied on the glass wafer 1102. The release layer RL (Release Layer) can be understood as: usually used to temporarily fix or support the chip or other components during the packaging process, and to release or remove it after the packaging is completed. The function of the release layer is to provide temporary connection or fixation during the manufacturing and packaging process for subsequent processing or operation. The release layer is usually made of a material that can be removed under specific conditions (such as heating, light or chemical treatment). During the packaging process, the release layer is placed between the chip or other components and the packaging structure to ensure that they maintain the correct position or shape during the processing. Once the packaging is completed, the release layer can be removed through appropriate processing to expose the final structure of the chip or other components. The use of the release layer can simplify the packaging process, improve production efficiency, and ensure the reliability and stability of the packaging structure.

[0101] Step S1012, forming a first conductive structure 112 on the surface of the release layer RL. In one embodiment, the first conductive structure 112 is formed by electroplating and growing a copper pillar. The height of the copper pillar needs to be greater than the height of the first conductive structure in the chip packaging structure shown in Figure 5. There are multiple copper pillars, and they are arranged around an enclosing space G on the surface of the release layer RL. This enclosing space G is used to accommodate the first bare chip 111. The first bare chip 111 is placed on the glass wafer 1102 in an upright manner. Specifically, the first bare chip 111 is adhered to the surface of the release layer RL through the protective layer 1101, and the first bare chip 111 is located in the enclosing space G. The top surface of the first bare chip 111 has a second conductive structure 114.

[0102] In step S1013, a packaging material is filled to form a first packaging structure 113. The first packaging structure 113 encapsulates the first conductive structure 112, the side surface S3 and active surface S1 of the first die 111, and the second conductive structure 114. Specifically, the packaging material may be epoxy molding compound.

[0103] In step S1014, the first sealing structure 113 is ground to remove a portion of the material of the first sealing structure 113, thereby exposing the top surfaces of the first conductive structure 112 and the second conductive structure 114. In one embodiment, during this process, a portion of the material of the first conductive structure 112 and the second conductive structure 114 is also removed by the grinding process, thereby reducing the height of the first conductive structure 112 and the second conductive structure 114.

[0104] In step S1015, a first redistribution layer L1 is formed on the surface of the first sealing structure 113, and a second unit 12P is formed on the surface of the first redistribution layer L1. Specifically, the second unit 12P is formed by flip-chip molding.

[0105] Step S1016: removing the glass wafer 1102 and the release layer RL. Specifically, the release layer RL is removed by laser removal, and the glass wafer 1102 can be directly removed.

[0106] FIG10 is a schematic diagram of a method for forming a second redistribution layer on the bottom surface of the first sealing structure and the bottom surface of the first die, according to one embodiment of the present application. Referring to FIG10 , in one embodiment, the method for forming the second redistribution layer on the bottom surface of the first sealing structure and the bottom surface of the first die includes the following steps:

[0107] Step S1031 , coating a first protective layer PL1 on the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first die 111 , wherein the first protective layer PL1 covers the exposed portion of the first conductive structure 112 and the through silicon via 1113 ;

[0108] Step S1032 , chemically mechanically polishing the surface of the first protection layer PL1 so that the end surfaces of the first conductive structure 112 and the through silicon via 1113 are exposed;

[0109] Step S1033 , manufacturing a second conductive circuit 118 , wherein one end of the second conductive circuit 118 is respectively connected to the end surface of the first conductive structure 112 and the end surface of the through silicon via 1113 ;

[0110] Step S1034 : applying a second protective layer PL2 , wherein the second protective layer PL2 wraps the second conductive trace 118 , and the other end of the second conductive trace 118 extends out of the second protective layer PL2 .

[0111] In one embodiment, the materials of the first protective layer PL1 and the second protective layer PL2 are both organic materials.

[0112] Referring to FIG. 8 , in one embodiment, before forming the second redistribution layer L3 on the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first die 111, the manufacturing method further includes: performing a pretreatment process on the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first die 111. The pretreatment process includes spraying an organic solution on the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first die 111. The material of the organic solution may include, but is not limited to, DMSO (dimethyl sulfoxide), NMP (n-methylpyrrolidone), DMAC (dimethylacetamide), TMAH (tetramethylammonium hydroxide), acetone, ethanolamine, etc. The organic solution is used to achieve consistency between the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first bare chip 111, so that during the process of making the second redistribution layer, the material of the second substrate 117 can be evenly and synchronously coated on the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first bare chip 111, thereby achieving structural stability at the junction between the second redistribution layer L3 and the first bare chip packaging layer L2.

[0113] The second surface S5 of the first sealing structure 113 and the passive surface S2 of the first bare chip 111 are consistent. It can be understood that through surface treatment processes such as spraying organic solutions, the second surface S5 of the first sealing structure 113 and the passive surface S2 of the first bare chip 111 have similar material adhesion. In the process of coating the organic material, the stability of the combination between the organic material and the second surface S5 of the first sealing structure 113 is similar (allowing a certain range of tolerance) or the same as the stability of the combination between the organic material and the passive surface S2 of the first bare chip 111.

[0114] FIG11 is a schematic diagram of a method for manufacturing a chip packaging structure provided in another embodiment of the present application. Referring to FIG11 , in one embodiment, the method for manufacturing a chip packaging structure includes the following steps.

[0115] Step S201 : providing a prefabricated packaging structure 10P.

[0116] The prefabricated packaging structure 10P provided in this embodiment includes a first unit 11P and a second unit 12P stacked together. The first unit 11P includes a first redistribution layer L1 and a first die packaging layer L2 stacked together. The first die packaging layer L2 includes a first die 111, a first conductive structure 112, a second conductive structure 114, a first sealing structure 113 and a protective structure 119. The first die 111 includes an active surface S1, a passive surface S2 and a substrate connected between the active surface S1 and the passive surface S2. On the side S3, the first sealing structure 113 wraps around the active surface S1 and the side S3 of the first die 111, and the passive surface S2 is covered by a protective layer 1101. The first conductive structure 112 is distributed around the periphery of the side S3 and extends through the first sealing structure 113. The protective structure 119 is partially embedded in the first sealing structure 113 and covers one end of the first conductive structure 112. A portion of the second surface S5 of the first sealing structure 113 is flush with the passive surface S2 of the first die 111. The second conductive structure 114 is located on the active surface S1 of the first die 111. One end of the second conductive structure 114 is electrically connected to the circuit layer 1112 within the first die 111, and the other end is located on the first surface of the first sealing structure 113. A through-silicon via 1113 is provided within the first die 111. One end of the through-silicon via 1113 is electrically connected to the circuit layer 1112 within the first die 111, and the other end is adjacent to the protective layer 1101. The second unit 12P is located on a side of the second conductive structure 114 away from the first bare die 111. The second unit 12P includes a second bare die 121 and a third conductive structure 122. Part of the third conductive structure 122 electrically connects the second bare die 121 and the second conductive structure 114, and part of the third conductive structure 122 electrically connects the second bare die 121 and the first conductive structure 112.

[0117] In step S202, the protective layer covering the bottom surface of the first die 111 and part of the material of the first die 111 are removed, so that the other end of the through silicon via 1113 extends from the bottom surface of the first die 111 and is exposed; part of the material of the first sealing structure 113 and part of the material of the protective structure 119 are simultaneously removed, and the first conductive structure 112 is covered by part of the protective structure 119.

[0118] In step S203, a second redistribution layer L3 is formed on the bottom surface of the first sealing structure 113 and the bottom surface of the first bare chip 111. A second conductive circuit 118 is provided in the second redistribution layer L3. Part of the through silicon via 1113 extends into the second redistribution layer L3 and is electrically connected to part of the second conductive circuit 118. Part of the second conductive circuit 118 extends into the protective structure 119 and is electrically connected to the first conductive structure 112.

[0119] FIG12 is a schematic diagram of a method for manufacturing a prefabricated package structure 10P according to another embodiment of the present application. Referring to FIG12 , in one embodiment, the method for manufacturing the prefabricated package structure 10P includes the following steps.

[0120] In step S2011, a release layer RL (Release Layer) is coated on the glass wafer 1102, and a protective structure 119 is formed on the surface of the release layer RL. In one embodiment, the protective structure 119 is formed by coating the surface of the release layer RL with an organic material (e.g., polyimide (PI)). There are multiple protective structures 119, which are arranged in sequence and surround an enclosing space G.

[0121] In step S2012 , a first conductive structure 112 is formed on the surface of the protection structure 119 , and the first die 111 is assembled on the surface of the release layer RL and located within the surrounding space G. The active surface S1 of the first die 111 has a second conductive structure 114 .

[0122] In step S2013, the packaging material is filled to form a first packaging structure 113. The first packaging structure 113 encapsulates the protection structure 119, the first conductive structure 112, the side surface S3 and the active surface S1 of the first die 111, and the second conductive structure 114. Specifically, the packaging material can be epoxy molding compound.

[0123] In step S2014, the first sealing structure 113 is ground to remove a portion of the material of the first sealing structure 113, thereby exposing the top surfaces of the first conductive structure 112 and the second conductive structure 114. In one embodiment, during this process, a portion of the material of the first conductive structure 112 and the second conductive structure 114 is also removed by the grinding process, thereby reducing the height of the first conductive structure 112 and the second conductive structure 114.

[0124] In step S2015, a first redistribution layer L1 is formed on the surface of the first sealing structure 113, and a second unit 12P is formed on the surface of the first redistribution layer L1. Specifically, the second unit 12P is formed by flip-chip molding.

[0125] In step S2016, the glass wafer 1102 and the release layer RL are removed. Specifically, the release layer RL is removed by laser removal, and the glass wafer 1102 can be directly removed.

[0126] FIG13 is a schematic diagram of a method for forming a second redistribution layer on the bottom surface of the first sealing structure and the bottom surface of the first die, according to one embodiment of the present application. Referring to FIG13 , in one embodiment, the method for forming the second redistribution layer on the bottom surface of the first sealing structure and the bottom surface of the first die includes the following steps:

[0127] In step S2031 , a first protective layer PL1 is applied on the second surface S5 of the first sealing structure 113 , the surface of the protection structure 119 , and the passive surface S2 of the first die 111 . The first protective layer PL1 covers the exposed portion of the through silicon via 1113 .

[0128] Step S2032 : performing chemical mechanical polishing on the surface of the first protection layer PL1 so that the end surface of the through silicon via 1113 is exposed.

[0129] In step S2033 , a portion of the first protective layer PL1 and the protective structure 119 corresponding to the first conductive structure 112 is removed to form a groove 1191 , so that at least a portion of the end surface of the first conductive structure 112 is exposed at the bottom of the groove 1191 .

[0130] Step S2034 , forming a second conductive circuit 118 , wherein one end of a portion of the second conductive circuit 118 is located in the groove 1191 and connected to the first conductive structure 112 , and one end of the second conductive circuit 118 is connected to an end surface of the through silicon via 1113 .

[0131] Step S2035 : applying a second protective layer PL2 , wherein the second protective layer PL2 wraps the second conductive trace 118 , and the other end of the second conductive trace 118 extends out of the second protective layer PL2 .

[0132] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: The method comprises a first packaging unit and a second packaging unit which are stacked, wherein the first packaging unit comprises a first redistribution layer, a first die packaging layer and a second redistribution layer which are stacked, The first die packaging layer includes a first die, a first conductive structure, a second conductive structure, and a first sealing structure, wherein the first die includes an active surface, a passive surface opposite to the active surface, and a side surface connected between the active surface and the passive surface, the first sealing structure partially wraps the first die, the first sealing structure includes a first surface and a second surface opposite to each other, the first conductive structure is distributed around the side surface of the first die and penetrates the first surface and the second surface, the second conductive structure is at least partially located between the active surface and the first surface of the first die and electrically connected to a circuit layer within the first die, the first die includes a through silicon via, one end of the through silicon via is electrically connected to the circuit layer within the first die, and the other end extends from the passive surface of the first die; The first redistribution layer is located between the second packaging unit and the first bare die packaging layer, the first redistribution layer is used to electrically connect the second bare die in the second packaging unit and the first conductive structure, and the first redistribution layer is also used to electrically connect the second bare die and the second conductive structure; The second redistribution layer is located on a side of the first die packaging layer away from the first redistribution layer. Part of the through silicon via extends into the second redistribution layer. The second redistribution layer is electrically connected to the through silicon via and the first conductive structure.

2. The chip packaging structure according to claim 1, wherein: The first die packaging layer further includes a protection structure, wherein a portion of the protection structure is embedded in the first sealing material structure and covers one end of the first conductive structure; a portion of the second surface is flush with the passive surface of the first die.

3. The chip packaging structure according to claim 1, wherein: All of the second surfaces are flush with the inactive surface of the first die.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The second redistribution layer includes a second substrate and a second conductive circuit embedded in the second substrate, the second substrate covers the second surface and the passive surface of the first bare chip, one end of a portion of the second conductive circuit is located inside the second substrate, and the other end extends out of the surface of the second substrate facing away from the first bare chip packaging layer, and the silicon through-via extends from the surface of the second substrate adjacent to the first bare chip packaging layer into the interior of the second substrate and connects the second conductive circuit.

5. The chip packaging structure according to claim 2, wherein: The second redistribution layer includes a second substrate and a second conductive circuit embedded in the second substrate, wherein the second substrate covers the protection structure, a portion of the second surface, and the passive surface of the first die; one end of a portion of the second conductive circuit is located inside the second substrate, and the other end extends out of a surface of the second substrate facing away from the first die packaging layer; the through silicon via extends from a surface of the second substrate adjacent to the first die packaging layer into the interior of the second substrate and connects to the corresponding second conductive circuit; Both ends of a portion of the second conductive traces extend out of the second substrate. A portion of the second conductive traces extends from a surface of the second substrate adjacent to the first die packaging layer, passes through the protection structure, and is connected to the first conductive structure.

6. The chip packaging structure according to claim 4 or 5, characterized in that: The dielectric constant of the second substrate is less than or equal to 3.

4.

7. The chip packaging structure according to claim 6, wherein: The material of the second substrate is any one or a combination of at least two of epoxy resin material (EMC), photosensitive polyimide (PSPI), polyimide (PI), photosensitive polybenzoxazole (PSPBO), polybenzoxazole (PBO), photosensitive benzocyclobutene (PSBCB), and benzocyclobutene (BCB).

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: There are multiple first dies, which are arranged in parallel and isolated from each other by the first sealing structure. The multiple first dies are electrically connected to each other by the first redistribution layer and / or the second redistribution layer.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The number of the second bare chips is at least two, and the second packaging unit further includes a second sealing structure and a circuit layer. The circuit layer includes a bottom filler and a third conductive structure. The bottom filler wraps the third conductive structure and connects the second bare chips. The second sealing structure at least wraps the second bare chip.

10. A chip, characterized in that: The invention comprises a substrate and the chip packaging structure according to any one of claims 1 to 9, wherein the chip packaging structure is arranged on the substrate.

11. An electronic device, characterized in that: The device comprises a circuit board and the chip according to claim 10, wherein the chip is arranged on the circuit board.

12. A method for manufacturing a chip packaging structure, characterized in that: include: A prefabricated packaging structure is provided, wherein the prefabricated packaging structure includes a first unit and a second unit stacked together. The first unit includes a first redistribution layer and a first die packaging layer arranged in a stacked manner, the first die packaging layer includes a first die, a first conductive structure, a second conductive structure, and a first sealing structure, the first die includes an active surface, a passive surface opposite to the active surface, and a side surface connected between the active surface and the passive surface, the first sealing structure partially wraps the first die, the passive surface is covered with a protective layer, the first conductive structure is distributed around the side surface and penetrates the first sealing structure, the first sealing structure includes a first surface and a second surface arranged opposite to each other, all of the second surfaces are flush with the passive surface, the second conductive structure is at least partially located between the active surface and the first surface of the first die and is electrically connected to a circuit layer in the first die, a through silicon via is provided in the first die, one end of the through silicon via is electrically connected to the circuit layer in the first die, and the other end is adjacent to the protective layer; The second unit is located on a side of the second conductive structure away from the first die, the second unit includes a second die and a third conductive structure, a portion of the third conductive structure is electrically connected to the second die and the second conductive structure, and a portion of the third conductive structure is electrically connected to the second die and the first conductive structure; removing the protective layer covering the passive surface of the first die and a portion of the material of the first die, so that the other end of the through silicon via extends out from the passive surface and is exposed; removing a portion of material on one side of the second surface of the first sealing structure so that one end of the first conductive structure extends out from the second surface and is exposed; A second redistribution layer is formed on the second surface of the first sealing structure and the passive surface of the first die. Part of the through silicon via extends into the second redistribution layer. The second redistribution layer electrically connects the through silicon via and the first conductive structure.

13. The method for manufacturing a chip packaging structure according to claim 12, wherein: The method of fabricating a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die includes: Coating a first protective layer on the second surface and the passive surface, wherein the first protective layer covers the exposed portion of the first conductive structure and the through silicon via; Performing chemical mechanical polishing on the surface of the first protective layer so that the end surfaces of the first conductive structure and the through silicon via are exposed; Fabricating a second conductive circuit, wherein one end of the second conductive circuit is respectively connected to the first conductive structure and an end surface of the through silicon via; A second protective layer is applied, wherein the second protective layer wraps the second conductive circuit, and the other end of the second conductive circuit extends out of the second protective layer.

14. The method for manufacturing a chip packaging structure according to claim 13, wherein: The materials of the first protective layer and the second protective layer are both organic materials.

15. The method for manufacturing a chip packaging structure according to claim 12, wherein: Before the step of forming a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die, the manufacturing method further includes: An organic solution is sprayed on the second surface and the passive surface, and the organic solution is used to achieve consistency between the second surface and the passive surface.

16. A method for manufacturing a chip packaging structure, characterized in that: include, A prefabricated packaging structure is provided, wherein the prefabricated packaging structure includes a first unit and a second unit stacked together. The first unit includes a first redistribution layer and a first die packaging layer arranged in a stacked manner, the first die packaging layer including a first die, a first conductive structure, a second conductive structure, a first sealing structure and a protective structure, the first die including an active surface, a passive surface opposite to the active surface, and a side surface connected between the active surface and the passive surface, the first sealing structure partially wraps the first die, the passive surface covers the protective layer, the first conductive structure is distributed around the periphery of the side surface and penetrates the first sealing structure, the protective structure is partially embedded in the first sealing structure and covers one end of the first conductive structure; a portion of the second surface is flush with the passive surface, the second conductive structure is at least partially located between the active surface and the first surface of the first die and is electrically connected to a circuit layer in the first die, a through silicon via is provided in the first die, one end of the through silicon via is electrically connected to the circuit layer in the first die, and the other end is adjacent to the protective layer; The second unit is located on a side of the second conductive structure away from the first die, the second unit includes a second die and a third conductive structure, a portion of the third conductive structure is electrically connected to the second die and the second conductive structure, and a portion of the third conductive structure is electrically connected to the second die and the first conductive structure; removing the protective layer and a portion of the material of the first die covering the passive surface, so that the other end of the through silicon via extends out from the passive surface and is exposed; Simultaneously removing a portion of the material of the first sealing structure and a portion of the material of the protective structure, so that the first conductive structure is partially covered by the protective structure; A second redistribution layer is formed on the second surface and the passive surface, a portion of the through silicon via extends into the second redistribution layer, and the second redistribution layer is electrically connected to the through silicon via and the first conductive structure.

17. The method for manufacturing a chip packaging structure according to claim 16, wherein: The method of forming a second redistribution layer on the second surface of the first sealing structure and the passive surface of the first die includes: Coating a first protective layer on the second surface, the surface of the protective structure and the passive surface, wherein the first protective layer covers the exposed portion of the through silicon via; Performing chemical mechanical polishing on the surface of the first protective layer so that the end surface of the through silicon via is exposed; Removing part of the first protective layer and part of the material of the protective structure corresponding to the first conductive structure to form a groove, so that at least part of the end surface of the first conductive structure is exposed at the bottom of the groove; Fabricating a second conductive circuit, wherein one end of a portion of the second conductive circuit is located in the groove and connected to the first conductive structure, and one end of the second conductive circuit is connected to an end surface of the through-silicon via; A second protective layer is applied, wherein the second protective layer wraps the second conductive circuit, and the other end of the second conductive circuit extends out of the second protective layer.

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