Inter-process communication method and apparatus, and electronic device, storage medium and computer program product

Abstract

Provided in the present disclosure are an inter-process communication method and apparatus, and an electronic device, a storage medium and a computer program product. The method comprises: setting different priorities for different IPC channels in a configuration table; and in response to an interrupt signal sent by a transmitting-end core, reading messages from message queues of the corresponding IPC channels in descending order of the priorities. In the solution of the present disclosure, a receiving-end core sets different priorities for different IPC channels in a configuration table, and a transmitting-end core acquires the priority of each message required to be sent to the receiving-end core; the transmitting-end core writes the messages into message queues of the IPC channels of the corresponding priorities, and sends an interrupt signal to the receiving-end core; and in response to the interrupt signal sent by the transmitting-end core, the receiving-end core may read a message, which has the highest priority, from the message queues of the corresponding IPC channels in descending order of the priorities, such that messages with high priorities can be preferentially processed by the receiving-end core.

Description

Inter-core communication method, device, electronic device, storage medium and computer program product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on March 19, 2024, with application number 202410317413.6 and application name “Inter-core communication method, device, electronic device and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of inter-core communication technology, and is related to, but not limited to, an inter-core communication method, device, electronic device, storage medium, and computer program product. Background Art

[0004] In the current inter-core communication technology, take the sending core sending a message to the receiving core as an example:

[0005] Both the sending and receiving kernels have built-in configuration tables, which mainly configure relevant parameters for different inter-process communication (IPC) channels. During the application process, the sending and receiving kernels establish an IPC channel by statically modifying the channel priority parameters in the configuration table. The sending kernel then writes the message to be transmitted into the message queue of the IPC channel, modifies the write index of the control block, and triggers an interrupt to send a terminal signal to the receiving kernel to notify the receiving kernel. After receiving the interrupt signal, the receiving kernel reads a message from the message queue of the IPC channel, modifies the read index of the control block, and then continues to process the next message in the IPC channel.

[0006] In the above inter-core communication scheme, messages are processed one by one according to the first-in, first-out principle of the message queue. If the sending core sends a higher-priority message that needs to be passed to the receiving core for processing, the higher-priority message will have to wait in the queue according to the first-in, first-out principle of the message queue and will not be processed by the receiving core first. Summary of the Invention

[0007] The present disclosure provides an inter-core communication method, apparatus, electronic device, storage medium, and computer program product.

[0008] According to a first aspect of the present disclosure, there is provided an inter-core communication method, comprising:

[0009] Set different priorities for different IPC channels in the configuration table, which is a preset configuration table for different IPC channels;

[0010] In response to the interrupt signal sent by the sending end core, the message is read from the message queue of the corresponding IPC channel in descending order of priority; the interrupt signal is used to indicate that the sending end core has completed writing the message to the message queue of the corresponding IPC channel.

[0011] In some embodiments of the present disclosure, in response to an interrupt signal sent by a sending-end kernel, reading messages from a message queue of a corresponding IPC channel in descending order of priority includes:

[0012] In response to an interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, obtain queue information in the message queue of the highest priority IPC channel in order of priority, where the queue information includes at least a queue head address, a read index, and a write index;

[0013] Read the message in the queue address indicated by the read index and the queue first address;

[0014] Update the read index using the read index incremented by 1 to obtain the updated read index;

[0015] Read the message in the queue address indicated by the updated read index and queue first address;

[0016] Determine whether the read index and write index are the same;

[0017] If the judgment result is yes, the message is read from the message queue of the IPC channel except the one with the highest priority in descending order of priority.

[0018] In some embodiments of the present disclosure, in response to an interrupt signal sent by a sending-end kernel, reading messages from a message queue of a corresponding IPC channel in descending order of priority includes:

[0019] In response to the interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, read the message from the message queue of the corresponding IPC channel in order of priority;

[0020] During the message reading process, if a new interrupt signal sent by the sending end kernel is obtained, it is determined whether the IPC channel associated with the new interrupt signal is marked with the priority ignored;

[0021] If the judgment result is no, read the message from the message queue of the corresponding IPC channel in descending order of priority.

[0022] According to a second aspect of the present disclosure, there is provided an inter-core communication method, comprising:

[0023] Obtaining the priority of each message in at least one message that needs to be sent to the receiving end kernel;

[0024] Write the message to the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving end kernel; the interrupt signal is used to enable the receiving end kernel to read the messages from the message queue of the corresponding IPC channel in descending order of priority.

[0025] In some embodiments of the present disclosure, writing a message to a message queue of an IPC channel of a corresponding priority includes:

[0026] Get the queue information of the message queue of the IPC channel corresponding to the message priority. The queue information includes at least the queue head address and write index.

[0027] Write the message to the queue address indicated by the write index and the queue first address;

[0028] Update the write index using the write index that has been incremented by 1.

[0029] In some embodiments of the present disclosure, after writing each message into the message queue of the IPC channel of the corresponding priority, the inter-core communication method provided by the present disclosure further includes:

[0030] In response to a new message that needs to be sent to the receiving end kernel, obtaining a priority corresponding to the new message;

[0031] Write the new message into the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving kernel.

[0032] In some embodiments of the present disclosure, sending an interrupt signal to a receiving-end core includes:

[0033] Determine whether the receiving core and the sending core belong to the same processor;

[0034] If the judgment result is yes, a software-triggered interrupt type interrupt signal is sent to the receiving end kernel;

[0035] If the judgment result is no, a shared peripheral interrupt type interrupt signal is sent to the receiving end core.

[0036] According to a third aspect of the present disclosure, an inter-core communication apparatus is provided, which is applied to a receiving-end core and includes:

[0037] The setting part is used to set different priorities for different IPC channels in the configuration table, and the configuration table is a preset configuration table for different IPC channels;

[0038] The reading part is used to respond to the interrupt signal sent by the sending end core and read the message from the message queue of the corresponding IPC channel in order of priority from high to low; the interrupt signal is used to indicate that the sending end core has completed writing the message to the message queue of the corresponding IPC channel.

[0039] According to a fourth aspect of the present disclosure, an inter-core communication apparatus is provided, which is applied to a sending-end kernel and includes:

[0040] An acquisition part, used for acquiring the priority of each message in at least one message that needs to be sent to the receiving end core;

[0041] The writing part is used to write the message into the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving end kernel; the interrupt signal is used to enable the receiving end kernel to read the message from the message queue of the corresponding IPC channel in descending order of priority.

[0042] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0043] at least one processor; and

[0044] a memory communicatively coupled to the at least one processor;

[0045] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any possible method in the first aspect or the second aspect.

[0046] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, where the computer instructions are used to enable a computer to execute any possible method of the first aspect or the second aspect.

[0047] According to a seventh aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions or a computer program, which, when executed by a processor, can implement any possible method in the aforementioned first aspect or second aspect.

[0048] The present disclosure provides an inter-core communication method, device, electronic device, storage medium and computer program product. The inter-core communication method includes: the receiving end core sets different priorities for different IPC channels in the configuration table, and the configuration table is a preset configuration table of different IPC channels; the sending end core obtains the priority of each message in at least one message that needs to be sent to the receiving end core; writes the message into the message queue of the IPC channel of the corresponding priority, and sends an interrupt signal to the receiving end core; the interrupt signal is used to enable the receiving end core to read the message from the message queue of the corresponding IPC channel in order of priority from high to low. The receiving end core responds to the interrupt signal sent by the sending end core and reads the message from the message queue of the corresponding IPC channel in order of priority from high to low; the interrupt signal is used to indicate that the sending end core has completed writing the message to the message queue of the corresponding IPC channel.

[0049] According to the solution disclosed in the present invention, different priorities are set for different IPC channels in the configuration table by the receiving-end kernel, and the sending-end kernel obtains the priority of each message in at least one message that needs to be sent to the receiving-end kernel; the message is written into the message queue of the IPC channel of the corresponding priority, and an interrupt signal is sent to the receiving-end kernel; the receiving-end kernel responds to the interrupt signal sent by the sending-end kernel, and can read the highest priority message from the message queue of the corresponding IPC channel in order from high to low priority, so that the high-priority message can be processed first by the receiving-end kernel.

[0050] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0052] FIG1 is a schematic diagram of a flow chart of a first inter-core communication method provided by an embodiment of the present disclosure;

[0053] FIG2 is a schematic diagram of a flow chart of a second inter-core communication method provided in an embodiment of the present disclosure;

[0054] FIG3 is a schematic structural diagram of a first inter-core communication device provided by an embodiment of the present disclosure;

[0055] FIG4 is a schematic structural diagram of a second inter-core communication device provided by an embodiment of the present disclosure;

[0056] FIG5 is a flow chart of an inter-core communication method provided by an application example of the present disclosure;

[0057] FIG6 is a schematic diagram of a multi-priority message processing process of a receiving end kernel provided by an application example of the present disclosure;

[0058] FIG7 is a schematic block diagram of an example electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0060] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present application, not all of the embodiments.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0062] In order to facilitate those skilled in the art to better understand the technical solutions described in the embodiments of the present disclosure, before introducing the embodiments of the present disclosure, a brief introduction to the relevant terms in this application is first given:

[0063] Inter-core communication / inter-process communication: In this application, it refers to the mechanism for different processor cores / processes to pass messages and share resources.

[0064] Mailbox interrupt: In this application, it refers to an IPC implementation based on hardware-specific memory access, which is mostly used for lightweight data communication (such as control information) between on-chip processors. It has the advantages of good real-time performance, high communication efficiency, and a wide range of applications. It is often used as an effective solution for heterogeneous core communication in real-time vehicle systems.

[0065] System on Chip (SoC): In this application, it refers to a dedicated integrated circuit product that includes a complete operating system and embedded software.

[0066] First In First Out (FIFO): in this application, it refers to a first-in-first-out data storage buffer.

[0067] An inter-core communication method provided by an embodiment of the present disclosure can be applied to a file system for managing a flash memory device. The execution subject of the method can be a file system or a file management module in an operating system kernel.

[0068] As shown in FIG1 , the first inter-core communication method provided by the embodiment of the present disclosure is executed by a receiving end of the inter-core communication. The method includes the following steps:

[0069] Step 101, setting different priorities for different IPC channels in a configuration table, where the configuration table is a preset configuration table for different IPC channels;

[0070] In one embodiment, the IPC channel refers to a channel for data communication between a sending-end core and a receiving-end core.

[0071] In one embodiment, both the sending end core and the receiving end core have a configuration table, and the configuration table is used to configure the priority, interrupt type, etc. for the IPC channel.

[0072] In one embodiment, the receiving end kernel sets different priorities for different IPC channels in the configuration table.

[0073] In one embodiment, the configuration table includes information such as channel ID, reverse channel ID, channel type, channel priority, buffer queue size, and first address.

[0074] In one embodiment, different IPC channels correspond to different channel IDs.

[0075] In one embodiment, different priorities may be set for different IPC channels in the configuration table by changing the channel priority parameters corresponding to different IPC channels in the configuration table.

[0076] In one embodiment, different priorities are set for different IPC channels in the configuration table in a static configuration manner.

[0077] In one embodiment, the channel type is used to indicate the type of interruption that triggers the message notification.

[0078] In one embodiment, the channel types include software-triggered interrupt types (such as software-generated interrupts (SGI)) and shared peripheral interrupt types (such as mailbox interrupts).

[0079] In one embodiment, multiple priority levels can be set according to the needs of the message to be sent. If the priority level of the message to be sent is relatively low, a relatively low priority level can be roughly divided; if the priority level of the message to be sent is relatively high, a relatively high priority level can be further divided.

[0080] In one embodiment, the priority of the IPC channel is used to indicate the order in which messages in different IPC channels are sent, and messages in IPC channels with higher priorities are processed first.

[0081] In one embodiment, only one IPC channel is configured in the configuration table, or the channel priority is not set for a certain IPC channel, that is, when it is configured to read information of different priorities, the specific configuration in the corresponding configuration table may be the reading priority order of the read messages.

[0082] Step 102: In response to the interrupt signal sent by the sending end kernel, read the message from the message queue of the corresponding IPC channel in descending order of priority;

[0083] In one embodiment, the message may be control information, status information, image information, voice information, etc.

[0084] In one embodiment, an interrupt signal is used to indicate that the sending core has completed writing a message to the message queue of the corresponding IPC channel. The interrupt signal can be a software-triggered interrupt signal or a shared peripheral interrupt signal. The interrupt signal type is determined by the sending core's determination of the attributes of the sending core and the receiving core.

[0085] In one embodiment, the interrupt signal may be sent by an interrupt controller of the sending-end core.

[0086] In one embodiment, when the configuration table includes multiple IPC channels with different priorities, each interrupt signal may correspond to one IPC channel.

[0087] In one embodiment, the IPC channel corresponding to the interrupt signal sent by the sending end kernel is obtained, the message queue of the current IPC channel and all message queues with higher priorities than the current IPC channel are traversed, and the message with the highest priority is read.

[0088] The inter-core communication method provided by the embodiment of the present disclosure includes: setting different priorities for different IPC channels in a configuration table, where the configuration table is a preset configuration table of different IPC channels; responding to an interrupt signal sent by a sending-end core, reading messages from the message queue of the corresponding IPC channel in descending order of priority; the interrupt signal is used to indicate that the sending-end core has completed writing messages to the message queue of the corresponding IPC channel.

[0089] According to the solution disclosed in the present invention, different priorities are set for different IPC channels in the configuration table by the receiving-end kernel, and the sending-end kernel obtains the priority of each message in at least one message that needs to be sent to the receiving-end kernel; the message is written into the message queue of the IPC channel of the corresponding priority, and an interrupt signal is sent to the receiving-end kernel; the receiving-end kernel responds to the interrupt signal sent by the sending-end kernel, and can read the highest priority message from the message queue of the corresponding IPC channel in order from high to low priority, so that the high-priority message can be processed first by the receiving-end kernel.

[0090] In Example 1, in a scenario where multiple IPC channels of different priority levels are configured for a configuration table, in response to an interrupt signal sent by the sending end kernel, messages are read from the message queue of the corresponding IPC channel in descending order of priority, including:

[0091] In response to an interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, queue information in the message queue of the highest priority IPC channel is obtained in order of priority;

[0092] In one embodiment, the queue information includes at least a queue head address, a read index, and a write index.

[0093] In one embodiment, the queue information of the message queue of the IPC channel is usually stored in the control block of the IPC channel.

[0094] In one embodiment, the queue first address is used to indicate the address of the first message in the current message queue.

[0095] In one embodiment, the read index is used to indicate index information of a message to be read, that is, an offset based on the first address of the queue.

[0096] In one embodiment, the write index is used to indicate index information of a message that needs to be written.

[0097] Read the message in the queue address indicated by the read index and the queue first address;

[0098] In one embodiment, after reading the message in the queue address indicated by the read index and the queue head address, the read message is passed to the IPC callback function registered in the control block for processing.

[0099] Update the read index using the read index incremented by 1 to obtain the updated read index;

[0100] In one embodiment, the updated read index is used to indicate index information of a message that needs to be read next in the current priority message queue.

[0101] In one embodiment, by updating the read index with a read index that is incremented by 1, the messages in the current priority message queue can be read in sequence.

[0102] Read the message in the queue address indicated by the updated read index and queue first address;

[0103] In one embodiment, the message in the queue address indicated by the updated read index and the queue first address is adjacent to the message in the queue address indicated by the read index and the queue first address before the update.

[0104] Determine whether the read index and write index are the same;

[0105] In one embodiment, when the read index and the write index are the same, it indicates that the message queue is empty, that is, there is no message in the message queue.

[0106] If the judgment result is yes, the message is read from the message queue of the IPC channel except the one with the highest priority in descending order of priority.

[0107] In one embodiment, if the read index and the write index are the same, it means that the messages in the message queue of the highest priority IPC channel have been read, and it is necessary to read messages from the message queue of the IPC channel other than the highest priority IPC channel.

[0108] In one embodiment, if the read index and the write index are different, the message is continued to be read from the message queue of the highest priority IPC channel.

[0109] It should be noted that Example 1 and steps 101 to 102 can be implemented in combination.

[0110] In Example 2, when only one IPC channel is configured in the configuration table, or when no channel priority is set for a certain IPC channel, that is, when it is configured to read information of different priorities, the corresponding configuration table may specifically configure a read priority order for reading messages. In this scenario, step 102 includes:

[0111] In response to the interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, read the message from the message queue of the corresponding IPC channel in order of priority;

[0112] In one embodiment, the interrupt signal is used to indicate that there is a new message written into the message queue.

[0113] In one embodiment, after each message is read, it is necessary to traverse all addresses in the message queue of each IPC channel in descending order of priority, and read the message in the address with the highest priority.

[0114] During the message reading process, if a new interrupt signal sent by the sending end kernel is obtained, it is determined whether the IPC channel associated with the new interrupt signal is marked with the priority ignored;

[0115] In one embodiment, the interrupt controller of the receiving-end core may obtain the new interrupt signal sent by the transmitting-end core.

[0116] In one embodiment, the processor used by the receiving core may be the same as or different from that used by the transmitting core.

[0117] In one embodiment, the IPC channel associated with the new interrupt signal refers to the IPC channel that receives the new interrupt signal.

[0118] In one embodiment, the tag-ignored priority refers to the IPC channel untagged priority.

[0119] In one embodiment, if the IPC channel tag associated with the interrupt signal ignores the priority, it does not conform to the application scenario of the inter-core communication method proposed in the present disclosure.

[0120] If the judgment result is no, read the message from the message queue of the corresponding IPC channel in descending order of priority.

[0121] In one embodiment, if the IPC channel associated with the interrupt signal is not marked to ignore priority, that is, the priority of the IPC channel is marked, it meets the application scenario of the inter-core communication method proposed in the present disclosure, and it is necessary to obtain the message in the first address of the message queue of the IPC channel with the highest priority in order from high to low priority of the IPC channel.

[0122] It should be noted that Example 2 can be implemented in combination with steps 101 to 102. In some special application scenarios, for example, when the configuration table includes IPC channels of different priorities and also includes IPC channels marked to ignore priority, Example 1, Example 2 and steps 102 to 102 can also be implemented in combination. The specific implementation can be determined by actual conditions and is not specifically limited here.

[0123] As shown in FIG2 , the second inter-core communication method provided by the embodiment of the present disclosure is executed by the sending core of the inter-core communication. The method includes the following steps:

[0124] Step 201, obtaining the priority of each message in at least one message to be sent to the receiving end kernel;

[0125] In one embodiment, the priorities of multiple messages in at least one message may be the same or different.

[0126] In one embodiment, the priority of each message in at least one message that needs to be sent to the receiving end kernel may be obtained by setting a priority parameter in RabbitMQ.

[0127] Step 202: Write the message into the message queue of the IPC channel of the corresponding priority, and send an interrupt signal to the receiving end kernel; the interrupt signal is used to enable the receiving end kernel to read the messages from the message queue of the corresponding IPC channel in descending order of priority.

[0128] In one embodiment, when the IPC channel is marked to ignore priority, messages in the message queue of the IPC channel may be read according to a first-in-first-out principle.

[0129] In one embodiment, when the IPC channel is not marked to ignore priority, messages in the message queue of the IPC channel may be read in order of priority.

[0130] In embodiment 3, writing a message into a message queue of an IPC channel of a corresponding priority level includes:

[0131] Get the queue information of the message queue of the IPC channel corresponding to the message priority;

[0132] In one embodiment, the queue information includes at least a queue head address and a write index.

[0133] In one embodiment, an IPC channel corresponding to the message priority is obtained. For example, if there are three IPC channels with high, medium and low priorities, message 1 is a very urgent message and belongs to the high-priority IPC channel. Message 4 is a generally urgent message and belongs to the medium-priority IPC channel. Message 7 is a non-urgent message and belongs to the low-priority IPC channel.

[0134] In one embodiment, the queue information of the message queue of the IPC channel corresponding to the message priority is obtained, including at least the queue first address and the write index, that is, the queue information of the message queue of the IPC channel corresponding to the message priority in the aforementioned embodiment is obtained, such as the queue information of the message queue of the high-priority IPC channel corresponding to the priority of message 1, including at least the queue first address and the write index.

[0135] Write the message to the queue address indicated by the write index and the queue first address;

[0136] In one embodiment, the queue address of the message queue is limited and may be 100 or 1000, which is not limited in the present disclosure.

[0137] In one embodiment, the message is written into the message queue of the IPC channel corresponding to the message priority, into the queue address indicated by the write index and the queue head address.

[0138] Update the write index using the write index that has been incremented by 1.

[0139] In one embodiment, the updated write index is used to indicate index information of a message to be written to the message queue of the current priority IPC channel next time.

[0140] It should be noted that Example 3 can be implemented in combination with steps 201 to 202.

[0141] In embodiment 4, after writing the message into the message queue of the IPC channel of the corresponding priority, the inter-core communication method further includes:

[0142] In response to a new message that needs to be sent to the receiving end kernel, obtaining a priority corresponding to the new message;

[0143] In one embodiment, the new message is a message newly written into the message queue by the sending kernel.

[0144] In one embodiment, there may be one or more new messages.

[0145] Write the new message into the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving kernel.

[0146] In one embodiment, after receiving the interrupt signal, the receiving end kernel will re-traverse the message queues of all IPC channels and obtain the message in the message queue with the highest current priority.

[0147] It should be noted that Example 4 can be implemented in combination with steps 201 to 202; Example 4 can also be combined with Example 3 and implemented in combination with steps 201 to 202. The specific combination process can be implemented by the actual application scenario and is not specifically limited here.

[0148] In embodiment 5, sending an interrupt signal to the receiving end core includes:

[0149] Determine whether the receiving core and the sending core belong to the same processor;

[0150] In one embodiment, the processor information of the receiving-end core and the transmitting-end core may be obtained from configuration information related to the receiving-end core and the transmitting-end core.

[0151] If the judgment result is yes, a software-triggered interrupt type interrupt signal is sent to the receiving end kernel;

[0152] In one embodiment, the software-triggered interrupt type interrupt signal refers to an interrupt signal generated by software by writing into a dedicated register.

[0153] If the judgment result is no, a shared peripheral interrupt type interrupt signal is sent to the receiving end core.

[0154] In one embodiment, the shared peripheral interrupt type interrupt signal refers to an interrupt signal sent by an external device accessible to the system.

[0155] In one embodiment, the external device may be a keyboard, a network adapter, a hard disk drive, or the like.

[0156] In one embodiment, the shared peripheral interrupt type interrupt signal may be level triggered or edge triggered.

[0157] In one embodiment, a Mailbox may be used to generate a shared peripheral interrupt type interrupt signal.

[0158] It should be noted that Example 5 can be implemented in combination with steps 201 to 202; Example 5 can also be implemented in combination with Example 4 and steps 201 to 202; Example 5 can also be implemented in combination with Example 3 and Example 4 and steps 201 to 202. The specific implementation process can be determined by the actual application scenario and is not specifically limited here.

[0159] According to the solution of this disclosure:

[0160] First, the receiving-end kernel sets different priorities for different IPC channels in the configuration table, and the sending-end kernel obtains the priority of each message in at least one message that needs to be sent to the receiving-end kernel; the message is written into the message queue of the IPC channel of the corresponding priority, and an interrupt signal is sent to the receiving-end kernel; the receiving-end kernel responds to the interrupt signal sent by the sending-end kernel, and reads the highest-priority message from the message queue of the corresponding IPC channel in descending order of priority, so that the high-priority message can be processed first by the receiving-end kernel.

[0161] Secondly, in the order of message priority, the highest priority message is written to the first address of the message queue of the IPC channel of the corresponding priority. Considering that the message queue reads and writes messages according to the first-in-first-out principle, higher priority messages can be written at the front of the message queue to facilitate the reading of high priority messages first.

[0162] The inter-core communication method disclosed in the present invention is further described below with a specific application example. Correspondingly, the scenario of this embodiment can be: there is a need to transmit messages of different urgency between two cores, and multiple IPC channels can be statically configured between the two cores, and these channels can be marked with different priority levels, wherein the multiple IPC channels can be obtained by flexibly dividing the priority levels according to business needs, that is, if N levels are subdivided, at least N IPC channels need to be established; if there is no such need, only one IPC channel can be configured, or multiple IPC channels can be marked with the same priority level or marked to ignore priority, but messages of different priorities can be transmitted in the same IPC channel, and can be processed according to the priority of the message during the transmission process.

[0163] FIG5 is a flow chart of an inter-core communication method provided by an application example of the present disclosure. As shown in FIG5 , the inter-core communication method provided by the application example of the present disclosure includes the following steps:

[0164] Step 501: The receiving end kernel sets different priorities for different IPC channels in a configuration table, where the configuration table is a preset configuration table for different IPC channels.

[0165] Step 502: The sending end core obtains the priority of each message in at least one message to be sent to the receiving end core;

[0166] Step 503: The sending end kernel obtains queue information of the message queue of the IPC channel corresponding to the priority of the message, where the queue information includes at least the queue head address and the write index.

[0167] Step 504: The sending end kernel writes the message to the queue address indicated by the write index and the queue first address;

[0168] In one embodiment, the sending end kernel updates the write index using the write index incremented by 1;

[0169] Step 505: In response to the presence of a new message that needs to be sent to the receiving end core, the sending end core obtains the priority corresponding to the new message;

[0170] Step 506: The sending end kernel writes the new message into the message queue of the IPC channel of the corresponding priority.

[0171] Step 507, determining whether the receiving end core and the sending end core belong to the same processor;

[0172] If the judgment result is yes, then go to step 508;

[0173] If the judgment result is no, then go to step 509;

[0174] Step 508: The sending end core sends a software-triggered interrupt signal to the receiving end core.

[0175] Step 509: The sending end core sends a shared peripheral interrupt type interrupt signal to the receiving end core;

[0176] Step 510: The receiving end core responds to the interrupt signal sent by the sending end core and obtains the interrupt signal sent by the sending end core; the interrupt signal is used to indicate that the sending end core has completed writing the message to the message queue of the corresponding IPC channel;

[0177] Step 511: In response to an interrupt signal associated with the highest-priority IPC channel sent by the sending-end core, the receiving-end core obtains queue information of the message queue of the highest-priority IPC channel in order of priority. The queue information includes at least a queue head address, a read index, and a write index.

[0178] Step 512: The receiving end kernel reads the message in the queue address indicated by the read index and the queue first address;

[0179] Step 513: The receiving end kernel updates the read index using the read index incremented by 1 to obtain an updated read index.

[0180] Step 514: The receiving end kernel reads the updated read index and the message in the queue address indicated by the queue first address;

[0181] Step 515, determine whether the read index and the write index are the same;

[0182] If the judgment result is yes, then go to step 516;

[0183] If the judgment result is no, return to step 513;

[0184] Step 516: Read messages from the message queue of the IPC channel except the one with the highest priority in descending order of priority.

[0185] In one embodiment, the receiving end core updates the read index using the read index incremented by 1 until the read index and the write index are the same.

[0186] In one embodiment, as shown in FIG6 , a schematic diagram of a multi-priority message processing process of a receiving-end kernel is shown.

[0187] Four IPC channels are established between the sending and receiving cores, with priorities increasing from bottom to top. The numbers in the blocks in the figure indicate the order in which messages are processed. Messages 1, 2, 3, 5, 6, 8, and 9 correspond to messages to be processed in each channel at the initial moment (when the interrupt service is initiated after receiving the L1 channel interrupt notification). Message 4 corresponds to a message sent during the processing of message 3, and message 7 corresponds to a message sent during the processing of message 6. The specific processing flow is as follows:

[0188] Prepare to process messages on the L1 channel. First, detect and process message 1 on the L3 channel. Then process message 2 on the L3 channel. At this time, there are no unprocessed messages in the L3 channel, and enter the L2 channel.

[0189] After processing message 3 of the L2 channel, if it detects that message 4 is put into the higher priority L3 channel, it will switch to the L3 channel to process message 4. At this time, there are no unprocessed messages in the L3 channel, so it enters the L2 channel.

[0190] After processing message 5 of the L2 channel, it is detected that there are no unprocessed messages in the L3 channel and the L2 channel, and then enters the L1 channel.

[0191] After processing message 6 of the L1 channel, if it is detected that there is no unprocessed message on the L3 channel but a new message 7 is put into the L2 channel, message 7 of the L2 channel will be processed first, and then messages 8 and 9 of the L1 channel will be processed.

[0192] In one embodiment, multiple message queues of different priorities may be placed in different buffers of an IPC channel to save interrupt resources.

[0193] Corresponding to the above-mentioned inter-core communication method, the present invention also provides an inter-core communication device. Since the device embodiment of the present invention corresponds to the above-mentioned method embodiment, details not disclosed in the device embodiment can be referred to the above-mentioned method embodiment and will not be repeated in this invention.

[0194] FIG3 is a schematic diagram of the structure of a first inter-core communication device provided by an embodiment of the present disclosure. As shown in FIG3 , the inter-core communication device 300 includes:

[0195] The setting part 301 is used to set different priorities for different IPC channels in the configuration table, where the configuration table is a preset configuration table for different IPC channels;

[0196] The reading part 302 is used to respond to the interrupt signal sent by the sending end core and read the message from the message queue of the corresponding IPC channel in order of priority from high to low; the interrupt signal is used to indicate that the sending end core has completed writing the message to the message queue of the corresponding IPC channel.

[0197] In one embodiment, the reading portion 302 is specifically configured to:

[0198] In response to an interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, obtain queue information in the message queue of the highest priority IPC channel in order of priority, where the queue information includes at least a queue head address, a read index, and a write index;

[0199] Read the message in the queue address indicated by the read index and the queue first address;

[0200] Update the read index using the read index incremented by 1 to obtain the updated read index;

[0201] Read the message in the queue address indicated by the updated read index and queue first address;

[0202] Determine whether the read index and write index are the same;

[0203] If the judgment result is yes, the message is read from the message queue of the IPC channel except the one with the highest priority in descending order of priority.

[0204] In one embodiment, the reading portion 302 is specifically configured to:

[0205] In response to the interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, read the message from the message queue of the corresponding IPC channel in order of priority;

[0206] During the message reading process, if a new interrupt signal sent by the sending end kernel is obtained, it is determined whether the IPC channel associated with the new interrupt signal is marked with the priority ignored;

[0207] If the judgment result is no, read the message from the message queue of the corresponding IPC channel in descending order of priority.

[0208] FIG4 is a schematic diagram of the structure of a second inter-core communication device provided by an embodiment of the present disclosure. As shown in FIG4 , the inter-core communication device 400 includes:

[0209] The acquisition part 401 is used to acquire the priority of each message in at least one message that needs to be sent to the receiving end core;

[0210] The writing part 402 is used to write the message into the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving end kernel; the interrupt signal is used to enable the receiving end kernel to read the message from the message queue of the corresponding IPC channel in descending order of priority.

[0211] In one embodiment, the writing portion 402 is specifically configured to:

[0212] Get the queue information of the message queue of the IPC channel corresponding to the message priority. The queue information includes at least the queue head address and write index.

[0213] Write the message to the queue address indicated by the write index and the queue first address;

[0214] Update the write index using the write index that has been incremented by 1.

[0215] In one embodiment, the inter-core communication device 400 further includes an interrupt sending portion, which is configured to:

[0216] In response to a new message that needs to be sent to the receiving end kernel, obtaining a priority corresponding to the new message;

[0217] Write the new message into the message queue of the IPC channel of the corresponding priority and send an interrupt signal to the receiving kernel.

[0218] In one embodiment, the interrupt sending portion is further configured to:

[0219] Determine whether the receiving core and the sending core belong to the same processor;

[0220] If the judgment result is yes, a software-triggered interrupt type interrupt signal is sent to the receiving end kernel;

[0221] If the judgment result is no, a shared peripheral interrupt type interrupt signal is sent to the receiving end core.

[0222] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and the principles are the same, which is not limited in this embodiment.

[0223] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device.

[0224] Specifically, an embodiment of the present disclosure provides an electronic device, including:

[0225] at least one processor; and

[0226] a memory communicatively connected to at least one processor; wherein,

[0227] The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the above-mentioned inter-core communication method.

[0228] An embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the steps of the aforementioned inter-core communication method.

[0229] An embodiment of the present disclosure provides a computer program product, including computer-executable instructions or a computer program, wherein the computer-executable instructions or the computer program implement the steps of the aforementioned inter-core communication method when executed by a processor.

[0230] FIG7 shows a schematic block diagram of an example electronic device 700 that can be used to implement an embodiment of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, vehicle-mounted devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0231] As shown in Figure 7, electronic device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in ROM (Read-Only Memory) 702 or a computer program loaded from a storage unit 708 into RAM (Random Access Memory) 703. In RAM 703, various programs and data required for the operation of device 700 can also be stored. Computing unit 701, ROM 702 and RAM 703 are connected to each other via bus 704. I / O (Input / Output) interface 705 is also connected to bus 704.

[0232] Various components in device 700 are connected to I / O interface 705, including an input unit 706, such as a keyboard, mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, optical disk, etc.; and a communication unit 709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0233] The computing unit 701 can be various general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), various specialized AI (Artificial Intelligence) computing chips, various computing units that run machine learning model algorithms, a DSP (Digital Signal Processor), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the inter-core communication method. For example, in some embodiments, the inter-core communication method can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the method described above can be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute the aforementioned inter-core communication method in any other appropriate manner (eg, by means of firmware).

[0234] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System on Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0235] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0236] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, RAM, ROM, EPROM (Electrically Programmable Read-Only-Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0237] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0238] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application. Industrial Applicability

[0239] This application discloses an inter-core communication method, apparatus, electronic device, storage medium, and computer program product. The method includes setting different priorities for different IPC channels in a configuration table; and, in response to an interrupt signal sent by a sending core, reading messages from the message queues of the corresponding IPC channels in descending order of priority. According to the disclosed solution, the highest-priority message can be read from the message queues of the corresponding IPC channels in descending order of priority, allowing the high-priority message to be processed first by the receiving core.

Claims

1. An inter-core communication method, applied to a receiving-end core, comprising: Setting different priorities for different IPC channels in a configuration table, where the configuration table is a preset configuration table for different IPC channels; In response to an interrupt signal sent by the sending end core, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low; the interrupt signal is used to indicate that the sending end core has completed writing messages to the message queue of the corresponding IPC channel.

2. The method according to claim 1, wherein The method of responding to the interrupt signal sent by the sending end kernel and reading the message from the message queue of the corresponding IPC channel in descending order of priority includes: In response to an interrupt signal associated with the highest priority IPC channel sent by the sending end kernel, obtaining queue information in a message queue of the highest priority IPC channel in order of priority, wherein the queue information includes at least a queue head address, a read index, and a write index; Reading a message in a queue address indicated by the read index and the queue first address; Updating the read index using the read index incremented by 1 to obtain an updated read index; Read the updated read index and the message in the queue address indicated by the queue first address; Determining whether the read index and the write index are the same; If the judgment result is yes, then read the messages from the message queue of the IPC channel except the one with the highest priority in descending order of priority.

3. The method according to claim 1, wherein The responding to the interrupt signal sent by the sending end kernel, reading the message from the message queue of the corresponding IPC channel in descending order of priority, includes: In response to an interrupt signal associated with the IPC channel with the highest priority sent by the sending end kernel, read messages from the message queue of the corresponding IPC channel in order of the priority; During the message reading process, if a new interrupt signal sent by the sending end kernel is obtained, determining whether the IPC channel associated with the new interrupt signal is marked with an ignore priority; If the judgment result is no, read the messages from the message queue of the corresponding IPC channel in descending order of priority.

4. An inter-core communication method, applied to a sending-end core, comprising: Obtaining the priority of each of at least one message that needs to be sent to the receiving end kernel; The message is written into the message queue of the IPC channel of the corresponding priority, and an interrupt signal is sent to the receiving end core; the interrupt signal is used to enable the receiving end core to read messages from the message queue of the corresponding IPC channel in order of the priority from high to low.

5. The method according to claim 4, wherein Writing the message into the message queue of the IPC channel of the corresponding priority includes: Obtain queue information of a message queue of the IPC channel corresponding to the priority of the message, wherein the queue information includes at least a queue head address and a write index; Writing the message into the queue address indicated by the write index and the queue first address; The write index is updated using the write index that is incremented by 1.

6. The method according to claim 4 or 5, wherein: After writing each of the messages into the message queue of the IPC channel of the corresponding priority, the method further comprises: In response to a new message that needs to be sent to the receiving end kernel, obtaining a priority corresponding to the new message; The new message is written into the message queue of the IPC channel of the corresponding priority, and an interrupt signal is sent to the receiving end kernel.

7. The method according to any one of claims 4 to 6, wherein: The sending of an interrupt signal to the receiving end core includes: Determining whether the receiving-end core and the sending-end core belong to the same processor; If the judgment result is yes, sending a software-triggered interrupt type interrupt signal to the receiving end kernel; If the judgment result is no, a shared peripheral interrupt type interrupt signal is sent to the receiving end core.

8. An inter-core communication device, applied to a receiving-end core, comprising: A setting part, used to set different priorities for different IPC channels in a configuration table, where the configuration table is a preset configuration table for different IPC channels; The reading part is used to respond to the interrupt signal sent by the sending end core and read the message from the message queue of the corresponding IPC channel in the order of the priority from high to low; the interrupt signal is used to indicate that the sending end core has completed the message writing to the message queue of the corresponding IPC channel.

9. An inter-core communication device, applied to a sending-end core, comprising: An acquisition part, used for acquiring the priority of each of at least one message to be sent to the receiving end core; A writing part, used for writing the message into the message queue of the IPC channel of the corresponding priority, and sending an interrupt signal to the receiving end kernel; The interrupt signal is used to enable the receiving end kernel to read messages from the message queue of the corresponding IPC channel in the order of the priorities from high to low.

10. An electronic device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 3 or claims 4 to 7.

11. A non-transitory computer-readable storage medium storing computer instructions, the computer instructions being configured to cause the computer to execute the method according to any one of claims 1 to 3 or claims 4 to 7.

12. A computer program product comprising computer executable instructions or a computer program, wherein the computer executable instructions or the computer program are capable of implementing the method according to any one of claims 1 to 3 or claims 4 to 7 when executed by a processor.

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