Communication method and communication apparatus based on PC code

Abstract

Provided in the present application are a communication method and communication apparatus based on a PC code, in which PC coding and CRC coding are mainly used to implement the precoding of information bit sequences transmitted in a broadcast channel, an uplink data channel and a downlink data channel, or information bit sequences carried in control information, followed by channel coding, so that the coding gain of channel coding can be improved, thereby facilitating an improvement in the communication quality. In addition, the method can improve the error correction performance when the number of payloads increases, and can also achieve a further improvement in the coding gain when a mother code length increases.

Description

A communication method and communication device based on PC code The present application claims priority to the Chinese patent application No. 202410345265.9, filed on March 22, 2024, and entitled "A communication method and communication device based on PC code", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present application relates to the field of channel coding, and more particularly, to a communication method and communication device based on PC code. BACKGROUND A communication system usually adopts channel coding to improve the reliability of data transmission and ensure the quality of communication. The coding gain of channel coding, such as physical broadcast channel (PBCH) coding, physical uplink shared channel (PUSCH) coding, physical downlink shared channel (PDSCH) coding, downlink control information (DCI) coding, and uplink control information (UCI) coding, is directly related to the quality of user communication. Therefore, how to further improve the coding gain of channel coding is a problem to be solved. SUMMARY The present application provides a communication method and communication device based on PC code, which can improve the coding gain of channel coding and help improve the quality of communication. In a first aspect, a method based on PC code is provided, which can be executed by a first communication device, a component (e.g., a processor, a chip, a chip system, a hardware circuit, etc.) in the first communication device, or a logic module or software capable of realizing all or part of the functions of the first communication device. The method comprises: obtaining a payload sequence, the payload sequence comprising an information bit sequence carried by control information or an information bit sequence transmitted in any of a broadcast channel, an uplink data channel, and a downlink data channel; performing pre-transformation coding on the payload sequence, the pre-transformation coding comprising cyclic redundancy check (CRC) coding and parity check (PC) coding, to obtain an output sequence; and performing channel coding on the output sequence to obtain a codeword sequence. In the above scheme, the PC encoding and the CRC encoding are adopted to implement pre-encoding on the information bit sequence transmitted in the broadcast channel, the uplink data channel, the downlink data channel, or the information bit sequence carried in the control information, and then channel encoding is performed, so that the coding gain of the channel encoding can be improved, and the communication quality can be improved. In a second aspect, a PC code-based method is provided, which can be executed by a second communication device, a component (for example, a processor, a chip, a chip system, a hardware circuit, etc.) in the second communication device, or a logic module or software capable of implementing all or part of the functions of the second communication device. The method comprises: obtaining a received sequence; performing channel decoding on the received sequence to obtain a first bit sequence; and performing pre-transformation decoding on the first bit sequence, the pre-transformation decoding comprising CRC decoding and parity check PC decoding, to obtain a decoded sequence; wherein the pre-transformation decoding is decoding on an encoded payload sequence, and the payload sequence comprises an information bit sequence carried in control information or an information bit sequence transmitted in any one of a broadcast channel, an uplink data channel, and a downlink data channel. In the above scheme, after the channel decoding on the received sequence, the pre-encoding decoding is performed, and the pre-transformation decoding comprises the CRC decoding and the parity check PC decoding on the information bit sequence transmitted in the broadcast channel, the uplink data channel, and the downlink data channel, or the information bit sequence carried in the control information, so that the decoding performance can be improved. In combination with the first aspect and the second aspect, in some implementations of the first aspect and the second aspect, the channel encoding comprises polar encoding, and a mother code length N of the polar encoding is greater than or equal to 1024. In this implementation, the channel encoding can adopt the polar encoding, the mother code length of the polar encoding can be increased, and the use of a longer mother code length can improve the coding gain, which is beneficial to improving the network coverage and the user transmission rate. In combination with the first aspect and the second aspect, in some implementations of the first aspect and the second aspect, a payload length K of the payload sequence comprises one of 32, 40, 48, 56, and 64. In this implementation, when the payload sequence comprises the information bit sequence of any one of the uplink data channel, the downlink data channel, the downlink control information, and the uplink control information, the payload length of the payload sequence can comprise one of 32, 40, 48, 56, and 64, or any other natural number. It should be understood that the payload length of the payload sequence refers to the information bit sequence in the channel or the information, and does not include the CRC bit sequence. In combination with the first aspect and the second aspect, in some implementations of the first aspect and the second aspect, the payload sequence comprises an information bit sequence in a broadcast channel. In the implementation, when the payload sequence comprises the information bit sequence in the broadcast channel, the payload length of the payload sequence can comprise one of 32, 40, 48, 56, and 64. With reference to the first aspect and the second aspect, in some implementations of the first aspect and the second aspect, the rate matching manner adopted by the polar encoding is puncturing. In the implementation, when the mother code length increases, the channel resource supports a code bit length of a first value (unchanged), and the mother code length is greater than the first value, the channel resource cannot support the current mother code length to adopt the repetition manner for rate matching, and the rate matching manner can be puncturing. It should be understood that when the channel resource supports a code bit length greater than the mother code length, the rate matching manner of the polar encoding can be repetition. With reference to the first aspect, in some implementations of the first aspect, the pre-transform encoding of the payload sequence comprises PC encoding of the payload sequence according to a first shift register. In the implementation, the PC bit can be generated based on the first shift register. With reference to the first aspect, in some implementations of the first aspect, the pre-transform encoding is a non-systematic code, and if the current position of the payload sequence corresponds to a message bit, the output bit of the first shift register is read from the first shift register. With reference to the first aspect, in some implementations of the first aspect, the pre-transform encoding is a systematic code, the output of the first shift register is related to a set to which the current position of the payload sequence belongs, if the current position of the payload sequence belongs to a message bit set, the output of the first shift register is the input of the first shift register; if the current position of the payload sequence belongs to a dynamic frozen bit set, the output bit of the first shift register is read from the first shift register; and if the current position of the payload sequence belongs to a frozen bit set, the output of the first shift register is 0. In some implementations of the first aspect, the pre-transform encoding the payload sequence comprises: PC encoding the payload sequence according to a second shift register; the second shift register has a length of 5; if the current position of the payload sequence corresponds to a message bit, then the current bit is XORed with the value of the leftmost shift register of the second shift register, and the result is stored in the leftmost shift register, and the current input message bit is taken as the bit at the current position, and then the second shift register is circularly shifted; if the current position of the payload sequence is a check bit, then the value of the leftmost shift register is taken as the check bit, and then the second shift register is circularly shifted; if the current position of the payload sequence is a frozen bit, then zero is directly output as the bit at the current position, and then the second shift register is circularly shifted. In this implementation, the PC bits can be generated based on the first shift register. In some implementations of the first aspect and the second aspect, the payload sequence comprises a sequence of information bits of a broadcast channel, and the n pc > 0, In this implementation, n pc The number of PC bits increases, but The number of PC bits is still 0. It means that some message bits with small row weight and highest reliability are sacrificed as PC positions, which affects the decoding performance under SC, It means that no message bits need to be sacrificed as PC positions, thereby ensuring decoding reliability. In a third aspect, a communication apparatus is provided, which has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation manner of the first aspect or the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions. In a fourth aspect, the present application provides a communication apparatus, which comprises at least one processor, and the at least one processor is coupled with at least one memory, the at least one memory is used to store computer programs or instructions, and the at least one processor is used to call and run the computer programs or instructions from the at least one memory, so that the communication apparatus executes the method in the first aspect or any possible implementation manner thereof, or executes the method in the second aspect or any possible implementation manner thereof. In a fifth aspect, the present application provides a communication apparatus, comprising a communication interface and a circuit, the communication interface is configured to receive a payload sequence and input the payload sequence into the circuit; the circuit is configured to pre-transformally encode the input sequence to obtain an output sequence; and the communication interface is further configured to output the output sequence. Optionally, the circuit can be configured to perform a systematic encoding on the output sequence to obtain a codeword sequence. In this case, the communication interface is configured to output the codeword sequence. As an example, the communication apparatus of the third aspect to the fifth aspect is an encoding apparatus, for example, an encoder. In a sixth aspect, the present application provides a computer readable storage medium, which stores computer program codes or instructions, when the computer program codes or instructions are run on a computer, the method in the first aspect or any possible implementation manner thereof is implemented, or the method in the second aspect or any possible implementation manner thereof is implemented. In a seventh aspect, the present application provides a computer program product, which comprises computer program codes or instructions, when the computer program codes or instructions are run on a computer, the method in the first aspect or any possible implementation manner thereof is implemented, or the method in the second aspect or any possible implementation manner thereof is implemented. In an eighth aspect, the present application provides a wireless communication system, comprising the communication apparatus in any one of the third aspect to the fifth aspect. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of a system architecture of a communication system suitable for embodiments of the present application. FIG. 2 is a schematic diagram of a flow of a communication system. FIG. 3 is a schematic diagram of a PBCH encoding flow. FIG. 4 is a schematic diagram of a communication method 400 based on a PC code suitable for embodiments of the present application. FIG. 5 is a schematic diagram of a simulation structure of encoding performance of different mother code lengths in an encoding process of an NR PBCH suitable for embodiments of the present application. FIG. 6 is a schematic diagram of an encoding flow suitable for embodiments of the present application. FIG. 7 is a schematic diagram of a structure of a first shift register suitable for embodiments of the present application. FIG. 8 is a schematic diagram of a structure of a first shift register suitable for embodiments of the present application. FIG. 9 is a schematic diagram of a structure of a first shift register suitable for embodiments of the present application. FIG. 10 is a schematic diagram of a structure of a first shift register suitable for embodiments of the present application. FIG. 11 is a schematic diagram of simulation results of encoding performance of PBCH based on PC encoding and CRC encoding of a first shift register suitable for embodiments of the present application. FIG. 12 is a structural diagram of a second shift register suitable for embodiments of the present application. FIG. 13 is a simulation result diagram of encoding performance of PBCH based on PC encoding and CRC encoding of the second shift register suitable for embodiments of the present application. FIG. 14 is a schematic structural diagram of a communication apparatus provided by the present application. FIG. 15 is a schematic structural diagram of another communication apparatus provided by the present application. FIG. 16 is a schematic structural diagram of still another communication apparatus provided by the present application. DETAILED DESCRIPTION The technical solutions in the present application will be described below with reference to the accompanying drawings. The technical solutions of embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) system, long term evolution (LTE) systems (LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems), etc. The technical solutions provided by the present application can also be applied to future communication systems, such as the 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and internet of things (IoT) communication systems, or other communication systems, etc., which are not limited herein. The technical solutions of the embodiments of the present application can also be applied to a narrow band-internet of things (NB-IoT), a global system for mobile communications (GSM), an enhanced data rate for gsm evolution (EDGE), a wideband code division multiple access (WCDMA), a code division multiple access 2000 (CDMA2000), a time division-synchronization code division multiple access (TD-SCDMA), and three application scenarios of a next-generation 5G mobile communication system, i.e., an enhanced mobile broadband (eMBB), an ultra-reliable and low-latency communications (URLLC), and a massive machine type communications (eMTC). FIG. 1 is a schematic diagram of a system architecture of a communication system applicable to the technical solutions of the present application. The communication system can include one or more network devices and one or more terminal devices. Exemplarily, the terminal device can also be referred to as a user equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity for a user, and can be used to connect people, things and machines, for example, handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a personal digital assistant, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a vehicle-mounted mobile terminal, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity, which provides sidelink signals between UEs in V2X or D2D, etc. In the embodiments of the present application, the device for implementing the function of the terminal can be a terminal, or a device capable of supporting the terminal to implement the function, for example, a chip system or a chip, which can be installed in the terminal. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices. Exemplarily, the network device can be a device with a wireless transceiving function, which can be a device providing a wireless communication function service, and is usually located at a network side, including but not limited to a next-generation base station (gNodeB, gNB) in a 5th generation (5G) communication system, a base station in a future mobile communication system, a base station in a future mobile communication system, or an access node in a wireless fidelity (Wi-Fi) system, an evolved node B (eNB) in a long term evolution (LTE) system, a radio network controller (RNC), a node B (NB), a base station controller (BSC), a home base station (for example, a home evolved NodeB or a home Node B, HNB), a base band unit (BBU), a transmission reception point (TRP), a transmitting point (TP), a base transceiver station (BTS), and the like. In a network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or include a RAN device including a CU node and a DU node, or include a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device can also be a wireless controller in a cloud radio access network (CRAN) scenario, a relay station, a vehicle-mounted device, a wearable device, and the like. In addition, the base station can be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station can also refer to a communication module, a modem, or a chip for being arranged in the foregoing devices or apparatuses. The base station can also be a mobile switching center, a device assuming a base station function in D2D, V2X, M2M communication, a network side device in a future communication network, a device assuming a base station function in a future communication system, and the like. The base station can support networks of the same or different access technologies, without limitation. In an embodiment of the present application, the apparatus for implementing the function of the network device can be a network device, or can be an apparatus capable of supporting the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In an embodiment of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices. It should be understood that the parity check (PC) code-based communication method provided in the present application can be used in special network devices or general devices, and can be applied to various network devices (for example, base station devices) as described above, and can also be applied to various terminal devices as described above. Specifically, the scheme is mainly realized by a channel coding unit in these devices. The method provided in the embodiments of the present application can also be realized by an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, or can be realized by software (for example, program code in a memory), without limitation. In order to facilitate understanding of the technical solutions of the present application, the related concepts or technologies involved in the embodiments are briefly introduced. 1. Polar code The polar code is also called a P polar code, which is a new encoding method based on channel polarization, has a deterministic construction method, and is the only channel coding method that is strictly proved to "reach" the channel capacity. From the perspective of algebraic coding and probabilistic coding, the polar code has the characteristics of both. The theoretical basis of the polar code is channel polarization. Channel polarization includes channel combination and channel decomposition parts. When the number of combined channels is regionally infinite, polarization phenomenon occurs: a part of the channels will tend to be noiseless channels, and the other part will tend to be all-noise channels. This phenomenon is the linear channel polarization. The transmission rate of the noiseless channel will reach the channel capacity, and the transmission rate of the all-noise channel tends to zero. The encoding strategy of the polar code is to use the characteristics of this phenomenon, that is, to use the noiseless channel to transmit user useful information, and to use the all-noise channel to transmit agreed information or no information. After channel polarization is completed, the part of the channels with a capacity tending to 1 can be used to carry information bits, and the remaining channels can be used to carry frozen bits consistent at the transmitting end and the receiving end, that is, the method of polar encoding. The polar code is a linear block code, and its encoding matrix (also called a generator matrix) is GN. The encoding process can be represented by the following formula: wherein, is a binary row vector (that is, an information bit sequence), with a length of N, and N=2 n , n is a positive integer. GN is an N*N matrix, defined as the Kronecker product of log2N matrices F2, The addition and multiplication operations involved in the above formulas are all binary Galois field addition and multiplication operations. The encoding generated by the method will produce a polarization phenomenon through the successive cancellation (SC) decoding method. That is, a part of the bits in u pass through an equivalent high reliability channel and are decoded with a high probability, and the remaining bits pass through an equivalent low reliability channel and are decoded with a low probability. Therefore, one can use the high reliability channel for information transmission, and set the bits corresponding to the low reliability channel to zero (i.e., frozen), which are not used for data transmission or transmission of data known to both parties. At the same time, the current algorithm for serial cancellation decoding includes successive cancellation list (SCL) decoding and CRC-aided successive cancellation list (CA-SCL) decoding. Among them, in terms of decoding performance, SC decoding is the worst, SCL decoding is better than SC decoding, and CA-SCL decoding with CRC check can make the performance of polar codes better than LDPC codes and Turbo codes. It should be noted that polar encoding is an example of a channel coding scheme, and other encoding methods can also be used for channel coding, which is not limited by the embodiments of the present application. In the present application, channel coding can include physical broadcast channel (PBCH) encoding, physical uplink shared channel (PUSCH) encoding, physical downlink shared channel (PDSCH) encoding, downlink control information (DCI) encoding, and uplink control information (UCI) encoding, etc., which are not limited by the embodiments of the present application. 2. Pre-transform encoding Performing upper triangular pre-transform encoding before polar encoding can improve the code spectrum of polar codes and improve the error correction performance of polar codes. CRC encoding, PC encoding, and convolutional encoding all belong to this type of upper triangular pre-transform that can improve the code spectrum of polar codes. FIG. 2 is a flowchart of a communication system. As shown in FIG. 2, the technical solution of the present application mainly involves the part of channel coding. Channel coding is located between source coding and modulation, responsible for channel coding of the bits generated by the source, and after modulation, the sending end sends the modulated symbols through the noisy channel to the receiving end. After demodulation, the receiving end performs channel decoding. Channel decoding is located between demodulation and source decoding, responsible for recovering the source bit stream. When Polar code is used for channel coding, the sending end uses Polar code for channel coding of the source from the media access control (MAC), and the receiving end sends the demodulated log likelihood ratio (LLR) soft information into the Polar decoder to recover the source information and upload it to the MAC. When wireless technology is used for communication, the source of the sending end generally goes through source coding, channel coding, rate matching and modulation before being sent on the channel. The receiving end receives the signal and obtains the sink after demodulation, de-rate matching, channel decoding and source decoding. Channel coding and decoding is one of the core technologies in the field of wireless communication, and the improvement of its performance will directly improve the network coverage and user transmission rate. The following takes PBCH as an example to explain the coding process. FIG. 3 is a schematic diagram of the PBCH coding process. The existing PBCH channel coding, Polar code uses a mother code length equal to 512, and then the rate matching mode is repetition, repeating sending 352 bits to 864 long. The specific process is as follows: Step 1: Generate PBCH payload bits; Step 2: Payload scrambling; Step 3: Add CRC bits; Step 4: DCRC interleaving; Step 5: Channel coding; Step 6: Rate matching; Step 7: Scrambling of coded bits; Step 8: QPSK modulation; Step 9: RE mapping. As described above, the existing channel (e.g., PBCH) coding uses Polar code with a mother code length of 512, and its error correction capability still needs to be improved; in addition, the number of future channel payloads may increase, which further requires the error correction capability of channel coding (e.g., Polar code). In general, the coding performance of channel coding directly affects the network coverage and user transmission efficiency. Therefore, the application provides a PC code-based communication method, which increases the mother code length during encoding to obtain greater coding gain, and meanwhile, PC coding can be added during channel coding, so that the coding gain can be further improved. FIG. 4 is a schematic flowchart of a PC code-based communication method 400 provided by the application. The method 400 can be executed by a first communication device, a component (for example, a chip, a chip system or a circuit, etc.) in the first communication device, or a logic module or software capable of realizing all or part of the functions of the first communication device. As an example, the first communication device can be an encoding device. The following will be described by taking the encoding device as an example. 410. The encoding device acquires a payload sequence. The payload sequence includes an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel and a downlink data channel. As an example, the uplink data channel can be a PUSCH, the downlink data channel can be a PDSCH, and the control information includes information transmitted on a physical uplink control channel (PUCCH) and a physical downlink control channel (PDCCH). In a possible implementation, the payload length of the payload sequence includes one of 32, 40, 48, 56 and 64. For example, when the payload sequence includes an information bit sequence in a broadcast channel, the payload length of the payload sequence can include one of 32, 40, 48, 56 and 64. For example, when the payload sequence includes an information bit sequence of any one of an uplink data channel, a downlink data channel, downlink control information and uplink control information, the payload length of the payload sequence can include one of 32, 40, 48, 56 and 64, or any other natural number. It should be understood that the payload length of the payload sequence refers to an information bit sequence in a channel or information, and does not include a CRC bit sequence. 420. The encoding device pre-transformally encodes the payload sequence to obtain an output sequence. Here, the payload sequence refers to an input sequence of pre-transformal encoding, and the output sequence refers to an output sequence of pre-transformal encoding. 430. The encoding device channel-encodes the output sequence to obtain a codeword sequence. The encoding device further channel-encodes the output sequence of pre-transformal encoding, for example, polar encoding. Through steps 410-430, the encoding device performs cascaded encoding of pre-transformal encoding and channel encoding to obtain a codeword sequence. In this embodiment, the way that the encoding device channel encodes the output sequence of pre-transformed encoding is illustrated by taking polar encoding as an example. Embodiments of the present application are not limited in this regard. In polar encoding, a longer mother code length can improve coding gain, which is conducive to improving network coverage and user transmission rate. In a possible implementation, the mother code length N used by polar encoding can be greater than 512. For example, N can be greater than or equal to 1024. For example, PBCH uses a polar code with a mother code length N = 2 n , where n can be greater than 9, for example, n ≥ 10. FIG. 5 shows a schematic diagram of the coding performance of different mother code lengths in the encoding process of NR PBCH. For example, the performance of NR PBCH with a mother code length of 512 (black dashed line) and a mother code length of 1024 (black solid line) is taken as an example. The horizontal coordinate in FIG. 5 is the symbol signal-to-noise ratio (Es / N0), and the vertical coordinate is the block error rate (BLER). The ratio of the energy per symbol to the noise power spectral density is proportional to the channel condition, and the larger the Es / N0, the better the channel condition. The block error rate refers to the percentage of error blocks in all transmitted blocks, or the ratio of the number of data transmission error blocks to the total number of received blocks in a certain time period. The lower the error rate, the better the communication quality. As shown in FIG. 5, as the number of PBCH payloads increases, the coding gain brought by increasing the mother code length of PBCH encoding also increases. In a possible implementation, when the mother code length increases, the rate matching method used by polar encoding is puncturing. It should be understood that when the mother code length increases, the channel resource supports the coding bit length as a first value (unchanged), and when the mother code length is greater than the first value, the channel resource cannot support the current mother code length to use the repetition method for rate matching, and the rate matching method can be puncturing. For example, when the mother code length is 512 and the channel resource supports a coding bit length of 864, repeating 352 bits can reach 864 bits, but when the mother code length is 1024, the channel resource supports the coding bit length unchanged, and the mother code with a length of 1024 needs to be punctured 160 bits to perform polar encoding on the channel resource. It should be understood that when the channel resource supports a coding bit length greater than the mother code length, the rate matching method of polar encoding can be repetition. For example, the following shows a description of the standard text of the mother code length increase scheme. One possible example is as follows: Information bits are delivered to the channel coding block. They are denoted by c0, c1, c2, c3,..., c K-1 , where K is the number of bits, and they are encoded via Polar coding according to Clause 5.3.1, by setting n max = 10, I IL = 1, n PC = 0, and After encoding the bits are denoted by d0, d1, d2, d3,..., d N-1 , where N is the number of coded bits. Another possible example is as follows: Information bits are delivered to the channel coding block. They are denoted by c0, c1, c2, c3,..., c K-1 , where K is the number of bits, and they are encoded via Polar coding according to Clause 5.3.1, by setting n = 10, I IL = 1, n PC = 0, and After encoding the bits are denoted by d0, d1, d2, d3,..., d N-1 , where N is the number of coded bits. To further improve the encoding of the channel under SCL, PC bits can be added in the pre-transform encoding process, i.e., n pc > 0. Hereinafter, the pre-encoding scheme proposed in the present application is described in detail. The pre-transform encoding includes CRC encoding and PC encoding. In a possible implementation, the PC bits can be added before the CRC encoding. In another possible implementation, the PC bits can be added after the CRC encoding. It should be understood that the CRC encoding is independent of the PC bits, and therefore the relative positions of the CRC module and the PC module do not affect the final encoding result. FIG. 6 shows schematic diagrams of encoding processes. As shown in (a) of FIG. 6, PC encoding is performed after CRC encoding, and then channel encoding is performed; as shown in (b) of FIG. 6, PC encoding is performed before CRC encoding, and then channel encoding is performed. The specific encoding process methods shown in FIG. 6(a) and FIG. 6(b) can refer to the encoding process shown in FIG. 3, and will not be described again. The PC encoding is performed according to a shift register. In a possible implementation, the payload sequence is PC encoded according to a first shift register. FIG. 7 shows a structural schematic diagram of the first shift register. The first shift register includes a register with a length of L and at least two taps, the direction of the at least two taps is writing, and the positions of the taps are determined by a PC encoding polynomial. The PC encoding polynomial is q(D) = 1 + q1D + q2D 2 +...+q m D m . q0, q1, …, q m are coefficients of the polynomial, the values of the polynomial coefficients are 0 or 1, and when the value of a polynomial coefficient is 0, it indicates that the tap corresponding to the register does not exist. D represents a register, the register length L is equal to the highest power m of the polynomial, or in other words, the Lth register is the register corresponding to the highest power term of the pre-encoding polynomial, and L is an integer greater than or equal to 1. In terms of timing, q0 corresponds to the tap at the current time, q1 corresponds to the tap at a time before the current time, that is, a time after one register; q2 corresponds to the tap at two times before the current time, that is, a time after two registers; similarly, q m corresponds to the tap at a time after m registers. In the shift register, q0 represents an exclusive or operation in a binary field, is a binary switch, the polynomial q(D) = 1 + q1D + q2D 2 +...+qm D m coefficient q i When the value is 0, If closed (no tap at time i), otherwise It is open (there is a tap at time i). The length of the shift register is L, which is generally equal to the highest power of the pretransform coding polynomial. For example, if the highest power of the pretransform coding polynomial is 1, then L = 1, and there is only one register. As another example, if the pretransform polynomial is 1 + D... 2 +D 3 The coefficients of the pretransform coding polynomial are q0 = 1, q1 = 0, q2 = 1, and q3 = 1, respectively. The highest power of this pretransform coding polynomial is 3. Therefore, L = 3, and there are three registers, including D. 2 Corresponding to the second register, D 3 This corresponds to the third register. D 1 Corresponding to the first register, but because of D 1 In this precoding polynomial, the coefficient q1 = 0; therefore, the tap corresponding to the first register does not exist. For example, if the pretransform coding polynomial is 1 + D + D... 3 The highest power of the pre-transform coding polynomial is 3. Therefore, L = 3, and there are three registers. D corresponds to the first register. 3 This corresponds to the third register. It should be understood that D... 2 Corresponding to the second register, but because of D 2 The coefficients in this precoding polynomial are 0; therefore, the tap corresponding to the second register does not exist. The taps corresponding to the shift registers (e.g., read taps and / or write taps) will be described in the following embodiments with reference to the specific shift register structure. The pre-transformed input sequence (simplified as the input sequence in this embodiment) is the message sequence to be encoded, v0, v1, v2, ..., v K-1 The output sequence is u0, u1, u2, ..., u N-1 N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined by the shift register and the pre-transform coding polynomial. The position output from the shift register during the pre-transformation can be independent of the set to which the current position belongs, or it can be related to the set to which the current position belongs. When the pre-transformation encoding is a non-system code, if the current position of the payload sequence corresponds to a message bit, the output bit of the first shift register is read from the first shift register, for example, from the tap at the end of the shift direction of the first shift register. In the present application, the message bits can also be referred to as information bits, and the specific name does not limit the embodiments of the present application. For example, as shown in FIG. 7, u i = z i . When the pre-transform coding is a systematic code, the output of the first shift register is related to the set to which the current position of the payload sequence belongs. If the current position of the payload sequence belongs to the set of message bits, the output of the first shift register is the input of the first shift register. For example, as shown in FIG. 7, u i = v i . If the current position of the payload sequence belongs to the set of dynamic frozen bits, the output bit of the first shift register is read from the first shift register, for example, from the tap at the end of the shift direction of the first shift register. For example, as shown in FIG. 7, u i = z i . If the current position of the payload sequence belongs to the set of frozen bits, the output of the first shift register is 0. In addition, in the embodiments of the present application, the shift direction of the first shift register can be left shift or right shift, which is not limited. In the following embodiments, right shift is taken as an example for description. Before starting coding, the values of the L shift registers need to be initialized, for example, the value of each shift register is initialized to 0. It can be understood that the puncturing and shortening positions directly output 0. In the present application, the payload size corresponding to the input sequence (payload sequence + CRC sequence) of the pre-transform coding is different, and the PC check relationship and PC bit are different. Specifically, the values of taps q o ~ q m in FIG. 7 can be determined according to the PC polynomial. The specific method is to convert the PC poly from decimal to binary sequence, q m The rightmost q0 is at the leftmost side, and the values of q o ~ q m are taken to determine the switch of the tap. For example, PC poly = 97, which corresponds to the binary sequence [1000011], from the highest bit to the lowest bit, q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 1. Wherein, q4-q1 are all zero, indicating that there is no write tap at the time corresponding to q4-q1. There is a write tap at the time corresponding to q0 and q6-q5, thus, the value at the write tap at the time corresponding to the coefficients equal to 1 will be XORed with the value in the corresponding register and then written into the register. The PC check relationship and PC bit corresponding to different payload sizes are exemplarily illustrated below. Fig. 8 shows a structural schematic diagram of a shift register. Fig. 8 shows a shift register taking a payload sequence of 32 bits and a CRC of 24 bits as an example for illustration, and the PBCH payload size is 56 bits. In the shift register, PC Poly=49, the binary sequence corresponding thereto is [100011], and from the highest bit to the lowest bit, q5=1, q4=1, q3=0, q2=0, q1=0, and q0=1. The polynomial corresponding thereto is expressed as q(D)=1+D 4 +D 5 . Fig. 9 shows a structural schematic diagram of a shift register. Fig. 9 shows a shift register taking a payload sequence of 40 bits and a CRC of 24 bits as an example for illustration, and the PBCH payload size is 64 bits. In the shift register, PC Poly=21, the binary sequence corresponding thereto is

[10101] , and from the highest bit to the lowest bit, q4=1, q3=0, q2=1, q1=0, and q0=1. The polynomial corresponding thereto is expressed as q(D)=1+D 2 +D 4 . Fig. 10 shows a structural schematic diagram of a shift register. Fig. 10 shows a shift register taking a payload sequence of 48 / 56 / 64 bits and a CRC of 24 bits as an example for illustration, and the PBCH payload size is 72 bits / 80 bits / 88 bits. In the shift register, PC Poly=35, the binary sequence corresponding thereto is

[10101] , and from the highest bit to the lowest bit, q5=1, q4=0, q3=0, q2=0, q1=1, and q0=1. The polynomial corresponding thereto is expressed as q(D)=1+D 1 +D 5 . The above PC check relationship and PC bit design is only exemplarily illustrated, and does not limit the application embodiments. Fig. 11 shows a simulation result schematic diagram of the encoding performance of PBCH based on the first shift register using PC encoding and CRC encoding. The performance results of the mother code length of 512 / CRC encoding (black dotted line), the mother code length of 1024 / CRC encoding (black solid line), and the mother code length of 1024 / PC encoding+CRC encoding (gray solid line) are shown in FIG. 11. wherein the PC check bits are generated based on the second shift register. wherein the PC check bits are taken as an example of 3-bit PC check. The horizontal and vertical coordinates in FIG. 11 can refer to the description of FIG. 5, and will not be repeated here. As can be seen from FIG. 11, the PBCH encoding performance of the PC encoding+CRC encoding (pre-encoding before Polar encoding includes CRC encoding and PC encoding) with the mother code length of 1024 has a significant improvement compared with the PBCH encoding performance of the CRC encoding (pre-encoding before Polar encoding includes CRC encoding, but does not include PC encoding) with the mother code length of 1024 and the PBCH encoding performance of the PC encoding+CRC encoding (pre-encoding before Polar encoding includes CRC encoding and PC encoding) with the mother code length of 1024. In addition, as the number of PBCH payloads increases (payload size is 32, 40, 48, 56, 64), the coding gain of the PBCH encoding mode using PC encoding+CRC encoding also increases. In this application, when the payload sequence includes the information bit sequence of the PBCH, the parameter The value of the parameter may be 0. The following is an exemplary description of the message bit set I, the dynamic frozen bit set DF, and the position of the frozen bit corresponding to different payload sizes. As an example, the PBCH uses CRC encoding+PC encoding, and when the PBCH payload size is 56 bits (32+CRC 24), the position of the corresponding dynamic frozen bit set DF is shown in Table 1 below, the position of the message bit set I is shown in Table 2 below, the position of the frozen bit is shown in Table 3 below, and the position of the effective DF bit (effective PC bit) is shown in Table 4 below. Table 1 Table 2 Table 3 Table 4 In the above scheme, the PBCH adopts a mother code length N = 2 n wherein n = 10, i.e., the mother code length is 1024 bits, which corresponds to bit indexes 0~1023, wherein Table 1 shows the bit indexes corresponding to the DF bits, Table 2 shows the bit indexes corresponding to the message bits, Table 3 shows the bit indexes corresponding to the punctured bits, and Table 4 shows the bit indexes corresponding to the effective DF bits. The above tables are only an example for listing the bit indexes for convenience, and a direct listing manner can also be adopted, for example, the DF is {161, 162, …, 1009}, which is not limited by the embodiments of the present application. For example, the encoding parameter n pc = 808, Alternatively, the encoding parameter n pc = 457, As another example, the PBCH adopts CRC encoding + PC encoding, when the PBCH payload size is 64 bits (40+CRC 24), the positions of the corresponding dynamic frozen bit set DF are shown in Table 5 below, the positions of the message bit set I are shown in Table 6 below, the positions of the frozen bits are shown in Table 7 below, and the positions of the effective DF bits (effective PC bits) are shown in Table 8 below. Table 5 Table 6 Table 7 Table 8 In the above scheme, the PBCH adopts a mother code length N = 2 n wherein n = 10. The meanings of Tables 5~8 can refer to Tables 1~4, and will not be repeated. For example, the encoding parameter n pc = 800, Alternatively, the encoding parameter n pc = 450, As another example, PBCH adopts CRC encoding + PC encoding, when PBCH payload size is 72 bits (48+CRC 24), the corresponding dynamic frozen bit set DF position is shown in Table 9, the message bit set I position is shown in Table 10, the frozen bit position is shown in Table 11, and the effective DF bit (effective PC bit) position is shown in Table 12. Table 9 Table 10 Table 11 Table 12 In the above scheme, PBCH adopts mother code length N = 2 n , where n = 10. Wherein the meaning of Table 9-Table 12 can refer to Table 1-Table 4, not described again. Exemplary, the encoding parameter n pc = 792, Or, the encoding parameter n pc = 443, As another example, PBCH adopts CRC encoding + PC encoding, when PBCH payload size is 80 bits (56+CRC 24), the corresponding dynamic frozen bit set DF position is shown in Table 13, the message bit set I position is shown in Table 14, the frozen bit position is shown in Table 15, and the effective DF bit (effective PC bit) position is shown in Table 16. Table 13 Table 14 Table 15 Table 16 In the above scheme, PBCH adopts mother code length N = 2 n , where n = 10. Wherein the meaning of Table 13-Table 16 can refer to Table 1-Table 4, not described again. Exemplary, the encoding parameter n pc = 784, Or, the encoding parameter n pc = 437, As another example, the PBCH adopts CRC encoding + PC encoding, when the PBCH payload size is 88 bits (64+CRC 24), the corresponding dynamic frozen bit set DF position is shown in Table 17, the message bit set I position is shown in Table 18, the frozen bit position is shown in Table 19, and the effective DF bit (effective PC bit) position is shown in Table 20. Table 17 Table 18 Table 19 Table 20 In the above scheme, the PBCH adopts a mother code length N = 2 n , where n = 10. Wherein, the meaning of Table 17-Table 20 can refer to Table 1-Table 4, and will not be repeated. For example, the encoding parameter n pc = 776, Alternatively, the encoding parameter n pc = 429, It should be noted that in the above examples, n pc > 0, n pc The number increases, but It is still 0. Meaning to sacrifice some row weight smaller and the most reliable message bits as PC position, will affect the decoding performance under SC, Meaning that no need to sacrifice message bits as PC position, thus ensuring the decoding reliability. It should be understood that the positions of the DF bits or message bits shown in the above tables are only exemplary and do not limit the application. In another possible implementation, the payload sequence is PC encoded according to a second shift register. The second shift register is a multiplexing of the existing NR mod 5 shift register, and the multiplexing of the existing shift register is used to generate PC check bits, which is beneficial to the more unified way of generating PC checks under different code types. FIG. 12 shows a structural diagram of the second shift register. The second shift register includes a register with a length L of 5. where y0 represents the value in the first register, y1 represents the value in the second register. Similarly, yL represents the value in the Lth register. L-1 where y0 represents the value in the first register, y1 represents the value in the second register. Similarly, yL represents the value in the Lth register. As shown in FIG. 12, if the current position of the payload sequence corresponds to a message bit, the current bit is XORed with the value of the leftmost shift register of the second shift register and stored in the leftmost shift register, and the current input message bit is taken as the bit at the current position, and then the second shift register is circularly shifted; if the current position of the payload sequence is a check bit, the value of the leftmost shift register is taken as the check bit, and then the second shift register is circularly shifted; if the current position of the payload sequence is a frozen bit, zero is directly output as the bit at the current position, and then the second shift register is circularly shifted. The pseudo code and its annotations of the pre-transform polar encoding based on the shift register in the NR standard are as follows: The pre-transformed code word u is further polar-encoded to obtain an output d = [d0d1d2...d N-1 ], d = uG N . As described above, the PC-polar code in the NR standard generates a pre-transformed encoding code word based on a single-tap feedback shift register. The shift register is in the form of a feedback shift register; the direction of the tap is writing; the number of taps is single tap; the shift direction of the shift register is left shift; the position of the feedback tap and the position of the output tap are both at the end (leftmost) of the moving direction; and the shift register can only be used to input bits at the message position; the shift register outputs bits at the current position as a check position. The moving timing logic of the shift register is that the reading is at time t and the writing is at time t+1. As an example, the PBCH adopts CRC encoding + PC encoding, when the PBCH payload size is {32, 40, 48, 56, 64} bits (32+CRC 24 / 40+CRC 24 / 48+CRC 24 / 56+CRC 24 / 64+CRC 24), in the shift register, PC Poly = 16, and the corresponding binary sequence is

[0001] , from the highest bit to the lowest bit, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 0. The corresponding polynomial is q(D) = D 5 , from the highest bit to the lowest bit, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 0. The corresponding polynomial is q(D) = D

[10000] . FIG. 13 shows a simulation result diagram of encoding performance of PBCH based on second shifter using PC encoding and CRC encoding. In FIG. 13, performance results of a mother code length of 512 / using CRC encoding (black dotted line), a mother code length of 512 / using CRC encoding+PC encoding (gray dotted line), and a mother code length of 1024 / using PC encoding+CRC encoding (gray solid line) are shown. wherein the PC check bits are generated based on the second shift register. wherein a 3-bit PC check is taken as an example. As can be seen from FIG. 13, for PBCH encoding with a mother code length of 512, the encoding performance of using CRC encoding+PC encoding (pre-encoding before Polar encoding includes CRC encoding and PC encoding) is better than that of using CRC encoding (pre-encoding before Polar encoding includes CRC encoding, but does not include PC encoding), and the encoding gain is greater as the PBCH payload length increases. As can also be seen from FIG. 13, for PBCH encoding with a mother code length of 1024, the encoding performance of using CRC encoding+PC encoding (pre-encoding before Polar encoding includes CRC encoding and PC encoding) is smaller as the PBCH payload length increases. In summary, if the NR PC equation and the shift register of NR are multiplexed, when the payload length is unchanged, such as 32+CRC 24 bits, using a longer mother code length has greater benefits; when the payload length increases, such as the PBCH payload size exceeds 56 bits, only using a mother code length of N=512 can maximize the encoding gain. In the present application, a PC code-based communication method is also provided, which can be executed by a second communication device, a component (for example, a chip, a chip system, or a circuit, etc.) in the second communication device, or a logic module or software capable of realizing all or part of the functions of the second communication device, etc. As an example, the second communication device can be a decoding device. For the decoding device, the decoding device can obtain a received sequence, which is a channel sequence transmitted by an encoding device to the decoding device based on an encoded code word sequence; the decoding device performs channel decoding on the received sequence to obtain a first bit sequence; the decoding device performs pre-transformation decoding on the first bit sequence, the pre-transformation decoding including CRC decoding and parity check PC decoding, to obtain a decoded sequence; wherein the pre-transformation decoding is decoding of an encoded payload sequence, and the payload sequence includes an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel. The specific scheme on the decoding device side can refer to that on the encoding device side, which will not be described herein again. Based on the above scheme, the embodiment of the present application provides a PC code-based communication method, for the information bit sequence transmitted in the broadcast channel, uplink data channel and downlink data channel or the information bit sequence carried in the control information, PC encoding and CRC encoding are used to realize pre-encoding, and then channel encoding is performed, the method can improve the error correction performance in the case of increasing the number of payloads, and can further improve the coding gain in the case of increasing the mother code length. The method of encoding provided by the present application is described in detail above, and the communication device provided by the present application is introduced below. As shown in FIG. 14, the present application provides a communication device 1400. The communication device 1400 can be an encoding device, or a device applied to the encoding device and capable of realizing the corresponding functions of the encoding device in the method embodiments of the present application, such as a chip, a chip system, a circuit, etc. Optionally, the communication device 1400 comprises a processing module 1401, which can be a processor, a processing board, a processing unit, or a processing device, etc. The processing module 1401 is configured to perform pre-transform encoding on the payload sequence to obtain an output sequence. Optionally, the processing module 1401 is further configured to further perform channel encoding on the pre-transform encoded output sequence to obtain a codeword sequence, and the specific process can refer to the detailed description of the method embodiments, which will not be described here. Optionally, the communication device 1400 further comprises a communication module 1402, which can also be referred to as a transceiver module, a transceiver, a transceiver device, or the like, and is configured to perform receiving (or input) and / or transmitting (or output) operations. For example, the communication module 1402 can be configured to obtain the pre-transform encoded payload sequence, output the pre-transform encoded output sequence, or output the concatenated encoded codeword sequence, etc. In some embodiments, the foregoing communication module and / or processing module can be implemented by a virtual module, for example, the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module can also be implemented by an entity device, for example, if the device is implemented by a chip / circuit (such as an integrated circuit, a special-purpose circuit, a logic circuit, etc.). The communication module can be an input / output circuit and / or a communication interface, and performs input operations (corresponding to the foregoing receiving operations) and output operations (corresponding to the foregoing transmitting operations); the processing module is an integrated processor or a microprocessor or a circuit (such as an integrated circuit, a logic circuit, etc.). ​The division of the modules in the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, the function modules in each example of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software function module. As shown in FIG. 15, the present application further provides a communication apparatus 1500. The communication apparatus 1500 includes at least one processor 1510, which implements the functions of the encoding device described in the foregoing method embodiments. Optionally, the processor 1510 is coupled with a memory. The memory can be located in the communication apparatus, or the memory can be integrated with the processor, or the memory can be located outside the communication apparatus. The communication apparatus 1500 can further include at least one memory 1520. The memory 1520 stores computer programs, instructions or data necessary for implementing any one of the foregoing method embodiments. The processor 1510 can execute the computer programs, instructions or data stored in the memory 1520 to complete the communication method of any one of the foregoing embodiments. Optionally, the communication apparatus 1500 can further include a communication interface 1530. The communication apparatus 1500 can interact with other devices through the communication interface 1530. Illustratively, the communication interface 1530 can be a transceiver, a circuit, a bus, a module, a pin or other types of interfaces. The coupling in the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, for information interaction between devices, units or modules. The processor 1510 can operate in cooperation with the memory 1520 and the communication interface 1530. The specific connection medium between the processor 1510, the memory 1520 and the communication interface 1530 is not limited in the present application. As shown in FIG. 16, the present application further provides a chip (or chip system). The chip (or chip system) 1600 can include a circuit 1610 and an input / output interface 1620. The circuit 1610 can be a logic circuit, an integrated circuit, etc. The input / output interface 1620 can also be an input / output circuit, or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system can be composed of a chip, or can include a chip and other discrete devices. The chip 1600 can be used to execute the method performed by the encoding device in each embodiment of the present application. In addition, the present application further provides a computer readable storage medium, which stores computer instructions. When the computer instructions run on a computer, the operations and / or processes performed by the encoding device in each method embodiment of the present application are executed. The present application also provides a computer program product including computer program codes or instructions, which, when run on a computer, cause the operations and / or processes performed by the encoding device in any of the method embodiments of the present application to be performed. Further, the present application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the encoding device in any of the method embodiments are performed. Further, the chip can also include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can also include a memory for storing codes and / or instructions required by the chip to perform the encoding method of the present application. The present application provides a communication system including the encoding device in the embodiments of the present application, which is configured to implement steps 410-430 of the method embodiments. In some embodiments, the encoding device is a communication device having corresponding encoding functions as shown in FIG. 14 or FIG. 15, or a chip configured to implement the encoding method of the embodiments of the present application as shown in FIG. 16. In the embodiments of the present application, “multiple” includes two or more. Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented by other manners. For example, the device embodiments described above are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme. In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

Claims

1. A PC code-based communication method characterized by comprising: The method comprises: obtaining a payload sequence, wherein the payload sequence comprises a sequence of information bits carried by control information or a sequence of information bits transmitted by any one of a broadcast channel, an uplink data channel and a downlink data channel; performing pre-transformation coding on the payload sequence, wherein the pre-transformation coding comprises CRC coding and PC coding, to obtain an output sequence; performing channel coding on the output sequence to obtain a sequence of code words.

2. A PC code-based communication method characterized by comprising: The method comprises: obtaining a received sequence; performing channel decoding on the received sequence to obtain a first sequence of bits; performing pre-transformation decoding on the first sequence of bits, wherein the pre-transformation decoding comprises CRC decoding and PC decoding, to obtain a decoded sequence; wherein the pre-transformation decoding is decoding of a coded payload sequence, and the payload sequence comprises a sequence of information bits carried by control information or a sequence of information bits transmitted by any one of a broadcast channel, an uplink data channel and a downlink data channel.

3. The method of claim 1, wherein, The channel coding comprises polar coding, and a mother code length N of the polar coding is greater than or equal to 1024.

4. The method according to one of claims 1 to 3, characterized in that, A payload length K of the payload sequence comprises one of 32, 40, 48, 56 and 64.

5. The method of claim 4, wherein, The payload sequence comprises a sequence of information bits in a broadcast channel.

6. The method of any one of claims 1 or 3-5, wherein, The polar coding adopts puncturing as a rate matching mode.

7. The method of any one of claims 1 or 3-6, wherein, The pre-transformation coding comprises: performing PC coding on the payload sequence according to a first shift register.

8. The method of claim 7, wherein, If a current position of the payload sequence corresponds to a message bit, an output bit of the first shift register is read from the first shift register.

9. The method of claim 7, wherein, If the pre-transformation coding is a systematic code, an output of the first shift register is related to a set to which the current position of the payload sequence belongs, and the method comprises: if the current position of the payload sequence belongs to a set of message bits, the output of the first shift register is an input of the first shift register; if the current position of the payload sequence belongs to a set of dynamic frozen bits, the output bit of the first shift register is read from the first shift register; if the current position of the payload sequence belongs to a set of frozen bits, the output of the first shift register is 0.

10. The method of any one of claims 1 or 3-6, wherein, The pre-transformation coding comprises: performing PC coding on the payload sequence according to a second shift register; a length of the second shift register is 5; if the current position of the payload sequence corresponds to a message bit, a value of a leftmost shift register of the second shift register is XORed with a current bit, and the value is stored in the leftmost shift register, and a current input message bit is taken as a bit at the current position, and then the second shift register is circularly shifted; if the current position of the payload sequence corresponds to a check bit, a value of the leftmost shift register is taken as the check bit, and then the second shift register is circularly shifted; if the current position of the payload sequence corresponds to a frozen bit, 0 is directly output as the bit at the current position, and then the second shift register is circularly shifted.

11. The method of any one of claim 10, the payload sequence comprising a sequence of information bits of a broadcast channel, characterized in that, The n pc > 0, 12. A communications device, characterized by The method comprises: The communication module is configured to obtain a payload sequence, the payload sequence comprising a sequence of information bits carried by control information or a sequence of information bits transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel; The processing module is configured to: perform pre-transformation encoding on the payload sequence, the pre-transformation encoding comprising CRC encoding and PC encoding, to obtain an output sequence; perform channel encoding on the output sequence, to obtain a sequence of code words.

13. A communications device, characterized by The communication module is configured to obtain a received sequence; The processing module is configured to: perform channel decoding on the received sequence, to obtain a first sequence of bits; perform pre-transformation decoding on the first sequence of bits, the pre-transformation decoding comprising CRC decoding and PC decoding, to obtain a decoded sequence; The pre-transformation decoding is decoding of an encoded payload sequence, the payload sequence comprising a sequence of information bits carried by control information or a sequence of information bits transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel. The channel encoding comprises polar encoding, and a mother code length N used by the polar encoding is greater than or equal to 1024.

14. The communication apparatus according to claim 12 or 13, characterized by A payload length K of the payload sequence comprises one of 32, 40, 48, 56, and 64.

15. The communication apparatus according to one of claims 12-14, wherein, The payload sequence comprises a sequence of information bits in a broadcast channel.

16. The communication apparatus according to claim 15, wherein The polar encoding uses puncturing as a rate matching manner.

17. The communication apparatus according to any one of claims 12 or 14-16, wherein, The processing module is configured to perform PC encoding on the payload sequence according to a first shift register.

18. The communication apparatus according to any one of claims 12 or 14-17, wherein, The pre-transformation encoding is a non-systematic code, and an output bit of the shift register is read from the shift register if a current position of the payload sequence corresponds to a message bit.

19. The communication apparatus according to claim 18, wherein The pre-transformation encoding is a systematic code, and an output of the shift register is related to a set to which the current position of the payload sequence belongs, the output of the shift register being an input of the shift register if the current position of the payload sequence belongs to a set of message bits, the output bit of the shift register being read from the shift register if the current position of the payload sequence belongs to a set of dynamic frozen bits, and the output of the shift register being 0 if the current position of the payload sequence belongs to a set of frozen bits.

20. The communication apparatus according to claim 18, wherein, The processing module is configured to:

21. The communication apparatus according to any one of claims 12 or 14-17, wherein, perform PC encoding on the payload sequence according to a second shift register; The second shift register has a length of 5. If the current position of the payload sequence corresponds to a message bit, a current bit is XORed with a value of a leftmost shift register of the second shift register, and the value is stored in the leftmost shift register, a message bit input at present is stored as a bit at the current position, and then the second shift register is circularly shifted. If the current position of the payload sequence is a check bit, a value of the leftmost shift register is taken as the check bit, and then the second shift register is circularly shifted. If the current position of the payload sequence is a frozen bit, 0 is directly output as the bit at the current position, and then the second shift register is circularly shifted. The communication interface and the circuit are configured to 22. The communication apparatus according to any one of claims 12-21, wherein the sequence of pay loads comprises a sequence of information bits of a broadcast channel. The n pc > 0, 23. A communications device, characterized by ​ The communication interface is configured to receive the payload sequence and input the payload sequence to the circuit; and output a codeword sequence, the codeword sequence being output by the circuit. The circuit is configured to cause the method of any one of claims 1-11 to be implemented.

24. A communications device, characterized by Comprising: a processor coupled to a memory, the processor configured to execute a computer program or instructions stored in the memory to cause the method of any one of claims 1-11 to be implemented.

25. A computer readable storage medium, characterized in that, The computer readable storage medium has stored therein computer instructions, when the computer instructions are run on a computer, the method of any one of claims 1-11 is implemented.

26. A computer program product, characterised in that, The computer program product comprises computer program code or instructions, when the computer program code or instructions are run on a computer, the method of any one of claims 1-11 is implemented.

27. A communication system, characterized by Comprising a communication device for performing the method of any one of claims 1, 3-11, and a communication device for performing the method of any one of claims 2-11.

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