Device and method for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase

Abstract

The device and the method for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase allow the respective subscriber, which is to be addressed, to be selected both according to one of two different bus shunt configurations and according to one of two addressing current feed variants. The two bus shunt configurations differ in that, in one case, the subscriber has only one internal bus shunt (Rint), while, in the second case, it has a parallel circuit comprising the internal bus shunt (Rint) and an external bus shunt (Rext). When the addressing current feed is selected, a distinction is made between the feed into the bus connection (28) facing the respective bus master (16) or the bus connection (24) facing away from the bus master (16).

Description

[0001] 01358DEWO 243071WO FK-Hi / wi17.03.2025 Device and method for detecting an addressing current in a bus shunt configuration of a participant in a communication bus system during an address assignment phase. The invention relates to a device and a method for detecting an addressing current in a bus shunt configuration of a participant in a communication bus system during an address assignment phase. The communication bus system has a bus master connected to a communication bus to which several participants are serially connected. The relative positions of the participants within the communication bus are defined below as "downstream" and / or "upstream." This definition is made "from the perspective of the bus master."Thus, all participants are located downstream of the bus master. Of the participants, one participant is the participant connected to the communication bus closest to the bus master downstream of the communication bus, and another participant is the participant connected to the communication bus furthest downstream from the bus master. Additional participants are connected to the communication bus between these two participants. A participant connected to the communication bus adjacent to another participant toward the bus master is located upstream of said other participant. Accordingly, a participant connected to the communication bus further away from the bus master than its neighbor isconnected to the communication bus downstream of the bus master. During the address assignment phase, in several consecutive address assignment cycles, one of the participants not yet assigned an address is successively identified as the participant to which an address can be assigned by the bus master. This participant no longer participates in subsequent address assignment cycles after receiving its address. The successive identification of the only participant to be assigned an address by the bus master always concerns the participant connected to the communication bus furthest downstream of the bus master from the group of participants not yet assigned an address. The "second-to-last participant" in this respect is therefore a participant that is connected to the communication bus upstream of this "last participant" with respect to the "last participant."while the "last participant" in relation to the "second-to-last participant" (and in relation to all other participants connected to the communication bus between the "second-to-last participant" and the bus master) is the participant connected to the communication bus downstream of the "second-to-last participant." In serial communication bus systems, the individual participants serially connected to a communication bus originating from a bus master are preferably addressed automatically. This occurs in several consecutive address assignment cycles within an address assignment phase, which typically occurs with the initialization of the communication bus system, for example, each time the communication bus system is started up. For each address assignment cycle, the participant that has not yet been addressed is identified among the participantswhich is connected to the communication bus furthest downstream from the master. The not yet addressed devices each feed an addressing current into the communication bus. Each device has an internal bus shunt, whereby the addressing current fed in by the device is, in a first variant, fed directly into the communication bus so that it does not flow through its internal bus shunt. This results in the last device, i.e., the one connected to the communication bus furthest from the bus master, essentially detecting a voltage drop of 0 via its internal bus shunt (a quiescent current possibly flowing through this device to stabilize the communication bus is not taken into account here), while the other not yet addressed devices connected upstream of said last device each detect a voltage drop via their internal bus shunt resistors.which is greater than a predefined threshold (close to 0 V). Thus, the last participant connected to the communication bus furthest from the bus master identifies itself. If an address is then placed on the communication bus by the bus master, only this last participant adopts this address as its address. 01358DEWO 243071WO FK-Hi / wi17.03.2025 The participant addressed in this way no longer participates in subsequent address assignment cycles. Typically, a preselect phase precedes each address assignment cycle, in which a group of "last participants" is selected from the multitude of not yet addressed participants. These groups, compared to the other not yet addressed participants, are the ones connected to the communication bus furthest from the bus master.not yet addressed participants. These preselect phases are generally known and serve to protect the communication bus from overload due to the feeding of the addressing current by all not yet addressed participants. The special features of this preselect phase will not be discussed further here, as they are generally known. However, there are also configurations in which, in addition to the internal bus hunt, an external bus shunt is connected to the communication bus for each participant. The bus shunt configuration per participant thus has a parallel connection of an external and internal bus shunt. The resistance value of the external bus shunt is typically smaller than that of the internal bus hunt, so that the series connection results in a total bus shunt with a value that is smaller than the smaller of the two parallel-connected bus shunts. It is obvious thatthat, depending on the bus shunt configuration, different thresholds must be provided for the detection of the addressing current in the last unaddressed device. Devices that are to be designed for both bus shunt configuration variants therefore require different circuit concepts, whereby, in particular, the gain factors of the amplifier that receives the voltage drop across the internal bus shunt alone or via the parallel connection of the internal and external bus shunt resistors must be selected differently. Another variant for determining the "last" unaddressed device in a serial communication bus system during address assignment 01358DEWO 243071WO FK-Hi / wi17.03.2025 has an addressing current source that feeds its addressing current into the communication bus via the internal bus shunt. The current source is controlled in such a way thatthat the voltage drop between the terminals of the internal bus shunt has a predetermined value. If this voltage drop is reached by feeding the address current with a predetermined value, this is a sign that the respective device is the last unaddressed device, i.e., the unaddressed device furthest from the bus master on the communication bus. If, on the other hand, the voltage drop of the predetermined value occurs with an addressing current that is smaller than the predetermined addressing current, this is a sign that an addressing current is also being fed into the communication bus from downstream of the communication bus by a device connected further "back" on the communication bus. Therefore, the device in question is not the last unaddressed device. Only the unaddressed deviceThe device that measures the voltage drop with the specified magnitude when the specified addressing current is applied is the last unaddressed device. Only this device then adopts the address that the bus master subsequently places on the communication bus as its address. To cover all three variants of bus shunt configurations and addressing current feeds with one and the same hardware, several pairs of bond pads on the hardware IC would be required to connect to the communication bus. Furthermore, the voltage measurement signals would have to be amplified to different levels within the device in order to be able to be preprocessed to the same magnitude for further digital signal processing, for example, in an analog-to-digital converter (ADC).which requires an input voltage in a predetermined minimum voltage range for its functional and reliable operation.01358DEWO 243071WO FK-Hi / wi17.03.2025 Bus systems of the two aforementioned types with automatic addressing of the bus participants are known from DE-A-102018104488 and DE-A-102018 104852. The object of the invention is to create a device for detecting an addressing current in a participant of a communication system in an address allocation phase, which device reliably covers the aforementioned cases and in particular the first two aforementioned cases and requires as little chip area as possible when integrated into an IC. The above object is achieved according to the invention by a device for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase, which has a bus master which is connected to a communication bus,to which several participants are serially connected, of which one participant is the participant connected to the communication bus closest to the bus master upstream of the communication bus, and of which another participant is the participant connected to the communication bus furthest away from the bus master downstream of the communication bus, with further participants being connected to the communication bus between these two participants, wherein in the address allocation phase, in several consecutive address allocation cycles, one of the participants not yet provided with an address is successively identified as the participant to which an address can be assigned by the bus master, and this participant no longer participates in subsequent address allocation cycles after receiving its address. The device according to the invention is provided with a first bus connection and a second bus connection,wherein the first bus connection is connectable to the communication bus via a first external electrical conductor downstream of the communication bus at a first connection point, and the second bus connection is connectable to the communication bus via a second external electrical conductor upstream of the communication bus at a second connection point, 01358DEWO 243071WO FK-Hi / wi17.03.2025 - an internal bus shunt with a first connection and with a second connection, - a first internal bonding wire between the first bus connection and the first connection of the internal bus shunt, - a second internal bonding wire between the second bus connection and the second connection of the internal bus shunt,- a first addressing current source connected to the second bus connection of the subscriber or to the second connection of the subscriber's internal bus shunt for feeding an addressing current into the first bus connection and / or the second bus connection, - an amplifier with a first input connection and a second input connection and with an output connection, - wherein the first input connection of the amplifier is connected to the first connection of the internal bus shunt and the second input connection of the amplifier is connected to the second connection of the internal bus shunt, and the amplifier outputs a voltage measurement signal between its two input connections amplified by a predetermined amplification factor at its output connection as an output signal, and - an electronic evaluation unit (with, for example, A / D and D / A converters, microcontroller, CPU, I / O interfaces, ROM,RAM) for evaluating the amplifier's output signal and for determining, based on a comparison of the size of the output signal with a selected one of several threshold values, which of the not yet addressed participants is the participant connected to the communication bus furthest downstream of the communication bus from the bus master, if necessary after an analog-to-digital conversion, -wherein in the address allocation phase, the evaluation in the evaluation unit takes place depending on the selection of the operation of the communication bus system according to one of several operating modes, -wherein in a first operating mode, the communication bus has no additional external bus shunt per participant and thus a first bus shunt configuration is given,in which the communication bus has an internal bus shunt for each participant, and the voltage difference between the two terminals of the internal bus shunt forms the measurement voltage signal, wherein in this first operating mode, the amplifier output signal is compared with a first threshold value, wherein the amplifier output signal of only one of the participants feeding an addressing current into the communication bus is smaller than the first threshold value, and - in a second operating mode, the communication bus has an additional, external bus shunt for each participant, which is arranged in the communication bus between the two connection points of the communication bus for the two external electrical conductors of a bus participant, thus providing a second bus shunt configuration,in which the communication bus has a parallel circuit consisting of the external bus shunt and the internal bus shunt for each participant, and the voltage difference between the two terminals of the internal bus shunt forms the measurement voltage signal. In this second operating mode, the amplifier output signal is compared with a second threshold value different from the first threshold value, with the amplifier output signal of only one of the participants feeding an addressing current into the communication bus being smaller than the second threshold value. A key feature of the invention is the ability to operate the amplifier amplifying the voltage measurement signal with one and the same gain factor for both possible bus shunt configurations. In this regard, a compromise has been found regarding the different magnitudes of the voltage measurement signal.which, with the same addressing current in the communication bus, flows through either the internal bus shunt alone or through the parallel connection of the external and internal bus shunts. 01358DEWO 243071WO FK-Hi / wi17.03.2025 An advantage of operating the amplifier with the same average gain for both cases is that the time required for the measurement is essentially the same in both cases. The reason for this is that a voltage measurement with low gain is faster than a voltage measurement with high gain, due to the reduced bandwidth at high gain. By selecting the same average gain, the measurements run in both operating modes.i.e., equally quickly in communication bus systems with the first bus shunt configuration and in bus communication systems with the second bus shunt configuration. Due to the elimination of a pair of connection pads and the multiplexer (this is required in the prior art to select the measurement voltage (voltage drop) assigned to the respective bus shunt configuration via only the internal bus shunt or via the parallel connection of internal and external bus shunts and to switch it to the amplifier), there is also the advantage of reduced chip area requirements. In a further advantageous embodiment of the invention, it is provided that in an address allocation phase, all participants to which no address has yet been assigned, or that in an address allocation phase, a group of neighboring participants not yet having an address,which are arranged downstream of the communication bus and which comprise the not yet addressed subscriber connected to the communication bus furthest from the bus master, each feed an addressing current into the communication bus by means of their addressing current sources, and that by comparing the output signal of the amplifier with the first threshold value or with the second threshold value in each of these subscribers, the subscriber whose measurement signal is smaller than the first threshold value or smaller than the second threshold value is identified as the subscriber connected to the communication bus furthest from the bus master downstream of the communication bus and not yet assigned an address, whereby an address can be assigned to this subscriber by the bus master.01358DEWO 243071WO FK-Hi / wi17.03.2025As already described above, it is common practice,that in a preselect phase preceding the address allocation phase, all participants to which no address has yet been assigned each feed a preselect current into the communication bus by means of their addressing current sources, and that the evaluation unit of each participant in the preselect phase compares the output signal of the amplifier with a selected one of several further threshold values, wherein - in the first operating mode, the comparison of the output signal of the amplifier with a third threshold value different from the first threshold value, which is smaller or larger than the first threshold value, or with the first threshold value takes place, and - in the second operating mode, the comparison of the output signal of the amplifier with a fourth threshold value different from the second threshold value, which is smaller or larger than the second threshold value, or with the second threshold value takes place. With further advantage, it can further be provided thatthat by comparing the amplifier output signal with the third or first threshold value or with the fourth or second threshold value in each of these participants in the preselect phase, those participants are identified as belonging to a group of participants whose amplifier output signals are smaller than the third or first threshold value or smaller than the fourth or second threshold value, whereby among the participants of this group, in the address allocation cycle following the preselect phase, in which only the participants of this group feed their addressing streams into the communication bus, an address can be assigned by the bus master to that participant,which is identifiable as the subscriber connected to the communication bus furthest away from the bus master downstream of the communication bus. In a further alternative for address assignment, there is an additional addressing current source connected to the subscriber's first bus connection, or there is a connection switching unit for selectively connecting the first addressing current source to either the subscriber's second bus connection or the subscriber's first bus connection, wherein the electronic evaluation unit has an addressing current controller, wherein in a third operating mode, an addressing current can be fed downstream, i.e., via the subscriber's first bus connection, into the communication bus through the additional addressing current source or through the first addressing current source connected to the subscriber's first bus connection by means of the connection switching unit.for whose magnitude the voltage measurement signal is representative, wherein the addressing current controller regulates the magnitude of the addressing current to a value at which an output signal is set at the amplifier which is equal to a fifth threshold value, and wherein of the not yet addressed participants, the participant connected to the communication bus furthest downstream of the communication bus from the bus master is identifiable,whose further addressing current source or whose first addressing current source feeds an addressing current of a predetermined magnitude into the communication bus (while the (first or further) addressing current sources of all other not yet addressed participants feed a lower or no addressing current). In the inventive concept, the amplifier operates in both operating mode 1 (hereinafter referred to as Type 1) and operating mode 2 (hereinafter referred to as Type 2) with the same average gain factor. In principle, the gain factor in Type 2 should be larger than in Type 1 due to the smaller overall bus shunt value due to the parallel bus shunt connection compared to Type 1. However, it has been found within the scope of the invention that the voltage measurement signal can be sufficiently amplified in both operating modes with one and the same average gain factor so that it can subsequently be processed by the ADC of an electronic evaluation unit,which, among other things, has a microcontroller, CPU, I / O interfaces, ROM, RAM, and can be preprocessed with sufficient quality for further digital signal processing, for example, to determine whether the respective threshold values ​​are exceeded or undershot. The "average gain" is considered to be a gain that lies between the "ideal" gain factors for each operating mode (e.g., arithmetic mean or weighted mean, or within an arithmetic or weighted mean range). The addressing current for operating modes 1 and 2 is approximately 2 mA. The internal bus shunt is approximately 1 Ω. In contrast, the resistance of the external bus shunt is approximately one order of magnitude smaller. It is, for example, 0.2 Ω to 0.3 Ω. This means,that the gain in the second operating mode would have to be about five times higher than the gain in the first operating mode. However, it has been shown that the ADC can always be operated at its (nominal) operating point or range if a medium gain is used in both cases. In the third operating state, the same gain can also be used. The addressing current supplied in the third operating state (hereinafter also referred to as Type 3) is approximately 10 mA. It is thus about five times as large as the addressing current of approximately 2 mA in the first and second operating modes. The larger addressing current in Type 3 results in a larger, i.e., approximately five times larger, voltage drop across the parallel circuit of the two bus shunt resistors, so that a smaller gain could be used. As stated, the invention, however, providesThis third operating mode also operates with the same average gain factor as for operating modes 1 and 2, so that the ADC is again operated in its (nominal) operating point or range. In the preselect phase, which applies to the first and second operating modes, an extremely low preselect addressing current, e.g., 300 µA, i.e., approximately 1 / 10 of the addressing current, is used. Those devices that internally detect a voltage measurement signal that, after amplification, has a value that is smaller than a prescribed threshold, are preselected. From this group of last devices, the last device in this group is then selected from the last unaddressed devices using the address assignment cycle 01358DEWO 243071WO FK-Hi / wi17.03.2025. As mentioned,This procedure is state of the art and will therefore not be discussed further. To achieve the above-mentioned object, the invention also proposes a method having the features of claim 6, with individual embodiments of the method according to the invention being the subject of claims 7 to 10. The invention is explained in more detail below using an exemplary embodiment and with reference to the drawing. In detail: Figs. 1 and 2 show block diagrams of two prior art circuits of subscribers connected to a serial communication bus for address assignment in a bus shunt configuration according to operating mode 1 or operating mode 2 (Fig. 1) or with address assignment according to each of these two operating modes and according to the third operating mode (Fig. 2). Fig. 3 shows the block diagram according to a first embodiment of the invention in operating mode 1, i.e., without an external bus shunt.Fig. 4 shows the block diagram according to the first embodiment of the invention in operating mode 2, i.e. with internal and external bus shunt, Fig. 5 shows the block diagram according to the second embodiment of the invention for optionally one of the three operating modes 1 to 3, shown here for operating mode 1, i.e. without external bus shunt, Fig. 6 shows the block diagram according to the second embodiment of the invention, optionally operable in operating mode 2 or 3 due to the now present external bus shunt, 01358DEWO 243071WO FK-Hi / wi17.03.2025 Fig. 7 shows a variant of the circuit according to Fig. 6 for optionally one of the operating modes 1 to 3, shown here for operating mode 1, i.e. without external bus shunt, and 8 the variant of the circuit according to Fig. 7, due to the now existing external bus shunt, can be operated either in operating mode 2 or 3. As already mentioned in the introduction to the description, it is generally knownthat in each participant 10 of a serial communication bus system, such as LIN, a device 12 is installed, which serves, among other things, to detect an addressing current flowing through the participant 10 during address assignment. The communication bus 14 has a plurality of participants 10 and, in addition, also a bus master 16. In Fig. 1 (as well as in all subsequent figures), it is indicated in the communication bus 14 above and below the participant 10 shown in detail with its device 12 that further participants are connected to the communication bus 14. In addition, the current source 18 symbolizes that the participant 10 shown with the detailed device 12 receives a current resulting from the addressing currents from the direction downstream of the communication bus 14 (seen from the bus master 16) during the address assignment phase.which are fed into the communication bus 14 by participants arranged further downstream of the communication bus. The device 12 comprises an integrated circuit in an IC die 20, which in this exemplary embodiment has a plurality of connection pads. These connection pads are connected to bus connections of an IC package 22 via bond wires. A first bus connection 24 of the IC package 22 is connected to a first communication bus connection point 26, while a second bus connection 28 of the IC package 22 is connected to a second communication bus connection point 30. The first bus connection 24 is connected to a first connection pad 34 of the IC die 01358DEWO 243071WO FK-Hi / wi17.03.202520 via a first bond wire line 32.while a second bond wire line 36 connects the second bus terminal 28 of the IC package 22 to a second connection pad 38 of the IC die 20. These bond wire lines and all others are referred to below as bond wire or bond wires. The two connection pads 34, 38 form the connections for an internal bus shunt Rint. The connections 34, 38 are identical to the first and second connections 34', 38' of the internal bus shunt Rint. The two bus connections 24 and 28 are also connected to further connection pads 44, 46 of the IC die 20 by further bond wires 40, 42. Finally, the IC die 20 has an additional connection pad 48 to which the output of an addressing current source 50 of the device 12 is connected and which in turn is connected to the second bus connection 28 via a bonding wire 49. The device 12 also has a connection switching unit 52 (hereinafter referred to as a multiplexer) which has two inputs 54,56 and an output 58. One of the two inputs 54 is formed by the two connections 34, 38 of the internal bus shunt Rint, while the other input 56 is formed by the two further connection pads 44, 46 of the IC die 20. The voltage drop across the internal bus shunt Rint is therefore present at one input 54, while the voltage difference between the two further connection pads 44, 46 is present at the other input 56. If the communication bus 14 is provided with an external bus shunt Rext for each participant 10, the voltage between the connection pads 44 and 46 is identical to the voltage between the bus connections 24 and 28, since no current flows via the bond wires 40, 42. Rather, a current flows through the bond wires 32, 36 via Rint, whereby the voltage at the connection pads 34, 38 is lower than at the connection pads 44, 46, since the bond wires 32, 36 each have a parasitic resistance,across which the current flow causes a voltage drop.01358DEWO 243071WO FK-Hi / wi17.03.2025 The output 58 of the multiplexer 52 is connected to an amplifier 60 whose gain factor is variably adjustable. The amplified analog output signal of the multiplexer 52 is converted into digital form for further processing by an analog-to-digital converter 62 of an evaluation unit 63. The device 12 according to Fig. 1 allows the subscriber 10 to be automatically addressed in two different bus shunt configurations (Type 1, Type 2). In the case of Type 1, only the internal bus shunt Rint exists, whereas in Type 2 of the address allocation method, the external bus shunt Rext also exists. As described above, during the address assignment phase, the bus participants each feed an addressing current into the communication bus 14, which flows to the bus master 16. Since this addressing current is fed into the second bus connection 28 (see Fig. 1),The bus current of a device does not influence the voltage drop across its internal bus shunt Rint in Type 1 or across the parallel connection of internal and external bus shunts (in Type 2). Therefore, if a voltage drop is detected at the connection pad pairs 34, 38 or 44, 46, respectively, this can only have been caused by a current flowing through the device 10 in the communication bus 14 from downstream of the device 10 in question, i.e., from the "rear" part of the communication bus 14 (any quiescent current flowing in the communication bus 14 for stabilization purposes will be disregarded for simplicity). The voltage drop across the internal bus shunt Rint in Type 1 is greater, with the same addressing current flowing into the device 10 via the communication bus 14, than in the case of Type 2, where the two bus shunts R, int and R extare connected in parallel, and thus their total resistance is smaller than Rint due to the external bus-hunt Rext, which is approximately one order of magnitude smaller than Rint. Accordingly, the gain factor in amplifier 60 changes (increases). Only the corresponding input is switched through to output 58 via multiplexer 52. Both are controlled by a select signal 64. The previously described circuit concept of Fig. 1 is known in an expanded form according to the prior art, as shown in Fig. 2. The additional option concerns the operating mode 3 already described above, in which an addressing current flows through the parallel circuit of internal and external bus shunts for each participant, and is then fed into the communication bus 14 in the direction of the bus master via the second bus connection 28. In Fig.2, a further bond switching unit 66 (hereinafter referred to as multiplexer) is connected between the output of the addressing current source 50 and the additional connection pad 48 of the IC die 20, one output 68 of which (type 1 and type 2) is connected to the additional connection pad 48 and the other output 70 of which (type 3) is connected to an additional connection pad 72 of the IC die 20, which is connected to the first bus connection 24 via a bond wire 74. In operating mode 3 (type 3), the input 76 of the multiplexer 66 is therefore connected to its output 70, whereby the addressing current is fed into the communication bus 14 via the first bus connection 24 and thus via the parallel connection of the two bus shunts. The multiplexer 66 is controlled via a further select signal 78 in order to feed the addressing current into the communication bus 14 either via the first bus connection 24 or via the second bus connection 28. In Figs.In Figures 1 and 2, A1, A2, and A3 indicate the respective amplification factor of amplifier 60 in the three operating modes (Type 1, Type 2, and Type 3). The amplification factor depends, among other things, on the analog-to-digital converter 62 operating at its operating point or operating point range and thus reliably. A certain disadvantage of the circuit concepts of Figures 1 and 2 can be seen in the comparatively large chip area required, due to the large number of connection pads of the IC die 20 and the two multiplexers, in particular the multiplexer 52. Finally, the requirement to make the amplification factor switchable is also a certain disadvantage, since the test time for series production is extended because tests must now be performed for multiple amplification factors. With the inventive approach, all of the previously mentioned disadvantages and limitations are eliminated. In Figures 1 and 2, the circuit concepts of Figures 1 and 2 are shown in Figures 2 and 3.3 to 8 show various embodiments of devices according to the invention for detecting the size of addressing currents flowing through the participants of a serial communication bus system during the address allocation phase. Insofar as the elements of the participant 10 and the communication bus system according to each of FIGS. 3 to 8 are the same or similar to those of FIGS. 1 and 2, they are identified in FIGS. 3 to 8 with the same reference numerals as in FIGS. 1 and 2. FIGS. 3 and 4 jointly cover operating modes 1 and 2, i.e. the two bus shunt configurations in which either only the internal bus shunt Rint is present or, in addition to this internal bus shunt, the external bus shunt Rext is also present. It can be seen that the multiplexer 52 according to FIGS. 1 and 2 can be dispensed with, which also means that the area on the IC die 20 for the two additional connection pads 44, 46 of Figs. 1 and 2 can be dispensed with.The amplifier 60 is also simplified in that it operates in both operating modes 1 and 2 with an identical, average gain factor, which allows both the comparatively large voltage drop signal across the internal bus shunt Rint in operating mode 1 (type 1) to be amplified so that the analog-to-digital converter 62 operates properly, and the comparatively small voltage drop signal in operating mode 2 (type 2 with bus shunt configuration as a parallel circuit of internal and external bus shunt) to be sufficiently amplified so that the analog-to-digital converter 62 again operates properly. Figs. 5 and 6 show a further embodiment of the device according to the invention, with which operation can be optionally carried out according to one of the operating modes 1 to 3 in the address assignment phase. Whether the addressing current in the01358DEWO 243071WO FK-Hi / wi17.03.2025 first bus connection 24 (type 3) or into the second bus connection 28 (types 1 and 2) is decided by the multiplexer 66, to which the select signal 64 is fed. In all three operating modes, the amplifier 60 can operate with one and the same average gain factor. A variant of the circuit concept according to Figs. 5 and 6 can be seen in Figs. 7 and 8. The difference between the concept according to these last two figures and the concept according to Figs. 5 and 6 is that the two additional connection pads 48 and 72 (as in the circuit according to Fig. 2) are provided for feeding the addressing current on the IC die 20.

[0002] 01358DEWO 243071WO FK-Hi / wi17.03.2025 LIST OF REFERENCE SYMBOLS 10 Teilnehmer 12 Device14 Communication bus16 Bus master18 Power source 20 IC-Die22 IC package 24 First bus connection 26 First communication bus connection point 28 Second bus connection 30 Second communication bus connection point 32 First bonding wire 34 First connection pad 34' First connection of the internal bus shunt 36 Second bonding wire 38 Second connection pad 38' Second connection of the internal bus shunt 40 Additional bonding wire 42 Additional bonding wire 44 Additional connection pad 46 Additional connection pad 48 Additional connection pad 49 Bonding wire 50 Addressing current source 52 Multiplexer (connection switching unit) 54 Input 56 Input 58 Output 60 Amplifier 62 Analog-to-digital converter 63 Evaluation unit 64 Select signal 01358DEWO 243071WO FK-Hi / wi 17.03.2025 66 Multiplexer (connection switching unit) 68 Output 70 Output 72 Additional connection pad 74 Bonding wire 76 Input 78 Additional select signal Rint Internal bus shunt Rext External bus shunt

Claims

01358DEWO 243071WO FK-Hi / wi17.03.2025 CLAIMS1. Device for detecting an addressing current in a bus shunt configuration of a participant of a communication bus system in an address allocation phase, which has a bus master (16) connected to a communication bus (14), to which several participants (10) are serially connected, of which one participant (10) is the participant (10) connected to the communication bus (14) closest to the bus master (16) downstream of the communication bus (14), and of which another participant (10) is the participant (10) connected to the communication bus (14) furthest away from the bus master (16) downstream of the communication bus (14), wherein further participants (10) are connected to the communication bus (14) between these two participants (10),wherein, in the address allocation phase, in several consecutive address allocation cycles, one of the participants (10) not yet provided with an address is successively identified as the participant (10) to whom an address can be assigned by the bus master (16), and this participant (10) no longer participates in subsequent address allocation cycles after receiving its address, and wherein the device (12) is provided with - a first bus connection (24) and a second bus connection (28), wherein the first bus connection (24) is connectable to the communication bus (14) via a first external electrical conductor downstream of the communication bus (14) at a first connection point (26), and the second bus connection (28) is connectable to the communication bus (14) via a second external electrical conductor upstream of the communication bus (14) at a second connection point (30),-an internal bus shunt (Rint) with a first terminal (34') and with a second terminal (38'), - a first internal bonding wire line (32) between the first bus terminal (28) and the first terminal (34') of the internal bus shunt (Rint),01358DEWO 243071WO FK-Hi / wi17.03.2025- a second internal bonding wire line (36) between the second bus terminal (28) and the second terminal (38') of the internal bus shunt, usshunts (Rint),- a first addressing current source (50) connected to the second bus connection (28) of the subscriber (10) or to the second connection (38') of the internal bus shunt (Rint) of the subscriber (10) for feeding an addressing current into the first bus connection (24) and / or into the second bus connection (28), - an amplifier (60) having a first input connection and a second input connection and an output connection, - wherein the first input connection of the amplifier (60) is connected to the first connection (34') of the internal bus shunt (Rint) and the second input connection of the amplifier (60) is connected to the second connection (38') of the internal bus shunt (Rint), and the amplifier (60) outputs a voltage measurement signal between its two input connections, amplified by a predetermined gain factor, as an output signal at its output connection,and- an electronic evaluation unit (63) for evaluating the output signal of the amplifier (60) and for determining, based on a determination, optionally after an analog-to-digital conversion, by comparing the magnitude of the output signal with a selected one of several threshold values, which of the not yet addressed subscribers (10) is the subscriber (10) connected to the communication bus (14) downstream of the communication bus (14) furthest from the bus master (16),- wherein, in the address allocation phase, the evaluation in the evaluation unit takes place depending on the selection of the operation of the communication bus system according to one of several operating modes, wherein - in a first operating mode, the communication bus (14) has no additional external bus shunt (Rext) per subscriber (10) and thus a first bus shunt configuration is given,in which the communication bus (14) has the internal bus shunt (Rint) for each participant (10) and the voltage difference between the two terminals (34', 38') of the internal bus shunt (Rint) forms the measurement voltage signal, wherein in this first operating mode the comparison of the output signal of the amplifier (60) with a first threshold value takes place, wherein the output signal of the amplifier (60) of only one of the participants (10) feeding an addressing current into the communication bus (14) is smaller than the first threshold value, and - in a second operating mode the communication bus (14) has an additional, external bus shunt (Rext) for each participant (10), which in the communication bus (14) between the two connection points (26, 28) of the communication bus (14) for the two external electrical conductors of a subscriber (10) are arranged and thus a second bus shunt configuration is given,in which the communication bus (14) has a parallel circuit of the external bus shunt (Rext) and the internal bus shunt (Rint) for each subscriber (10), and the voltage difference between the two terminals (34', 38') of the internal bus shunt (Rint) forms the measurement voltage signal, wherein in this second operating mode, the comparison of the output signal of the amplifier (60) with a second threshold different from the first threshold is carried out, wherein the output signal of the amplifier (60) of only one of the subscribers (10) feeding an addressing current into the communication bus (14) is smaller than the second threshold.

2. Device according to claim 1, characterized in that in an address allocation phase, all subscribers (10) to which no address has yet been assigned or a group of neighboring subscribers (10) not yet having an address,which are arranged downstream of the communication bus (14) and which comprise the not yet addressed subscriber (10) connected to the communication bus (14) furthest from the bus master (16), each feed an addressing current into the communication bus (14) by means of their addressing current sources (50), and that by comparing the output signal of the amplifier (60) with the first threshold value or with the second threshold value in each of these subscribers (10), the subscriber (10) whose measurement signal is smaller than the first threshold value or smaller than the second threshold value is identified as the subscriber connected to the communication bus (14) furthest from the bus master (16) and not yet assigned an address provided subscriber (10) is identified, whereby the bus master (16) can assign an address for this subscriber (10).

3. Device according to claim 1 or 2,characterized in that in a preselect phase preceding the address allocation phase, all participants (10) to which no address has yet been assigned each feed a preselect current into the communication bus (14) by means of their addressing current sources (50), and in that the evaluation unit (63) of each participant (10) compares the output signal of the amplifier (60) with a selected one of several further threshold values ​​in the preselect phase, wherein - in the first operating mode, the comparison of the output signal of the amplifier (60) with the first threshold value or with a third threshold value different from the first threshold value, which is smaller or larger than the first threshold value, takes place, and - in the second operating mode, the comparison of the output signal of the amplifier (60) with the second threshold value or with a fourth threshold value different from the second threshold value, which is smaller or larger than the second threshold value,occurs.

4. Device according to claim 3, characterized in that by comparing the output signal of the amplifier (60) with the first or with the third threshold value or with the second or with the fourth threshold value in each of these participants (10) in the preselect phase, those participants (10) are identified as belonging to a group of participants (10) whose amplifier output signals are smaller than the first or third threshold value or smaller than the second or fourth threshold value, wherein, among the participants (10) of this group, an address can be assigned by the bus master (16) in the address allocation cycle following the preselect phase to that participant (10) which, as the participant connected to the communication bus (14) downstream of the communication bus (14), is furthest away from the bus master (16). (10) is identifiable.

5. Device according to one of claims 1 to 4,characterized by - a further addressing current source connected to the first bus connection (24) of the subscriber (10) or - a connection switching unit (66) for selectively connecting the first addressing current source (50) to either the second bus connection (28) of the subscriber (10) or the first bus connection (24) of the subscriber (10), - wherein the electronic evaluation unit (63) has an addressing current regulator, - wherein in a third operating mode, in which the bus shunt configuration is the same as in the second operating mode, an addressing current can be fed downstream into the communication bus (14) by the further addressing current source or by the first addressing current source (50) connected to the first bus connection (24) of the subscriber (10) by means of the connection switching unit (66), for the magnitude of which addressing current the voltage measurement signal is representative, - wherein the addressing current regulator determines the magnitude of the Addressing current to a value,in which an output signal equal to a fifth threshold value is established at the amplifier (60), and -wherein of the not yet addressed participants (10), the participant (10) connected to the communication bus (14) furthest downstream of the communication bus (14) from the bus master (16) and thus the only one of the not yet addressed participants (10) is identifiable whose further addressing current source or whose first addressing current source (50) feeds an addressing current with a predetermined size into the communication bus (14).01358DEWO 243071WO FK-Hi / wi17.03.20256. Method for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase, which has a bus master (16) connected to a communication bus (14) to which several subscribers (10) are serially connected,of which one participant (10) is the participant (10) connected to the communication bus (14) closest to the bus master (16) downstream of the communication bus (14), and of which another participant (10) is the participant (10) connected to the communication bus (14) furthest away from the bus master (16) downstream of the communication bus (14), with further participants (10) being connected to the communication bus (14) between these two participants (10), with each of the participants (10) not yet provided with an address being successively identified in the address allocation phase in several consecutive address allocation cycles as the participant (10) to whom an address can be assigned by the bus master (16), and this participant (10) no longer participates in subsequent address allocation cycles after receiving its address,-wherein the device (12) is provided with- a first bus connection (24) and a second bus connection (28), wherein the first bus connection (24) is connectable to the communication bus (14) via a first external electrical conductor downstream of the communication bus (14) at a first connection point (26), and the second bus connection (28) is connectable to the communication bus (14) via a second external electrical conductor upstream of the communication bus (14) at a second connection point (30), -an internal bus shunt (Rint) with a first connection (34') and with a second connection (38'), -a first internal bonding wire line (32) between the first bus connection (28) and the first connection (34') of the internal bus shunt (Rint),01358DEWO 243071WO FK-Hi / wi17.03.2025 -a second internal bonding wire (36) between the second bus terminal (28) and the second terminal (38') of the internal bus shunt (Rint),-a first addressing current source (50) connected to the second bus connection (28) of the subscriber (10) or to the second connection (38') of the internal bus shunt (Rint) of the subscriber (10) for feeding an addressing current into the first bus connection (24) and / or the second bus connection (28), -an amplifier (60) having a first input connection and a second input connection and an output connection, -wherein the first input connection of the amplifier (60) is connected to the first connection (34') of the internal bus shunt (Rint) and the second input connection of the amplifier (60) is connected to the second connection (38') of the internal bus shunt (Rint), and the amplifier (60) outputs a voltage measurement signal between its two input connections, amplified by a predetermined amplification factor, at its output connection as an output signal,and -an electronic evaluation unit (63) for evaluating the output signal of the amplifier (60) and for determining, based on a determination, optionally after an analog-to-digital conversion, by comparing the magnitude of the output signal with a selected one of several threshold values, which of the not yet addressed subscribers (10) is the subscriber (10) connected to the communication bus (14) downstream of the communication bus (14) furthest from the bus master (16), - wherein, in the address allocation phase, the evaluation in the evaluation unit takes place depending on the selection of the operation of the communication bus system according to one of several operating modes, wherein -in a first operating mode, the communication bus (14) has no additional external bus shunt (Rext) per subscriber (10) and thus a first bus shunt configuration is given,01358DEWO 243071WO FK-Hi / wi17.03.2025 in which the communication bus (14) has the internal bus shunt (Rint) for each participant (10), and the voltage difference between the two terminals (34', 38') of the internal bus shunt (Rint) forms the measurement voltage signal, wherein in this first operating mode, the comparison of the output signal of the amplifier (60) with a first threshold value takes place, wherein the output signal of the amplifier (60) of only one of the participants (10) feeding an addressing current into the communication bus (14) is smaller than the first threshold value, and - in a second operating mode, the communication bus (14) has an additional, external bus shunt (Rext) for each participant (10), which is arranged in the communication bus (14) between the two connection points (26, 28) of the communication bus (14). is arranged for the two external electrical conductors of a subscriber (10) and thus a second bus shunt configuration is provided,in which the communication bus (14) has a parallel circuit comprising the external bus shunt (Rext) and the internal bus shunt (Rint) for each subscriber (10), and the voltage difference between the two terminals (34', 38') of the internal bus shunt (Rint) forms the measurement voltage signal, wherein in this second operating mode, the comparison of the output signal of the amplifier (60) with a second threshold different from the first threshold is carried out, wherein the output signal of the amplifier (60) of only one of the subscribers (10) feeding an addressing current into the communication bus (14) is smaller than the second threshold.

7. Method according to claim 6, characterized in that in an address allocation phase, all subscribers (10) to which no address has yet been assigned or a group of neighboring subscribers (10) not yet having an address,which are arranged downstream of the communication bus (14) and which comprise the subscriber (10) connected furthest from the bus master (16) to the communication bus (14) and not yet addressed, by means of their addressing current sources (50) each feed an addressing current into the communication bus (14), and that by comparing the output signal of the amplifier (60) with the first threshold value or with the second threshold value in each of these subscribers (10), the subscriber (10) whose measurement signal is smaller than the first threshold value or smaller than the second threshold value is identified as the subscriber connected furthest from the bus master (16) to the communication bus (14) and not yet assigned an address provided subscriber (10) is identified, whereby the bus master (16) can assign an address for this subscriber (10).

8. Method according to claim 6 or 7,characterized in that in a preselect phase preceding the address allocation phase, all participants (10) to which no address has yet been assigned each feed a preselect current into the communication bus (14) by means of their addressing current sources (50), and in that the evaluation unit (63) of each participant (10) compares the output signal of the amplifier (60) with a selected one of several further threshold values ​​in the preselect phase, wherein - in the first operating mode, the comparison of the output signal of the amplifier (60) with the first threshold value or with a third threshold value different from the first threshold value, which is smaller or larger than the first threshold value, and - in the second operating mode, the comparison of the output signal of the amplifier (60) with the second threshold value or with a fourth threshold value different from the second threshold value, which is smaller or larger than the second threshold value,occurs.

9. Method according to claim 8, characterized in that by comparing the output signal of the amplifier (60) with the first or with the third threshold value or with the second or with the fourth threshold value in each of these participants (10) in the preselect phase, those participants (10) are identified as belonging to a group of participants (10) whose amplifier output signals are smaller than the first or third threshold value or smaller than the second or fourth threshold value, wherein, among the participants (10) of this group, in the address allocation cycle following the preselect phase, an address can be allocated by the bus master (16) to that participant (10) which, as the participant connected to the communication bus (14) downstream of the communication bus (14), is furthest away from the bus master (16). (10) is identifiable.

10. Method according to one of claims 6 to 9,characterized by - a further addressing current source connected to the first bus connection (24) of the subscriber (10) or - a connection switching unit (66) for selectively connecting the first addressing current source (50) to either the second bus connection (28) of the subscriber (10) or the first bus connection (24) of the subscriber (10), - wherein the electronic evaluation unit (63) has an addressing current regulator, - wherein in a third operating mode, in which the bus shunt configuration is the same as in the second operating mode, an addressing current can be fed downstream into the communication bus (14) by the further addressing current source or by the first addressing current source (50) connected to the first bus connection (24) of the subscriber (10) by means of the connection switching unit (66), for the magnitude of which addressing current the voltage measurement signal is representative, - wherein the addressing current regulator determines the magnitude of the Addressing current to a value,in which an output signal equal to a fifth threshold value is established at the amplifier (60), and -wherein of the not yet addressed participants (10), the participant (10) connected to the communication bus (14) furthest downstream of the communication bus (14) from the bus master (16) and thus the only one of the not yet addressed participants (10) is identifiable whose further addressing current source or whose first addressing current source (50) feeds an addressing current of a predetermined magnitude into the communication bus (14).,

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