Quantum semiconductor

Abstract

The present invention comprises a quantum bit array including: a first transistor for storing electrons or holes in a semiconductor layer; a second transistor and a third transistor which are disposed at positions on opposite sides of the first transistor and which control the spin state of electrons or holes by applying a control voltage or sweeping a control current; a first fin part and a second fin part disposed on the semiconductor layer side, below gate electrodes included in the first, second, and third transistors; and a diffusion layer contact which is electrically connected to the first fin part out of the first and second fin parts and which injects electrons or holes into the first fin part, wherein the first fin part is a pathway along which injected electrons or holes move.

Description

quantum semiconductor

[0001] The present disclosure relates to quantum semiconductors.

[0002] There is great interest in building quantum computers that can perform at high speeds and in a cost-effective manner. Quantum computers use superconducting logic-based devices, which are typically cooled to cryogenic temperatures in order to function in a superconducting state. U.S. Patent No. 6,233,999 discloses a system including at least two sets of superconducting logic devices, a cooling apparatus adapted to cool the logic devices to a first operating temperature, and an interconnect coupling the superconducting logic devices.

[0003] Special table 2021-523572 publication Special table 2019-537239 publication

[0004] Previously, quantum semiconductors have demonstrated quantum operation on the order of 1 to 100 qubits in an absolute zero atmosphere achieved using dilution refrigerators and other devices. However, systems with a medium number of qubits do not provide sufficient computational resources for analyzing complex phenomena. On the other hand, in order to secure sufficient computational resources by further increasing the number of qubits, it becomes important to highly integrate the semiconductor elements that make up the qubits. To achieve this, it is desirable to construct qubit elements using advanced micro-semiconductor processes. However, fabricating semiconductor elements using micro-processes is extremely difficult, and the layout dimensions of semiconductor elements that can be fabricated may be limited by the performance of the exposure equipment.

[0005] Patent Document 2 discloses a quantum bit device structure fabricated using advanced miniaturized semiconductor processes. This device structure comprises two active elements, a quantum bit storage section and a quantum bit readout section, constructed using a minimum number of semiconductor transistors. Specifically, two fin-type transistors, which are active elements, are fabricated, one for the quantum bit and the other for the quantum bit readout. In this configuration, there is no structure similar to a fin-type transistor on the opposite side of the opposing quantum bit section and quantum bit readout section. Therefore, when fabricating the transistor shape using an exposure tool, the structure of the fin section of the fin-type transistor collapses. As a result, the desired layout dimensions cannot be obtained, and quantum bits (charged particles such as electrons and holes) may not be stored in the positions where they should be, resulting in unstable quantum operations.

[0006] In view of the above background, the present invention aims to provide a quantum semiconductor device structure for a silicon semiconductor quantum bit using an advanced manufacturing process, in which a quantum bit storage structure is manufactured with high yield and characteristics variations are suppressed by using multiple adjacent fin transistors, and in a case where one quantum bit is stored in each of the multiple adjacent fin transistors, to prevent the occurrence of quantum interactions between the quantum bits and the occurrence of unintended entanglement, thereby realizing stable quantum operation.

[0007] The quantum semiconductor according to the present disclosure is configured as a quantum bit array including: a first transistor for storing electrons or holes in a semiconductor layer; second and third transistors arranged on either side of the first transistor and controlling the spin state of the electrons or the holes by applying a control voltage or sweeping a control current; first and second fin portions arranged on the side of the semiconductor layer below gate electrodes of the first, second, and third transistors; and a diffusion layer contact of the first and second fin portions, electrically connected to the first fin portion and for injecting the electrons or the holes into the first fin portion, wherein the first fin portion is a path for the injected electrons or holes to travel.

[0008] According to the present disclosure, a quantum computer with high quantum fidelity can be provided when a large-capacity quantum semiconductor is operated in quantum mode.

[0009] Fig. 1 is a wiring diagram of a quantum bit unit and a readout unit according to an embodiment. Fig. 2 is a structural bird's-eye view of a quantum bit unit according to an embodiment. Fig. 3 is a structural bird's-eye view of a readout unit according to an embodiment. Fig. 4 is an integrated bird's-eye view of a quantum bit unit and a readout unit according to an embodiment. Fig. 5 is a planar layout diagram of a quantum bit unit according to an embodiment. Fig. 6 is a layout cross-sectional view of a quantum bit unit according to an embodiment. Fig. 7 is a structural diagram of a transistor used in a quantum semiconductor according to an embodiment (fin transistor). Fig. 8 is a structural diagram of a transistor used in a quantum semiconductor according to an embodiment (planar transistor).

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the number of characteristics, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] When describing elements of the same type without distinguishing between them, the common portion (the portion excluding the branch number) of the reference sign including the branch number may be used, and when describing elements of the same type while distinguishing between them, the reference sign including the branch number may be used. For example, taking the quantum bit transistor wiring shown in Figure 1 as an example, when describing individual quantum bit transistor wirings without particular distinction, they may be written as "quantum bit transistor wiring XJ," and when describing individual quantum bit transistor wirings while distinguishing between them, they may be written as "quantum bit transistor wiring XJL0," "quantum bit transistor wiring XJL1," etc.

[0013] The circuit configuration of the quantum semiconductor and its element structure in this embodiment will be described with reference to FIGS. 1 to 7. FIG.

[0014] FIG. 1 is a wiring diagram of a quantum bit array and a readout array according to an embodiment. The quantum semiconductor 100 shown in FIG. 1 has two parts: a quantum bit array QBA (Qbit Array) and a readout array STA (Single Transistor Array). The main components of the quantum bit array QBA are a quantum bit transistor MQ1 for storing a quantum bit Qbit, and barrier transistors MQ0 and MQ2 for controlling the spin state of the stored quantum bit Qbit. The quantum bit array QBA comprises a transistor group using these transistors. Furthermore, the barrier transistors MQ0 and MQ2 that make up the barrier transistor group also constitute a barrier transistor group. Each of the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 that make up the transistor group of the quantum bit array QBA is physically composed of two transistors. These transistors are, for example, composed of MISFETs.

[0015] 1, the transistors constituting these transistor groups are connected to each other via diffusion layer regions n1, n2, n5, and n6, which are their respective drain and source portions. That is, one of the two transistors constituting quantum bit transistor MQ1 is connected to one of the two transistors constituting barrier transistor MQ0 via the diffusion layer region n1, and the one transistor constituting quantum bit transistor MQ1 is connected to one of the two transistors constituting barrier transistor MQ2 via the diffusion layer region n2. Furthermore, the other of the two transistors constituting quantum bit transistor MQ1 is connected to the other of the two transistors constituting barrier transistor MQ0 via the diffusion layer region n5, and the other transistor constituting quantum bit transistor MQ1 is connected to the other of the two transistors constituting barrier transistor MQ2 via the diffusion layer region n6.

[0016] A dummy transistor DM0 constituting the dummy transistor group is connected to the outer end side of the barrier transistor MQ0, and a dummy transistor DM1 constituting the dummy transistor group is connected to the outer end side of the barrier transistor MQ2. The outer end sides are both end sides in a direction perpendicular to the arrangement direction of the two transistors constituting the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 (the left-right direction on the drawing). In other words, the outer end sides can be said to be both end sides in the arrangement direction of the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2.

[0017] Each transistor constituting the dummy transistor DM0 is connected to the barrier transistor MQ0 via the diffusion layer regions n0 and n4. Each transistor constituting the dummy transistor DM1 is connected to the barrier transistor MQ2 via the diffusion layer regions n3 and n7. In the example of FIG. 1 , the outermost diffusion layer region of the dummy transistor DM0, which is the diffusion layer region not connected to the diffusion layer regions n0 and n4 of the barrier transistor MQ0, is electrically at the floating potential FLOAT, but it may also be at the ground potential. Similarly, the diffusion layer region of the dummy transistor DM1, which is the diffusion layer region not connected to the diffusion layer regions n3 and n7 of the barrier transistor MQ2, may also be at the ground potential rather than the floating potential FLOAT. As described above, each transistor group is physically composed of two transistors having two separate channel regions, but their gate electrodes are electrically at the same potential via the same wiring. The barrier transistor MQ0 is connected by gate wiring XJL0, and the barrier transistor MQ2 is connected by gate wiring XJR0. Furthermore, the quantum bit transistor MQ1 is connected by gate wiring XQ0. The dummy transistor DM0 is connected by gate wiring DGL0, and the dummy transistor DM1 is connected by gate wiring DGR0. The gate wiring is a wiring portion of the transistor common to the fin portions FIN0 and FIN1 (both described later) for connecting the gate electrodes.

[0018] In the quantum bit array QBA connected as described above, in this embodiment, the quantum bit Qbit is stored in only one of the transistors constituting the quantum bit transistor MQ1. Specifically, the diffusion layer contact CTL0 is connected to the node of the diffusion layer region n4, and the diffusion layer contact CTR0 is connected to the node of the diffusion layer region n7. Then, by adjusting the barrier transistors MQ0 and MQ2 to a desired potential, for example, one electron, which is a charged particle, is stored at the position shown in FIG. 1 via the nodes of the diffusion layer regions n4 and n5. Alternatively, the quantum bit may be transmitted and stored via the nodes of the diffusion layer regions n7 and n6. In this case, the diffusion layer regions n0, n1, n2, and n3 connecting the outer transistors constituting the quantum bit array QBA, including the transistors of the quantum bit transistor MQ1 that do not store electrons, are not used to transmit the quantum bit's charged particle electrons. Because they are not used to transmit electrons, they are unnecessary for storing quantum bits in the transistors themselves. However, the presence of the transistor group 101 arranged on the outside has the advantage that the transistor group 102, which is arranged on the inside of the transistor group 101 and includes the quantum bit transistor MQ1 in which the electrons are stored, and the diffusion layer regions n4, n5, n6, and n7 connecting the transistor group 102 can be manufactured stably without losing their shapes.

[0019] The outer side refers to the side of each of the two transistors constituting the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 opposite the readout array STA (the upper side in the drawing). In other words, the outer side refers to the side of each of the two transistors constituting the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 that is farther away from the readout array STA. The inner side refers to the side of each of the two transistors constituting the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 that is closer to the readout array STA (the lower side in the drawing). In other words, the inner side refers to the side of each of the two transistors constituting the quantum bit transistor MQ1 and the barrier transistors MQ0 and MQ2 that is closer to the readout array STA.

[0020] In the barrier transistor MQ0, gate contacts FCTL0 and FCTL1, made of metal for sweeping the gate potential and gate current, are connected to the gate wiring XJL0. As will be described later, the gate contacts FCTL0 and FCTL1 are preferably arranged to sandwich the position where the quantum bit Qbit is stored. In the example of FIG. 1 , the quantum bit Qbit is stored in the quantum bit transistor MQ1 so as to fit within the width between the gate contact FCTL0 connected to the transistor arranged above (i.e., the outer side) of the quantum bit Qbit, and the gate contact FCTL1 connected to the transistor arranged below (i.e., the inner side) of the quantum bit Qbit, of the two transistors constituting the barrier transistor MQ0. Gate contacts FCTL0 and FCTL1 are arranged on the outer and inner sides (above and below in FIG. 1 ). The gate contacts FCTR0 and FCTR1 of the barrier transistor MQ2 are preferably arranged and connected in a similar manner. 1, the quantum bit Qbit is stored in the quantum bit transistor MQ1 so as to fit within the width between the gate contact FCTR0 connected to the transistor arranged above the quantum bit Qbit (i.e., the above-mentioned outside) of the two transistors constituting the barrier transistor MQ2, and the gate contact FCTR1 connected to the transistor arranged below the quantum bit Qbit (i.e., the above-mentioned inside).The gate contacts FCTR0 and FCTR1 are arranged on the outside and inside thereof (above and below in FIG. 1).

[0021] For the gate wiring XQ0 of the quantum bit transistor MQ1, it is sufficient to perform the potential control necessary to store the quantum bit Qbit at a desired position, so a single gate contact FCTC0 to the gate wiring XQ0 is sufficient. Furthermore, the connection position should be positioned so that the separation distance from the adjacent gate contacts FCTL and FCTR on either side can be secured at a necessary and sufficient distance so that the shape will not be distorted during manufacturing and the gate contacts will not come into contact with each other.

[0022] Next, the readout array STA will be described. As shown in FIG. 1, the main components of the readout array STA include the same components as those of the quantum bit array QBA. The readout transistor MQ4, like the quantum bit transistor MQ1, is composed of two transistors having two independent channel regions. The readout current control transistors MQ3 and MQ5, and the dummy transistors DM2 and DM3, which are dummy transistors not connected to the diffusion layer regions of these readout current control transistors, are also composed of two transistors each. These transistors are composed of, for example, MISFETs, like the quantum bit array QBA. The gate wiring is a wiring portion of the transistor common to the fin portions FIN2 and FIN3 (both described below) for connecting the gate electrodes.

[0023] The source and drain nodes of each transistor are electrically connected to one another via diffusion layer regions n8, n9, n10, n11, n12, n13, n14, and n15, as shown in Fig. 1. In Fig. 1, each transistor constituting the dummy transistor DM2 is connected to the read current control transistor MQ3 via the diffusion layer regions n8 and n12. Each transistor constituting the dummy transistor DM3 is connected to the read current control transistor MQ5 via the diffusion layer regions n11 and n15.

[0024] One transistor constituting read transistor MQ4 and one transistor constituting read current control transistor MQ3 are connected via the diffusion layer region n9, and the one transistor constituting read transistor MQ4 and one transistor constituting read current control transistor MQ5 are connected via the diffusion layer region n10. The other transistor constituting read transistor MQ4 and the other transistor constituting read current control transistor MQ3 are connected via the diffusion layer region n13, and the other transistor constituting read transistor MQ4 and the other transistor constituting read current control transistor MQ5 are connected via the diffusion layer region n14.

[0025] The read current control transistors MQ3 and MQ5 of the read array STA, like those of the quantum bit array QBA, each serve as a barrier transistor constituting a barrier transistor group. Similarly to the quantum bit array QBA, the outer end of the read current control transistor MQ3 is connected to a dummy transistor DM2 constituting a dummy transistor group, and the outer end of the read current control transistor MQ5 is connected to a dummy transistor DM3 constituting the dummy transistor group. As in the quantum bit array QBA, the outer end refers to both ends of the read transistor MQ4 and the read current control transistors MQ3 and MQ5 in a direction perpendicular to the arrangement direction of the two transistors (left-right direction on the drawing). In other words, the outer end refers to both ends of the arrangement direction of the read transistor MQ4 and the read current control transistors MQ3 and MQ5.

[0026] The outermost diffusion layer regions of the dummy transistors DM2 and DM3 are at a floating potential FLOAT, similar to the dummy transistors of the quantum bit array QBA. The main function of the readout array STA is to determine and output a readout current via the readout transistor MQ4 according to the spin state of the quantum bit Qbit.

[0027] The read array STA of this embodiment outputs the read current to the outside via diffusion layer regions n8 to n11. On the other hand, diffusion layer regions n12 to n15 are not used as an output path for the read current. Therefore, a diffusion layer contact CTL1 for outputting the read current is connected to the diffusion layer region n8, and a diffusion layer contact CTR1 is connected to the diffusion layer region n11.

[0028] With this configuration, similar to the concept of the quantum bit array QBA, of the two transistors constituting the readout transistor MQ4 that are not used as an output path for the readout current, the transistor group 103 including the transistors arranged on the outer side (lower side in FIG. 1 ) that are not on the quantum bit array QBA side is unnecessary. However, the presence of the transistor group 103 arranged on the outer side has the advantage that the shape of the transistor group 104 including the transistors arranged on the quantum bit array QBA side of the two transistors constituting the readout transistor MQ4 that are arranged on the inner side of the transistor group 103, and the diffusion layer regions n8, n9, n10, and n11 that connect the transistor group 104, can be stably manufactured without being distorted.

[0029] The "outside" refers to the opposite side of the quantum bit array QBA (the lower side in the drawing) of the two transistors constituting the readout transistor MQ4 and the readout current control transistors MQ3 and MQ5. In other words, the "outside" refers to the side of the two transistors constituting the readout transistor MQ4 and the readout current control transistors MQ3 and MQ5 that is farther away from the quantum bit array QBA. The "inside" refers to the side of the two transistors constituting the readout transistor MQ4 and the readout current control transistors MQ3 and MQ5 that is closer to the quantum bit array QBA (the upper side in the drawing). In other words, the "inside" refers to the side of the two transistors constituting the readout transistor MQ4 and the readout current control transistors MQ3 and MQ5 that is closer to the quantum bit array QBA.

[0030] For the read current control transistor MQ3, a gate contact FCTL2 for applying a control potential is connected to the gate wiring XJL1, and for the read current control transistor MQ5, a gate contact FCTR2 for applying a control potential is connected to the gate wiring XJR1. A gate contact FCTC1 for applying a control potential is connected to the gate wiring XS0 of the read transistor MQ4. The configuration shown in FIG. 1 is the circuit wiring of the quantum semiconductor of this embodiment.

[0031] Next, a quantum manipulation method for a quantum semiconductor in this embodiment will be described. The quantum semiconductor in this embodiment preferably utilizes a magnetic resonance method. This quantum semiconductor is mounted in a 100 mK atmosphere within a so-called dilution refrigerator, and a predetermined static magnetic field is applied to the quantum bits by sweeping a magnetic field generating current through a superconducting magnet mounted in the dilution refrigerator housing. By applying a static magnetic field, the spin states of electrons and holes, which are charged particles in the quantum semiconductor, are aligned to the ground state, resulting in an initialized state. The initialized quantum bits precess at a constant resonance frequency. In a quantum semiconductor having multiple quantum bits, all of the quantum bits precess at approximately the same frequency. To selectively manipulate a quantum bit from a group of these quantum bits, it is advisable to pass currents in opposite directions through the barrier transistors MQ0 and MQ2.

[0032] For example, in the example of FIG. 1 , in the barrier transistor MQ0, current flows from the gate contact FCTL0 to FCTL1, and in the barrier transistor MQ2, current flows from the gate contact FCTR1 to FCTR0. In this way, by passing currents in opposite directions through the barrier transistors MQ0 and MQ2 that sandwich the quantum bit Qbit, a local magnetic field can be generated at the position of the quantum bit Qbit. The gate contacts FCTL0 and FCTL1 and FCTR0 and FCTR1 can be arranged above and below the quantum bit. This arrangement has the advantage that the direction of the generated local magnetic field can be controlled to a constant direction, making it easier to control the deviation in the resonant frequency. This local magnetic field causes the resonant frequency of the quantum bit Qbit to shift by a constant value. By irradiating the entire quantum bit array with microwaves of the same frequency as the resonant frequency shifted by a constant value for the quantum bit with the constant shift and the other quantum bits, it is possible to selectively rotate only the desired quantum bit.

[0033] The information of the selectively quantum-manipulated quantum bit Qbit is transferred to a downstream circuit by the readout array STA as an output current corresponding to the spin state. When the quantum bit Qbit in FIG. 1 is in an up-spin state, tunneling occurs by adjusting the gate potential of the barrier transistor to a desired potential. The quantum bit in the up-spin state then migrates to an adjacent diffusion layer region with a certain probability, then transitions to a down-spin state and is stored at the original quantum bit position. The readout transistor MQ4 is a readout element whose current gain changes depending on the spin state of the electron. It detects this spin state transition and detects the difference in information as a difference in channel current.

[0034] Because the spin state is detected using this mechanism, it is desirable to have a short separation between the quantum bit Qbit and the readout transistor that reads its spin state. Therefore, in this embodiment, as an example of the arrangement of the quantum bit transistor MQ1 and the readout transistor MQ4, they are arranged in close proximity as shown in the circuit diagram of FIG. 1. This close proximity refers to a position in FIG. 1 where the quantum bit transistor MQ1 and the readout transistor MQ4 are adjacent to each other in the vertical direction and face each other. As a repetitive explanation, the presence of transistor groups 101 and 103 on the outer periphery of the transistor group present in the path transmitting charged particles to the quantum bit transistor MQ1 and the transistor group present in the path through which the detection current for the quantum bit spin state flows allows for the formation of a repeatable layout pattern, preventing deformation of the transistor shape during exposure, etc. In other words, quantum semiconductors can be manufactured with a high yield.

[0035] FIG. 2 is an overhead view of the element structure of the quantum bit array QBA shown in FIG. In the quantum bit array QBA of this embodiment, an active element formation region PW is formed on a Si substrate Psub. Fin portions FIN0 and FIN1, which are paths for electrons or holes, which are charged particles, are formed within the active region PW. The respective FIN regions are electrically isolated using an insulating element isolation layer STI formed by a thermal oxidation process or the like. The pair of formed FIN structures are then subjected to the following processing during the subsequent manufacturing process. For example, the gate wiring XQ0, XJL0, XJR0, DGL0, and DGR0, and the various contacts CTL0, FCTL0, FCTL1, FCTC0, FCTR0, FCTR1, and CTR0 described in FIG. 1 are formed by depositing metal such as Cu and then patterning them. Through this processing, the fin portions are positioned at the desired positions. In this embodiment, the quantum bit Qbit is stored in the vicinity of a channel region formed by the fin portion FIN1 and the gate wiring XQ0.

[0036] The fin portion FIN0 serves as a dummy fin, and functions effectively because the two fin portions FIN0 and FIN1 can be manufactured with a high yield according to the layout design dimensions. Although not shown in the figure, it goes without saying that a dummy fin structure may also be formed in a location adjacent to the fin portion FIN0. The adjacent location is a region farther from the quantum bit Qbit than the transistor group 101, which includes the quantum bit transistor MQ1 that does not store electrons, and is arranged outside the transistor groups that make up the quantum bit array QBA, as described in FIG. 1 .

[0037] 2, the ends of the gate wiring XJL0 and the gate wiring XJR0 on the readout array STA side are preferably arranged to protrude by a length d (≧0) beyond the end of the gate wiring XQ0. This is because it makes it easier to control the direction of the local magnetic field generated in the quantum bit Qbit when sweeping the quantum operation current for the two gate contact pairs, the gate contacts FCTL0 and FCTL1 and the gate contacts FCTR0 and FCTR1. The native element formation region NONDP in the figure indicates a region where so-called impurity ion implantation is not performed. The reason for providing this region is to exclude as many electrons and holes as possible that could disturb the charged particles that function as quantum bit elements in the fin portions FIN1 and FIN0.

[0038] On the other hand, impurities such as phosphorus or boron may be ion-implanted into the region of the fin portion where the diffusion layer contacts CTL0 and CTR0 are connected. This can function as a reservoir for charged particles, and by controlling the gate potential of the barrier transistors MQ0 and MQ2, the charged particles in the reservoir are stored in a predetermined location of the quantum bit transistor MQ1 via the fin portion FIN1. As described in FIG. 1 , the diffusion layer contact only contacts one of the multiple fin portions. In FIG. 2 , the diffusion layer contacts CTL0 and CTR0 for injecting electrons or holes into the quantum bit transistor MQ1 are connected only to the fin portion FIN1 side, and the quantum bit Qbit is stored at the desired location. By using such circuit wiring and element structure, a quantum bit Qbit with the same quantum state is not stored on the fin portion FIN0 side. Therefore, it is possible to prevent the quantum bits Qbit and Qbit from interacting with each other and causing quantum coupling unintended by the design. In other words, even when a large number of quantum bits according to this embodiment are laid out and arranged to increase capacity, the information of each quantum bit can maintain high fidelity.

[0039] FIG. 3 is an overhead view of the element structure of the readout array STA shown in FIG. 1. Because the basic structure is the same as the quantum bit array QBA, the following mainly describes the differences from FIG. 2. The main difference between the element structure shown in FIG. 2 and FIG. 2 is that the gate wiring XJL1 and the gate wiring XJR1 each have one gate contact. In FIG. 2, a gate contact FCTL2 is provided as the gate contact for the gate wiring XJL1, and a gate contact FCTR2 is provided as the gate contact for the gate wiring XJR1. This is because the readout current control transistors MQ3 and MQ5 perform potential application control, so no current sweep is required. The readout transistor MQ4, like the quantum bit transistor MQ1 shown in FIG. 2, is physically composed of two transistors.

[0040] In this embodiment, diffusion layer contacts CTL1 and CTR1 are connected and arranged only on the fin portion FIN2 side and used as an output path for the read current. Therefore, the fin portion FIN3 side is not used as an output path for the read current. Of the two transistors constituting read transistors MQ3 and MQ5 that detect the read current, the read current is detected by the transistor arranged on the fin portion FIN2 side. Therefore, by using the element structure and circuit wiring as in this embodiment, the distance between the quantum bit Qbit stored in quantum bit transistor MQ1 and the transistor of read transistor MQ4 on the quantum bit transistor MQ1 side that detects the read current is minimized. As a result, the spin state of the quantum bit Qbit can be efficiently detected, and the read current can be amplified using the read transistor on the fin portion FIN2 side and transferred to a downstream integrated circuit.

[0041] As described in FIG. 2 , the readout array STA of this embodiment may include three or more fins, similar to the quantum bit array QBA. That is, a dummy fin structure may be formed adjacent to the fin portion FIN3. The adjacent portion refers to a region where the fin portion FIN2 is not formed, far from the quantum bit transistor MQ1 that detects the readout current. As described in FIG. 1 , this region is located outside the transistor group 103 that includes the readout transistors MQ3 and MQ5, to which the diffusion layer contacts CTL1 and CTR1 are not connected, and is arranged outside the transistor group that constitutes the readout array STA. In this case, the dummy transistor group having the dummy fin structure is laid out and arranged outside the fin portion FIN3. This arrangement allows for a repeated pattern to be formed, which has the advantage of enabling the present element structure to be manufactured with a high yield.

[0042] FIG. 4 is a diagram showing an example of a quantum semiconductor integrating a quantum bit array QBA and a readout array STA constituting the quantum semiconductor of this embodiment, and is a structural overhead view. Symbols in the diagram that are the same as those in FIGS. 1 to 3 have similar functions and will not be described here. In FIG. 4, the fin portion FIN1 storing the quantum bit Qbit faces the fin portion FIN2 used as the output path for the readout current, and the quantum bit transistor MQ1 and the readout transistor MQ4 are arranged in close proximity to each other. The fin portion FIN0 is arranged outside the fin portion FIN1, and the fin portion FIN3 is arranged outside the fin portion FIN2. The separation distance L in the diagram indicates the distance from the channel region where the quantum bit Qbit is stored or its vicinity to the channel region of the readout transistor MQ4. In this way, when the quantum bit transistor MQ1 and the read transistor MQ4 are arranged close to each other so that they face each other, as already explained, the amplification effect of the read transistor that detects changes in the spin state of the quantum bit Qbit is increased, and a large current difference between up spin and down spin can be ensured.

[0043] FIG. 5 is a planar layout of the quantum semiconductor shown in FIG. 4 viewed from above. The fin sections FIN0, FIN1, FIN2, and FIN3 in the figure show the top surfaces of the convex portions of the fins shown in FIG. 4 . The sidewalls are not visible from above and are therefore not shown in FIG. 5 . Furthermore, the squares marked with an "x" in the figure represent the top surfaces of the respective diffusion layer contacts. For example, these are the gate contacts FCTL0 and FCTL1 on the gate wiring XJL0. For other contacts, the same components as those in FIGS. 2, 3, and 4 described above are denoted by the same reference numerals. As shown in FIG. 5 , the multiple diffusion layer contacts are arranged at approximately equal distances 501 and 502 from each other. In FIG. 5 , the diffusion layer contacts of the quantum bit array QBA are arranged at approximately equal distances 501, and the diffusion layer contacts of the readout array STA are arranged at approximately equal distances 502. In this way, by laying out and arranging the diffusion layer contacts at equal intervals, optical disturbances are less likely to occur during exposure, and it becomes possible to manufacture the shape as designed.

[0044] Next, Fig. 6 shows a cross-sectional view of the fin portion FIN1 shown in Fig. 5 taken along the line A-A'. In this embodiment, it is preferable that the structure has the upper surfaces of the gate contacts FCTL1, FCTR1, and FCTC0 arranged on the gate and the upper surfaces of the diffusion layer contacts CTL0 and CTR0 at the same height. In Fig. 6, the upper surfaces of the gate contacts and diffusion layer contacts are all configured to have a height h from the upper surface of the fin portion FIN1.

[0045] The necessary voltages and currents are applied to these contacts from upper metal wiring. Therefore, when the metal wiring directly above the gate contact or diffusion layer contact is M1 wiring, the heights of the gate contact and the diffusion layer contact are aligned, which has the advantage of minimizing the metal wiring layers required for voltage and current supply. This configuration has the advantage of reducing the number of wiring layers, thereby reducing the number of mask layers and lowering the manufacturing costs of quantum semiconductors.

[0046] 7A and 7B show examples of active elements (transistors) used as quantum bit transistors, barrier transistors, or readout transistors used in the quantum semiconductor of this embodiment.

[0047] FIG. 7A is an overhead view of the fin transistor shown in FIGS. 2 to 6 . The advantage of a fin transistor is that it can minimize the chip size when quantum semiconductors and so-called CMOS LSI circuits that control the quantum semiconductors are monolithically integrated. This fin transistor has multiple channel surfaces (surfaces indicated by bold lines 701 in FIG. 7 ) through which current flows. Even with advanced miniaturization processes, the fin transistor has the advantage of being able to strongly control the gate applied potential, suppressing the short-channel effect and ensuring the on-current as designed. As shown in FIG. 7 , the bold lines 701 indicate the contact surfaces between the lower surface of the gate wiring GATE and the upper surface of the insulating film isolation layer STI formed by a thermal oxidation process or the like, and the contact surfaces between the side and upper surfaces of the fin portion FIN and the side and lower surfaces of the gate wiring GATE, which is shaped to fit these surfaces. In other words, the fin portions FIN such as fin portions FIN0, FIN1, FIN2, and FIN3 are arranged below the element isolation layer STI of the insulating film formed by a thermal oxidation process or the like, so that their heights are approximately half the heights of the gate wirings XJR0, XQ0, XJL0, DGR0, and DGL0 of the quantum bit array QBA and the gate wirings XJR1, XS0, XJL1, DGR1, and DGL1 of the readout array STA. This minimizes the constants of the LSI circuit, and as a result, minimizes the chip area. Minimizing the chip area means that a larger capacity quantum bit can be realized with the same chip size than a quantum bit chip using a general planar transistor.

[0048] On the other hand, FIG. 7B shows an overhead view of a planar transistor. This is a common transistor structure in semiconductor technology nodes of 20 nm or higher. In the example of FIG. 7B, planar diffusion layers PLD are arranged on the left and right of the gate. Two transistors are physically shown, and the gate wiring GATE is shared. Planar transistors have the advantage of being able to manufacture chips at low cost compared to fin transistors, since the structure of the transistor itself is simple and fewer masks are required for manufacturing. If the gate length and gate pitch required for quantum bit manipulation can be appropriately selected, quantum semiconductors can be manufactured at low cost with high yield.

[0049] The quantum semiconductor according to this embodiment has been described above with reference to the drawings. As described with reference to Figures 1, 2, 4, 7A, etc., the quantum semiconductor according to this embodiment comprises a first transistor (e.g., gate wiring XQ0 of quantum bit transistor MQ1) for storing electrons or holes in a semiconductor layer, a second transistor (e.g., gate wiring XJR0) and a third transistor (e.g., gate wiring XJL0) that are disposed on either side of the first transistor and control the spin state of the electrons or holes by applying a control voltage or sweeping a control current, and upper electrodes below the gate electrodes of the first transistor, the second transistor, and the third transistor. The quantum bit array (e.g., quantum bit array QBA) includes a first fin portion (e.g., fin portion FIN1) and a second fin portion (e.g., fin portion FIN2) disposed on the side of the semiconductor layer (e.g., an element isolation layer STI of an insulating film formed by a thermal oxidation process or the like shown in FIG. 7 ), and a diffusion layer contact (e.g., diffusion layer contacts CTL0, CTR0) electrically connected to the first fin portion of the first fin portion and for injecting the electrons or the holes into the first fin portion, the first fin portion being a path for movement of the injected electrons or the holes. With this configuration, even when quantum operations are performed at a large capacity, it is possible to manufacture the structure of the quantum bit storage unit with high yield while suppressing variations in transistor characteristics, and it becomes possible to provide a quantum semiconductor with high quantum fidelity.

[0050] 1 and 2, the diffusion layer contact is electrically connected only to the first fin portion. This configuration prevents quantum bits Qbit having the same quantum state from being stored on the fin portion FIN0 side. Therefore, it is possible to suppress the occurrence of quantum coupling unintended in the design due to interactions between quantum bits Qbit and quantum bits Qbit. Even when a large number of quantum bits according to this embodiment are arranged in a layout to increase capacity, the information of each quantum bit can maintain high fidelity.

[0051] 1, 3, 4, 7A, etc., the quantum bit further includes a readout array (e.g., readout array STA) that outputs a readout current according to the spin state of the quantum bit, and includes a fourth transistor (e.g., gate wiring XS0 of readout transistor MQ4) that is a readout element whose current amplification factor changes according to the spin state of the electron, and a fifth transistor (e.g., gate wiring XJR1 of readout current control transistor MQ5) and a sixth transistor (e.g., gate wiring XJL1 of readout current control transistor MQ3) that are readout current control elements that are arranged on either side of the fourth transistor and control the magnitude and direction of the current of the readout element, and a third fin portion (e.g., fin portion FIN2) that is arranged on the side of the semiconductor layer below the fourth transistor, the fifth transistor, and the sixth transistor and is a path for electrons of the readout element. With this configuration, the quantum bit Qbit stored in the quantum bit transistor MQ1 and the transistor of the read transistor MQ4 on the quantum bit transistor MQ1 side that detects the read current are positioned close to each other, making it possible to efficiently detect the spin state of the quantum bit Qbit.

[0052] 1, 3, 4, 7A, etc., the readout array includes a fourth fin portion (e.g., fin portion FIN3) disposed on the semiconductor layer below the fourth transistor, the fifth transistor, and the sixth transistor, in addition to the third fin portion. The fourth fin portion, which is one of the third and fourth fin portions, includes a plurality of diffusion layer contacts (e.g., diffusion layer contacts CTL1, CTR1) for sweeping the current of the readout element. The diffusion layer contacts are electrically connected only to the third fin portion that constitutes the path for sweeping the current of the readout element. With this configuration, the distance between the quantum bit Qbit stored in quantum bit transistor MQ1 and the transistor of the readout transistor MQ4 that detects the readout current on the quantum bit transistor MQ1 side is minimized, allowing the spin state of the quantum bit Qbit to be detected efficiently. As a result, the readout current can be amplified using the readout transistor on the fin portion FIN2 side and transferred to a downstream integrated circuit.

[0053] 1, 2, 4, 7A, etc., two or more contact layers for current sweeping are connected to the gate wiring constituting the second transistor and the third transistor. For example, gate contacts FCTR0 and FCTR1 are connected to the second transistor, and gate contacts FCTL0 and FCTL1 are connected to the third transistor. With this configuration, a necessary current can be supplied from the upper metal wiring, and a current in the opposite direction can be passed through the barrier transistors MQ0 and MQ2 that sandwich the quantum bit Qbit, thereby generating a local magnetic field at the position of the quantum bit Qbit.

[0054] 1-4, 7A, etc., one or more contact layers for applying voltage are connected to the gate wirings constituting the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor. For example, a gate contact FCTC0 is connected to the gate wiring XQ0, a gate contact FCTC1 is connected to the gate wiring XS0, a gate contact FCTR2 is connected to the gate wiring XJR1, and a gate contact FCTL2 is connected to the gate wiring XJL1. With this configuration, the strength of the current flowing through the barrier transistors MQ0 and MQ2 can be controlled via the current control transistors MQ3 and MQ5 by applying a required voltage from the upper metal wiring.

[0055] 1, 2, 4, 7A, etc., the diffusion layer contact of the quantum bit array, the diffusion layer contact of the readout array, the contact layer for current sweeping of the quantum bit array, and the contact layer for voltage application of the readout array are formed to have the same height at the surface that contacts the upper layer metal wiring (for example, formed to have the height h shown in FIG. 6). With this configuration, the heights of the gate contact and the diffusion layer contact are the same, so that the metal wiring layers required for potential supply and current supply can be minimized. As a result, the number of wiring layers can be reduced, which reduces the number of mask layers and reduces the manufacturing cost of quantum semiconductors.

[0056] 5 and other figures, the diffusion layer contacts of the quantum bit array are arranged at approximately equal intervals between the contact layers for current sweeping that the quantum bit array has. Also, as described with reference to Fig. 5 and other figures, the diffusion layer contacts of the readout array are arranged at approximately equal intervals between the contact layers for voltage application that the readout array has. With this configuration, optical disturbances that occur during exposure can be suppressed, and the shape as designed can be manufactured.

[0057] 5 and the like, each of the first to sixth transistors is configured with a transistor element having a fin structure. This configuration makes it possible to realize a larger capacity quantum bit in the same chip size than a quantum bit chip using general planar transistors.

[0058] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0059] The above-described embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to having all of the described configurations. Furthermore, some of the configurations of the embodiment may be added to, deleted from, or replaced with other configurations.

[0060] Furthermore, for example, in the above embodiment, a case where a silicon quantum semiconductor is used has been described as an example, but the present invention is not limited to this and can also be applied to superconducting quantum semiconductors, etc.

[0061] 100 Quantum semiconductor QBA Quantum bit array STA Readout array MQ1 Quantum bit transistor MQ0, MQ2 Barrier transistor MQ4 Readout transistor MQ3, MQ5 Readout current control transistor DM0, DM1, DM2, DM3 Dummy transistor 101-104 Transistor group n0-n15 Diffusion layer region FCTC0, FCTC1, FCTL0-FCTL2, FCTR0-FCTR2 Gate contact CTL0, CTL1, CTR0, CTR1 Diffusion layer contact XJR0, XQ0, XJL0, DGR0, DGL0 Gate wiring (QBA) XJR1, XS0, XJL1, DGR1, DGL1 Gate wiring (STA)

Claims

1. A quantum semiconductor comprising a quantum bit array having: a first transistor for storing electrons or holes in a semiconductor layer; second and third transistors arranged on either side of the first transistor and controlling the spin state of the electrons or holes by applying a control voltage or sweeping a control current; first and second fin sections arranged on the side of the semiconductor layer below the gate electrodes of the first, second, and third transistors; and a diffusion layer contact of the first and second fin sections, electrically connected to the first fin section, for injecting the electrons or holes into the first fin section, wherein the first fin section is a path for the injected electrons or holes.

2. The quantum semiconductor according to claim 1, wherein the diffusion layer contact is electrically connected only to the first fin portion.

3. A quantum semiconductor according to claim 1, further comprising a readout array that outputs a readout current according to the spin state of a quantum bit, the readout array comprising: a fourth transistor that is a readout element whose current amplification factor changes according to the spin state of the electron; a fifth transistor and a sixth transistor that are readout current control elements that are arranged on either side of the fourth transistor and that control the magnitude and direction of the current in the readout element; and a third fin portion that is arranged on the side of the semiconductor layer below the fourth transistor, the fifth transistor, and the sixth transistor and that serves as a path for electrons in the readout element.

4. A quantum semiconductor according to claim 3, wherein the readout array has a fourth fin portion that is separate from the third fin portion and is arranged on the side of the semiconductor layer below the fourth transistor, the fifth transistor, and the sixth transistor; the fourth fin portion, which is one of the third fin portion and the fourth fin portion, has a plurality of diffusion layer contacts for sweeping the current of the readout element; and the diffusion layer contacts are electrically connected only to the third fin portion that constitutes the path for sweeping the current of the readout element.

5. A quantum semiconductor according to claim 2, wherein two or more contact layers for current sweep are connected to the gate wiring constituting the second transistor and the third transistor, respectively.

6. A quantum semiconductor according to claim 4, wherein one or more contact layers for applying voltage are connected to gate wirings constituting the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

7. A quantum semiconductor according to claim 4, wherein the diffusion layer contact of the quantum bit array, the diffusion layer contact of the readout array, the contact layer for current sweeping of the quantum bit array, and the contact layer for voltage application of the readout array are formed to have the same height at the surface in contact with the upper metal wiring.

8. A quantum semiconductor according to claim 5, wherein the diffusion layer contacts of the quantum bit array are arranged at approximately equal intervals between contact layers for current sweeping of the quantum bit array.

9. A quantum semiconductor according to claim 6, wherein the diffusion layer contacts of the readout array are arranged at approximately equal intervals between contact layers for applying voltages that the readout array has.

10. A quantum semiconductor according to claim 1, wherein each of the first to sixth transistors is configured as a transistor element having a fin-type structure.

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