Imaging device

Abstract

The present invention enables pulse drive of a capacitor provided to a pixel while suppressing settling insufficiency during a pixel read.　An imaging apparatus includes: a first pixel circuit including a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; and a second pixel circuit including a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit. One of the first pixel circuit and the second pixel circuit includes a reset transistor for resetting the first floating diffusion and the second floating diffusion. The other of the first pixel circuit and the second pixel circuit includes a capacitance reset transistor for resetting the first capacitor and the second capacitor.

Description

Imaging device

[0001] The present technology relates to an imaging device, and more particularly, to an imaging device in which a capacitor is provided in each pixel.

[0002] In order to expand the dynamic range of imaging, a pixel may be provided with a capacitor that accumulates charge overflowing from a photodiode. In this case, the capacitor electrode may be pulse-driven to reduce the dark current of the capacitor. For example, a unit pixel provided with a capacitor to which a power supply voltage is supplied has been disclosed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-149093

[0004] However, in the above-mentioned conventional technology, when the capacitor is connected to a voltage control line in order to pulse-drive the capacitor, the load capacitance seen from the voltage control line increases, which may lead to insufficient settling when reading the pixel.

[0005] This technology was developed in light of these circumstances, and aims to enable pulse driving of capacitors provided in pixels while suppressing insufficient settling during pixel reads.

[0006] The present technology has been made to solve the above-described problems, and a first aspect thereof provides an imaging device including: a first pixel circuit having a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; and a second pixel circuit having a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit, wherein one of the first pixel circuit and the second pixel circuit includes a reset transistor that resets the first floating diffusion and the second floating diffusion, and the other of the first pixel circuit and the second pixel circuit includes a capacitance reset transistor that resets the first capacitor and the second capacitor. This brings about an effect that the reset transistor and the capacitance reset transistor are shared by the first pixel circuit and the second pixel circuit.

[0007] In the first aspect, the pixel circuit may further include a voltage control line that transmits a control voltage for pulse-driving the first capacitor and the second capacitor, and a power supply line that applies a power supply voltage to the capacitance reset transistor, thereby controlling the voltages applied to the first capacitor and the second capacitor in accordance with read timings of the first pixel circuit and the second pixel circuit, and eliminating insufficient settling during reset.

[0008] In the first aspect, the first photoelectric conversion unit and the second photoelectric conversion unit may each include a plurality of photoelectric conversion units having different sensitivities, thereby providing an effect of expanding the dynamic range of imaging while sharing a reset transistor and a capacitance reset transistor between the first pixel circuit and the second pixel circuit.

[0009] In addition, in the first aspect, the pixel array unit may include pixels arranged in a matrix in the row and column directions, and the pixels may include first pixels to which the first pixel circuit is assigned and second pixels to which the second pixel circuit is assigned. This brings about the effect that a captured image is generated while the reset transistor and the capacitance reset transistor are shared by the first pixel circuit and the second pixel circuit.

[0010] In the first aspect, the first pixel and the second pixel may be arranged adjacent to each other in the column direction, thereby alleviating layout constraints on the first pixel circuit and the second pixel circuit and allowing the reset transistor and the capacitance reset transistor to be shared by the first pixel circuit and the second pixel circuit.

[0011] In the first aspect, the first pixel and the second pixel may be arranged adjacent to each other in the row direction, thereby alleviating layout constraints on the first pixel circuit and the second pixel circuit and allowing the reset transistor and the capacitance reset transistor to be shared by the first pixel circuit and the second pixel circuit.

[0012] In the first aspect, the voltage control lines may be wired in the row direction, which alleviates layout constraints on the first pixel circuit and the second pixel circuit and allows the reset transistor and the capacitance reset transistor to be shared by the first pixel circuit and the second pixel circuit.

[0013] In the first aspect, the control voltage may be set to a high level during a read period of the pixel and to a low level during a storage period of the pixel, thereby reducing dark currents in the first capacitor and the second capacitor during the storage period without interfering with the read operation.

[0014] In the first aspect, the layout of the transistors of the first pixel circuit and the layout of the transistors of the second pixel circuit may be the same, thereby suppressing an increase in layout area and allowing the reset transistor and the capacitance reset transistor to be shared by the first pixel circuit and the second pixel circuit.

[0015] In the first aspect, the position of the reset transistor in one of the layouts of the first pixel circuit and the second pixel circuit may be equal to the position of the capacitance reset transistor in the other of the layouts of the first pixel circuit and the second pixel circuit, thereby providing an effect that the capacitance reset transistor can be added without changing the layouts of the first pixel circuit and the second pixel circuit.

[0016] In the first aspect, the upper electrodes of the first capacitor and the second capacitor may extend in the row direction and serve as the voltage control lines, thereby providing an effect of forming the voltage control lines while suppressing an increase in layout area.

[0017] The second aspect includes a first pixel circuit having a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; a second pixel circuit having a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit; and a third pixel circuit having a third photoelectric conversion unit, a third floating diffusion connected to the third photoelectric conversion unit, and a third capacitor connected to the third photoelectric conversion unit. and a fourth pixel circuit having a fourth photoelectric conversion unit, a fourth floating diffusion connected to the fourth photoelectric conversion unit, and a fourth capacitor connected to the fourth photoelectric conversion unit, wherein at most three of the first pixel circuit to the fourth pixel circuit include a reset transistor that resets the fourth floating diffusion from the first floating diffusion, and one of the first pixel circuit to the fourth pixel circuit includes a capacitance reset transistor that resets the fourth capacitor from the first capacitor. This brings about an effect that the reset transistor and the capacitance reset transistor are shared by the first pixel circuit to the fourth pixel circuit.

[0018] In a second aspect, at least two of the first pixel circuit to the fourth pixel circuit may include a switching transistor capable of switching the connection between the first floating diffusion and the fourth floating diffusion, and the switching transistor may be disposed in an empty space in the layout positions of the first pixel circuit to the fourth pixel circuit from which the reset transistor has been removed. This makes it possible to reset the first floating diffusion to the fourth floating diffusion and the first capacitor to the fourth capacitor while suppressing an increase in layout area, and provides the effect of enabling switching of conversion efficiency while shortening a readout time from a plurality of pixels.

[0019] In the second aspect, the pixel circuit may further include a voltage control line that transmits a control voltage for pulse-driving the first capacitor to the fourth capacitor, and a power supply line that applies a power supply voltage to the capacitance reset transistor, thereby controlling the voltage applied from the first capacitor to the fourth capacitor in accordance with read timings from the first pixel circuit to the fourth pixel circuit, and eliminating insufficient settling during reset.

[0020] In the second aspect, the first to fourth photoelectric conversion units may each include a plurality of photoelectric conversion units having different sensitivities, thereby enabling the first to fourth pixel circuits to share a reset transistor and a capacitance reset transistor, and expanding the dynamic range of imaging.

[0021] In a second aspect, the pixel array unit may include pixels arranged in a matrix in the row and column directions, the pixels including a first pixel to which the first pixel circuit is assigned, a second pixel to which the second pixel circuit is assigned, a third pixel to which the third pixel circuit is assigned, and a fourth pixel to which the fourth pixel circuit is assigned, thereby achieving the effect of generating a captured image while sharing the reset transistor and the capacitance reset transistor among the first to fourth pixel circuits.

[0022] In the second aspect, the first to fourth pixels may be arranged adjacent to each other in the column direction and the row direction, thereby alleviating layout constraints on the first to fourth pixel circuits and allowing the reset transistor and the capacitance reset transistor to be shared by the first to fourth pixel circuits.

[0023] In the second aspect, the voltage control line may be wired in the row direction, thereby alleviating layout constraints on the first to fourth pixel circuits and allowing the reset transistor and the capacitance reset transistor to be shared by the first to fourth pixel circuits.

[0024] In a second aspect, the first pixel and the second pixel may be arranged adjacent to each other in the column direction, the third pixel and the fourth pixel may be arranged adjacent to each other in the column direction, the first pixel and the third pixel may be arranged adjacent to each other in the row direction, the second pixel and the fourth pixel may be arranged adjacent to each other in the row direction, a layout of transistors of the first pixel and a layout of transistors of the second pixel may be arranged line-symmetrically with respect to the row direction, a layout of transistors of the third pixel and a layout of transistors of the fourth pixel may be arranged line-symmetrically with respect to the row direction, a layout of transistors of the first pixel and a layout of transistors of the third pixel may be arranged line-symmetrically with respect to the column direction, and a layout of transistors of the second pixel and a layout of transistors of the fourth pixel may be arranged line-symmetrically with respect to the column direction. This provides an effect that a reset transistor and a capacitance reset transistor are shared by the first pixel circuit to the fourth pixel circuit while suppressing an increase in layout area.

[0025] In the second aspect, the position of the reset transistor in the layout of one of the first to fourth pixel circuits may be equal to the position of the capacitance reset transistor in the layout of one of the first to fourth pixel circuits, thereby providing an effect of adding the capacitance reset transistor while suppressing changes to the layout of the first to fourth pixel circuits.

[0026] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment; FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment; FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment; FIG. 4 is a timing chart showing an example of a waveform of each unit in a readout operation of the solid-state imaging device according to the first embodiment; FIG. 5 is a timing chart showing another example of the waveform of each unit in a readout operation of the solid-state imaging device according to the first embodiment; FIG. 6 is a plan view showing an example of the layout of a pixel provided in the solid-state imaging device according to the first embodiment; FIG. 7 is a plan view showing an example of the layout of a pixel provided in the solid-state imaging device according to the first embodiment; FIG. 8 is a plan view showing an example of the layout of a pixel provided in the solid-state imaging device according to the first embodiment; FIG. 9 is a plan view showing an example of the layout of a pixel provided in the solid-state imaging device according to the first embodiment; FIG. 10 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to a second embodiment; FIG. 11 is a timing chart showing an example of the waveform of each unit in a readout operation of the solid-state imaging device according to the second embodiment; FIG. 12 is a timing chart showing another example of the waveform of each unit in a readout operation of the solid-state imaging device according to the second embodiment. 10 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to a second embodiment; FIG. 11 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the second embodiment; FIG. 12 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the second embodiment; FIG. 13 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the second embodiment; FIG. 14 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the second embodiment; FIG. 15 is a diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a third embodiment; FIG. 16 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the third embodiment; FIG. 17 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the third embodiment;FIG. 10 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to a third embodiment. FIG. 11 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the third embodiment. FIG. 12 is a diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a fourth embodiment. FIG. 13 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. FIG. 14 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. FIG. 15 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. FIG. 16 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. FIG. 17 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. FIG. 18 is a diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a fifth embodiment. FIG. 19 is a timing chart showing an example of waveforms of each unit in a readout operation of a solid-state imaging device according to the fifth embodiment. FIG. 19 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fifth embodiment. 10 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to a fifth embodiment; FIG. 11 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fifth embodiment; FIG. 12 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the fifth embodiment; FIG. 13 is a diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a sixth embodiment; FIG. 14 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the sixth embodiment; FIG. 15 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the sixth embodiment; FIG. 16 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the sixth embodiment; FIG. 17 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the sixth embodiment; FIG. 18 is a diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a seventh embodiment; FIG. 19 is a plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the seventh embodiment.10. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to a seventh embodiment. 11. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the seventh embodiment. 12. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the seventh embodiment. 13. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the seventh embodiment. 14. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to an eighth embodiment. 15. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. 16. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. 17. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. 18. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. 19. A plan view showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. 20. A diagram showing an example of a circuit configuration of pixels provided in a solid-state imaging device according to a ninth embodiment. 21. A timing chart showing an example of waveforms of each unit in a readout operation of a solid-state imaging device according to the ninth embodiment. 22. A perspective view showing an example of a stacking of pixel array units according to a tenth embodiment. 23. A block diagram showing a schematic configuration example of a vehicle control system. 24. An explanatory diagram showing an example of an installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a reset transistor and a capacitance reset transistor are shared between LOFIC (Lateral Overflow Integration Capacitor) pixels adjacent in the column direction) 2. Second embodiment (an example in which a reset transistor and a capacitance reset transistor are shared between pixels adjacent in the column direction, and each pixel is provided with a plurality of photoelectric conversion units having different sensitivities) 3. Third embodiment (an example in which a reset transistor and a capacitance reset transistor are shared between LOFIC pixels adjacent in the row direction) 4. Fourth embodiment (an example in which a reset transistor and a capacitance reset transistor are shared between pixels adjacent in the row direction, and each pixel is provided with a plurality of photoelectric conversion units having different sensitivities) 5. Fifth embodiment (an example in which a reset transistor, a capacitance reset transistor, and a switching transistor are shared between pixels adjacent in the column direction and the row direction) 6. Sixth embodiment (an example in which a reset transistor, a capacitance reset transistor, and two switching transistors are shared between pixels adjacent in the column direction and the row direction) 7. 7. Seventh embodiment (an example in which a reset transistor and a capacitance reset transistor are shared by pixels adjacent in the column direction and row direction) 8. Eighth embodiment (an example in which a reset transistor and a capacitance reset transistor are shared by pixels adjacent in the column direction and row direction, and horizontal drive lines are reduced) 9. Ninth embodiment (an example in which a reset transistor and a capacitance reset transistor are shared by pixels adjacent in the row direction and row direction, and a plurality of photoelectric conversion units with mutually different sensitivities are provided in each pixel) 10. Tenth embodiment (an example in which pixel array units are stacked) 11. Application example to a moving body

[0028] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC image sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0038] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0039] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0040] The pixel array unit 111 includes a plurality of pixels 120A and 120B. These pixels 120A and 120B are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). The pixels 120A and 120B are arranged adjacent to each other in the column direction. The pixels 120A and 120B may be arranged alternately in the column direction, with each pixel 120A and 120B being arranged in the same row. Each pixel 120A and 120B includes a capacitor that accumulates charge overflowing from the photodiode. This capacitor may be a horizontal overflow accumulation capacitor. Each pixel 120A and 120B may include a plurality of photodiodes with different sensitivities. Furthermore, each pixel 120A and 120B can form a source follower with the column readout circuit 113 during signal readout.

[0041] The capacitors of the pixels 120A and 120B can be pulse-driven for each column. For example, the drive potential of the capacitors of the pixels 120A and 120B can be set to a high level during the shutter period and the read period, and to a low level during the accumulation period. Note that the low level of the drive potential of the capacitors of the pixels 120A and 120B is a potential lower than the high level, and for example, the high level may be 3.3 V and the low level may be 2.4 V.

[0042] Each pixel 120A, 120B is connected to a horizontal drive line 131 for each row and to a vertical signal line 132A, 132B for each column. The horizontal drive line 131 drives each pixel 120A, 120B for each row when reading out a signal from each pixel 120. The horizontal drive line 131 may include a voltage control line that transmits a control voltage MVDD that pulse-drives the capacitors of each pixel 120A, 120B for each row. Each vertical signal line 132A, 132B transmits a potential based on a current that flows when reading out a signal from each pixel 120A, 120B to the column signal processing unit 114 for each column.

[0043] The pixels 120A and 120B may be arranged in a Bayer array or a quad-Bayer array. The light received by the pixels 120A and 120B may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0044] The vertical scanning circuit 112 scans the pixels 120A and 120B to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may also include a decoder that specifies the pixels 120A and 120B to be read.

[0045] When reading out signals from the pixels 120A and 120B, the column readout circuit 113 can form a source follower between the pixels 120A and 120B. At this time, the column readout circuit 113 can change the potentials of the vertical signal lines 132A and 132B based on the charges held in the pixels 120A and 120B.

[0046] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120A, 120B. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120A, 120B. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120A, 120B, and output an image pickup signal Gout.

[0047] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the result of comparing the pixel signals read from each pixel 120A, 120B with a reference signal.

[0048] The horizontal scanning circuit 115 scans the pixels 120A and 120B to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0049] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0050] FIG. 3 is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0051] In the figure, pixels 120A and 120B are arranged adjacent to each other in the column direction in a pixel array section 111.

[0052] The pixel 120A includes a photodiode PD1A, a transfer transistor 122A, a capacitance reset transistor 129, an amplifier transistor 124A, a selection transistor 125A, and floating diffusions FD1A to FD3A. The pixel 120A also includes a capacitor 126A, a pass transistor 127A, a switching transistor 128A, and an overflow control transistor 130A. The transfer transistor 122A, the capacitance reset transistor 129, the amplifier transistor 124A, the selection transistor 125A, the pass transistor 127A, the switching transistor 128A, and the overflow control transistor 130A may be MOS (Metal Oxide Semiconductor) transistors. The capacitor 126A may be a metal-insulation-metal (MIM) capacitor. The capacitor 126A may also be a three-dimensional MIM capacitor.

[0053] The photodiode PD1A performs photoelectric conversion and accumulates the photoelectrically converted charge. The capacitor 126A accumulates charge that overflows from the photodiode PD1A. The capacitor 126A may be light-shielded. One end of the capacitor 126A is connected to a control voltage MVDD, and the other end of the capacitor 126A is connected to the cathode of the photodiode PD1A via the overflow control transistor 130A. The capacitor 126A may be a high-dielectric capacitor.

[0054] The transfer transistor 122A transfers the charge accumulated in the photodiode PD1A to the floating diffusion FD1A. The capacitance reset transistor 129 resets the capacitors 126A and 126B of the pixels 120A and 120B. At this time, the capacitance reset transistor 129 is shared by the pixels 120A and 120B. The amplification transistor 124A outputs a signal corresponding to the potential of the floating diffusion FD1A. The selection transistor 125A selects the output of the amplification transistor 124A. The pass transistor 127A sets a path for transferring the charge accumulated in the capacitor 126A to the floating diffusion FD1A. The switching transistor 128A switches the conversion efficiency of the amplification transistor 124A. The overflow control transistor 130A controls the overflow of charge from the photodiode PD1A to the capacitor 126A.

[0055] The transfer transistor 122A is connected between the cathode of the photodiode PD1A and the floating diffusion FD1A. The amplification transistor 124A and the selection transistor 125A are connected in series. The drain of the amplification transistor 124A is connected to the power supply voltage VDD. The gate of the amplification transistor 124A is connected to the floating diffusion FD1A. The source of the selection transistor 125A is connected to the vertical signal line 132A.

[0056] The pass transistor 127A is connected between the connection point of the overflow control transistor 130A and the capacitor 126A and the switching transistor 128A. A floating diffusion FD3A is formed at the connection point of the overflow control transistor 130A and the capacitor 126A. A floating diffusion FD2A is formed at the connection point of the pass transistor 127A and the switching transistor 128A. The switching transistor 128A is connected between the floating diffusions FD1A and FD2A. The capacitance reset transistor 129 is connected between the capacitor 126A and the power supply voltage VDD. The capacitance reset transistor 129 is also connected to the capacitor 126B. The overflow control transistor 130A is connected between the photodiode PD1A and the capacitor 126A.

[0057] A transfer signal TGLA is applied to the gate of the transfer transistor 122A. A reset signal RST is applied to the gate of the reset transistor 123. A capacitance reset signal FCR is applied to the gate of the capacitance reset transistor 129. A selection signal SELA is applied to the gate of the selection transistor 125A. A pass setting signal FCGA is applied to the gate of the pass transistor 127A. A switching signal FDGA is applied to the gate of the switching transistor 128A. An overflow control voltage OFGA is applied to the gate of the overflow control transistor 130A. A control voltage MVDD is applied to the capacitor 126A. The transfer signal TGLA, reset signal RST, capacitance reset signal FCR, selection signal SELA, pass setting signal FCGA, switching signal FDGA, overflow control voltage OFGA, and control voltage MVDD can be transmitted to the pixel 120A via the horizontal drive line 131 of FIG. 2. The overflow control voltage OFGA may be a fixed voltage.

[0058] The pixel 120B includes a photodiode PD1B, a transfer transistor 122B, a reset transistor 123, an amplifier transistor 124B, a selection transistor 125B, and floating diffusions FD1B to FD3B. The pixel 120B further includes a capacitor 126B, a pass transistor 127B, a switching transistor 128B, and an overflow control transistor 130B. The transfer transistor 122B, the reset transistor 123, the amplifier transistor 124B, the selection transistor 125B, the pass transistor 127B, the switching transistor 128B, and the overflow control transistor 130B may be MOS transistors. The capacitor 126B may be a metal-insulator-metal (MIM) capacitor. The capacitor 126B may also be a three-dimensional metal-insulator-metal (MIM) capacitor.

[0059] The photodiode PD1B performs photoelectric conversion and accumulates the photoelectrically converted charge. The capacitor 126B accumulates charge that overflows from the photodiode PD1B. The capacitor 126B may be light-shielded. One end of the capacitor 126B is connected to a control voltage MVDD, and the other end of the capacitor 126B is connected to the cathode of the photodiode PD1B via the overflow control transistor 130B. The capacitor 126B may be a high-dielectric capacitor.

[0060] The transfer transistor 122B transfers the charge accumulated in the photodiode PD1B to the floating diffusion FD1B. The reset transistor 123 resets the photodiodes PD1A and PD1B of each pixel 120A and 120B. At this time, the reset transistor 123 is shared by the pixels 120A and 120B. The amplifier transistor 124B outputs a signal corresponding to the potential of the floating diffusion FD1B. The selection transistor 125B selects the output of the amplifier transistor 124B. The pass transistor 127B sets a path for the charge accumulated in the capacitor 126B to be transferred to the floating diffusion FD1B. The switching transistor 128B switches the conversion efficiency of the amplifier transistor 124B. The overflow control transistor 130B controls the overflow of charge from the photodiode PD1B to the capacitor 126B.

[0061] The transfer transistor 122B is connected between the cathode of the photodiode PD1B and the floating diffusion FD1B. The amplification transistor 124B and the selection transistor 125B are connected in series. The drain of the amplification transistor 124B is connected to the power supply voltage VDD. The gate of the amplification transistor 124B is connected to the floating diffusion FD1B. The source of the selection transistor 125B is connected to the vertical signal line 132B.

[0062] The pass transistor 127B is connected between the connection point of the overflow control transistor 130B and capacitor 126B and the connection point of the reset transistor 123 and switching transistor 128B. A floating diffusion FD3B is formed at the connection point of the overflow control transistor 130B and capacitor 126B. A floating diffusion FD2B is formed at the connection point of the pass transistor 127B and switching transistor 128B. The switching transistor 128B is connected between the connection point of the reset transistor 123 and pass transistor 127B and the floating diffusion FD1A. The reset transistor 123 is connected between the floating diffusion FD2B and power supply voltage VDD. The reset transistor 123 is also connected to the floating diffusion FD2B. The overflow control transistor 130B is connected between the photodiode PD1B and capacitor 126B.

[0063] A transfer signal TGLB is applied to the gate of the transfer transistor 122B. A reset signal RST is applied to the gate of the reset transistor 123. A select signal SELB is applied to the gate of the select transistor 125B. A pass setting signal FCGB is applied to the gate of the pass transistor 127B. A switching signal FDGB is applied to the gate of the switching transistor 128B. An overflow control voltage OFGB is applied to the gate of the overflow control transistor 130B. A control voltage MVDD is applied to the capacitors 126A and 126B. The transfer signal TGLB, reset signal RSTB, select signal SELB, pass setting signal FCGB, switching signal FDGB, and overflow control voltage OFGB can be transmitted to the pixel 120B via the horizontal drive line 131 of FIG. 2. The overflow control voltage OFGB may be a fixed voltage.

[0064] FIG. 4 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the first embodiment.

[0065] As shown in the figure, the overflow control voltages OFGA and OFGB are set to fixed voltages throughout the entire period of each frame.

[0066] Furthermore, in each frame, a shutter period and an accumulation period are provided before the readout operation. A control voltage MVDD is applied to the upper electrodes of the capacitors 126A and 126B, and during the accumulation period, the upper electrodes of the capacitors 126A and 126B are set to a low level. By setting the control voltage MVDD to a low level during the accumulation period, the dark current of the capacitors 126A and 126B can be reduced. During the shutter period, the control voltage MVDD may be set to a low level or a high level.

[0067] During the read period, in the low-efficiency P-phase single read period K11, the reset signal RST, the selection signals SELA and SELB, and the control voltage MVDD rise, followed by the switching signals FDGA and FDGB. At this time, the control voltage MVDD is set to a high level, and the upper electrodes of the capacitors 126A and 126B are set to a high level. The high level of the control voltage MVDD can be matched to the power supply voltage VDD. The reset transistor 123 and the switching transistors 128A and 128B are turned on, discharging the charges from the floating diffusions FD1A and FD1B and reducing the conversion efficiency of the amplifier transistors 124A and 124B. After the charges from the floating diffusions FD1A and FD1B are discharged, the reset signal RST falls, and the reset transistor 123 is turned off.

[0068] Furthermore, when the selection transistors 125A and 125B are turned on and the reset transistor 123 is turned off, the potentials of the vertical signal lines 132A and 132B are set based on the source follower operation when the low-efficiency P-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B, respectively. Then, the low-efficiency P-phase levels of the pixels 120A and 120B are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0069] Next, during the high-efficiency P-phase single readout period K12, the switching signals FDGA and FDGB fall. At this time, the switching transistors 128A and 128B are turned off, increasing the conversion efficiency of the amplifier transistors 124A and 124B. The potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-efficiency P-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplifier transistors 124A and 124B. The high-efficiency P-phase levels of the pixels 120A and 120B are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0070] Next, during a high-efficiency D-phase individual readout period K13, the transfer signals TGLA and TGLB rise. At this time, the transfer transistors 122A and 122B turn on, and the charges accumulated in the photodiodes PD1A and PD1B are transferred to the floating diffusions FD1A and FD1B. Then, the transfer signals TGLA and TGLB fall. At this time, the transfer transistors 122A and 122B turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-efficiency D-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. Then, the high-efficiency D-phase levels of the pixels 120A and 120B are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0071] Next, during the low-efficiency D-phase single read period K14, the switching signals FDGA and FDGB rise, turning on the switching transistors 128A and 128B. At this time, the conversion efficiency of the amplification transistors 124A and 124B is reduced. The transfer signals TGLA and TGLB also rise. At this time, the transfer transistors 122A and 122B turn on, and the charges accumulated in the photodiodes PD1A and PD1B are transferred to the floating diffusions FD1A and FD1B. The transfer signals TGLA and TGLB then fall. At this time, the transfer transistors 122A and 122B turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the low-efficiency D-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. Then, based on the potentials of the vertical signal lines 132A and 132B at that time, the low-efficiency D-phase levels of the pixels 120A and 120B are AD converted.

[0072] CDS reading can be performed in the low-efficiency P-phase single read period K11, the high-efficiency P-phase single read period K12, the high-efficiency D-phase single read period K13, and the low-efficiency D-phase single read period K14.

[0073] Next, during a D-phase batch readout period K15, the path setting signals FCGA and FCGB rise. At this time, the path transistors 127A and 127B are turned on, and the potentials of the vertical signal lines 132A and 132B are set based on the source follower operation when the D-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. Then, the D-phase levels of the pixels 120A and 120B are AD converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0074] Next, during the P-phase batch readout period K16, the selection signals SELA and SELB fall, while the capacitance reset signal FCR and the reset signal RST rise. At this time, the selection transistors 125A and 125B turn off, the reset transistor 123 turns on, and the charge in the floating diffusions FD1A and FD1B is discharged. The capacitance reset transistor 129 also turns on, supplying the power supply voltage VDD to the upper electrodes of the capacitors 126A and 126B. This allows power to be supplied from the power supply voltage VDD to the upper electrodes of the capacitors 126A and 126B, shortening the power supply path to the upper electrodes of the capacitors 126A and 126B. This eliminates insufficient settling during resetting and reduces degradation of image quality, such as horizontal streaks.

[0075] Then, the path setting signals FCGA and FCGB fall, turning off the path transistors 127A and 127B, and then the selection signals SELA and SELB rise, turning on the selection transistors 125A and 125B. Then, the capacitance reset signal FCR and the reset signal RST fall, turning off the capacitance reset transistor 129 and the reset transistor 123, and then the path setting signals FCGA and FCGB rise, turning on the path transistors 127A and 127B. At this time, the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the P-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. Then, the P-phase levels of the pixels 120A and 120B are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0076] During the D-phase batch read period K15 and the P-phase batch read period K16, DDS (Double Data Sampling) readout can be performed.

[0077] Next, during a DOL (Digital Overlap) period K17, the path setting signals FCGA and FCGB fall, turning off the path transistors 127A and 127B, and then the selection signals SELA and SELB fall, turning off the selection transistors 125A and 125B. At this time, during the DOL period K17, the accumulation time for each frame is minimized, and the brightest scene is captured in a time-division manner. Note that the DOL period K17 may be omitted.

[0078] FIG. 5 is a timing chart showing another example of waveforms at various parts during the readout operation of the solid-state imaging device according to the first embodiment.

[0079] In the same figure, in the read operation of Figure 4, the capacitance reset signal FCR rises together with the rising edge of the reset signal RST. In this read operation, the capacitance reset signal FCR rises together with the rising edge of the control voltage MVDD. Other timings of this read operation are the same as those of the read operation of Figure 4 described above.

[0080] In the read operation of Figure 5, an example is shown in which the capacitance reset signal FCR rises together with the rise of the control voltage MVDD, but the capacitance reset signal FCR may rise at any timing between the rise timing of the control voltage MVDD and the rise timing of the reset signal RST.

[0081] 6 to 10 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the first embodiment. This layout shows a five-layer wiring structure. Also, FIG. 6 shows an example of a layout of a semiconductor substrate and a first wiring layer, FIG. 7 shows an example of a layout of a second wiring layer, FIG. 8 shows an example of a layout of a third wiring layer, FIG. 9 shows an example of a layout of a fourth wiring layer, and FIG. 10 shows an example of a layout of a fifth wiring layer. Also, FIGS. 6 to 10 show an example of a layout of a back-illuminated image sensor.

[0082] 6 , the semiconductor substrate SUB is separated into pixels 120A and 120B by pixel isolation regions ISG. The pixel isolation regions ISG may be, for example, full-thickness front deep trench isolation (FFTI). Photodiodes PD1A and PD1B are formed on the back surface side of the semiconductor substrate SUB for the pixels 120A and 120B. Active regions AK are provided on the front surface side of the semiconductor substrate SUB, and the active regions AK are isolated by element isolation regions ISA. The element isolation regions ISA may be shallow trench isolation (STI). A channel region and an impurity diffusion layer are formed in the active region AK. A floating diffusion, a source layer, and a drain layer are formed in the impurity diffusion layer.

[0083] In the pixel 120A, gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, and G9 are formed on the channel region of the active region AK via a gate insulating film. The gate electrode GA0 can be used for the overflow control transistor 130A. The gate electrode GA2 can be used for the transfer transistor 122A. The gate electrode GA4 can be used for the amplification transistor 124A. The gate electrode GA5 can be used for the selection transistor 125A. The gate electrode GA7 can be used for the pass transistor 127A. The gate electrode GA8 can be used for the switching transistor 128A. The gate electrode G9 can be used for the capacitance reset transistor 129.

[0084] In pixel 120B, gate electrodes GB0, GB2, GB4, GB5, GB7, GB8, and G3 are formed on the channel region of the active region AK via a gate insulating film. Gate electrode GB0 can be used for the overflow control transistor 130B. Gate electrode GB2 can be used for the transfer transistor 122B. Gate electrode GB4 can be used for the amplification transistor 124B. Gate electrode GB5 can be used for the selection transistor 125B. Gate electrode GB7 can be used for the pass transistor 127B. Gate electrode GB8 can be used for the switching transistor 128B. Gate electrode G3 can be used for the reset transistor 123B.

[0085] Here, the layout of each transistor in each pixel 120A can be made the same as that of each transistor in each pixel 120B. In this case, the position of the capacitance reset transistor 129 in the pixel 120A and the position of the reset transistor 123 in the pixel 120B can be made the same as that of each transistor in each pixel 120B.

[0086] The material of the semiconductor substrate SUB may be Si, InGaAs, InP, InSb, HgCdTe, etc. The material of the gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 may be, for example, polycrystalline silicon.

[0087] A first wiring layer is formed on the semiconductor substrate SUB. Wiring H1 is formed in the first wiring layer. The wiring H1 is used to connect gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK. The wiring H1 is connected to gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK via contact CN1. For example, the wiring H1 includes wirings H1C, H1F, H1R, H1M, H1N, H1X, and H1Y. The wiring H1C is used to connect the source layer of the capacitance reset transistor 129 and the upper electrodes of the capacitors 126A and 126B. The wiring H1F is used to connect the drain layer of the capacitance reset transistor 129 to the power supply voltage VDD. The wiring H1R is used to connect the drain layer of the reset transistor 123 to the power supply voltage VDD. The wirings H1M and H1N are used to connect the floating diffusions FD2A and FD2B. The wirings H1X and H1Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B.

[0088] 7, a second wiring layer is formed on the first wiring layer. Wiring H2 is formed in the second wiring layer. Wiring H2 is connected between layers via contacts CN2. For example, wiring H2 includes wirings H2C, H2M, H2V1, H2V2, H2G, H2X, and H2Y. Wiring H2C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. Wiring H2M is used to connect the floating diffusions FD2A and FD2B. Wirings H2V1 and H2V2 are used for vertical signal lines 132A and 132B. Wiring H2G is used as ground wiring. Wirings H2X and H2Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B.

[0089] In FIG. 8 , a third wiring layer is formed on the second wiring layer. Wiring H3 is formed in the third wiring layer. Wiring H3 is connected between layers via contact CN3. For example, wiring H3 includes wirings H3C, H3X, H3Y, H3D, H3K, H3J, H3GA, H3GB, H3DA, H3DB, H3TA, H3TB, H3SA, and H3SB. Wiring H3C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each capacitor 126A and 126B. Wiring H3X and H3Y are used to connect each floating diffusion FD3A and FD3B to the lower electrodes of each capacitor 126A and 126B. Wiring H3D is used to supply power supply voltage VDD. Wiring H3K is used to drive the gate electrode G3 of the reset transistor 123. The wiring H3J is used to drive the gate electrode G9 of the capacitance reset transistor 129. The wiring H3GA is used to drive the gate electrode GA7 of the pass transistor 127A. The wiring H3GB is used to drive the gate electrode GB7 of the pass transistor 127B. The wiring H3DA is used to drive the gate electrode GA8 of the switching transistor 128A. The wiring H3DB is used to drive the gate electrode GB8 of the switching transistor 128B. The wiring H3TA is used to drive the gate electrode GA2 of the transfer transistor 122A. The wiring H3TB is used to drive the gate electrode GB2 of the transfer transistor 122B. The wiring H3SA is used to drive the gate electrode GA5 of the selection transistor 125A. The wiring H3SB is used to drive the gate electrode GB5 of the selection transistor 125B.

[0090] 9, a fourth wiring layer is formed on the third wiring layer. Wiring H4 and the lower electrodes CLA and CLB of each capacitor 126A, 126B are formed in the fourth wiring layer. The wiring H4 and the lower electrodes CLA and CLB of each capacitor 126A, 126B are connected to each other via contacts CN4. For example, the wiring H4 includes wiring H4C and a power supply line H4D. The wiring H4C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each capacitor 126A, 126B. The power supply line H4D is used to supply the power supply voltage VDD. The power supply line H4D can be wired, for example, vertically and horizontally along the pixel isolation region ISG.

[0091] 10, a fifth wiring layer is formed on the fourth wiring layer. Wiring H5 and the upper electrodes CUA and CUB of the capacitors 126A and 126B are formed in the fifth wiring layer. The upper electrodes CUA and CUB of the capacitors 126A and 126B are connected to each other via wiring H5. The upper electrodes CUA and CUB can extend in the row direction. In this case, the upper electrodes CUA and CUB can also serve as voltage control lines that supply the control voltage MVDD.

[0092] The wirings H1 to H5 may be made of a metal such as Al, Cu, AlCu, AlSiCu, or Co. The insulating material for insulating the wirings H1 to H5 may be made of, for example, SiO. ２ can be used.

[0093] As described above, in the first embodiment, the pixels 120A and 120B adjacent to each other in the column direction are provided with the capacitors 126A and 126B, respectively, and the reset transistor 123 and the capacitance reset transistor 129 are shared by the pixels 120A and 120B. This allows switching between the control voltage MVDD and the power supply voltage VDD applied to the capacitors 126A and 126B while easing layout restrictions on the pixels 120A and 120B. This makes it possible to eliminate insufficient settling during resetting while suppressing an increase in layout area, and to reduce degradation of image quality such as horizontal stripes.

[0094] 2. Second Embodiment In the first embodiment described above, the pixels 120A and 120B adjacent to each other in the column direction are provided with the capacitors 126A and 126B, respectively, and share the reset transistor 123 and the capacitance reset transistor 129. In this second embodiment, the pixels adjacent to each other in the column direction share the reset transistor 123 and the capacitance reset transistor 129, and a plurality of photodiodes are provided in the pixels.

[0095] FIG. 11 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the second embodiment.

[0096] In the figure, this imaging device includes pixels 220A and 220B instead of the pixels 120A and 120B of the first embodiment described above. The pixels 220A and 220B are arranged adjacent to each other in the column direction.

[0097] Each pixel 220A, 220B is obtained by adding a photodiode PD2A, PD2B to the pixels 120A, 120B of the first embodiment described above. Furthermore, each pixel 220A, 220B is obtained by removing the overflow control transistors 130A, 130B from the pixels 120A, 120B of the first embodiment described above. The remaining configuration of each pixel 220A, 220B of the second embodiment is the same as the configuration of each pixel 120A, 120B of the first embodiment described above.

[0098] In pixel 220A, the cathode of photodiode PD2A is connected to floating diffusion FD3A, and in pixel 220B, the cathode of photodiode PD2B is connected to floating diffusion FD3B.

[0099] FIG. 12 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the second embodiment.

[0100] In the figure, the read operation of the second embodiment includes a second D-phase individual read period K25 and a second P-phase individual read period K26 instead of the D-phase batch read period K15 and the P-phase batch read period K16 of Fig. 4. Other processing in the read operation of the second embodiment is similar to the processing in the read operation of Fig. 4.

[0101] At this time, in the low-efficiency D-phase individual read period K14, the transfer signals TGLA and TGLB fall, and then the reset signal RST rises. At this time, the reset transistor 123 turns on, and the charges in the floating diffusions FD1A and FD1B are discharged.

[0102] Next, during the second D-phase individual readout period K25, after the charges in the floating diffusions FD1A and FD1B are discharged, the reset signal RST falls, turning off the reset transistor 123. Then, when the path setting signals FCGA and FCGB rise and the path transistors 127A and 127B turn on, the charges accumulated in the photodiodes PD2A and PD2B are transferred to the floating diffusions FD1A and FD1B. The potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the second D-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. The second D-phase levels of the pixels 120A and 120B are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0103] Next, in the second P-phase read period K26, the selection signals SELA and SELB fall, and the capacitance reset signal FCR and reset signal RST rise. At this time, the selection transistors 125A and 125B turn off, the reset transistor 123 turns on, and the charges in the floating diffusions FD1A and FD1B are discharged. In addition, the capacitance reset transistor 129 turns on, and the power supply voltage VDD is supplied to the upper electrodes of the capacitors 126A and 126B.

[0104] Then, the path setting signals FCGA and FCGB fall, turning off the path transistors 127A and 127B, and then the selection signals SELA and SELB rise, turning on the selection transistors 125A and 125B. Then, the capacitance reset signal FCR and the reset signal RST fall, turning off the capacitance reset transistor 129 and the reset transistor 123, and then the path setting signals FCGA and FCGB rise, turning on the path transistors 127A and 127B. At this time, the potentials of the vertical signal lines 132A and 132B are set based on the source follower operation when the second P-phase levels of the floating diffusions FD1A and FD1B are applied to the gates of the amplification transistors 124A and 124B. Then, the second P-phase levels of the pixels 120A and 120B are AD converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0105] FIG. 13 is a timing chart showing another example of waveforms at various parts in the readout operation of the solid-state imaging device according to the second embodiment.

[0106] 12, the capacitance reset signal FCR rises with the rise of the reset signal RST, but in this read operation, the capacitance reset signal FCR rises with the rise of the control voltage MVDD. Other timings of this read operation are the same as those of the read operation in FIG. 12 described above.

[0107] 13 shows an example in which the capacitance reset signal FCR rises together with the rise of the control voltage MVDD. The capacitance reset signal FCR may rise at any timing between the rise timing of the control voltage MVDD and the rise timing of the reset signal RST.

[0108] 14 to 18 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the second embodiment. This layout shows a five-layer wiring structure. Also, Fig. 14 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 15 shows an example of a layout of a second wiring layer, Fig. 16 shows an example of a layout of a third wiring layer, Fig. 17 shows an example of a layout of a fourth wiring layer, and Fig. 18 shows an example of a layout of a fifth wiring layer.

[0109] In FIG. 14 , the semiconductor substrate SUB is separated into pixels 220A and 220B by a pixel isolation region ISG2. On the back surface side of the semiconductor substrate SUB, photodiodes PD1A and PD2A are formed in pixel 220A, and photodiodes PD1B and PD2B are formed in pixel 220B. Here, the photodiodes PD1A, PD2A, PD1B, and PD2B can be separated by the pixel isolation region ISG2. In this case, the planar size of each photodiode PD2A or PD2B surrounded by the pixel isolation region ISG2 can be made smaller than the planar size of each photodiode PD1A or PD1B surrounded by the pixel isolation region ISG2. This allows the sensitivity of each photodiode PD2A or PD2B to be smaller than the sensitivity of each photodiode PD1A or PD1B. An active region AK2 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK2 is isolated by an element isolation region ISA2.

[0110] In pixel 220A, gate electrodes GA2, GA4, GA5, GA7, GA8, and G9 are formed on the channel region of active region AK2 with a gate insulating film interposed therebetween. Also, in pixel 220B, gate electrodes GB2, GB4, GB5, GB7, GB8, and G3 are formed on the channel region of active region AK2 with a gate insulating film interposed therebetween.

[0111] Here, the layout of each transistor in each pixel 220A can be made the same as that of each transistor in each pixel 220B. In this case, the position of the capacitance reset transistor 129 in the pixel 220A and the position of the reset transistor 123 in the pixel 220B can be made the same as that of each transistor in each pixel 220B.

[0112] A first wiring layer is formed on the semiconductor substrate SUB. Wiring H21 is formed in the first wiring layer. The wiring H21 is used to connect to gate electrodes GA2, GA4, GA5, GA7, GA8, G9, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK2. The wiring H21 is connected to gate electrodes GA2, GA4, GA5, GA7, GA8, G9, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK2 via contacts CN21. For example, the wiring H21 includes wirings H21C, H21F, H21R, H21M, H21N, H21X, and H21Y. The wiring H21C is used to connect the source layer of the capacitance reset transistor 129 and the upper electrodes of the capacitors 126A and 126B. The wiring H21F is used to connect the drain layer of the capacitance reset transistor 129 to the power supply voltage VDD. The wiring H21R is used to connect the drain layer of the reset transistor 123 to the power supply voltage VDD. The wiring H21M and H21N are used to connect the floating diffusions FD2A and FD2B. The wiring H21X and H21Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B.

[0113] 15 , a second wiring layer is formed on the first wiring layer. A wiring H22 is formed in the second wiring layer. The wiring H22 is connected between layers via a contact CN22. For example, the wiring H22 includes wirings H22C, H22M, H22V1, H22V2, H22G, H22X, and H22Y. The wiring H22C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. The wiring H22M is used to connect the floating diffusions FD2A and FD2B. The wirings H22V1 and H22V2 are used for the vertical signal lines 132A and 132B. The wiring H22G is used as a ground wiring. The wirings H22X and H22Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B, respectively.

[0114] 16 , a third wiring layer is formed on the second wiring layer. Wiring H23 is formed in the third wiring layer. Wiring H23 is connected between layers via contact CN23. For example, wiring H23 includes wirings H23C, H23X, H23Y, H23D, H23K, H23J, H23GA, H23GB, H23DA, H23DB, H23TA, H23TB, H23SA, and H23SB. Wiring H23C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. Wiring H23X and H23Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B. Wiring H23D is used to supply the power supply voltage VDD. The wiring H23K is used to drive the gate electrode G3 of the reset transistor 123. The wiring H23J is used to drive the gate electrode G9 of the capacitance reset transistor 129. The wiring H23GA is used to drive the gate electrode GA7 of the pass transistor 127A. The wiring H23GB is used to drive the gate electrode GB7 of the pass transistor 127B. The wiring H23DA is used to drive the gate electrode GA8 of the switching transistor 128A. The wiring H23DB is used to drive the gate electrode GB8 of the switching transistor 128B. The wiring H23TA is used to drive the gate electrode GA2 of the transfer transistor 122A. The wiring H23TB is used to drive the gate electrode GB2 of the transfer transistor 122B. The wiring H23SA is used to drive the gate electrode GA5 of the selection transistor 125A. The wiring H23SB is used to drive the gate electrode GB5 of the selection transistor 125B.

[0115] 17, a fourth wiring layer is formed on the third wiring layer. Wiring H24 and the lower electrodes CLA2 and CLB2 of each capacitor 126A, 126B are formed in the fourth wiring layer. The wiring H24 and the lower electrodes CLA2 and CLB2 of each capacitor 126A, 126B are connected to each other via contacts CN24. For example, the wiring H24 includes wiring H24C and a power supply line H24D. The wiring H24C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each capacitor 126A, 126B. The power supply line H24D is used to supply a power supply voltage VDD. The power supply line H24D can be wired, for example, vertically and horizontally along the pixel isolation region ISG2.

[0116] 18, a fifth wiring layer is formed on the fourth wiring layer. Wiring H25 and upper electrodes CUA2 and CUB2 of each capacitor 126A and 126B are formed in the fifth wiring layer. The upper electrodes CUA2 and CUB2 of each capacitor 126A and 126B are connected to each other via wiring H25. The upper electrodes CUA2 and CUB2 can extend in the row direction. In this case, the upper electrodes CUA2 and CUB2 can also be used as voltage control lines that supply the control voltage MVDD.

[0117] In this way, in the second embodiment described above, the pixels 220A and 220B adjacent in the column direction share the reset transistor 123 and the capacitance reset transistor 129, and multiple photodiodes PD1A, PD2A, PD1B, and PD2B are provided in each of the pixels 220A and 220B. This makes it possible to expand the dynamic range while suppressing an increase in layout area, and also to eliminate insufficient settling during resetting, thereby reducing degradation of image quality such as horizontal stripes.

[0118] In the above embodiment, two vertical signal lines 132A and 132B are provided for each column, and pixel signals for two rows are read out in parallel in each frame and AD converted. In addition to this configuration, one vertical signal line may be provided for each column, and pixel signals for one row may be read out sequentially in each frame and AD converted.

[0119] 3. Third Embodiment In the first embodiment described above, the pixels 120A and 120B adjacent to each other in the column direction are provided with the capacitors 126A and 126B, respectively, and share the reset transistor 123 and the capacitance reset transistor 129. In this third embodiment, the pixels adjacent to each other in the row direction are provided with the capacitors 126A and 126B, respectively, and share the reset transistor 123 and the capacitance reset transistor 129.

[0120] FIG. 19 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment.

[0121] In the figure, this imaging device includes pixels 320A and 320B instead of the pixels 120A and 120B of the first embodiment described above. The pixels 320A and 320B are arranged adjacent to each other in the row direction.

[0122] The pixels 320A and 320B have the same configuration as the pixels 120A and 120B of the first embodiment described above, except that the pixels 120A and 120B of the first embodiment described above are connected in the column direction, whereas the pixels 320A and 320B of the third embodiment are connected in the row direction.

[0123] 20 to 24 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the third embodiment. This layout shows a five-layer wiring structure. Also, Fig. 20 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 21 shows an example of a layout of a second wiring layer, Fig. 22 shows an example of a layout of a third wiring layer, Fig. 23 shows an example of a layout of a fourth wiring layer, and Fig. 24 shows an example of a layout of a fifth wiring layer.

[0124] 20, a semiconductor substrate SUB is separated into pixels 320A and 320B by a pixel isolation region ISG3. Photodiodes PD1A and PD1B are formed on the back surface side of the semiconductor substrate SUB for each of the pixels 320A and 320B. An active region AK3 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK3 is isolated by an element isolation region ISA3.

[0125] In pixel 320A, gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, and G3 are formed on the channel region of active region AK3 with a gate insulating film interposed therebetween.In pixel 320B, gate electrodes GB0, GB2, GB4, GB5, GB7, GB8, and G9 are formed on the channel region of active region AK3 with a gate insulating film interposed therebetween.

[0126] Here, the layout of each transistor in each pixel 320A can be made the same as that of each transistor in each pixel 320B. In this case, the position of the capacitance reset transistor 129 in the pixel 320A and the position of the reset transistor 123 in the pixel 320B can be made the same as that of each transistor in each pixel 320B.

[0127] A first wiring layer is formed on the semiconductor substrate SUB. Wiring H31 is formed in the first wiring layer. The wiring H31 is used to connect to gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK3. In this case, the wiring H31 is connected to gate electrodes GA0, GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK3 via contacts CN31. For example, the wiring H31 includes wirings H31C, H31F, H31R, H31M, H31X, and H31Y. The wiring H31C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. The wiring H31F is used to connect the drain layer of the capacitance reset transistor 129 to the power supply voltage VDD. The wiring H31R is used to connect the drain layer of the reset transistor 123 to the power supply voltage VDD. The wiring H31M is used to connect the floating diffusions FD2A and FD2B. The wirings H31X and H31Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B.

[0128] 21 , a second wiring layer is formed on the first wiring layer. Wiring H32 is formed in the second wiring layer. Wiring H32 is connected between layers via contact CN32. For example, wiring H32 includes wirings H32C, H32V1, H32V2, H32G, H32X, and H2Y. Wiring H32C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each of the capacitors 126A and 126B. Wirings H32V1 and H32V2 are used for vertical signal lines 132A and 132B. Wiring H32G is used as ground wiring. Wirings H32X and H32Y are used to connect each of the floating diffusions FD3A and FD3B to the lower electrodes of each of the capacitors 126A and 126B.

[0129] 22 , a third wiring layer is formed on the second wiring layer. Wiring H33 is formed in the third wiring layer. Wiring H33 is connected between layers via contact CN33. For example, wiring H33 includes wirings H33C, H33X, H33Y, H33D, H33K, H33J, H33GA, H33GB, H33DA, H33TA, H33TB, and H33SA. Wiring H33C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. Wirings H33X and H33Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B. Wiring H33D is used to supply the power supply voltage VDD. The wiring H33K is used to drive the gate electrode G3 of the reset transistor 123. The wiring H33J is used to drive the gate electrode G9 of the capacitance reset transistor 129. The wiring H33GA is used to drive the gate electrode GA7 of the pass transistor 127A. The wiring H33GB is used to drive the gate electrode GB7 of the pass transistor 127B. The wiring H33DA is used to drive the gate electrodes GA8 and GB8 of the switching transistors 128A and 128B. The wiring H33TA is used to drive the gate electrode GA2 of the transfer transistor 122A. The wiring H33TB is used to drive the gate electrode GB2 of the transfer transistor 122B. The wiring H33SA is used to drive the gate electrodes GA5 and GB5 of the selection transistors 125A and 125B.

[0130] 23 , a fourth wiring layer is formed on the third wiring layer. Wiring H34 and the lower electrodes CLA3 and CLB3 of the capacitors 126A and 126B are formed in the fourth wiring layer. The wiring H34 and the lower electrodes CLA3 and CLB3 of the capacitors 126A and 126B are connected to each other via contacts CN34. For example, the wiring H34 includes wiring H34C and a power supply line H34D. The wiring H34C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. The power supply line H34D is used to supply the power supply voltage VDD. The power supply line H34D can be wired, for example, vertically and horizontally along the pixel isolation region ISG3.

[0131] 24, a fifth wiring layer is formed on the fourth wiring layer. Upper electrodes CUA3 and CUB3 of the capacitors 126A and 126B are formed on the fifth wiring layer. The upper electrodes CUA3 and CUB3 of the capacitors 126A and 126B extend in the row direction and are connected to each other. In this case, the upper electrodes CUA3 and CUB3 can also be used as voltage control lines that supply the control voltage MVDD.

[0132] In this way, in the third embodiment described above, capacitors 126A and 126B are provided in pixels 320A and 320B adjacent to each other in the row direction, and the reset transistor 123 and the capacitance reset transistor 129 are shared by the pixels 320A and 320B. This makes it possible to prevent an increase in the layout area, while eliminating insufficient settling during resetting, and reducing degradation of image quality such as horizontal stripes.

[0133] 4. Fourth Embodiment In the third embodiment described above, the pixels 320A and 320B adjacent in the row direction are provided with the capacitors 126A and 126B, respectively, and share the reset transistor 123 and the capacitance reset transistor 129. In this fourth embodiment, the pixels adjacent in the row direction share the reset transistor 123 and the capacitance reset transistor 129, and each pixel is provided with a plurality of photodiodes.

[0134] FIG. 25 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment.

[0135] In the figure, this imaging device includes pixels 420A and 420B instead of the pixels 320A and 320B of the third embodiment described above. The pixels 420A and 420B are arranged adjacent to each other in the row direction.

[0136] Each of the pixels 420A and 420B has a configuration in which photodiodes PD2A and PD2B are added to the pixels 320A and 320B of the third embodiment described above. Furthermore, each of the pixels 420A and 420B has the overflow control transistors 130A and 130B removed from the pixels 320A and 320B of the third embodiment described above. The remaining configuration of each of the pixels 420A and 420B of the fourth embodiment is the same as the configuration of each of the pixels 320A and 320B of the third embodiment described above.

[0137] 26 to 30 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the fourth embodiment. This layout shows a five-layer wiring structure. Also, Fig. 26 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 27 shows an example of a layout of a second wiring layer, Fig. 28 shows an example of a layout of a third wiring layer, Fig. 29 shows an example of a layout of a fourth wiring layer, and Fig. 30 shows an example of a layout of a fifth wiring layer.

[0138] 26, the semiconductor substrate SUB is separated into pixels 420A and 420B by a pixel isolation region ISG4. On the back surface side of the semiconductor substrate SUB, photodiodes PD1A and PD2A are formed in the pixel 420A, and photodiodes PD1B and PD2B are formed in the pixel 420B. Here, the photodiodes PD1A, PD2A, PD1B, and PD2B can be separated by the pixel isolation region ISG4. On the front surface side of the semiconductor substrate SUB, an active region AK4 is provided, and the active region AK4 is isolated by an element isolation region ISA4.

[0139] In pixel 420A, gate electrodes GA2, GA4, GA5, GA7, GA8, and G3 are formed on the channel region of active region AK4 via a gate insulating film.In pixel 420B, gate electrodes GB2, GB4, GB5, GB7, GB8, and G9 are formed on the channel region of active region AK4 via a gate insulating film.

[0140] Here, the layout of each transistor in each pixel 420A can be made the same as that in each pixel 420B. In this case, the position of the capacitance reset transistor 129 in the pixel 420A and the position of the reset transistor 123 in the pixel 420B can be made the same as that in each pixel 420B.

[0141] A first wiring layer is formed on the semiconductor substrate SUB. Wiring H41 is formed in the first wiring layer. The wiring H41 is used to connect to gate electrodes GA2, GA4, GA5, GA7, GA8, G9, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK4. At this time, the wiring H41 is connected to gate electrodes GA2, GA4, GA5, GA7, GA8, G9, GB0, GB2, GB4, GB5, GB7, GB8, and G3 and the active region AK4 via contacts CN41. For example, the wiring H41 includes wirings H41C, H41F, H41R, H41M, H41X, H41Y, and H41TA. The wiring H41C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each of the capacitors 126A and 126B. The wiring H41F is used to connect the drain layer of the capacitance reset transistor 129 to the power supply voltage VDD. The wiring H41R is used to connect the drain layer of the reset transistor 123 to the power supply voltage VDD. The wiring H41M is used to connect the floating diffusions FD2A and FD2B. The wirings H41X and H41Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of each of the capacitors 126A and 126B. The wiring H41TA is used to drive the gate electrode GA2 of the transfer transistor 122A.

[0142] 27 , a second wiring layer is formed on the first wiring layer. Wiring H42 is formed in the second wiring layer. Wiring H42 is connected between layers via contact CN42. For example, wiring H42 includes wirings H42C, H42V1, H42V2, H42G, H42X, and H42Y. Wiring H42C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each of the capacitors 126A and 126B. Wirings H42V1 and H42V2 are used for vertical signal lines 132A and 132B. Wiring H42G is used as ground wiring. Wirings H42X and H42Y are used to connect each of the floating diffusions FD3A and FD3B to the lower electrodes of each of the capacitors 126A and 126B.

[0143] 28 , a third wiring layer is formed on the second wiring layer. Wiring H43 is formed in the third wiring layer. Wiring H43 is connected between layers via contact CN43. For example, wiring H43 includes wirings H43C, H43X, H43Y, H43D, H43K, H43J, H43GA, H43GB, H43DA, H43TB, and H43SA. Wiring H43C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of the capacitors 126A and 126B. Wiring H43X and H43Y are used to connect the floating diffusions FD3A and FD3B to the lower electrodes of the capacitors 126A and 126B. Wiring H43M is used to connect the floating diffusions FD2A and FD2B. The wiring H43D is used to supply the power supply voltage VDD. The wiring H43K is used to drive the gate electrode G3 of the reset transistor 123. The wiring H43J is used to drive the gate electrode G9 of the capacitance reset transistor 129. The wiring H43GA is used to drive the gate electrode GA7 of the pass transistor 127A. The wiring H43GB is used to drive the gate electrode GB7 of the pass transistor 127B. The wiring H43DA is used to drive the gate electrodes GA8 and GB8 of the switching transistors 128A and 128B. The wiring H43TB is used to drive the gate electrode GB2 of the transfer transistor 122B. The wiring H43SA is used to drive the gate electrodes GA5 and GB5 of the selection transistors 125A and 125B.

[0144] 29, a fourth wiring layer is formed on the third wiring layer. Wiring H44 and the lower electrodes CLA4, CLB4 of each capacitor 126A, 126B are formed in the fourth wiring layer. The wiring H44 and the lower electrodes CLA4, CLB4 of each capacitor 126A, 126B are connected to each other via contacts CN44. For example, the wiring H44 includes wiring H44C and a power supply line H44D. The wiring H44C is used to connect the source layer of the capacitance reset transistor 129 to the upper electrodes of each capacitor 126A, 126B. The power supply line H44D is used to supply the power supply voltage VDD. The power supply line H44D can be wired, for example, vertically and horizontally along the pixel isolation region ISG3.

[0145] 30, a fifth wiring layer is formed on the fourth wiring layer. Upper electrodes CUA4 and CUB4 of the capacitors 126A and 126B are formed on the fifth wiring layer. The upper electrodes CUA4 and CUB4 of the capacitors 126A and 126B extend in the row direction and are connected to each other. In this case, the upper electrodes CUA4 and CUB4 can also be used as voltage control lines that supply the control voltage MVDD.

[0146] In this way, in the fourth embodiment described above, the pixels 420A and 420B adjacent in the row direction share the reset transistor 123 and the capacitance reset transistor 129, and multiple photodiodes PD1A, PD2A, PD1B, and PD2B are provided in each pixel 420A, 420B. This makes it possible to expand the dynamic range while suppressing an increase in layout area, and also to eliminate insufficient settling during resetting, thereby reducing degradation of image quality such as horizontal stripes.

[0147] 5. Fifth Embodiment In the first embodiment described above, the pixels 120A and 120B adjacent to each other in the column direction are provided with the capacitors 126A and 126B, respectively, and share the reset transistor 123 and the capacitance reset transistor 129. In this fifth embodiment, a capacitor is provided in each of four pixels adjacent to each other in the column direction and the row direction, and the reset transistor, the capacitance reset transistor, and the switching transistor are shared.

[0148] FIG. 31 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0149] In the figure, pixels 520A to 520D are arranged adjacent to each other in the column direction and the row direction in the pixel array section 111. In this case, pixels 520A and 520B are arranged adjacent to each other in the column direction, and pixels 520C and 520D are arranged adjacent to each other in the column direction. Pixels 520A and 520C are arranged adjacent to each other in the row direction, and pixels 520B and 520D are arranged adjacent to each other in the row direction.

[0150] The pixel 520A includes a photodiode PD5A, a transfer transistor 522A, an amplifier transistor 524A, a selection transistor 525A, and floating diffusions FD5A to FD7A. The pixel 520A further includes a capacitor 526A, a pass transistor 527A, a switching transistor 528A, and an overflow control transistor 530A.

[0151] One end of the capacitor 526A is connected to the control voltage MVDD, and the other end of the capacitor 526A is connected to the cathode of the photodiode PD5A via the overflow control transistor 530A. The transfer transistor 522A is connected between the cathode of the photodiode PD5A and the floating diffusion FD5A. The amplification transistor 524A and the selection transistor 525A are connected in series. The drain of the amplification transistor 524A is connected to the power supply voltage VDD. The gate of the amplification transistor 524A is connected to the floating diffusion FD5A. The source of the selection transistor 525A is connected to the vertical signal line 132A.

[0152] The pass transistor 527A is connected between the connection point of the overflow control transistor 530A and the capacitor 56A and the switching transistor 528A. A floating diffusion FD7A is formed at the connection point of the overflow control transistor 530A and the capacitor 56A. A floating diffusion FD6A is formed at the connection point of the pass transistor 527A and the switching transistor 528A. The switching transistor 528A is connected between the floating diffusions FD5A and FD6A. The overflow control transistor 530A is connected between the photodiode PD5A and the capacitor 526A.

[0153] A transfer signal TGLA is applied to the gate of the transfer transistor 522A. A selection signal SELA is applied to the gate of the selection transistor 525A. A pass setting signal FCGA is applied to the gate of the pass transistor 527A. A switching signal FDGA is applied to the gate of the switching transistor 528A. An overflow control voltage OFGA is applied to the gate of the overflow control transistor 530A. A control voltage MVDD is applied to the capacitor 526A.

[0154] The pixel 520B includes a photodiode PD5B, a transfer transistor 522B, an amplifier transistor 524B, a selection transistor 525B, and floating diffusions FD5B to FD7B. The pixel 520B further includes a capacitor 526B, a pass transistor 527B, a switching transistor 528B, and an overflow control transistor 530B.

[0155] One end of the capacitor 526B is connected to the control voltage MVDD, and the other end of the capacitor 526B is connected to the cathode of the photodiode PD5B via the overflow control transistor 530B. The transfer transistor 522B is connected between the cathode of the photodiode PD5B and the floating diffusion FD5B. The amplification transistor 524B and the selection transistor 525B are connected in series. The drain of the amplification transistor 54B is connected to the power supply voltage VDD. The gate of the amplification transistor 524B is connected to the floating diffusion FD5B. The source of the selection transistor 525B is connected to the vertical signal line 132A.

[0156] The pass transistor 527B is connected between the connection point of the overflow control transistor 530B and capacitor 56B and the switching transistor 528B. A floating diffusion FD7B is formed at the connection point of the overflow control transistor 530B and capacitor 526B. A floating diffusion FD6B is formed at the connection point of the pass transistor 527B and switching transistor 528B. The switching transistor 528B is connected between the floating diffusions FD5B and FD6B. The overflow control transistor 530B is connected between the photodiode PD5B and capacitor 526B.

[0157] A transfer signal TGLB is applied to the gate of the transfer transistor 522B. A selection signal SELB is applied to the gate of the selection transistor 525B. A path setting signal FCGB is applied to the gate of the pass transistor 527B. A switching signal FDGB is applied to the gate of the switching transistor 528B. An overflow control voltage OFGB is applied to the gate of the overflow control transistor 530B. A control voltage MVDD is applied to the capacitor 526B.

[0158] The pixel 520C includes a photodiode PD5C, a transfer transistor 522C, an amplifier transistor 524C, a selection transistor 525C, and floating diffusions FD5C to FD7C. The pixel 520C further includes a capacitor 526C, a pass transistor 527C, a switching transistor 528C, and an overflow control transistor 530C.

[0159] One end of the capacitor 526C is connected to the control voltage MVDD, and the other end of the capacitor 526C is connected to the cathode of the photodiode PD5C via the overflow control transistor 530C. The transfer transistor 522C is connected between the cathode of the photodiode PD5C and the floating diffusion FD5C. The amplification transistor 524C and the selection transistor 525C are connected in series. The drain of the amplification transistor 54C is connected to the power supply voltage VDD. The gate of the amplification transistor 524C is connected to the floating diffusion FD5C. The source of the selection transistor 525C is connected to the vertical signal line 132B.

[0160] The pass transistor 527C is connected between the connection point of the overflow control transistor 530C and the capacitor 56C and the switching transistor 528C. A floating diffusion FD7C is formed at the connection point of the overflow control transistor 530C and the capacitor 526C. A floating diffusion FD6C is formed at the connection point of the pass transistor 527C and the switching transistor 528C. The switching transistor 528C is connected between the floating diffusions FD5C and FD6C. The overflow control transistor 530C is connected between the photodiode PD5C and the capacitor 526C.

[0161] A transfer signal TGLA is applied to the gate of the transfer transistor 522C. A selection signal SELA is applied to the gate of the selection transistor 525C. A pass setting signal FCGA is applied to the gate of the pass transistor 527C. A switching signal FDGA is applied to the gate of the switching transistor 528C. An overflow control voltage OFGA is applied to the gate of the overflow control transistor 530C. A control voltage MVDD is applied to the capacitor 526C.

[0162] The pixel 520D includes a photodiode PD5D, a transfer transistor 522D, an amplifier transistor 524D, a selection transistor 525D, and floating diffusions FD5D to FD7D. The pixel 520D also includes a reset transistor 523. The pixel 520D further includes a capacitor 526D, a pass transistor 527D, a switching transistor 528D, and an overflow control transistor 530D.

[0163] The reset transistor 523 resets the photodiodes PD5A to PD5D of the pixels 520A to 520D. At this time, the reset transistor 523 is shared by the pixels 520A to 520D. The reset transistor 523 is connected between the floating diffusion FD6D and the power supply voltage VDD.

[0164] One end of the capacitor 526D is connected to the control voltage MVDD, and the other end of the capacitor 526D is connected to the cathode of the photodiode PD5D via the overflow control transistor 530D. The transfer transistor 522D is connected between the cathode of the photodiode PD5D and the floating diffusion FD5D. The amplification transistor 524D and the selection transistor 525D are connected in series. The drain of the amplification transistor 54D is connected to the power supply voltage VDD. The gate of the amplification transistor 524D is connected to the floating diffusion FD5D. The source of the selection transistor 525D is connected to the vertical signal line 132B.

[0165] The pass transistor 527D is connected between the connection point of the overflow control transistor 530D and the capacitor 56D and the switching transistor 528D. A floating diffusion FD7D is formed at the connection point of the overflow control transistor 530D and the capacitor 526D. A floating diffusion FD6D is formed at the connection point of the pass transistor 527D and the switching transistor 528D. The switching transistor 528D is connected between the floating diffusions FD5D and FD6D. The overflow control transistor 530D is connected between the photodiode PD5D and the capacitor 526D.

[0166] A transfer signal TGLB is applied to the gate of the transfer transistor 522D. A reset signal RST is applied to the gate of the reset transistor 523. A selection signal SELB is applied to the gate of the selection transistor 525D. A path setting signal FCGB is applied to the gate of the pass transistor 527D. A switching signal FDGB is applied to the gate of the switching transistor 528D. An overflow control voltage OFGB is applied to the gate of the overflow control transistor 530D. A control voltage MVDD is applied to the capacitor 526D.

[0167] The capacitance reset transistor 529 resets the capacitors 526A to 526D of each of the pixels 520A to 520D. The capacitance reset transistor 529 is shared by the pixels 520A to 520D. In this case, the capacitance reset transistor 529 can be arranged in any of the pixels 520A to 520C in which the reset transistor 523 is not arranged. One end of the capacitance reset transistor 529 is connected to the power supply voltage VDD. The other end of the capacitance reset transistor 529 is connected to each of the capacitors 526A to 526D. A capacitance reset signal FCR is applied to the gate of the capacitance reset transistor 529.

[0168] The switching transistor 531 switches the connection between the pixels 520A and 520B and the pixels 520C and 520D. The switching transistor 531 is shared by the pixels 520A to 520D. The switching transistor 531 can be placed in any of the pixels 520A to 520C in which the reset transistor 523 and the capacitance reset transistor 529 are not placed. The switching transistor 531 is connected between the floating diffusions FD6A and FD6B and the floating diffusions FD6C and FD6D. A switching signal CNG is applied to the gate of the switching transistor 531. By turning on the switching transistor 531, the floating diffusions FD6A to FD6D of each of the pixels 520A to 520D can be coupled. This reduces the conversion efficiency of each of the pixels 520A to 520D, thereby further expanding the dynamic range.

[0169] FIG. 32 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the fifth embodiment.

[0170] As shown in the figure, the overflow control voltages OFGA and OFGB are set to fixed voltages throughout the entire period of each frame.

[0171] Furthermore, in each frame, a shutter period and an accumulation period are provided before the readout operation. A control voltage MVDD is applied to the upper electrode of each of the capacitors 526A to 526D, and during the accumulation period, the upper electrode of each of the capacitors 526A to 526D is set to a low level. By setting the control voltage MVDD to a low level during the accumulation period, the dark current of each of the capacitors 526A to 526D can be reduced. During the shutter period, the control voltage MVDD may be set to a low level or a high level.

[0172] During the read period, in a low-efficiency P-phase single read period K51, the reset signal RST, the selection signals SELA and SELB, the switching signal CNG, and the control voltage MVDD rise, followed by the switching signals FDGA and FDGB. At this time, the control voltage MVDD is set to a high level, and the upper electrodes of the capacitors 526A to 526D are set to a high level. Furthermore, the reset transistor 523 and the switching transistor 531 are turned on, and the switching transistors 528A to 528D are turned on row by row, thereby discharging the charge from the floating diffusions FD5A to FD5D and reducing the conversion efficiency of the amplification transistors 524A to 524D. After the charge from the floating diffusions FD5A to FD5B is discharged, the reset signal RST falls, and the reset transistor 523 is turned off.

[0173] Furthermore, when the selection transistors 525A to 525D are turned on for each row and the reset transistor 523 is turned off, the potential of each vertical signal line 132A, 132B is set for each row based on the source follower operation when the low-efficiency P-phase levels of each floating diffusion FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D, respectively. Then, based on the potential of each vertical signal line 132A, 132B for each row at that time, the low-efficiency P-phase levels of each pixel 520A to 520D are AD converted for each row. Then, the switching signal CNG falls, turning off the switching transistor 531. At this time, the floating diffusions FD6A, FD6B and the floating diffusions FD6C, FD6D are isolated from each other, and the conversion efficiency of each pixel 520A to 520D is set to low to medium conversion efficiency.

[0174] Next, in a medium-efficiency P-phase single readout period K52, the potential of each vertical signal line 132A, 132B is set based on the source follower operation when the medium-efficiency P-phase level of each floating diffusion FD5A to FD5D is applied to the gates of the amplification transistors 524A to 524D for each row. Then, based on the potential of each vertical signal line 132A, 132B for each row at that time, the medium-efficiency P-phase level of each pixel 520A to 520D is AD converted for each row.

[0175] Next, during a high-efficiency P-phase single readout period K53, the switching signals FDGA and FDGB fall. At this time, the switching transistors 528A to 528D are turned off, increasing the conversion efficiency of the amplification transistors 524A to 524D. The potentials of the vertical signal lines 132A and 132B are set based on the source follower operation when the high-efficiency P-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. The high-efficiency P-phase levels of the pixels 520A to 520D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0176] Next, during a high-efficiency D-phase individual readout period K54, the transfer signals TGLA and TGLB rise. At this time, the transfer transistors 522A to 522D turn on, and the charges stored in the photodiodes PD5A to PD5D are transferred to the floating diffusions FD5A to FD5D. Then, the transfer signals TGLA and TGLB fall. At this time, the transfer transistors 522A to 522D turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-efficiency D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, the high-efficiency D-phase levels of the pixels 520A to 520D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0177] Next, during a medium-efficiency D-phase single readout period K55, the switching signals FDGA and FDGB and the transfer signals TGLA and TGLB rise. At this time, the switching transistors 528A to 528D are turned on row by row, and the conversion efficiency of each pixel 520A to 520D is set from high conversion efficiency to medium conversion efficiency. Furthermore, the transfer transistors 522A to 522D are turned on, and the charges stored in the photodiodes PD5A to PD5D are transferred to the floating diffusions FD5A to FD5D. Then, the transfer signals TGLA and TGLB fall. At this time, the transfer transistors 522A to 522D are turned off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the medium-efficiency D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, based on the potential of each vertical signal line 132A, 132B at that time, the medium-efficiency D-phase level of each of the pixels 520A to 520D is AD converted.

[0178] Next, during the low-efficiency D-phase single read period K56, the switching signal CNG and the transfer signals TGLA and TGLB rise. At this time, the switching transistor 531 turns on, reducing the conversion efficiency of the amplifier transistors 524A to 524D. The transfer transistors 522A to 522D turn on, transferring the charges stored in the photodiodes PD5A to PD5D to the floating diffusions FD5A to FD5D. The transfer signals TGLA and TGLB then fall. At this time, the transfer transistors 522A to 522D turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the low-efficiency D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplifier transistors 524A to 524D. Then, based on the potential of each vertical signal line 132A, 132B at that time, the low-efficiency D-phase level of each pixel 520A to 520D is AD converted. Then, the switching signal CNG falls, turning off the switching transistor 531. At this time, the floating diffusions FD6A, FD6B and the floating diffusions FD6C, FD6D are separated from each other, and the conversion efficiency of each pixel 520A to 520D is reduced.

[0179] CDS reading can be performed in the low-efficiency P-phase single read period K51, the medium-efficiency P-phase single read period K52, the high-efficiency P-phase single read period K53, the high-efficiency D-phase single read period K54, the medium-efficiency D-phase single read period K55 and the low-efficiency D-phase single read period K56.

[0180] Next, during a D-phase batch readout period K57, the path setting signals FCGA and FCGB rise. At this time, the path transistors 527A to 527D are turned on, and the potentials of the vertical signal lines 132A and 132B are set based on the source follower operation when the D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, the D-phase batch levels of the pixels 520A to 520D are AD converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0181] Next, during the P-phase batch read period K58, the selection signals SELA and SELB fall, while the capacitance reset signal FCR, reset signal RST, and switching signal CNG rise. At this time, the switching transistor 531 turns on, reducing the conversion efficiency of the amplifier transistors 524A to 524D. The selection transistors 525A to 525D turn off, and the reset transistor 523 turns on, draining the charge from the floating diffusions FD5A to FD5D. The capacitance reset transistor 529 turns on, supplying the power supply voltage VDD to the upper electrodes of the capacitors 526A to 526D. This allows power to be supplied from the power supply voltage VDD to the upper electrodes of the capacitors 526A to 526D, shortening the power supply path to the upper electrodes of the capacitors 526A to 526D. This eliminates insufficient settling during resetting and reduces degradation of image quality, such as horizontal streaks.

[0182] Then, the path setting signals FCGA and FCGB fall, turning off the path transistors 527A to 527D, and then the selection signals SELA and SELB rise, turning on the selection transistors 525A to 525D. Then, the capacitance reset signal FCR, reset signal RST, and switching signal CNG fall, turning off the capacitance reset transistor 529, reset transistor 523, and switching transistor 531, and then the path setting signals FCGA and FCGB rise, turning on the path transistors 527A to 527D. At this time, the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the P-phase collective levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, the P-phase collective levels of each pixel 520A to 520D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0183] During the D-phase batch read period K57 and the P-phase batch read period K58, DDS readout can be performed.

[0184] Next, in a DOL period K59, the path setting signals FCGA and FCGB fall, turning off the path transistors 527A to 527D, and then the selection signals SELA and SELB fall, turning off the selection transistors 525A to 525D. At this time, during the DOL period K57, the accumulation time of each frame is minimized, and the brightest scene is captured in a time-division manner. Note that the DOL period K57 may be omitted.

[0185] 33 to 37 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the fifth embodiment. This layout shows a five-layer wiring structure. Also, Fig. 33 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 34 shows an example of a layout of a second wiring layer, Fig. 35 shows an example of a layout of a third wiring layer, Fig. 36 shows an example of a layout of a fourth wiring layer, and Fig. 37 shows an example of a layout of a fifth wiring layer.

[0186] 33, a semiconductor substrate SUB is separated into pixels 520A to 520D by pixel isolation regions ISG. Photodiodes PD5A to PD5D are formed on the back surface side of the semiconductor substrate SUB for the pixels 520A to 520D. An active region AK5 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK5 is isolated by element isolation regions ISA5.

[0187] In each of the pixels 520A to 520D, gate electrodes G52, G54, G55, G57, G58, and G50 are formed on the channel region of the active region AK5 via a gate insulating film. The gate electrode G52 can be used for the transfer transistors 522A to 522D of each of the pixels 520A to 520D. The gate electrode G54 can be used for the amplification transistors 524A to 524D of each of the pixels 520A to 520D. The gate electrode G55 can be used for the selection transistors 525A to 525D of each of the pixels 520A to 520D. The gate electrode G57 can be used for the pass transistors 527A to 527D of each of the pixels 520A to 520D. The gate electrode G58 can be used for the switching transistors 528A to 528D of each of the pixels 520A to 520D. The gate electrode G50 can be used for the overflow control transistors 530A to 530D of each pixel 520A to 520D.

[0188] In the pixel 520A, a gate electrode G51A is formed on the channel region of the active region AK5 with a gate insulating film interposed therebetween. The gate electrode G51A can be used for the switching transistor 531.

[0189] In the pixel 520B, a gate electrode G59 is formed on the channel region of the active region AK5 via a gate insulating film. The gate electrode G59 can be used for a capacitance reset transistor 529.

[0190] In the pixel 520C, a gate electrode G51C is formed on the channel region of the active region AK5 via a gate insulating film. The gate electrode G51C can be used for the switching transistor 531.

[0191] In the pixel 520D, a gate electrode G53 is formed on the channel region of the active region AK5 via a gate insulating film. The gate electrode G53 can be used for the reset transistor 523.

[0192] Here, the layout of each transistor in each pixel 520A to 520D can be made equal to one another. In this case, the layout of each transistor in each pixel 520A, 520B can be arranged line-symmetrically with respect to the row direction, and the layout of each transistor in each pixel 520C, 520D can be arranged line-symmetrically with respect to the row direction. Furthermore, the layout of each transistor in each pixel 520A, 520C can be arranged line-symmetrically with respect to the column direction, and the layout of each transistor in each pixel 520B, 520D can be arranged line-symmetrically with respect to the column direction. Furthermore, the position of the switching transistor 531 in pixel 520A, the position of the capacitance reset transistor 529 in pixel 520B, the position of the switching transistor 531 in pixel 520C, and the position of the reset transistor 523 in pixel 520D can be made equal to one another.

[0193] A first wiring layer H51 is formed on the semiconductor substrate SUB. The first wiring layer H51 is connected to gate electrodes G52 to G55, G57 to G50, G51A, G51C and the active region AK5 via contacts CN51.

[0194] 34 , a second wiring layer H52 is formed on a first wiring layer H51. The second wiring layer H52 is connected to the other layers via a contact CN52. The second wiring layer H52 includes wirings H52A to H52H. The wirings H52A and H52B are used for the vertical signal lines 132A and 132B, respectively. The wirings H52C and H52D are used to supply the power supply voltage VDD. The wiring H52E is used to connect the floating diffusions FD6A and FD6B of the pixels 520A and 520B. The wiring H52F is used to connect the floating diffusions FD6C and FD6D of the pixels 520C and 520D. The wiring H52G is used to connect the switching transistor 531. The wiring H52H is used to connect the capacitance reset transistor 529.

[0195] 35, a third wiring layer H53 is formed on the second wiring layer H52. The third wiring layer H53 is connected to the other layers via contacts CN53. The third wiring layer H53 includes wirings H53A1, H53A2, H53B1, H53B2, H53D1, H53D2, H53E1, H53E2, H53F1, H53F2, H53C, H53G, H53H, and H53I. The wirings H53A1 and H53A2 are used to transmit the selection signals SELA and SELB, respectively. The wirings H53B1 and H53B2 are used to supply the power supply voltage VDD. The wirings H53D1 and H53D2 are used to transmit the transfer signals TGLA and TGLB, respectively. The wirings H53E1 and H53E2 are used to transmit the switching signals FDGA and FDGB, respectively. The wirings H53F1 and H53F2 are used to transmit the path setting signals FCGA and FCGB, respectively. The wiring H53C is used to transmit the switching signal CNG. The wiring H53G is used to transmit the overflow control voltages OFGA and OFGB. The wiring H53H is used to transmit the capacitance reset signal FCR. The wiring H53I is used to transmit the reset signal SEL.

[0196] 36, a fourth wiring layer H54 is formed on the third wiring layer H53. The fourth wiring layer H54 is connected between layers via a contact CN54. The fourth wiring layer H54 includes wirings H54A to H54E. The wirings H54A to H54D are used for the lower electrodes of the capacitors 526A to 526D, respectively. The wiring H54E is used to transmit a capacitance reset signal FCR.

[0197] 37, a fifth wiring layer H55 is formed on the fourth wiring layer H54. The fifth wiring layer H55 is used for the upper electrodes of each of the capacitors 526A to 526D. The fifth wiring layer H55 can extend in the row direction. In this case, the upper electrodes of each of the capacitors 526A to 526D can also be used as voltage control lines that supply the control voltage MVDD.

[0198] In this way, in the fifth embodiment described above, capacitors 526A to 526D are provided in pixels 520A to 520D adjacent in the column direction and row direction, respectively, and share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531. This makes it possible to expand the dynamic range in multiple stages while suppressing an increase in layout area, and also to eliminate insufficient settling during resetting, thereby reducing degradation of image quality such as horizontal stripes.

[0199] 6. Sixth Embodiment In the fifth embodiment described above, capacitors 526A to 526D are provided in four pixels adjacent in the column direction and row direction, and they share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531. In this sixth embodiment, capacitors 526A to 526D are provided in pixels 520A to 520D adjacent in the column direction and row direction, and they share the reset transistor 523, the capacitance reset transistor 529, and two switching transistors.

[0200] FIG. 38 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the sixth embodiment.

[0201] In the figure, this imaging device includes pixels 620A to 620D instead of the pixels 520A to 520D of the fifth embodiment described above. The pixels 620A to 620D are arranged adjacent to each other in the column and row directions.

[0202] Each of the pixels 620A to 620D can be configured in the same manner as the pixels 520A to 520D of the fifth embodiment, except that this imaging device includes switching transistors 531A and 531B instead of the switching transistor 531 of the fifth embodiment.

[0203] The switching transistors 531A and 531B switch the connections between the pixels 620A and 620B and the pixels 620C and 620D. The switching transistors 531A and 531B are connected in series with each other. The switching transistors 531A and 531B are shared by the pixels 620A to 620D. The switching transistor 531A can be arranged in any of the pixels 620A to 620C in which the reset transistor 523 and the capacitance reset transistor 529 are not arranged. The switching transistor 531B can be arranged in any of the pixels 620A to 620C in which the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531A are not arranged. A switching signal CNGA is applied to the gate of the switching transistor 531A. A switching signal CNGB is applied to the gate of the switching transistor 531B. At this time, by simultaneously turning on the switching signals CNGA and CNGB, the floating diffusions FD6A to FD6D of the pixels 620A to 620D can be coupled together.

[0204] A capacitance may be connected to the connection point of the switching transistors 531A and 531B. In this case, by turning on one of the switching signals CNGA and CNGB, a capacitance can be added and connected to the pixels 620A and 620B or the pixels 620C and 620D, thereby further expanding the dynamic range.

[0205] 39 to 43 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the sixth embodiment. This layout shows a five-layer wiring structure. Also, Fig. 39 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 40 shows an example of a layout of a second wiring layer, Fig. 41 shows an example of a layout of a third wiring layer, Fig. 42 shows an example of a layout of a fourth wiring layer, and Fig. 43 shows an example of a layout of a fifth wiring layer.

[0206] 39, a semiconductor substrate SUB is separated into pixels 620A to 620D by pixel isolation regions ISG. Photodiodes PD5A to PD5D are formed on the back surface side of the semiconductor substrate SUB for the pixels 620A to 620D. An active region AK6 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK6 is isolated by element isolation regions ISA6.

[0207] In each of the pixels 620A to 620D, gate electrodes G62, G64, G65, G67, G68, and G60 are formed on the channel region of the active region AK6 via a gate insulating film. The gate electrode G62 can be used for the transfer transistors 522A to 522D of each of the pixels 620A to 620D. The gate electrode G64 can be used for the amplification transistors 524A to 524D of each of the pixels 620A to 620D. The gate electrode G65 can be used for the selection transistors 525A to 525D of each of the pixels 620A to 620D. The gate electrode G67 can be used for the pass transistors 527A to 527D of each of the pixels 620A to 620D. The gate electrode G68 can be used for the switching transistors 528A to 528D of each of the pixels 620A to 620D. The gate electrode G60 can be used for the overflow control transistors 530A to 530D of each pixel 620A to 620D.

[0208] In the pixel 620A, a gate electrode G69 is formed on the channel region of the active region AK6 via a gate insulating film. The gate electrode G69 can be used for the capacitance reset transistor 529.

[0209] In the pixel 620B, a gate electrode G63 is formed on the channel region of the active region AK6 via a gate insulating film. The gate electrode G63 can be used for the reset transistor 523.

[0210] In the pixel 620C, a gate electrode G61C is formed on the channel region of the active region AK6 via a gate insulating film. The gate electrode G61C can be used for the switching transistor 531A.

[0211] In the pixel 620D, a gate electrode G61D is formed on the channel region of the active region AK6 via a gate insulating film. The gate electrode G61D can be used for the switching transistor 531B.

[0212] Here, the layout of each transistor in each pixel 620A to 620D can be made equal to one another. In this case, the layout of each transistor in each pixel 620A, 620B can be arranged line-symmetrically with respect to the row direction, and the layout of each transistor in each pixel 620C, 620D can be arranged line-symmetrically with respect to the row direction. Furthermore, the layout of each transistor in each pixel 620A, 620C can be arranged line-symmetrically with respect to the column direction, and the layout of each transistor in each pixel 620B, 620D can be arranged line-symmetrically with respect to the column direction. Furthermore, the position of the capacitance reset transistor 529 in pixel 620A, the position of the reset transistor 523 in pixel 620B, the position of the switching transistor 531A in pixel 620C, and the position of the switching transistor 531B in pixel 620D can be made equal to one another.

[0213] A first wiring layer H61 is formed on the semiconductor substrate SUB. The first wiring layer H61 is connected to gate electrodes G62 to G65, G67 to G60, G61A, G61C and the active region AK6 via contacts CN61.

[0214] 40 , a second wiring layer H62 is formed on a first wiring layer H61. The second wiring layer H62 is connected between layers via a contact CN62. The second wiring layer H62 includes wirings H62A to H62I. The wirings H62A and H62B are used for the vertical signal lines 132A and 132B, respectively. The wirings H62C and H62D are used to supply the power supply voltage VDD. The wiring H62E is used to connect the floating diffusions FD6A and FD6C of the pixels 620A and 620C. The wiring H62F is used to connect the floating diffusions FD6B and FD6D of the pixels 620B and 620D. The wiring H62G is used to connect the switching transistor 531A. The wiring H62H is used to connect the switching transistor 531B. The wiring H62I is used to connect the capacitance reset transistor 529.

[0215] 41, a third wiring layer H63 is formed on the second wiring layer H62. The third wiring layer H63 is inter-layer connected via a contact CN63. The third wiring layer H63 includes wirings H63A1, H63A2, H63B1, H63B2, H63D1, H63D2, H63E1, H63E2, H63F1, H63F2, H63C, H63G, H63H, and H63I. The wirings H63A1 and H63A2 are used to transmit the selection signals SELA and SELB, respectively. The wiring H63B is used to supply the power supply voltage VDD. The wirings H63D1 and H63D2 are used to transmit the transfer signals TGLA and TGLB, respectively. The wirings H63E1 and H63E2 are used to transmit the switching signals FDGA and FDGB, respectively. The wirings H63F1 and H63F2 are used to transmit the path setting signals FCGA and FCGB, respectively. The wirings H63C1 and H63C2 are used to transmit the switching signals CNGA and CNGB. The wirings H63G1 and H63G2 are used to transmit the overflow control voltages OFGA and OFGB. The wiring H63H is used to transmit the capacitance reset signal FCR. The wiring H63I is used to transmit the reset signal SEL.

[0216] 42, a fourth wiring layer H64 is formed on the third wiring layer H63. The fourth wiring layer H64 is connected between layers via a contact CN64. The fourth wiring layer H64 includes wirings H64A to H64E. The wirings H64A to H64D are used for the lower electrodes of the capacitors 526A to 526D, respectively. The wiring H64E is used to transmit a capacitance reset signal FCR.

[0217] 43, a fifth wiring layer H65 is formed on the fourth wiring layer H64. The fifth wiring layer H65 is used for the upper electrodes of each of the capacitors 526A to 526D. The fifth wiring layer H65 can extend in the row direction. In this case, the upper electrodes of each of the capacitors 526A to 526D can also be used as voltage control lines that supply the control voltage MVDD.

[0218] In this way, in the sixth embodiment described above, capacitors 526A to 526D are provided in pixels 620A to 620D adjacent in the column direction and row direction, respectively, and the reset transistor 523, the capacitance reset transistor 529, and the two switching transistors 531A and 531B are shared. This makes it possible to expand the dynamic range in multiple stages while suppressing an increase in layout area, and also to eliminate insufficient settling during resetting, thereby reducing degradation of image quality such as horizontal stripes.

[0219] 7. Seventh Embodiment In the above-described fifth embodiment, the capacitors 526A to 526D are provided in the pixels 520A to 520D adjacent in the column direction and the row direction, respectively, and share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531. In this seventh embodiment, the capacitors 526A to 526D are provided in four pixels adjacent in the column direction and the row direction, respectively, and share the reset transistor 523 and the capacitance reset transistor 529.

[0220] FIG. 44 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the seventh embodiment.

[0221] In the figure, this imaging device includes pixels 720A to 720D instead of the pixels 520A to 520D of the fifth embodiment described above. The pixels 720A to 720D are arranged adjacent to each other in the column and row directions.

[0222] Each of the pixels 720A to 720D can be configured in the same manner as the pixels 520A to 520D of the fifth embodiment described above. However, in this imaging device, the switching transistor 531 is removed from the imaging device of the fifth embodiment described above. In this case, the floating diffusions FD6A to FD6D of the pixels 620A to 620D are connected to each other.

[0223] 45 to 49 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the seventh embodiment. This layout shows a five-layer wiring structure. Also, Fig. 45 shows an example of a layout of a semiconductor substrate and a first wiring layer, Fig. 46 shows an example of a layout of a second wiring layer, Fig. 47 shows an example of a layout of a third wiring layer, Fig. 48 shows an example of a layout of a fourth wiring layer, and Fig. 49 shows an example of a layout of a fifth wiring layer.

[0224] 45, the semiconductor substrate SUB is separated into pixels 720A to 720D by pixel isolation regions ISG. Photodiodes PD5A to PD5D are formed on the back surface side of the semiconductor substrate SUB for the pixels 720A to 720D. An active region AK7 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK7 is isolated by element isolation regions ISA7.

[0225] In each of the pixels 720A to 720D, gate electrodes G72, G74, G75, G77, G78, and G70 are formed on the channel region of the active region AK7 via a gate insulating film. The gate electrode G72 can be used for the transfer transistors 522A to 522D of each of the pixels 720A to 720D. The gate electrode G74 can be used for the amplification transistors 524A to 524D of each of the pixels 720A to 720D. The gate electrode G75 can be used for the selection transistors 525A to 525D of each of the pixels 720A to 720D. The gate electrode G77 can be used for the pass transistors 527A to 527D of each of the pixels 720A to 720D. The gate electrode G78 can be used for the switching transistors 528A to 528D of each of the pixels 720A to 720D. The gate electrode G70 can be used for the overflow control transistors 530A to 530D of each pixel 720A to 720D.

[0226] In the pixel 720A, a gate electrode G79 is formed on the channel region of the active region AK7 via a gate insulating film. The gate electrode G79 can be used for the capacitance reset transistor 529.

[0227] In the pixel 720B, a gate electrode G71B is formed on the channel region of the active region AK7 via a gate insulating film. The gate electrode G71B can be used for the reset transistor 523.

[0228] In the pixel 720C, a gate electrode G71C is formed on the channel region of the active region AK7 via a gate insulating film. The gate electrode G71C can be used for the reset transistor 523.

[0229] In the pixel 720D, a gate electrode G71D is formed on the channel region of the active region AK7 via a gate insulating film. The gate electrode G71D can be used for the reset transistor 523.

[0230] Here, the layout of each transistor in each pixel 720A to 720D can be made equal to one another. In this case, the layout of each transistor in each pixel 720A and 720C can be arranged line-symmetrically with respect to the column direction, and the layout of each transistor in each pixel 720B and 720D can be arranged line-symmetrically with respect to the column direction. Furthermore, the position of the capacitance reset transistor 529 in pixel 720A, the position of the reset transistor 523 in pixel 720B, the position of the reset transistor 523 in pixel 720C, and the position of the reset transistor 523 in pixel 720D can be made equal to one another.

[0231] A first wiring layer H71 is formed on the semiconductor substrate SUB. The first wiring layer H71 is connected to gate electrodes G72 to G75, G77 to G70, G71B to G71D and active region AK7 via contacts CN71.

[0232] 46, a second wiring layer H72 is formed on a first wiring layer H71. The second wiring layer H72 is connected between layers via a contact CN72. The second wiring layer H72 includes wirings H72A to H72E and H72I. The wirings H72A and H72B are used for the vertical signal lines 132A and 132B, respectively. The wirings H72C and H72D are used to supply the power supply voltage VDD. The wiring H72E is used to connect the floating diffusions FD6A to FD6D of the pixels 720A to 720D. The wiring H72I is used to connect the capacitance reset transistor 529.

[0233] 47, a third wiring layer H73 is formed on the second wiring layer H72. The third wiring layer H73 is interlayer-connected via a contact CN73. The third wiring layer H73 includes wirings H73A1, H73A2, H73B1, H73B2, H73D1, H73D2, H73E1, H73E2, H73G1, H73G2, H73H, H73I, and H73J. The wirings H73A1 and H73A2 are used to transmit the selection signals SELA and SELB, respectively. The wirings H73B1 and H73B2 are used to supply the power supply voltage VDD. The wirings H73D1 and H73D2 are used to transmit the transfer signals TGLA and TGLB, respectively. The wirings H73E1 and H73E2 are used to transmit the switching signals FDGA and FDGB, respectively. The wirings H73G1 and H73G2 are used to transmit the overflow control voltages OFGA and OFGB. The wirings H73H and H73J are used to transmit the capacitance reset signal FCR. The wiring H73I is used to transmit the reset signal SEL.

[0234] 48, a fourth wiring layer H74 is formed on the third wiring layer H73. The fourth wiring layer H74 is connected between layers via a contact CN74. The fourth wiring layer H74 includes wirings H74A to H74E. The wirings H74A to H74D are used for the lower electrodes of the capacitors 526A to 526D, respectively. The wiring H74E is used to transmit a capacitance reset signal FCR.

[0235] 49, a fifth wiring layer H75 is formed on the fourth wiring layer H74. The fifth wiring layer H75 is used for the upper electrodes of each of the capacitors 526A to 526D. The fifth wiring layer H75 can be extended in the row direction. In this case, the upper electrodes of each of the capacitors 526A to 526D can also be used as voltage control lines that supply the control voltage MVDD.

[0236] In this way, in the seventh embodiment described above, the capacitors 526A to 526D are provided in the pixels 720A to 720D adjacent in the column direction and the row direction, respectively, and share the reset transistor 523 and the capacitance reset transistor 529. This makes it possible to reduce the number of control lines used to switch the conversion efficiency while expanding the dynamic range, and also makes it possible to effectively utilize the empty space of each of the pixels 720A to 720D while ensuring symmetry in the layout of each of the pixels 720A to 720D.

[0237] 8. Eighth Embodiment In the fifth embodiment described above, the capacitors 526A to 526D are provided in the pixels 520A to 520D adjacent in the column direction and the row direction, respectively, and share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531. In this eighth embodiment, the reset transistor 523 and the capacitance reset transistor 529 are shared by four pixels adjacent in the column direction and the row direction, thereby reducing the number of horizontal drive lines.

[0238] 50 to 54 are plan views showing an example of a layout of pixels provided in a solid-state imaging device according to the eighth embodiment. This layout shows a five-layer wiring structure. Also, FIG. 50 shows an example of a layout of a semiconductor substrate and a first wiring layer, FIG. 51 shows an example of a layout of a second wiring layer, FIG. 52 shows an example of a layout of a third wiring layer, FIG. 53 shows an example of a layout of a fourth wiring layer, and FIG. 54 shows an example of a layout of a fifth wiring layer. The circuit configuration of the eighth embodiment is similar to that of the seventh embodiment described above.

[0239] 50, a semiconductor substrate SUB is separated into pixels 820A to 820D by pixel isolation regions ISG. Photodiodes PD5A to PD5D are formed on the back surface side of the semiconductor substrate SUB for the pixels 820A to 820D. An active region AK8 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK8 is isolated by element isolation regions ISA8.

[0240] In each of the pixels 820A to 820D, gate electrodes G82, G84, G85, G87, G88, and G80 are formed on the channel region of the active region AK8 via a gate insulating film. The gate electrode G82 can be used for the transfer transistors 522A to 522D of each of the pixels 820A to 820D. The gate electrode G84 can be used for the amplification transistors 524A to 524D of each of the pixels 820A to 820D. The gate electrode G85 can be used for the selection transistors 525A to 525D of each of the pixels 820A to 820D. The gate electrode G87 can be used for the pass transistors 527A to 527D of each of the pixels 820A to 820D. The gate electrode G88 can be used for the switching transistors 528A to 528D of each of the pixels 820A to 820D. The gate electrode G80 can be used for the overflow control transistors 530A to 530D of each pixel 820A to 820D.

[0241] In the pixel 820A, a gate electrode G89 is formed on the channel region of the active region AK8 via a gate insulating film. The gate electrode G89 can be used for the capacitance reset transistor 529.

[0242] In the pixel 820B, a gate electrode G81B is formed on the channel region of the active region AK8 via a gate insulating film. The gate electrode G81B can be used for the reset transistor 523.

[0243] In the pixel 820C, a gate electrode G81C is formed on the channel region of the active region AK8 via a gate insulating film. The gate electrode G81C can be used for the reset transistor 523.

[0244] In the pixel 820D, a gate electrode G81D is formed on the channel region of the active region AK8 via a gate insulating film. The gate electrode G81D can be used for the reset transistor 523.

[0245] Here, the layout of each transistor in each pixel 820A to 820D can be made equal to one another. In this case, the layout of each transistor in each pixel 820A and 820B can be arranged line-symmetrically with respect to the row direction, and the layout of each transistor in each pixel 820C and 860D can be arranged line-symmetrically with respect to the row direction. Furthermore, the layout of each transistor in each pixel 820A and 820C can be arranged line-symmetrically with respect to the column direction, and the layout of each transistor in each pixel 820B and 860D can be arranged line-symmetrically with respect to the column direction. Furthermore, the position of the capacitance reset transistor 529 in pixel 820A, the position of the reset transistor 523 in pixel 820B, the position of the reset transistor 523 in pixel 820C, and the position of the reset transistor 523 in pixel 820D can be made equal to one another.

[0246] A first wiring layer H81 is formed on the semiconductor substrate SUB. The first wiring layer H81 is connected to gate electrodes G82 to G85, G87 to G80, G81B to G81D and active region AK8 via contacts CN81.

[0247] 51 , a second wiring layer H82 is formed on a first wiring layer H81. The second wiring layer H82 is connected between layers via contacts CN82. The second wiring layer H82 includes wirings H82A to H82E and H82I. The wirings H82A and H82B are used for vertical signal lines 132A and 132B, respectively. The wirings H82C and H82D are used as power supply lines for the power supply voltage VDD. The wiring H82E is used to connect floating diffusions FD6A to FD6D of pixels 820A to 820D. The wiring H82I is used to connect the capacitance reset transistor 529.

[0248] 52, a third wiring layer H83 is formed on the second wiring layer H82. The third wiring layer H83 is inter-layer connected via a contact CN83. The third wiring layer H83 includes wirings H83A1, H83A2, H83B, H83D1, H83D2, H83E1, H83E2, H83G1, H83G2, H83H, H83I, and H83J. The wirings H83A1 and H83A2 are used to transmit the selection signals SELA and SELB, respectively. The wiring H83B is used to supply the power supply voltage VDD. The wirings H83D1 and H83D2 are used to transmit the transfer signals TGLA and TGLB, respectively. The wirings H83E1 and H83E2 are used to transmit the switching signals FDGA and FDGB, respectively. The lines H83G1 and H83G2 are used to transmit overflow control voltages OFGA and OFGB, the lines H83H and H83J are used to transmit a capacitance reset signal FCR, and the line H83I is used to transmit a reset signal SEL.

[0249] 53, a fourth wiring layer H84 is formed on the third wiring layer H83. The fourth wiring layer H84 is connected between layers via a contact CN84. The fourth wiring layer H84 includes wirings H84A to H84E. The wirings H84A to H84D are used for the lower electrodes of the capacitors 526A to 526D, respectively. The wiring H84E is used to transmit a capacitance reset signal FCR.

[0250] 54, a fifth wiring layer H85 is formed on the fourth wiring layer H84. The fifth wiring layer H85 is used for the upper electrodes of each of the capacitors 526A to 526D. The fifth wiring layer H85 can be extended in the row direction. In this case, the upper electrodes of each of the capacitors 526A to 526D can also be used as voltage control lines that supply the control voltage MVDD.

[0251] In this way, in the above-described eighth embodiment, the capacitors 526A to 526D are provided in the pixels 820A to 820D adjacent in the column direction and the row direction, respectively, and share the reset transistor 523 and the capacitance reset transistor 529. This makes it possible to reduce the number of control lines used to switch the conversion efficiency while expanding the dynamic range, and also makes it possible to effectively utilize the empty space of each of the pixels 820A to 820D while ensuring symmetry in the layout of each of the pixels 820A to 820D.

[0252] 9. Ninth Embodiment In the fifth embodiment described above, the capacitors 526A to 526D are provided in the pixels 520A to 520D adjacent in the column direction and the row direction, respectively, and share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531. In this ninth embodiment, the capacitors 526A to 526D are provided in four pixels adjacent in the column direction and the row direction, respectively, and share the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531, and each pixel is provided with a plurality of photodiodes.

[0253] FIG. 55 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the ninth embodiment.

[0254] In the figure, this imaging device includes pixels 920A to 920D instead of the pixels 520A to 520D of the fifth embodiment described above. The pixels 920A to 920D are arranged adjacent to each other in the row and column directions.

[0255] Each of the pixels 920A to 920D is obtained by adding a photodiode PD9A to PD9D to the pixels 520A to 520D of the fifth embodiment described above. The cathodes of the photodiodes PD9A to PD9D are connected to capacitors 526A to 526D, respectively. The sensitivity of the photodiodes PD9A to PD9D can be made smaller than the sensitivity of the photodiodes PD5A to PD5D. In this case, the planar size of the photodiodes PD9A to PD9D may be smaller than the planar size of the photodiodes PD5A to PD5D.

[0256] Furthermore, the pixels 920A to 920D are the same as the pixels 520A to 520D of the fifth embodiment except that the overflow control transistors 530A to 530D are removed from the pixels 520A to 520D of the fifth embodiment. The remaining configuration of the pixels 920A to 920D of the ninth embodiment is the same as the configuration of the pixels 520A to 520D of the fifth embodiment.

[0257] FIG. 56 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the ninth embodiment.

[0258] In the figure, a shutter period and an accumulation period are provided before the readout operation of each frame. A control voltage MVDD is applied to the upper electrode of each of the capacitors 526A to 526D, and during the accumulation period, the upper electrode of each of the capacitors 526A to 526D is set to a low level. By setting the control voltage MVDD to a low level during the accumulation period, the dark current of each of the capacitors 526A to 526D can be reduced. During the shutter period, the control voltage MVDD may be set to a low level or a high level.

[0259] During the readout period, in a high-sensitivity, low-efficiency P-phase single-unit readout period K91, the reset signal RST, the selection signals SELA and SELB, and the control voltage MVDD rise, followed by the switching signals FDGA and FDGB. At this time, the control voltage MVDD is set to a high level, and the upper electrodes of the capacitors 526A to 526D are set to a high level. Furthermore, the reset transistor 523 turns on, and the switching transistors 528A to 528D turn on row by row, discharging the charge from the floating diffusions FD5A to FD5D and reducing the conversion efficiency of the amplification transistors 524A to 524D. After the charge from the floating diffusions FD5A to FD5B is discharged, the reset signal RST falls, and the reset transistor 523 turns off.

[0260] Furthermore, when the selection transistors 525A to 525D are turned on for each row and the reset transistor 523 is turned off, the potential of each vertical signal line 132A, 132B is set for each row based on the source follower operation when the high-sensitivity, low-efficiency P-phase level of each floating diffusion FD5A to FD5D is applied to the gate of each amplification transistor 524A to 524D. Then, based on the potential of each vertical signal line 132A, 132B for each row at that time, the high-sensitivity, low-efficiency P-phase level of each pixel 920A to 920D is AD converted for each row.

[0261] Next, during a high-sensitivity, high-efficiency P-phase single readout period K92, the switching signals FDGA and FDGB fall. At this time, the switching transistors 528A to 528D are turned off, increasing the conversion efficiency of the amplification transistors 524A to 524D. The potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-sensitivity, high-efficiency P-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. The high-sensitivity, high-efficiency P-phase levels of the pixels 920A to 920D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0262] Next, during a high-sensitivity, high-efficiency D-phase individual readout period K93, the transfer signals TGLA and TGLB rise. At this time, the transfer transistors 522A to 522D turn on, and the charges stored in the photodiodes PD5A to PD5D are transferred to the floating diffusions FD5A to FD5D. Then, the transfer signals TGLA and TGLB fall. At this time, the transfer transistors 522A to 522D turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-sensitivity, high-efficiency D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, the high-sensitivity, high-efficiency D-phase levels of the pixels 520A to 920D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at this time.

[0263] Next, during the high-sensitivity, low-efficiency D-phase single read period K94, the switching signals FDGA and FDGB rise. At this time, the switching transistors 528A to 528D turn on, reducing the conversion efficiency of the amplification transistors 524A to 524D. The transfer signals TGLA and TGLB also rise. At this time, the transfer transistors 522A to 522D turn on, transferring the charges stored in the photodiodes PD5A to PD5D to the floating diffusions FD5A to FD5D. The transfer signals TGLA and TGLB then fall. At this time, the transfer transistors 522A to 522D turn off, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the high-sensitivity, low-efficiency D-phase levels of the floating diffusions FD5A to FD5D are applied to the gates of the amplification transistors 524A to 524D. Then, based on the potentials of the vertical signal lines 132A and 132B at that time, the high-sensitivity, low-efficiency D-phase levels of the pixels 920A to 920D are AD-converted. Next, the reset signal RST rises, turning on the reset transistor 523. At this time, the charges in the floating diffusions FD5A and FD5B are discharged.

[0264] CDS reading can be performed in the high-sensitivity, low-efficiency P-phase single read period K91, the high-sensitivity, high-efficiency P-phase single read period K92, the high-sensitivity, high-efficiency D-phase single read period K93, and the high-sensitivity, low-efficiency D-phase single read period K94.

[0265] Next, during a low-sensitivity, low-efficiency D-phase single readout period K95, the reset signal RST falls, turning off the reset transistor 523. Then, the path setting signals FCGA and FCGB and the switching signal CNG rise. At this time, the path transistors 527A to 527D and the switching transistor 531 turn on, and the potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the low-sensitivity, low-efficiency D-phase levels of the floating diffusions FD5A to FD5D, FD6A to FD6D, and FD7A to FD7D are applied to the gates of the amplification transistors 524A to 524D. Then, the low-sensitivity, low-efficiency D-phase levels of each pixel 920A to 920D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0266] Next, in a low-sensitivity, high-efficiency D-phase individual readout period K96, the switching signal CNG falls, turning off the switching transistor 531. At this time, the floating diffusions FD6A and FD6B and the floating diffusions FD6C and FD6D are separated from each other, reducing the conversion efficiency of each of the pixels 520A to 520D. The potential of the vertical signal line 132A is set based on the source-follower operation when the low-sensitivity, high-efficiency D-phase levels of the floating diffusions FD5A, FD5B, FD6A, FD6B, FD7A, and FD7B are applied to the gates of the amplification transistors 524A and 524B. Furthermore, the potential of the vertical signal line 132A is set based on the source follower operation when the low-sensitivity, high-efficiency D-phase levels of the floating diffusions FD5C, FD5D, FDCA, FD6D, FDCA, and FD7D are applied to the gates of the amplification transistors 524C and 524D. Then, based on the potentials of the vertical signal lines 132A and 132B at that time, the low-sensitivity, low-efficiency D-phase levels of the pixels 920A to 920D are AD-converted.

[0267] Next, during the low-sensitivity, high-efficiency P-phase single-unit readout period K97, the selection signals SELA and SELB fall, and the capacitance reset signal FCR and reset signal RST rise. At this time, the selection transistors 525A to 525D turn off, and the reset transistor 523 turns on, discharging the charge from the floating diffusions FD5A to FD5D. The capacitance reset transistor 529 also turns on, supplying the power supply voltage VDD to the upper electrodes of the capacitors 526A to 526D. This allows power to be supplied from the power supply voltage VDD to the upper electrodes of the capacitors 526A to 526D, shortening the power supply path to the upper electrodes of the capacitors 526A to 526D. This eliminates insufficient settling during reset and reduces degradation of image quality, such as horizontal streaks.

[0268] Then, the path setting signals FCGA and FCGB fall, turning off the path transistors 527A to 527D, and then the selection signals SELA and SELB rise, turning on the selection transistors 525A to 525D. Then, the capacitance reset signal FCR and the reset signal RST fall, turning off the capacitance reset transistor 529 and the reset transistor 523, and then the path setting signals FCGA and FCGB rise, turning on the path transistors 527A to 527D. At this time, the potential of the vertical signal line 132A is set based on the source follower operation when the low-sensitivity, high-efficiency D-phase levels of the floating diffusions FD5A, FD5B, FD6A, FD6B, FD7A, and FD7B are applied to the gates of the amplification transistors 524A and 524B. Furthermore, the potential of the vertical signal line 132A is set based on the source follower operation when the low-sensitivity, high-efficiency D-phase levels of the floating diffusions FD5C, FD5D, FDCA, FD6D, FDCA, and FD7D are applied to the gates of the amplification transistors 524C and 524D. Then, based on the potentials of the vertical signal lines 132A and 132B at that time, the low-sensitivity, high-efficiency D-phase levels of the pixels 920A to 920D are AD-converted.

[0269] Next, in a low-sensitivity, low-efficiency P-phase single readout period K98, the switching signal CNG rises, turning on the switching transistor 531. The potentials of the vertical signal lines 132A and 132B are set based on the source-follower operation when the low-sensitivity, low-efficiency D-phase levels of the floating diffusions FD5A to FD5D, FD6A to FD6D, and FD7A to FD7D are applied to the gates of the amplification transistors 524A to 524D. The low-sensitivity, low-efficiency P-phase levels of each of the pixels 920A to 920D are AD-converted based on the potentials of the vertical signal lines 132A and 132B at that time.

[0270] Next, in the DOL period K99, the switching signal CNG falls, turning off the switching transistor 531. Also, the path setting signals FCGA and FCGB fall, turning off the path transistors 527A to 527D, and then the selection signals SELA and SELB fall, turning off the selection transistors 525A to 525D. At this time, during the DOL period K57, the accumulation time for each frame is minimized, and the brightest scene is captured in a time-division manner. The DOL period K99 may be omitted.

[0271] In this way, in the ninth embodiment described above, the capacitors 526A to 526D are provided in the pixels 920A to 920D adjacent in the column direction and the row direction, and the reset transistor 523, the capacitance reset transistor 529, and the switching transistor 531 are shared, and photodiodes with different sensitivities are provided in each of the pixels 920A to 920D. This makes it possible to expand the dynamic range while suppressing an increase in layout area, and also to eliminate insufficient settling during resetting, thereby reducing degradation of image quality such as horizontal stripes.

[0272] 10. Tenth Embodiment In the first embodiment described above, capacitors 126A and 126B are provided in pixels 120A and 120B adjacent to each other in the column direction, and the pixels share the reset transistor 123 and the capacitance reset transistor 129. In this tenth embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0273] FIG. 57 is a perspective view showing an example of lamination of a pixel array unit according to the tenth embodiment.

[0274] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0275] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be the pixels 120A and 120B of the first embodiment described above, the pixels 220A and 220B of the second embodiment described above, the pixels 320A and 320B of the third embodiment described above, or the pixels 420A and 420B of the fourth embodiment described above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0276] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and a control circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0277] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0278] As described above, in the tenth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0279] 11. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0280] FIG. 58 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0281] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 58, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0282] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0283] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0284] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0285] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0286] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0287] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0288] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0289] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0290] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 58, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0291] FIG. 59 is a diagram showing an example of the installation position of the imaging unit 12031.

[0292] In FIG. 59, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0293] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0294] 59 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0295] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0296] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0297] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0298] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0299] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to suppress an increase in layout area while eliminating insufficient settling during reset, and to reduce degradation of image quality such as horizontal streaks.

[0300] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0301] Note that the present technology may also have the following configuration: (1) An imaging device comprising: a first pixel circuit having a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; and a second pixel circuit having a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit, wherein one of the first pixel circuit and the second pixel circuit comprises a reset transistor that resets the first floating diffusion and the second floating diffusion, and the other of the first pixel circuit and the second pixel circuit comprises a capacitance reset transistor that resets the first capacitor and the second capacitor. (2) The imaging device according to (1), comprising: a voltage control line that transmits a control voltage that pulse-drives the first capacitor and the second capacitor; and a power supply line that applies a power supply voltage to the capacitance reset transistor. (3) The imaging device according to (1) or (2), wherein the first photoelectric conversion unit and the second photoelectric conversion unit each include a plurality of photoelectric conversion units having different sensitivities. (4) The imaging device according to any one of (1) to (3), comprising a pixel array unit in which pixels are arranged in a matrix in a row direction and a column direction, wherein the pixels include: a first pixel to which the first pixel circuit is assigned; and a second pixel to which the second pixel circuit is assigned. (5) The imaging device according to (4), wherein the first pixel and the second pixel are arranged adjacent to each other in the column direction. (6) The imaging device according to (4), wherein the first pixel and the second pixel are arranged adjacent to each other in the row direction. (7) The imaging device according to any one of (4) to (6), wherein the voltage control line is wired in the row direction. (8) The imaging device according to any one of (4) to (7), wherein the control voltage is set to a high level during a read period of the pixel and set to a low level during an accumulation period of the pixel. (9) The imaging device according to any one of (4) to (8), wherein the layout of the transistors of the first pixel circuit and the layout of the transistors of the second pixel circuit are the same.(10) The imaging device according to (9), wherein a position of the reset transistor in a layout of one of the first pixel circuit and the second pixel circuit is equal to a position of the capacitance reset transistor in a layout of the other of the first pixel circuit and the second pixel circuit. (11) The imaging device according to any one of (4) to (10), wherein upper electrodes of the first capacitor and the second capacitor extend in the row direction and are also used as the voltage control line. (12) A pixel circuit including a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; a second pixel circuit including a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit; a third pixel circuit including a third photoelectric conversion unit, a third floating diffusion connected to the third photoelectric conversion unit, and a third capacitor connected to the third photoelectric conversion unit; and a fourth pixel circuit including a fourth photoelectric conversion unit, a fourth floating diffusion connected to the fourth photoelectric conversion unit, and a fourth capacitor connected to the fourth photoelectric conversion unit, wherein at most three of the first pixel circuit to the fourth pixel circuit include reset transistors that reset the first floating diffusion to the fourth floating diffusion, (13) The imaging device according to (12), wherein one of the first pixel circuit to the fourth pixel circuit includes a capacitance reset transistor that resets the first capacitor to the fourth capacitor. At least two of the first pixel circuit to the fourth pixel circuit include a switching transistor that can switch a connection from the first floating diffusion to the fourth floating diffusion, and the switching transistor is disposed in an empty space in a layout position of the first pixel circuit to the fourth pixel circuit after the reset transistor has been removed.(14) The imaging device according to (12) or (13), comprising: a voltage control line that transmits a control voltage for pulse-driving the first capacitor to the fourth capacitor; and a power supply line that applies a power supply voltage to the capacitance reset transistor. (15) The imaging device according to any of (12) to (14), wherein the first to fourth photoelectric conversion units each comprise a plurality of photoelectric conversion units having different sensitivities from one another. (16) The imaging device according to any of (12) to (15), comprising: a pixel array unit in which pixels are arranged in a matrix in row and column directions, the pixels comprising: a first pixel to which the first pixel circuit is assigned, a second pixel to which the second pixel circuit is assigned, a third pixel to which the third pixel circuit is assigned, and a fourth pixel to which the fourth pixel circuit is assigned. (17) The imaging device according to (16), wherein the first to fourth pixels are arranged adjacent to one another in the column and row directions. (18) The imaging device according to (16) or (17), wherein the voltage control line is wired in the row direction. (19) The imaging device according to any of (1) to (18), wherein the first pixel and the second pixel are arranged adjacent to each other in the column direction, the third pixel and the fourth pixel are arranged adjacent to each other in the column direction, the first pixel and the third pixel are arranged adjacent to each other in the row direction, the second pixel and the fourth pixel are arranged adjacent to each other in the row direction, a layout of transistors of the first pixel and a layout of transistors of the second pixel are arranged line-symmetrically with respect to the row direction, a layout of transistors of the third pixel and a layout of transistors of the fourth pixel are arranged line-symmetrically with respect to the row direction, a layout of transistors of the first pixel and a layout of transistors of the third pixel are arranged line-symmetrically with respect to the column direction, and a layout of transistors of the second pixel and a layout of transistors of the fourth pixel are arranged line-symmetrically with respect to the column direction.(20) The imaging device described in (19), wherein the position of the reset transistor in the layout of one of the first pixel circuit to the fourth pixel circuit is equal to the position of the capacitance reset transistor in the layout of one of the first pixel circuit to the fourth pixel circuit.

[0302] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 120A, 120B Pixel PD1A, PD1B Photodiode 122A, 122B Transfer transistor 123 Reset transistor 124A, 124B Amplification transistor 125A, 125B Selection transistor 126A, 126B Capacitor 127A, 127B Pass transistor 128A, 128B Switching transistor 129 Capacitor reset transistor 131 Horizontal drive line 132A, 132B Vertical signal line

Claims

1. An imaging device comprising: a first pixel circuit having a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; and a second pixel circuit having a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit, wherein one of the first pixel circuit and the second pixel circuit comprises a reset transistor that resets the first floating diffusion and the second floating diffusion, and the other of the first pixel circuit and the second pixel circuit comprises a capacitance reset transistor that resets the first capacitor and the second capacitor.

2. The imaging device according to claim 1, further comprising: a voltage control line for transmitting a control voltage for pulse-driving the first capacitor and the second capacitor; and a power supply line for applying a power supply voltage to the capacitance reset transistor.

3. The imaging device according to claim 1, wherein the first photoelectric conversion unit and the second photoelectric conversion unit each include a plurality of photoelectric conversion units having different sensitivities.

4. An imaging device according to claim 2, comprising a pixel array section in which pixels are arranged in a matrix in the row and column directions, the pixels comprising: first pixels to which the first pixel circuits are assigned; and second pixels to which the second pixel circuits are assigned.

5. The imaging device according to claim 4, wherein the first pixel and the second pixel are arranged adjacent to each other in the column direction.

6. The imaging device according to claim 4, wherein the first pixel and the second pixel are arranged adjacent to each other in the row direction.

7. The imaging device according to claim 4, wherein the voltage control lines are wired in the row direction.

8. The imaging device according to claim 4, wherein the control voltage is set to a high level during a read period of the pixel, and is set to a low level during an accumulation period of the pixel.

9. The imaging device according to claim 4, wherein the layout of the transistors of the first pixel circuit and the layout of the transistors of the second pixel circuit are the same.

10. The imaging device according to claim 9, wherein the position of the reset transistor in the layout of one of the first pixel circuit and the second pixel circuit is equal to the position of the capacitance reset transistor in the layout of the other of the first pixel circuit and the second pixel circuit.

11. The imaging device according to claim 4, wherein the upper electrodes of the first capacitor and the second capacitor extend in the row direction and also serve as the voltage control lines.

12. A pixel circuit including a first photoelectric conversion unit, a first floating diffusion connected to the first photoelectric conversion unit, and a first capacitor connected to the first photoelectric conversion unit; a second pixel circuit including a second photoelectric conversion unit, a second floating diffusion connected to the second photoelectric conversion unit, and a second capacitor connected to the second photoelectric conversion unit; a third pixel circuit including a third photoelectric conversion unit, a third floating diffusion connected to the third photoelectric conversion unit, and a third capacitor connected to the third photoelectric conversion unit; and a fourth pixel circuit including a fourth photoelectric conversion unit, a fourth floating diffusion connected to the fourth photoelectric conversion unit, and a fourth capacitor connected to the fourth photoelectric conversion unit, wherein at most three of the first pixel circuit to the fourth pixel circuit include reset transistors that reset the first floating diffusion to the fourth floating diffusion, An imaging device, wherein one of the first pixel circuit to the fourth pixel circuit includes a capacitance reset transistor that resets the first capacitor to the fourth capacitor.

13. The imaging device according to claim 12, wherein at least two of the first pixel circuit to the fourth pixel circuit are provided with a switching transistor capable of switching the connection from the first floating diffusion to the fourth floating diffusion, and the switching transistor is arranged in an empty space in the layout positions of the first pixel circuit to the fourth pixel circuit from which the reset transistor has been removed.

14. The imaging device according to claim 12, further comprising: a voltage control line for transmitting a control voltage for pulse-driving the first capacitor to the fourth capacitor; and a power supply line for applying a power supply voltage to the capacitance reset transistor.

15. The imaging device according to claim 12, wherein the first to fourth photoelectric conversion units each include a plurality of photoelectric conversion units having different sensitivities.

16. An imaging device as described in claim 12, comprising a pixel array section in which pixels are arranged in a matrix in the row and column directions, the pixels comprising: a first pixel to which the first pixel circuit is assigned, a second pixel to which the second pixel circuit is assigned, a third pixel to which the third pixel circuit is assigned, and a fourth pixel to which the fourth pixel circuit is assigned.

17. The imaging device according to claim 16, wherein the first pixel to the fourth pixel are arranged adjacent to each other in the column direction and the row direction.

18. The imaging device according to claim 16, wherein the voltage control lines are wired in the row direction.

19. The imaging device of claim 16, wherein the first pixel and the second pixel are arranged adjacent to each other in the column direction, the third pixel and the fourth pixel are arranged adjacent to each other in the column direction, the first pixel and the third pixel are arranged adjacent to each other in the row direction, the second pixel and the fourth pixel are arranged adjacent to each other in the row direction, a layout of the transistors of the first pixel and a layout of the transistors of the second pixel are arranged line-symmetrically with respect to the row direction, a layout of the transistors of the third pixel and a layout of the transistors of the fourth pixel are arranged line-symmetrically with respect to the row direction, a layout of the transistors of the first pixel and a layout of the transistors of the third pixel are arranged line-symmetrically with respect to the column direction, and a layout of the transistors of the second pixel and a layout of the transistors of the fourth pixel are arranged line-symmetrically with respect to the column direction.

20. The imaging device according to claim 19, wherein the position of the reset transistor in the layout of one of the first pixel circuit to the fourth pixel circuit is equal to the position of the capacitance reset transistor in the layout of one of the first pixel circuit to the fourth pixel circuit.

Images