Wiring board

Abstract

This wiring board includes a build-up part which is a plurality of conductor layers and a plurality of insulating layers and which has a via conductor for interlayer connection of the plurality of conductor layers, and an optical waveguide (OPW). The build-up part is made of a first build-up part (10), a second build-up part (20), and a third build-up part (30). The first build-up part (10) includes a plurality of conductor layers (12) and insulating layers (11). The second build-up part (20) includes a plurality of conductor layers (22) and insulating layers (21). The third build-up part (30) includes a plurality of conductor layers (32) and insulating layers (31). The optical waveguide (OPW) is formed on a first surface (10F) of the first build-up part (10). The thickness (T1) of the first insulating layers, the thickness (T2) of the second insulating layers, and the thickness (T3) of the third insulating layers satisfy the relationship T1 ≠ T2 ≠ T3, and the second insulating layers (21) or the insulating layers (31) contain a core material.

Description

wiring board

[0001] The present invention relates to a wiring board.

[0002] Patent Document 1 discloses an optical-electrical hybrid circuit board. The optical-electrical hybrid circuit board has a base substrate portion, a micro-wiring circuit portion, and an optical wiring circuit portion. It also discloses that the optical wiring circuit portion includes an optical waveguide and a pair of optical elements.

[0003] Japanese Patent Application Laid-Open No. 2004-146602

[0004] In the optical-electrical hybrid circuit board disclosed in Patent Document 1, a fine wiring circuit section is formed on a base substrate section, and an optical wiring circuit section is disposed on the fine wiring circuit section. The fine wiring circuit section is formed by stacking unit wiring layers each consisting of an insulating resin layer and a fine wiring layer. The base substrate section is formed as a build-up wiring substrate. If warping occurs in the base substrate, distortion may also occur in the optical wiring circuit section on the fine wiring circuit section due to the influence of the warping of the base substrate. As a result, it is thought that coupling loss may be caused in the optical coupling between the optical waveguide and the optical element.

[0005] The wiring board of the present invention includes a buildup section having a plurality of conductor layers and a plurality of insulating layers and having via conductors for interlayer connection between the plurality of conductor layers, and an optical waveguide disposed on the buildup section. The buildup section includes a first buildup section, a second buildup section, and a third buildup section, the first buildup section including a plurality of first conductor layers and a plurality of first insulating layers and having a first surface and a second surface opposite to the first surface, the second buildup section including a plurality of second conductor layers and a plurality of second insulating layers and having a first surface and a second surface opposite to the first surface, and is formed on the second surface side of the first buildup section, the second conductor layers and the first conductor layers are electrically connected, and the third buildup section includes a third buildup section. The second buildup section includes a plurality of third conductor layers and a plurality of third insulating layers, has a first surface and a second surface opposite to the first surface, is formed on the second surface side of the second buildup section, the third conductor layers and the second conductor layers are electrically connected, the optical waveguide is formed on the first surface of the first buildup section, a thickness (T1) of the first insulating layer, a thickness (T2) of the second insulating layer, and a thickness (T3) of the third insulating layer satisfy the following formula (1), and the second insulating layer or the third insulating layer includes a core material: T1 ≠ T2 ≠ T3 (1)

[0006] 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention; 2 is a view showing an example of a manufacturing method for a wiring board according to an embodiment of the present invention; 3 is a view showing an example of a manufacturing method for a wiring board according to an embodiment of the present invention; 4 is a view showing an example of a manufacturing method for a wiring board according to an embodiment of the present invention; 5 is a view showing an example of a manufacturing method for a wiring board according to an embodiment of the present invention; 6 is a view showing an example of a manufacturing method for a wiring board according to an embodiment of the present invention;

[0007] A wiring board according to one embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 1, which is an example of a wiring board according to one embodiment. Note that the wiring board 1 is merely an example of a wiring board according to this embodiment. The number of conductor layers and the number of insulating layers of the wiring board according to this embodiment are not limited to the number of conductor layers and the number of insulating layers included in the wiring board 1 shown in FIG. 1 . Furthermore, the drawings referred to are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0008] The wiring board 1 of the embodiment has a buildup section composed of multiple conductor layers and multiple insulating layers. The buildup section has via conductors that connect the multiple conductor layers to each other. An optical waveguide is disposed on the buildup section. The buildup section has a layered structure including a first buildup section 10, a second buildup section 20, and a third buildup section 30. The first buildup section 10 is composed of multiple conductor layers that are alternately stacked and via conductors that connect the multiple insulating layers to each other. The second buildup section 20 is composed of multiple conductor layers that are alternately stacked and via conductors that connect the multiple insulating layers to each other. The third buildup section 30 is composed of multiple conductor layers that are alternately stacked and via conductors that connect the multiple insulating layers to each other. The vial section that constitutes the wiring board 1 has two surfaces that are perpendicular to its thickness direction. The wiring board 1 has one surface 1F and another surface 1B opposite to the one surface 1F. An optical waveguide OPW is disposed on the upper side of one surface 1F of the wiring board 1 .

[0009] The first buildup section 10 has a first surface 10F and a second surface 10B opposite the first surface 10F. The second buildup section 20 has a first surface 20F and a second surface 20B opposite the first surface 20F. The third buildup section 30 has a first surface 30F and a second surface 30B opposite the first surface 30F. As shown in FIG. 1 , the first surface 10F of the first buildup section 10 constitutes one surface 1F. The other surface 1B is constituted by the second surface 30B of the third buildup section 30.

[0010] 1 , the second buildup section 20 is disposed below the first buildup section 10 (toward the second surface 10B), and the first surface 20F of the second buildup section 20 is formed to face the second surface 10B of the first buildup section 10. The third buildup section 30 is disposed below the second buildup section 20 (toward the second surface 20B), and the first surface 30F of the third buildup section 30 is formed to face the second surface 20B of the second buildup section 20.

[0011] 1, the first surface 10F of the first buildup portion 10, i.e., the one surface 1F side, will be referred to as the "top" or "upper side," and the other surface 1B side will be referred to as the "bottom" or "lower side." In addition, for each component, the surface facing the one surface 1F side of the wiring board 1 will also be referred to as the "top surface," and the surface facing the other surface 1B side of the wiring board 1 will also be referred to as the "bottom surface."

[0012] 1 , the first buildup section 10 includes five first insulating layers 11 and six first conductor layers 12, the second buildup section 20 includes four second insulating layers 21 and four second conductor layers 22, and the third buildup section 30 includes two third insulating layers 31 and two third conductor layers 32. The first conductor layers 12 of the first buildup section 10 and the second conductor layers 22 of the second buildup section 20 are electrically connected, and the second conductor layers 22 of the second buildup section 20 and the third conductor layers 32 of the third buildup section 30 are electrically connected. Note that the illustrated numbers of insulating layers and conductor layers are merely examples, and the numbers of insulating layers and conductor layers are not limited.

[0013] In the example of FIG. 1 , conductor layers 12 and 12 located opposite each other across one insulating layer 11 in the first buildup section 10 are connected to each other by via conductors (first via conductors) 13. The conductor layer 12 on the bottom side of the first buildup section 10 and the conductor layer 22 on the top side of the second buildup section 20 are connected to each other by via conductors (second via conductors) 23. The conductor layers 22 and 22 located opposite each other across one insulating layer 21 in the second buildup section 20 are connected to each other by via conductors (second via conductors) 23. The conductor layer 22 on the bottom side of the second buildup section 20 and the conductor layer 32 on the top side of the third buildup section 20 are connected to each other by via conductors (third via conductors) 33. The conductor layers 32 and 32 located opposite each other across one insulating layer 31 in the third buildup section 30 are connected to each other by via conductors (third via conductors) 33.

[0014] The first surface 10F of the first buildup section 10 is formed by the upper surfaces of the first insulating layer 11 and conductor layer 12, which are the uppermost layers in the first buildup section 10. The second surface 10B of the first buildup section 10 is formed by the lower surface of the insulating layer 11, which is the lowermost layer in the first buildup section 10, and the surface of the conductor layer 12. The first surface 20F of the second buildup section 20 is formed by the surface of the second insulating layer 21, which is the uppermost layer in the second buildup section 20, and the upper surfaces of the second via conductors 23. The second surface 20B of the second buildup section 20 is formed by the lower surface of the insulating layer 21, which is the lowermost layer in the second buildup section 20, and the surface of the conductor layer 22. The first surface 30F of the third buildup section 30 is formed by the surface of the third insulating layer 31, which is the uppermost layer in the third buildup section 30, and the upper surfaces of the third via conductors 33. The second surface 30B of the third buildup section 30 is composed of the lower surface of the insulating layer 31 and the surface of the conductor layer 32 on the lowest layer side of the third buildup section 30 .

[0015] Each conductor layer 12, 22, and 32 is patterned to have a predetermined conductor pattern. In the example of FIG. 1 , the conductor layer 12 constituting the first surface 10F is formed into a pattern having a plurality of conductor pads (component mounting pads) 12p. The component mounting pads 12p are formed on the outermost surface of the wiring substrate 1. A conductive bonding material, such as solder or a conductive post, is disposed on the component mounting pads 12p. The component mounting pads 12p on which the conductive bonding material is formed can be connected to the connection pads of external electronic components. As an example, the component mounting pads 12p can be electrically and mechanically connected to an optical element OPD, which is an external electronic component. A metal layer, such as a plating layer (not shown) including a nickel layer and a tin layer, can be formed on the upper surface of the component mounting pads 12p.

[0016] In the example of FIG. 1 , a solder resist layer SR1 is formed on one surface 1F of the wiring board 1. A solder resist layer SR2 is formed on the other surface 1B of the wiring board 1. The solder resist layers SR1 and SR2 are formed using a thermosetting resin or a photocurable resin, such as a photosensitive polyimide resin or an epoxy resin. An opening SR1a is formed in the solder resist layer SR1, and component mounting pads 12p included in the conductor layer 12 constituting the first surface 10F are exposed through the opening SR1a. An opening SR2a is formed in the solder resist layer SR2, and conductor pads 32p included in the conductor layer 32 constituting the second surface 30F are exposed through the opening SR2a. The conductor pads 32p included in the conductor layer 32 constituting the other surface 1B of the wiring board 1 can be connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board. The external wiring board may be, for example, a motherboard for an electrical device.

[0017] 1, the optical waveguide OPW is disposed on the solder resist layer SR1 on the first surface 10F of the first buildup section 10. The optical waveguide OPW is formed by a lower clad C1, a core C2, and an upper clad C3. The core C2 is disposed between the upper clad C3 and the lower clad C1. The lower clad C1 is disposed on the side of the optical waveguide OPW facing the solder resist layer SR1, and the upper clad C3 is disposed on the side of the core C2 opposite the lower clad C1.

[0018] The optical waveguide OPW has two opposing ends. For convenience of explanation, the two opposing ends of the optical waveguide OPW are referred to as one end E1 and the other end E2. An optical signal is incident on the one end E1 or the other end E2 of the optical waveguide OPW, and the optical signal is output from the other end E2 or the one end E1. When an optical signal is incident on the one end E1, the optical signal is output from the other end E2. When an optical signal is incident on the other end E2, the optical signal is output from the one end E1. When the optical waveguide OPW is in use, the core C2 is optically coupled at the one end E1 and the other end E2 to optical components such as a photoelectric conversion component, such as a semiconductor device including a photoelectric conversion element, and / or a connector member, such as an optical fiber or an optical connector, that connects the waveguide to the outside. The optical waveguide OPW in the illustrated example has an upper cladding-free region A1 on one end E1 side and an upper cladding-formed region A2 on the other end E2 side. The core C2 has an exposed portion C2a exposing its upper surface to the upper cladding-free region A1.

[0019] When the wiring board 1 is used, a component OPD can be mounted on the first buildup section 10. The component OPD is an optical component including a photoelectric conversion element. Examples of the component OPD include a light-receiving element such as a photodiode, and a light-emitting element such as a light-emitting diode (LED), an organic light-emitting diode (OLED), a laser diode (LD), and a vertical-cavity surface-emitting laser (VCSEL). The component OPD includes a light-receiving or light-emitting portion OPDa and an electrode OPDb. When the component OPD is a light-emitting element, the component OPD generates an optical signal based on an electrical signal input to the electrode OPDb, and emits the optical signal from the light-receiving or light-emitting portion OPDa, which functions as a light-emitting portion, toward the core C2. When the component OPD is a light-receiving element, an electrical signal based on an optical signal input from the light-receiving or light-emitting portion OPDa, which functions as a light-receiving portion, is generated and output from the electrode OPDb. The component OPD is connected to the first buildup section 10 by connecting the electrode OPDb to the component mounting pad 12p. In the illustrated example, the component OPD is flip-chip mounted, and the light receiving or emitting portion OPDa and the exposed portion C2a of the core C2 of the optical waveguide OPW are positioned to face each other and are optically coupled.

[0020] The core C2 and clads C1 and C3 constituting the optical waveguide OPW can be formed of any light-transmitting material. The optical waveguide OPW can be formed of, for example, an organic material, an inorganic material, or a hybrid material containing an organic material and an inorganic material, such as an inorganic polymer. Examples of organic materials include acrylic resins such as polymethyl methacrylate (PMMA), polyimide resins, polyamide resins, polyether resins, and epoxy resins. Examples of inorganic materials include quartz glass and silicon.

[0021] The first insulating layer 11 of the first buildup section 10 can be formed using an insulating resin such as an epoxy resin or a phenolic resin. The insulating layer 11 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). The insulating layer 21 constituting the second buildup section 20 and the insulating layer 31 constituting the third buildup section 30 can be formed using an insulating resin similar to the insulating layer 11. The insulating layers 11, 21, and 31 within each buildup section may contain the same insulating resin or different insulating resins.

[0022] The thickness of the first insulating layer 11 in the first buildup section 10, the thickness of the second insulating layer 21 in the second buildup section 20, and the thickness of the third insulating layer 31 in the third buildup section 30 are all different. If the thickness of the first insulating layer 11 in the first buildup section 10 is defined as T1, the thickness of the second insulating layer 21 in the second buildup section 20 is defined as T2, and the thickness of the third insulating layer 31 in the third buildup section 30 is defined as T3, then the relationship T1 ≠ T2 ≠ T3 holds. Furthermore, it is desirable to make the thickness T1 of the first insulating layer 11 in the first buildup section 10 smaller than the thickness T2 of the second insulating layer 21 in the second buildup section 20, in which case the relationship T1 < T2 holds. It is desirable to make the thickness T1 of the first insulating layer 11 in the first buildup section 10 smaller than the thickness T3 of the third insulating layer 31 in the third buildup section 30, in which case the relationship T1 < T3 holds. It is desirable to make the thickness T2 of the second insulating layer 21 of the second buildup section 20 smaller than the thickness T3 of the third insulating layer 31 of the third buildup section 30, so that the relationship T2<T3 is satisfied. As a result, it is desirable for the thickness T1 of the first insulating layer 11 of the first buildup section 10, the thickness T2 of the second insulating layer 21 of the second buildup section 20, and the thickness T3 of the third insulating layer 31 of the third buildup section 30 to satisfy the relationship T1<T2<T3. By satisfying the relationship T1<T2<T3, warping of the wiring board is suppressed. As a result, the effects of warping in the first insulating layer 11 are suppressed, warping in the optical waveguide OPW is suppressed, and coupling loss is less likely to occur in the optical coupling between the optical waveguide OPW and the optical element. In the first buildup section 10, the thickness T1 of the insulating layer 11 is not limited, but is, for example, approximately 7 to 15 μm. In the second buildup section 20, the thickness T2 of the insulating layer 21 is not limited, but is, for example, about 15 to 50 μm. In the third buildup section 30, the thickness T3 of the insulating layer 31 is not limited, but is, for example, about 30 to 100 μm.

[0023] 1 , of the insulating layers 11, 21, and 31, the insulating layers 11 and 21 do not contain a core material, but the insulating layer 31 does contain a core material. In the wiring board of the embodiment, the insulating resin in the insulating layer 21 or the insulating layer 31 contains a core material. Examples of the core material include a reinforcing material made of glass fiber or aramid fiber. As will be described later, when the first buildup section 10 is a fine wiring, it may be preferable that the insulating layer 11 does not contain a reinforcing material made of glass fiber, aramid fiber, or the like as a core material.

[0024] The insulating layer 21 included in the second buildup section 20 or the insulating layer 31 included in the third buildup section 30 of the buildup sections constituting the wiring board 1 contains a core material in the insulating resin, thereby ensuring the strength of the wiring board 1 and making it relatively resistant to warping. In other words, the combination of the three buildup sections ensures strength and makes it relatively resistant to warping. In prior art wiring boards, if warping occurs in the buildup section, the warping can cause distortion in the optical waveguide. This distortion is thought to cause coupling loss in the optical coupling between the optical waveguide and optical components. In the wiring board of the embodiment, the optical waveguide is disposed on the buildup section. As described above, the buildup section is relatively resistant to warping. Therefore, good optical coupling between the optical waveguide and optical components provided in the wiring board is achieved during use. Note that the insulating layers 11, 21, and 31 may contain an inorganic filler (not shown) made of fine particles such as silica (SiO), alumina, or mullite.

[0025] Examples of conductors constituting the conductor layers 12, 22, 32 and the via conductors 13, 23, 33 include copper, nickel, and silver, and it is preferable to use copper or a metal material mainly composed of copper as the conductor. In the example shown in Figure 1, the conductor layers 12, 22, 32 and the via conductors 13, 23, 33 are shown as single layers, but the conductor layers 12, 22, 32 and the via conductors 13, 23, 33 may be configured as a multilayer structure of two or more layers. For example, the conductor layers 12, 22, 32 and the via conductors 13, 23, 33 have a two-layer structure including a metal film layer, such as a sputtering film layer or an electroless plating film layer, and a plating film layer, such as an electrolytic plating film layer.

[0026] The via conductor 13 is formed by filling a through hole 11a that penetrates the insulating layer 11 with a metal conductor. The via conductor 23 is formed by filling a through hole 21a that penetrates the insulating layer 21 with a metal conductor. The via conductor 33 is formed by filling a through hole 31a that penetrates the insulating layer 31 with a metal conductor. In the example of FIG. 1 , the via conductor 13 is formed integrally with the conductor layer 12 provided below the insulating layer 11. The via conductor 23 is formed integrally with the conductor layer 22 provided below the insulating layer 21. The via conductor 33 is formed integrally with the conductor layer 32 provided below the insulating layer 31.

[0027] The through holes 11a, 21a, and 31a for forming the via conductors 13, 23, and 33 are drilled in the insulating layers 11, 21, and 31 at positions where the via conductors 13, 23, and 33 are to be formed. For example, the drilling method involves irradiating the lower surface of each insulating layer 11, 21, and 31 with laser light. The diameters of the formed through holes 11a, 21a, and 31a are larger on the laser light irradiation side and smaller on the opposite side (the back side) from the laser light irradiation side. Therefore, the through holes 11a, 21a, and 31a are formed so that the diameter is larger on the lower side and smaller on the upper side. As shown in FIG. 1 , each of the via conductors 13, 23, and 33 included in the first buildup section 10 is formed in a tapered shape whose diameter decreases from one surface 1F to the other surface 1B. Note that "reduced diameter" simply means that the distance between the longest two points on the periphery of the via conductor 13 in a horizontal cross section is reduced.

[0028] The diameters of the via conductors 13 constituting the first buildup section 10, the via conductors 23 constituting the second buildup section 20, and the via conductors 33 constituting the third buildup section 30 may be different. Although the term "diameter" is used, the planar shape of the via conductors 13, 23, and 33 is not necessarily limited to a circular shape. The term "diameter" used with respect to the via conductors 13, 23, and 33 refers to the distance between the longest two points on the periphery of the via conductor on the underside of the insulating layer through which the via conductor passes. The maximum diameter of the via conductors 13 included in the first buildup section 10 is defined as V1, the maximum diameter of the via conductors 23 included in the second buildup section 20 is defined as V2, and the maximum diameter of the via conductors 33 included in the third buildup section 30 is defined as V3. It is desirable that V1, V2, and V3 have a relationship of V1 ≠ V2 ≠ V3. Furthermore, it is more desirable that V1, V2, and V3 have the relationship V1<V2<V3. The maximum diameter V1 of the via conductors 13 included in the first buildup section 10 is not particularly limited, but is approximately 3 to 20 μm. The maximum diameter V2 of the via conductors 23 included in the second buildup section 20 is not particularly limited, but is approximately 10 to 60 μm. The maximum diameter V3 of the via conductors 33 included in the third buildup section 30 is not particularly limited, but is approximately 30 to 100 μm.

[0029] The number of insulating layers 11 included in the first buildup section 10, the number of insulating layers 21 included in the second buildup section 20, and the number of insulating layers 31 included in the third buildup section 30 may be different. The number of insulating layers 11 included in the first buildup section 10 is defined as S1, the number of insulating layers 21 included in the second buildup section 20 is defined as S2, and the number of insulating layers 31 included in the third buildup section 30 is defined as S3. It is desirable that S1, S2, and S2 have a relationship of S1 ≠ S2 ≠ S3. It is even more desirable that S1, S2, and S2 have a relationship of S1 > S2 > S3. The number S1 of insulating layers 11 included in the first buildup section 10 is not particularly limited, but is desirably three or more. The number S2 of insulating layers 21 included in the second buildup section 20 is not particularly limited, but is desirably two or more. The number S3 of insulating layers 31 included in third buildup section 30 is not particularly limited, but is preferably one or more.

[0030] The wiring width of the wiring included in the conductor layer 12 constituting the first buildup section 10, the wiring width of the wiring included in the conductor layer 22 constituting the second buildup section 20, and the wiring width of the wiring included in the conductor layer 32 constituting the third buildup section 30 may be different. The minimum wiring width of the wiring included in the conductor layer 12 constituting the first buildup section 10, the minimum wiring width of the wiring included in the conductor layer 22 constituting the second buildup section 20, and the minimum wiring width of the wiring included in the conductor layer 32 constituting the third buildup section 30 may be different. The minimum wiring width of the wiring included in the conductor layer 12 of the first buildup section 10 is defined as W1, the minimum wiring width of the wiring included in the conductor layer 22 of the second buildup section 20 is defined as W2, and the minimum wiring width of the wiring included in the conductor layer 32 of the third buildup section 30 is defined as W3. W1, W2, and W3 may have a relationship of W1 ≠ W2 ≠ W3.

[0031] The inter-wiring distance between the wirings included in the conductor layer 12 constituting the first buildup section 10, the inter-wiring distance between the wirings included in the conductor layer 22 constituting the second buildup section 20, and the inter-wiring distance between the wirings included in the conductor layer 32 constituting the third buildup section 30 may be different. The minimum inter-wiring distance between the wirings included in the conductor layer 12 of the first buildup section 10, the minimum inter-wiring distance between the wirings included in the conductor layer 22 of the second buildup section 20, and the minimum inter-wiring distance between the wirings included in the conductor layer 32 of the third buildup section 30 may be different. The minimum inter-wiring distance between the wirings included in the conductor layer 12 of the first buildup section 10 is defined as D1, the minimum inter-wiring distance between the wirings included in the conductor layer 22 of the second buildup section 20 is defined as D2, and the minimum inter-wiring distance between the wirings included in the conductor layer 32 of the third buildup section 30 is defined as D3. D1, D2, and D3 may have a relationship of D1 ≠ D2 ≠ D3.

[0032] The pattern width and inter-pattern distance of the conductor layers 12 of the wiring board 1 can be made relatively small, and can be made into wiring (first wiring) FW, which is high-density wiring. The wiring FW can have the smallest wiring width and the smallest inter-wiring distance among the wirings constituting the wiring board 1. In the example of FIG. 1 , three of the multiple conductor layers 12 included in the first buildup section 10 have wiring FW, which is high-density wiring. Note that the number of conductor layers 12 that have wiring FW in the first buildup section 10 is not limited.

[0033] The wiring width W1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum wiring width W2 of the wiring in the conductor layer 22 (second conductor layer 22) in the second buildup section 20. The wiring width W1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum wiring width W3 of the wiring included in the conductor layer 32 (third conductor layer 32) in the third buildup section 30. The wiring width W1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum wiring width W2 of the wiring in the conductor layer 22 (second conductor layer 22) in the second buildup section 20 and the minimum wiring width W3 of the wiring in the conductor layer 32 (third conductor layer 32) in the third buildup section 20. The minimum wiring width W1 of the wiring FW is not particularly limited, but is preferably 3 μm or less.

[0034] The minimum wiring width W2 of the wiring included in the conductor layer 22 of the second buildup section 20 is smaller than the minimum wiring width W3 of the wiring included in the conductor layer 32 of the third buildup section 30. The minimum wiring width W1 of the wiring included in the conductor layer 12, the minimum wiring width W2 of the wiring included in the conductor layer 22, and the minimum wiring width W3 of the wiring included in the conductor layer 32 may have a relationship of W1 < W2 < W3. The relationship W1 < W2 < W3 ensures the strength of the wiring board and suppresses warping. As a result, the effects of warping in the first insulating layer 11 are suppressed, warping in the optical waveguide OPW is suppressed, and it is thought that coupling loss is less likely to occur in the optical coupling between the optical waveguide OPW and the optical element.

[0035] For example, the wiring width W2 of the wiring included in the conductor layer 22 is about 4 to 10 μm. For example, the wiring width W3 of the wiring included in the conductor layer 32 is about 15 to 50 μm.

[0036] The thickness of the wiring included in the conductor layer 12 constituting the first buildup section 10, the thickness of the wiring included in the conductor layer 22 constituting the second buildup section 20, and the thickness of the wiring included in the conductor layer 32 constituting the third buildup section 30 may be different. The thickness of the wiring included in the conductor layer 12 constituting the first buildup section 10 is defined as H1, the thickness of the wiring included in the conductor layer 22 constituting the second buildup section 20 is defined as H2, and the thickness of the wiring included in the conductor layer 32 constituting the third buildup section 30 is defined as H3. H1, H2, and H3 may have a relationship of H1 ≠ H2 ≠ H3. Furthermore, H1, H2, and H3 may have a relationship of H1 < H2 < H3. Although not particularly limited, the thickness H1 of the conductor layer 12 is approximately 3 to 5 μm, the thickness H2 of the conductor layer 22 is approximately 5 to 15 μm, and the thickness H3 of the conductor layer 32 is approximately 15 to 30 μm. The wiring width and thickness in each build-up portion may have the relationship W1<W2<W3 and H1<H2<H3.

[0037] The inter-wiring distance D1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum inter-wiring distance D2 of the wiring in the conductor layer 22 (second conductor layer 22) in the second buildup section 20. The inter-wiring distance D1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum inter-wiring distance D3 of the conductor layer 32 (third conductor layer 32) in the third buildup section 30. Note that the inter-wiring distance D1 of the wiring (first wiring) FW included in the first buildup section 10 is smaller than the minimum inter-wiring distance D2 of the wiring in the conductor layer 22 (second conductor layer 22) in the second buildup section 20 and the minimum inter-wiring distance D3 of the conductor layer 32 (third conductor layer 32) in the third buildup section 30. The minimum inter-wiring distance D1 of the wiring width of the wiring FW is not particularly limited, but is preferably 3 μm or less. By having relatively fine wiring FW in the first buildup section 10, wiring with more suitable characteristics corresponding to the electrical signals carried by the wiring within the first buildup section 10 may be provided.

[0038] Furthermore, the minimum inter-wiring distance D2 of the wiring included in the conductor layer 22 of the second buildup section 20 is smaller than the minimum inter-wiring distance D3 of the wiring included in the conductor layer 32 of the third buildup section 30. The inter-wiring distance D1 of the wiring (first wiring) FW included in the first buildup section 10, the minimum inter-wiring distance D2 of the wiring included in the conductor layer 22 of the second buildup section 20, and the minimum inter-wiring distance D3 of the wiring included in the conductor layer 32 of the third buildup section 30 may have a relationship of D1 < D2 < D3. The relationship D1 < D2 < D3 ensures the strength of the wiring board and suppresses warping. As a result, the effects of warping in the first insulating layer 11 are suppressed, warping in the optical waveguide OPW is suppressed, and it is thought that coupling loss is less likely to occur in the optical coupling between the optical waveguide OPW and the optical element.

[0039] The distance D2 between the wires of the conductor layer 22 is about 6 to 15 μm, and the distance D3 between the wires of the conductor layer 32 is about 15 to 50 μm.

[0040] The relationship between the wiring width and the distance between wirings in the build-up section may be W1<W2<W3 and D1<D2<D3.

[0041] Next, with reference to Figures 2A to 2N, a method for manufacturing a wiring board according to an embodiment will be described, taking the case of manufacturing the wiring board 1 shown in Figure 1 as an example. Note that, unless otherwise specified, each component formed in the manufacturing method described below is formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in Figure 1. Note that, in the following description of the manufacturing of the wiring board 1 with reference to Figures 2A to 2K, the side of the support substrate SP closer to the core material GS will be referred to as the "bottom" or "lower side," and the side farther from the support substrate SP will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board 1 that faces the support substrate SP will be referred to as the "lower surface," and the surface facing the opposite side from the support substrate SP will also be referred to as the "upper surface."

[0042] The wiring substrate 1 is formed by manufacturing a first buildup section 10 on a support substrate SP, manufacturing a second buildup section 20 on the first buildup section 10, and manufacturing a third buildup section 30 on the second buildup section 20 (see Figure 1).

[0043] Of the Figures 2A to 2N referred to below, in Figures 2A to 2G, each conductor layer is depicted as two layers, with the metal film layer and electrolytic plating film layer, which are the components of each conductor layer, being separated, whereas in Figures 2H to 2N, each conductor layer is depicted as a single layer, as in Figure 1.

[0044] First, as shown in FIG. 2A , a support substrate SP with excellent surface flatness is prepared. The support substrate SP is formed using a core material GS as a starting material. For example, a glass substrate can be used as the core material GS. In the support substrate SP, a first metal film layer ML1 is formed on both surfaces of the core material GS. Furthermore, an adhesive layer AL is formed on the first metal film layer ML1, and a second metal film layer ML2 is formed on the adhesive layer AL. This results in a three-layer structure consisting of the first metal film layer ML1, the adhesive layer AL, and the second metal film layer ML2 on the core material GS. The first metal film layer ML1 and the second metal film layer ML2 are formed as metal film layers by, for example, electroless plating or sputtering. Although the first metal film layer ML1 and the second metal film layer ML2 are depicted as single layers in FIG. 2A , they may also be formed as multiple layers of two or more layers. For example, the first metal film layer ML1 and the second metal film layer ML2 may be formed of a titanium layer and a copper layer, thereby forming a two-layer structure of the metal film layer. The material of the adhesive layer AL is not particularly limited, but for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation may be used.

[0045] Next, as shown in FIG. 2B , a conductor layer 12 having a plurality of conductor pads 12p is formed on the support substrate SP. In forming the conductor layer 12 in contact with the support substrate SP, for example, a plating resist is formed on the metal film layer ML2. Pattern openings are formed in the plating resist by photolithography using a mask corresponding to the formation of the pattern of the conductor pads 12p. Next, a plating film layer is formed in the pattern openings by electrolytic plating using the metal film layer ML2 as a seed layer. After the plating film layer is formed, the plating resist is removed, resulting in the state shown in FIG. 2B .

[0046] Next, as shown in FIG. 2C , an insulating layer 11 is formed to cover the conductor layer 12. Thermosetting resins or photocurable resins can be used for the insulating layer 11, such as epoxy resins and phenolic resins. Fluorine resins, liquid crystal polymers (LCPs), fluoroethylene resins (PTFEs), polyester resins (PEs), and modified polyimide resins (MPIs) can also be used. The insulating layer 11 is formed by thermocompression bonding of these resins formed into films. Next, through holes 11a are formed in the insulating layer 11 at positions where the via conductors 13 (see FIG. 1 ) will be formed by, for example, irradiating the insulating layer 11 with carbon dioxide laser light or excimer laser light. The laser light is irradiated from above the insulating layer 11. The through holes 11a are formed so that their diameters decrease from top to bottom in the figure.

[0047] Although not shown, the formation of the through holes 11a by irradiation with a laser such as a carbon dioxide laser beam is performed by irradiating the laser while the surface of the insulating layer 11 is protected by covering it with a protective film such as a polyethylene terephthalate (PET) film. The through holes 11a are formed by penetrating the protective film and the insulating layer 11. After the formation of the through holes 11a, a desmearing process may be performed to remove processing-degraded products generated at the bottom of the through holes 11. The desmearing process is preferably a dry desmearing process using plasma gas. The desmearing process may also be performed while protecting the surface of the insulating layer 11 with a protective film such as a polyethylene terephthalate (PET) film formed on the surface of the insulating layer 11.

[0048] 2C and 2D to 2J, which will be referred to below, show stacks formed on one surface of the support substrate SP, and do not show stacks formed on the opposite surface. However, stacks may be formed on the opposite surface in the same manner and with the same number, or conductive layers and insulating layers may be formed in a different manner and with a different number from those on the one surface, or such conductive layers and insulating layers may not be formed.

[0049] Next, as shown in FIG. 2D , a conductor layer 12 having a two-layer structure including a metal film layer 121 and an electrolytic plated film layer 122 and including wiring FW is formed. Furthermore, the interior of the through hole 11a is completely filled with the conductor constituting the electrolytic plated film layer 122, thereby forming a via conductor 13. The metal film layer 121 is formed by electroless plating or sputtering on the inner wall of the through hole 11a and on the surface of the insulating layer 11. Note that a protective film may be provided on the surface of the insulating layer 11 during the formation of the through hole 11a and / or the desmearing process. Preferably, the protective film is removed before the formation of the metal film layer 121. A plating resist having an opening R11 corresponding to the conductor pattern included in the conductor layer 12 is provided on the metal film layer 121. An electrolytic plated film layer 122 is formed in the opening of the plating resist by electrolytic plating using the metal film layer 121 as a power supply layer. Next, after the plating resist is removed, the portion of the metal film layer 121 that is not covered with the electrolytic plated film layer 122 is removed by etching or the like, resulting in the state shown in FIG. 2D.

[0050] Next, as shown in Figure 2E, the desired number of insulating layers 11 and the desired number of conductor layers 12, as well as the via conductors 13 penetrating each insulating layer 11, are formed in a manner similar to the method for forming the insulating layers 11, conductor layers 12, and via conductors 13 described above.

[0051] 2F , the outermost insulating layer 11, conductor layer 12, and via conductor 13 of the insulating layers 11, conductor layers 12, and via conductors 13 of the first buildup section 10 are formed on the upper side of the conductor layer 12. This completes the formation of the first buildup section 10 having a plurality of first insulating layers 11, first conductor layers 12, and first via conductors 13.

[0052] 2G , an insulating layer 21 is formed on the upper side of the first buildup section 10, and then through holes 21a for forming the via conductors 23 are formed by laser processing in the insulating layer 21 at positions corresponding to the locations where the via conductors 13 are to be formed. Next, a conductor layer 22 is formed simultaneously with the via conductors 23 filling the through holes 21a by using any conductor pattern forming method, such as a semi-additive method similar to the above-described method for forming the conductor layer 12 and the via conductors 13.

[0053] 2H , the above-described steps of forming insulating layers 21, conductor layers 22, and via conductors 23 are repeated to form a desired number of insulating layers 21 and conductor layers 22, as well as via conductors 23 that penetrate each insulating layer 21. Formation of second buildup section 20 on first buildup section 10 is completed. Note that, in forming first buildup section 10 and second buildup section 20, first insulating layer 11 and second insulating layer 21 are formed so that their thicknesses are different. Specifically, second insulating layer 21 may be formed to have a thickness greater than that of first insulating layer 11. A prepreg containing insulating resin impregnated in a reinforcing material (core material) made of glass fiber may be used as the insulating resin that forms insulating layer 21. Furthermore, in forming the first buildup section 10 and the second buildup section 20, the wiring FW in the first conductor layer 12 is formed so that the minimum wiring width is different from the minimum wiring width of the wiring in the second conductor layer 22, and the minimum wiring interval between the wiring FW in the first conductor layer 12 is different from the minimum wiring interval between the wiring in the second conductor layer 22. Specifically, in forming the first buildup section 10 and the second buildup section 20, the wiring FW in the first conductor layer 12 may be formed so that the minimum wiring width is smaller than the minimum wiring width of the wiring in the second conductor layer 22, and the minimum wiring interval between the wiring FW in the first conductor layer 12 is smaller than the minimum wiring interval between the wiring in the second conductor layer 22.

[0054] Next, as shown in FIG. 2I , insulating layer 31, conductor layer 32, and via conductor 33 filling through-hole 31a penetrating insulating layer 31 are formed on outermost insulating layer 21 and conductor layer 22 of second buildup section 20. Insulating layer 31, conductor layer 32, and via conductor 33 are formed using a method similar to that used to form insulating layer 21, conductor layer 22, and via conductor 23. Prepreg containing an insulating resin such as epoxy resin or BT resin impregnated in a reinforcing material (core material) made of glass fiber can be used as the insulating resin forming insulating layer 31. As shown in the figure, a third buildup section 30 is formed, including two insulating layers 31 and two conductor layers 32. In forming the third buildup section 30, third insulating layer 31 is formed so that its thickness is different from that of second insulating layer 21. Specifically, third insulating layer 31 may be formed to have a thickness greater than that of second insulating layer 21. Furthermore, in forming the third build-up section 30, the wiring may be formed so that the minimum wiring width of the wiring in the third conductor layer 32 is different from the minimum wiring width of the wiring in the second conductor layer 22, and the minimum wiring spacing of the wiring in the third conductor layer 32 is different from the minimum wiring spacing of the wiring in the second conductor layer 22. Specifically, in forming the third build-up section 30, the wiring may be formed so that the minimum wiring width of the wiring in the third conductor layer 32 is larger than the minimum wiring width of the wiring in the second conductor layer 22, and the minimum wiring spacing of the wiring in the third conductor layer 32 is larger than the minimum wiring spacing of the wiring in the second conductor layer 22.

[0055] Next, a solder resist layer SR2 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 31 and the conductor layer 32. Then, openings SR2a that expose the conductor pads 32p are formed by photolithography.

[0056] 2J, the support substrate SP is removed. The lower surface of the second metal film layer ML2 below the conductor pad 12p is exposed. In removing the support substrate SP, the adhesive layer AL is softened by being irradiated with, for example, laser light, and then the second metal film layer ML2 of the support substrate SP is peeled off.

[0057] Next, the second metal film layer ML2 is removed by etching. A solder resist layer SR1 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the first surface 10F of the first buildup section 10 exposed by removing the second metal film layer ML2. Openings SR1a exposing the conductor pads 12p are formed in the solder resist layer SR1 by photolithography. The state shown in FIG. 2K is completed.

[0058] Next, the formation of the optical waveguide OPW on the build-up portion constituting the wiring board will be described with reference to Figures 2L to 2N. Figures 2L to 2N show an enlarged and upside-down view of the portion corresponding to the region L surrounded by the dashed line in Figure 2K. Note that in the description of the formation of the optical waveguide OPW with reference to Figures 2L to 2N, the side of the elements constituting the optical waveguide OPW that is closer to the solder resist layer SR1 will be referred to as the "bottom" or "lower side," and the side that is farther from the solder resist layer SR1 will be referred to as the "top" or "upper side."

[0059] 2L, a lower clad C1 is formed on the surface of a solder resist layer SR1, and a core C2 is formed on the lower clad C1. The lower clad C1 is formed, for example, by thermocompression bonding a film-shaped constituent material of the lower clad C1 to the solder resist layer SR1. The constituent material of the lower clad C1, such as PMMA, is formed into a film shape and thermocompression bonded.

[0060] Next, the core C2 is formed using, for example, photolithography technology. For example, a photosensitive layer made of the material for the core C2, such as PMMA, is formed on the entire upper surface of the lower clad C1. As an example, the material for the core C2 is applied to the entire upper surface of the lower clad C1 to form a film made of the material for the core C2. Alternatively, the material for the core C2 may be formed into a film and then thermocompressed onto the surface of the lower clad C1. Then, the layer made of the material for the core C2 is patterned by exposing it to light through a mask corresponding to the shape of the core C2 to be formed and developing it. The core C2 having the desired pattern is formed.

[0061] Next, as shown in FIG. 2M , an upper clad C3 is formed on the core C2 and the lower clad C1. For example, similar to the formation of the lower clad C1, a material for the upper clad C3, such as PMMA, is formed into a film and thermocompressed to form a film made of the material for the upper clad C3. The upper clad C3 is integrated with or at least closely adhered to the lower clad C1, thereby forming the upper clad C3 surrounding the core C2. As a result, a waveguide having a core-exposed portion at one end in a planar view and a core-exposed end surface at the other end is disposed on the wiring board. Note that the waveguide may have a form other than that shown in FIG. 2M . For example, the waveguide may have core-exposed portions at both ends in a planar view, or the core may be exposed at both end surfaces of the waveguide.

[0062] 2N, the portion of the upper clad C3 covering part of the core C2 is removed. As an example, the portion of the upper clad C3 to be removed is removed using photolithography. The portion of the upper clad C3 to be removed may also be removed by laser processing, and the removal method is not limited to these methods. In forming the upper clad C3 described above, a film that is a constituent material of the upper clad C3 may be thermocompression bonded so that the exposed portion C2a of the core C2 is not covered. By removing part of the upper clad C3, an upper clad non-forming region A1 and an upper clad forming region A2 are provided, and the exposed portion C2a of the core C2 is exposed in the upper clad non-forming region A1. The formation of the optical waveguide OPW on the first buildup section 10 is completed, and the formation of the wiring substrate 1 is also completed.

[0063] As an example of the embodiment, the thickness T1 of the first insulating layer 11 is 8 μm, the thickness T2 of the second insulating layer 21 is 17 μm, the thickness T3 of the third insulating layer 31 is 35 μm, the thickness H1 of the wiring of the first conductor layer 12 is 4 μm, the minimum value W1 of the wiring width of the wiring of the first conductor layer 12 is 3 μm, the minimum value D1 of the wiring spacing of the wiring of the first conductor layer 12 is 3 μm, The thickness H2 of the wiring in the second conductor layer 22 is 7 μm, the minimum wiring width W2 of the wiring in the second conductor layer 22 is 7 μm, the minimum wiring spacing D2 of the wiring in the second conductor layer 22 is 10 μm, the thickness H3 of the wiring in the third conductor layer 32 is 20 μm, the minimum wiring width W3 of the wiring in the third conductor layer 32 is 20 μm, and the minimum wiring spacing D3 of the wiring in the third conductor layer 32 is 20 μm. Furthermore, as an example, the maximum diameter V1 of the via conductors 13 is 10 μm, the maximum diameter V2 of the via conductors 23 is 20 μm, and the maximum diameter V3 of the via conductors 33 is 40 μm. As an example, the number of layers S1 of the first buildup section 10 is five, the number of layers S2 of the second buildup section 20 is four, and the number of layers S3 of the third buildup section 30 is two. For example, the thickness of the lower clad C1 is 30 μm, the thickness of the upper clad C3 is 20 μm, and the thickness of the core C2 is 5 μm. The planar shape of the core C2 of the optical waveguide OPW is rectangular, and for example, the width of the core C2 is 5 μm, the arrangement pitch of the core C2 is 5 μm, and the length of the exposed portion C2a of the core C2 is 2000 μm.

[0064] According to an embodiment of the present invention, an optical waveguide can be provided in which it is easy to align, in the thickness direction, a light receiving or emitting portion (light guiding portion) of a connecting material (e.g., an optical element or an optical interposer) that can be connected to the optical waveguide with a core portion of the optical waveguide.

[0065] REFERENCE SIGNS LIST 1 wiring substrate 10 first buildup section 20 second buildup section 30 third buildup section 11 insulating layer (first insulating layer) 21 insulating layer (second insulating layer) 31 insulating layer (third insulating layer) 12 conductor layer (first conductor layer) 22 conductor layer (second conductor layer) 32 conductor layer (third conductor layer) 13 via conductor (first via conductor) 23 via conductor (second via conductor) 33 via conductor (third via conductor) 12p, 32p conductor pad C1 lower cladding C2 core C3 upper cladding OPW optical waveguide OPD component (optical element) A1 upper cladding non-forming region A2 upper cladding forming region FW wiring SP supporting substrate

Claims

1. A wiring board including a buildup section which is made up of multiple conductor layers and multiple insulating layers and has via conductors connecting the multiple conductor layers to each other, and an optical waveguide arranged on the buildup section, wherein the buildup section is composed of a first buildup section, a second buildup section, and a third buildup section, wherein the first buildup section includes multiple first conductor layers and multiple first insulating layers and has a first surface and a second surface opposite to the first surface, the second buildup section includes multiple second conductor layers and multiple second insulating layers and has a first surface and a second surface opposite to the first surface, and is formed on the second surface side of the first buildup section, the second conductor layers and the first conductor layers being electrically connected, the third buildup section includes multiple third conductor layers and multiple third insulating layers and has a first surface and a second surface opposite to the first surface, and is formed on the second surface side of the second buildup section, and the third conductor layers and the second conductor layers being electrically connected, The optical waveguide is formed on a first surface of a first buildup section, and the thickness (T1) of the first insulating layer, the thickness (T2) of the second insulating layer, and the thickness (T3) of the third insulating layer satisfy the following formula (1), where the second insulating layer or the third insulating layer includes a core material: T1 ≠ T2 ≠ T3 (1) 2. A wiring board according to claim 1, wherein the first surface of the first build-up section includes component mounting pads that are the first conductor layer.

3. A wiring board according to claim 1, wherein the second insulating layer and the third insulating layer include a core material.

4. The wiring board according to claim 1, wherein the core material is glass fiber.

5. The wiring board according to claim 1, wherein the thickness (T1) of the first insulating layer, the thickness (T2) of the second insulating layer, and the thickness (T3) of the third insulating layer satisfy the relationship of the following formula (2): T1<T2<T3 (2) 6. In the wiring board according to claim 1, the minimum wiring width (W1) of the wiring included in the first conductor layer, the minimum wiring width (W2) of the wiring included in the second conductor layer, and the minimum wiring width (W3) of the wiring included in the third conductor layer satisfy the relationship of the following formula (3): W1 ≠ W2 ≠ W3 (3) 7. A wiring board according to claim 6, wherein the minimum wiring width (W1) of the wiring included in the first conductor layer, the minimum wiring width (W2) of the wiring included in the second conductor layer, and the minimum wiring width (W3) of the wiring included in the third conductor layer satisfy the relationship of the following formula (4): W1<W2<W3 (4) 8. A wiring board according to claim 7, wherein the minimum value (W1) of the wiring width of the wiring included in the first conductor layer is 3 μm or less.

9. A wiring board as claimed in claim 1, wherein the optical waveguide comprises an upper clad, a core, and a lower clad, the core being disposed between the upper clad and the lower clad, the optical waveguide comprising an upper clad non-forming region and an upper clad formed region, the lower clad comprising a core-forming surface and a core-non-forming surface, the core-non-forming surface being disposed so as to face the first surface of the first build-up section, the upper surface of the core being exposed in the upper clad non-forming region, and the upper surface of the core being covered by the upper clad in the upper clad formed region.

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